Semiconductor device and manufacturing method of semiconductor device

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes: a gate structure comprising conductive and insulating layers alternately stacked on top of each other; a channel structure passing through the gate structure and arranged in a first direction; a dicing structure extending in the first direction and passing through the channel structure; and a first slit structure passing through the gate structure and extending in a second direction intersecting the first direction.

Description

Technical Field

[0001] The disclosed technology generally relates to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0053233, filed on April 23, 2021, which is incorporated herein by reference in its entirety. Prior Technology

[0003] The integration density of semiconductor devices can be primarily determined by the area of ​​a single memory cell. Recently, increasing the integration density of semiconductor devices with memory cells formed in a single layer on a substrate has been limited. Therefore, a three-dimensional semiconductor device with memory cells stacked on a substrate has been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0004] Various embodiments relate to a semiconductor device having a stable structure and improved properties, as well as a method of manufacturing the semiconductor device.

[0005] According to one embodiment, a semiconductor device may include: a gate structure including conductive layers and insulating layers stacked alternately on each other; a channel structure passing through the gate structure and arranged in a first direction; a dicing structure extending in the first direction and passing through the channel structure; and a first slit structure passing through the gate structure and extending in a second direction intersecting the first direction.

[0006] According to one embodiment, a semiconductor device may include: a gate structure including conductive layers and insulating layers stacked alternately on top of each other; a columnar structure passing through the gate structure; a dicing structure passing through the columnar structure and separating each of the columnar structures into a first columnar structure and a second columnar structure; a first slit structure passing through the gate structure and extending in a direction intersecting the dicing structure; a first interconnect extending in a direction intersecting the first slit structure and coupled to the first columnar structure; and a second interconnect extending in a direction intersecting the first slit structure and coupled to the second columnar structure.

[0007] According to one embodiment, a method of manufacturing a semiconductor device may include the steps of: forming a stacked structure; forming a channel structure that passes through the stacked structure and is arranged in a first direction; forming a slit structure that passes through the channel structure and extends in the first direction; and forming a first slit structure that passes through the stacked structure and extends in a second direction intersecting the first direction. Simple Explanation of the Diagram

[0008] Figures 1A to 1D are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0009] Figures 2A to 2C are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0010] Figures 3A to 3C are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0011] Figures 4A to 4D are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0012] Figures 5A and 5B, 6A and 6B, 7A to 7C, and 8A to 8C are figures illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure;

[0013] [Figure 9A] and [Figure 9B] are figures illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure;

[0014] [Figure 10] is a diagram illustrating a memory system according to one embodiment of the present disclosure;

[0015] [Figure 11] is a diagram illustrating a memory system according to one embodiment of the present disclosure;

[0016] Figure 12 is a diagram illustrating a memory system according to one embodiment of the present disclosure;

[0017] [Figure 13] is a diagram illustrating a memory system according to one embodiment of the present disclosure; and

[0018] [Figure 14] is a diagram illustrating a memory system according to one embodiment of the present disclosure. Implementation

[0019] The specific structural or functional descriptions illustrating examples of embodiments of the concepts disclosed in this specification are for illustrative purposes only and may be implemented in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0020] Figures 1A to 1D are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0021] Referring to Figures 1A to 1C, the semiconductor device may include a gate structure GST, a columnar structure P, a diced structure CS, and a first slit structure SLS1. The semiconductor device may include a base 10, a second slit structure SLS2, a first contact plug CT1, a second contact plug CT2, or a combination thereof.

[0022] The gate structure GST may include conductive layers 11 and insulating layers 12 stacked alternately on top of each other. Each of the conductive layers 11 may be a gate electrode for selecting a transistor or memory cell. The conductive layers 11 may include conductive materials such as polysilicon or metals (e.g., tungsten, molybdenum). The insulating layers 12 may insulate the stacked conductive layers 11 from each other. The insulating layers 12 may include insulating materials such as oxides, nitrides, or air gaps.

[0023] The gate structure GST can be located on the base 10. The base 10 can be a semiconductor substrate or a source layer. The semiconductor substrate can include a source region doped with impurities. The source layer can include a conductive material such as polysilicon or a metal (e.g., tungsten, molybdenum).

[0024] The columnar structure P can pass through the gate structure GST. The columnar structure P can be arranged in a first direction I and a second direction II intersecting the first direction I. Intersecting directions mean directions that are not parallel. For example, these directions can be substantially perpendicular to each other. According to an embodiment, the columnar structure P can be arranged in a matrix.

[0025] Each of the columnar structures P may include a pair of first columnar structures P1 and second columnar structures P2. Each of the columnar structures P may be divided into a pair of first columnar structures P1 and second columnar structures P2 by a cutting structure CS. The pair of first columnar structures P1 and second columnar structures P2 may be adjacent to each other in the second direction II, with the cutting structure CS inserted therebetween, or may have a structure symmetrical with respect to the cutting structure CS.

[0026] According to the embodiment, each of the columnar structures P can be a channel structure including channel layers 13A and 13B. The first columnar structure P1 can be a first channel structure and the second columnar structure P2 can be a second channel structure. A first memory cell or select transistor can be arranged at the intersection of the first columnar structure P1 and the conductive layer 11. A second memory cell or select transistor can be arranged at the intersection of the second columnar structure P2 and the conductive layer 11. The first and second memory cells, which are adjacent to each other in the second direction II and in which the cut structure CS is inserted, can be driven independently of each other.

[0027] The first columnar structure P1 may include a first channel layer 13A. The first channel layer 13A may refer to a region where channels such as memory cells and selection transistors are formed. The first channel layer 13A may include a semiconductor material such as silicon or germanium. The first columnar structure P1 may also include a first conductive pad 14A. The first conductive pad 14A may be coupled to the first channel layer 13A and includes a conductive material. The first columnar structure P1 may include a first insulating core 15A. The first insulating core 15A may include an insulating material such as oxides, nitrides, and air gaps. The first columnar structure P1 may also include a memory layer (not shown) located between the first channel layer 13A and the conductive layer 11. The memory layer may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, a charge trapping material, polysilicon, nitrides, variable resistance materials, nanostructures, or combinations thereof.

[0028] The second columnar structure P2 may have a structure similar to that of the first columnar structure P1. The second columnar structure P2 may include a second channel layer 13B. The second columnar structure P2 may also include a second conductive pad 14B, a second insulating core 15B, or a combination thereof.

[0029] According to one embodiment, each of the columnar structures P can be an electrode structure including an electrode layer. The first columnar structure P1 can be a first electrode structure, and the second columnar structure P2 can be a second electrode structure. The first electrode structure can include a first electrode layer instead of the first channel layer 13A. The first electrode structure can also include a first conductive pad 14A, a first insulating core 15A, or a combination thereof. The first columnar structure P1 can also include a memory layer (not shown) located between the first electrode layer and the conductive layer 11. The second electrode structure can include a second electrode layer instead of the second channel layer 13B. The second electrode structure can also include a second conductive pad 14B, a second insulating core 15B, or a combination thereof. The second columnar structure P2 can also include a memory layer (not shown) located between the second electrode layer and the conductive layer 11.

[0030] The cut structure CS can pass through the columnar structure P and extend to the base 10. The cut structure CS can pass through the gate structure GST and the columnar structure P1 and extend in the first direction I. The cut structure CS can pass through the columnar structure P successively. The cut structure CS can intersect with at least two columnar structures P arranged in the first direction I and can separate each columnar structure P into a pair of first columnar structures P1 and second columnar structures P2. The cut structure CS can include insulating materials such as oxides, nitrides, and air gaps.

[0031] Multiple cutting structures CS can be located between a pair of first slit structures SLS1. The cutting structures CS can be arranged in a first direction I and a second direction II. According to one embodiment, the cutting structures CS can be arranged in a matrix form.

[0032] The first slit structure SLS1 can pass through the gate structure GST. The first slit structure SLS1 can extend in a direction intersecting the cutting structure CS. The first slit structure SLS1 can extend in a second direction II. According to one embodiment, the first slit structure SLS1 can be arranged perpendicular to the cutting structure CS. The first slit structure SLS1 may include an insulating material. According to one embodiment, the first slit structure SLS1 may include a contact structure electrically coupled to the base 10 and an insulating spacer that insulates the contact structure and the conductive layer 11 from each other.

[0033] The second slit structure SLS2 can penetrate the gate structure GST at a shallower depth than the first slit structure SLS1 or the cut structure CS. The second slit structure SLS2 can have a depth that penetrates at least one of the uppermost conductive layers 11. According to one embodiment, the depth of the second slit structure SLS2 is such that the second slit structure SLS2 penetrates at least one conductive layer 11 corresponding to the select line, but does not penetrate the conductive layer 11 corresponding to the word line.

[0034] At least one second slit structure SLS2 may be located between a pair of first slit structures SLS1. The second slit structure SLS2 may extend in a direction intersecting the cutting structure CS. The second slit structure SLS2 may extend parallel to the first slit structures SLS1. The second slit structure SLS2 may extend in a second direction II. The cutting structure CS may be arranged symmetrically or asymmetrically on both sides relative to the second slit structure SLS2. The second slit structure SLS2 may contact at least one cutting structure CS. A columnar structure P may be located between the first slit structures SLS1 and the second slit structure SLS2. Some columnar structures P may contact the second slit structure SLS2.

[0035] Referring to Figures 1A and 1D, the semiconductor device may further include a first interconnect IL1 and a second interconnect IL2. The first interconnect IL1 and the second interconnect IL2 may extend in a direction intersecting the first slit structure SLS1 or the second slit structure SLS2. The first interconnect IL1 and the second interconnect IL2 may travel parallel to the dicing structure CS and extend in a first direction I.

[0036] According to one embodiment, a first contact plug CT1 can be coupled to a first columnar structure P12, and a second contact plug CT2 can be coupled to the first contact plug CT1. According to one embodiment, the first contact plug CT1 and the second contact plug CT2 can be located at different heights, and the upper surface of the first contact plug CT1 and the bottom surface of the second contact plug CT2 can be coupled to each other. A first interconnect line IL11 can be coupled to the first columnar structure P12 via the first contact plug CT1 and the second contact plug CT2. A first interconnect line IL12 can be coupled to the first columnar structure P11 via the first contact plug CT1 and the second contact plug CT2. A second interconnect line IL21 can be coupled to the second columnar structure P22 via the first contact plug CT1 and the second contact plug CT2. A second interconnect line IL22 can be connected to the second columnar structure P21 via the first contact plug CT1 and the second contact plug CT2.

[0037] However, the number of the first slit structure SLS1, the second slit structure SLS2, and the columnar structure P shown in Figures 1A and 1D can be varied. For example, the number of columnar structures P located between a pair of first slit structures SLS1, the number of columnar structures P located between the first slit structure SLS1 and the second slit structure SLS2, the number of cutting structures CS located between a pair of first slit structures SLS1, and the number of cutting structures CS located between the first slit structure SLS1 and the second slit structure SLS2 can be varied.

[0038] Based on the above structure, a columnar structure P can be separated into multiple columnar structures P1 and P2 using a cutting structure CS. Therefore, the number of memory cells implemented using a single columnar structure P can be increased. Thus, even without increasing the number of stacked conductive layers 11 included in the gate structure GST, the number of memory cells included in the gate structure GST can be increased.

[0039] Figures 2A to 2C are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. For the sake of brevity, repeated descriptions of certain elements described above are omitted below.

[0040] Referring to Figures 2A to 2C, the semiconductor device may include a gate structure GST, a columnar structure P, a diced structure CS, and a first slit structure SLS1. The semiconductor device may include a base 10, a second slit structure SLS2, a first contact plug CT1, a second contact plug CT2, or a combination thereof.

[0041] The columnar structures P can be staggered relative to each other. According to one embodiment, the centers of columnar structures P that are adjacent to each other in a first direction I can coincide with each other, while the centers of columnar structures P that are adjacent to each other in a second direction II can be offset from each other.

[0042] The cutting structures CS can be staggered relative to each other. According to one embodiment, the centers of the cutting structures CS that are adjacent to each other in the first direction I can coincide with each other, while the centers of the cutting structures CS that are adjacent to each other in the second direction II can be offset from each other.

[0043] Two or more second slit structures SLS2 may be located between a pair of first slit structures SLS1. For example, Figure 2A shows two second slit structures SLS2 between a pair of first slit structures SLS1. A columnar structure P may be located between the first slit structures SLS1 and the second slit structures SLS2, as well as between the second slit structures SLS2.

[0044] The second slit structure SLS2 can contact some cutting structures CS on both sides. The second slit structure SLS2 can contact the cutting structure CS on one side and separate from the cutting structure CS on the other side.

[0045] Figures 3A to 3C are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, repeated descriptions of certain elements described above are omitted below.

[0046] Referring to Figures 3A and 3B, the semiconductor device may include a gate structure GST, a pillar structure P, a dicing structure CS, and a first slit structure SLS1. The semiconductor device may also include a base 10, a second slit structure SLS2, or a combination thereof.

[0047] The cutting structure CS can pass through three or more columnar structures P arranged in the first direction I. The second slit structure SLS2 can have a zigzag shape, such as a shape including joined end-to-end non-parallel line segments, or a wavy shape, such as a shape including joined curves. For example, a zigzag shape is depicted in Figure 3A. The second slit structure SLS2 can be separated from the cutting structure CS on both sides.

[0048] Referring to FIG3C, the semiconductor device may further include a first interconnect IL1 and a second interconnect IL2. The first interconnect IL1 and the second interconnect IL2 may extend in a first direction I.

[0049] According to one embodiment, a first interconnect IL11 can be coupled to a first columnar structure P13 via a first contact plug CT1 and a second contact plug CT2. A first interconnect IL12 can be coupled to a first columnar structure P12 via a first contact plug CT1 and a second contact plug CT2. A first interconnect IL13 can be coupled to a first columnar structure P11 via a first contact plug CT1 and a second contact plug CT2. A second interconnect IL21 can be coupled to a second columnar structure P23. A second interconnect IL22 can be coupled to a second columnar structure P22. A second interconnect IL23 can be coupled to a second columnar structure P21.

[0050] Figures 4A to 4D are diagrams illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. For the sake of brevity, repeated descriptions of certain elements described above are omitted below.

[0051] Referring to Figures 4A to 4C, the semiconductor device may include a gate structure GST, a columnar structure P, a diced structure CS, and a first slit structure SLS1. The semiconductor device may include a base 10, a second slit structure SLS2, a first contact plug CT1, a second contact plug CT2, or a combination thereof.

[0052] Each of the columnar structures P can include a first columnar structure P1 and a second columnar structure P2. The first columnar structure P1 can include a first sub-columnar structure P1A and a second sub-columnar structure P1B. The second columnar structure P2 can include a first sub-columnar structure P2A and a second sub-columnar structure P2B.

[0053] The second sub-pillar structures P1B and P2B may include at least one of the uppermost conductive layers in the conductive layers 11. The first sub-pillar structures P1A and P2A may extend through the remaining conductive layers 11 in the conductive layers 11. According to one embodiment, the first sub-pillar structures P1A and P2A may correspond to a memory cell or a source-select transistor, and the second sub-pillar structures P1B and P2B may correspond to a drain-select transistor.

[0054] The first sub-pillar structure P1A may include a first channel layer 13A, a first conductive pad 14A, a first insulating core 15A, or a combination thereof. The second sub-pillar structure P1B may include a first channel layer 23A, a first conductive pad 24A, a first insulating core 25A, or a combination thereof. The first sub-pillar structure P2A may include a second channel layer 13B, a second conductive pad 14B, a second insulating core 15B, or a combination thereof. The second sub-pillar structure P2B may include a second channel layer 23B, a second conductive pad 24B, a second insulating core 25B, or a combination thereof. The first electrode layer and the second electrode layer may replace the first channel layer 13A or 23A and the second channel layer 13B or 23B.

[0055] Referring to FIG4D, the semiconductor device may further include a first interconnect IL1 and a second interconnect IL2. The first interconnect IL1 and the second interconnect IL2 may extend in a first direction I.

[0056] According to one embodiment, the first columnar structure P11 may include a first sub-columnar structure P11A and a second sub-columnar structure P11B. The first columnar structure P12 may include a first sub-columnar structure P12A and a second sub-columnar structure P12B. The first columnar structure P13 may include a first sub-columnar structure P13A and a second sub-columnar structure P13B. The first columnar structure P14 may include a first sub-columnar structure P14A and a second sub-columnar structure P14B. The first contact plug CT1 may be coupled to the second sub-columnar structures P11B to P14B of the first columnar structures P11 to P14. The second contact plug CT2 may be coupled to the first contact plug CT1.

[0057] The second columnar structure P21 may include a first sub-column structure P21A and a second sub-column structure P21B. The second columnar structure P22 may include a first sub-column structure P22A and a second sub-column structure P22B. The second columnar structure P23 may include a first sub-column structure P23A and a second sub-column structure P23B. The second columnar structure P24 may include a first sub-column structure P24A and a second sub-column structure P24B. The first contact plug CT1 may be coupled to the second sub-column structures P21B to P24B of the second columnar structures P21 to P24. The second contact plug CT2 may be coupled to the first contact plug CT1. The first interconnect IL11 may be coupled to the first columnar structure P12 and the first columnar structure P14 via the first contact plug CT1 and the second contact plug CT2. The first interconnect IL12 may be coupled to the first columnar structure P11 and the first columnar structure P13 via the first contact plug CT1 and the second contact plug CT2. The second interconnect IL21 can be coupled to the second columnar structure P22 and the second columnar structure P24 via the first contact plug CT1 and the second contact plug CT2. The second interconnect IL22 can be coupled to the second columnar structure P21 and the second columnar structure P23 via the first contact plug CT1 and the second contact plug CT2.

[0058] Figures 5A and 5B, 6A and 6B, 7A to 7C, and 8A to 8C are figures illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0059] Referring to Figures 5A and 5B, a stacked structure ST can be formed on a base 50. The base 50 can be a semiconductor substrate, a source structure, or the like. The semiconductor substrate can include a source region doped with impurities. The source structure can include a source layer comprising a conductive material such as polysilicon or a metal (e.g., tungsten, molybdenum). Alternatively, the source region can include a sacrificial layer that will be replaced by the source layer during subsequent processes.

[0060] A stacked structure ST can be formed by alternately forming a first material layer 51 and a second material layer 52. The first material layer 51 may include a material with high etch selectivity relative to the second material layer 52. For example, the first material layer 51 may include a sacrificial material such as a nitride, and the second material layer 52 may include an insulating material such as an oxide. In another example, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 52 may include an insulating material such as an oxide.

[0061] Subsequently, columnar structures P can be formed by passing through the stacked structure ST. Columnar structures P can be arranged along a first direction I and a second direction II intersecting the first direction I. Columnar structures P adjacent to each other along the first direction I can be arranged such that their centers coincide. Conversely, columnar structures P adjacent to each other along the second direction II can be arranged such that their centers are offset from each other.

[0062] In the plane defined by the first direction I and the second direction II, the columnar structure P can have various shapes such as circular, elliptical, and polygonal. The planar cross-section of the columnar structure P can have a first width W1 in the first direction I and a second width W2 in the second direction II. The first width W1 and the second width W2 can be the same as or different from each other. Considering the width of the cut structure to be formed during subsequent processes, the second width W2 can be greater than the first width W1.

[0063] Each columnar structure P may include a channel layer 53. According to one embodiment, the channel layer 53 may be formed in the opening after an opening is formed through the stacked structure ST. A memory layer may be formed before the channel layer 53 is formed. A conductive pad 54 may be formed after the insulating core 55 is formed. Each columnar structure P may include an electrode layer instead of the channel layer 53. The insulating core 55 or the conductive pad 54 may be omitted.

[0064] Referring to Figures 6A and 6B, a cutting structure 56 can be formed. Each cutting structure 56 can pass through at least two columnar structures P and extend in a first direction I. Each columnar structure P can be separated into a first columnar structure P1 and a second columnar structure P2.

[0065] The first columnar structure P1 can be a first channel structure and the second columnar structure P2 can be a second channel structure. The first columnar structure P1 may include a first channel layer 53A, a first conductive pad 54A, and a first insulating core 55A. The second columnar structure P2 may include a second channel layer 53B, a second conductive pad 54B, and a second insulating core 55B. Alternatively, the first columnar structure P1 can be a first electrode structure, and the second columnar structure P2 can be a second electrode structure. The first electrode structure may include a first electrode layer instead of the second channel layer 53A. The second electrode structure may include a second electrode layer instead of the second channel layer 53B.

[0066] According to one embodiment, a trench T can be formed through the stacked structure ST and the columnar structure P. The trench T can extend in depth to completely penetrate the columnar structure P and reach the base 50. The trench T can extend in a first direction I and penetrate at least two columnar structures P. Subsequently, a cutting structure 56 can be formed in the trench T. The cutting structure 56 can be configured to insulate the first columnar structure P1 and the second columnar structure P2 from each other, and can include an insulating material.

[0067] Referring to Figures 7A to 7C, a first slit SL1 can be formed through the stacked structure ST. The first slit SL1 can extend in a direction intersecting the cutting structure 56. The first slit SL1 can extend in a second direction II and can be spaced apart from the cutting structure 56. The first slit SL1 can have a depth that exposes the first material layer 51 and extends to the base 50.

[0068] Subsequently, the first material layer 51 can be replaced with a third material layer 57. For example, when the first material layer 51 is a sacrificial layer and the second material layer 52 is an insulating layer, the first material layer 51 can be replaced by a conductive layer. After the first material layer 51 is selectively etched, the third material layer 57 can be formed in the etched area of ​​the first material layer 51. However, the memory layer can be formed before the third material layer 57 is formed. In another example, when the first material layer 51 is a conductive layer and the second material layer 52 is an insulating layer, the first material layer 51 can be silicided. As a result, a gate structure GST in which the third material layer 57 and the second material layer 52 are stacked alternately can be formed. Subsequently, a first slit structure 58 can be formed in the first slit SL1.

[0069] Referring to Figures 8A to 8C, a second slit SL2 can be formed through the gate structure GST. The second slit structure SL2 can penetrate the gate structure GST at a shallower depth than the first slit structure 58 or the cutting structure 56. The second slit SL2 can extend in a direction intersecting the cutting structure 56, and can also extend in a second direction II. Within the plane defined by the first direction I and the second direction II, the second slit SL2 can have a straight shape, a zigzag shape, a wavy shape, etc.

[0070] A second slit SL2 can be formed between the columnar structures P. When the second slit SL2 is formed, the cut structure 56 or the columnar structure P can be etched together with the stacked structure ST. Therefore, the cut structure 56 or the columnar structure P can be exposed by the second slit SL2. The second slit SL2 can be formed to intersect with the cut structure 56. A cut structure 56 can be separated into multiple patterns by the second slit SL2.

[0071] Subsequently, a second slit structure 59 can be formed in the second slit SL2. The second slit structure 59 may include an insulating material. At least one uppermost third material layer 57 may be separated into multiple patterns by the second slit structure 59. The second slit structure 59 may contact adjacent cut structures 56 or columnar structures P.

[0072] Although not shown in the figure, interconnects coupled to the columnar structure P can be formed. According to one embodiment, at least one first bit line extending in the first direction I and coupled to the first columnar structure P1 can be formed, and at least one second bit line extending in the first direction I and coupled to the second columnar structure P2 can be formed.

[0073] According to the manufacturing method described above, a columnar structure P can be separated into multiple columnar structures P1 and P2 using the cutting structure 56. Therefore, the number of memory cells implemented using a single columnar structure P can be increased. Furthermore, by forming a second slit SL2 in the direction intersecting the cutting structure 56, the process of replacing the first material layer 51 with a third material layer 57 can be improved.

[0074] Figures 9A and 9B are diagrams illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0075] Figures 9A and 9B are diagrams visualizing the effect of the arrangement of the cutting structures 56 and 56' and the first slit SL1 during the process of replacing the first material layer 51 with the third material layer 57. To replace the first material layer 51 with the third material layer 57, the third material layer 57 can be deposited on the etched areas of the first material layer 51 after the first material layer 51 has been selectively etched. Chemicals such as etchants can be used to perform the etching process of the first material layer 51. Chemicals (as indicated by arrows) can be introduced between the columnar structure P and the cutting structures 56 and 56' to selectively etch the first material layer 51.

[0076] Referring to FIG9A, the first slit SL1 may be formed parallel to the cut structure 56'. The flow path of the chemical substance may be restricted by the cut structure 56' extending in the second direction II. Therefore, it may be possible to prevent the flow of chemical substance between the cut structures 56' that are adjacent to each other in the first direction I, and the region R of the first material layer may be preserved without being etched.

[0077] Referring to FIG9B, the first slit SL1 can be formed to intersect the cutting structure 56. According to one embodiment, the first slit SL1 can be formed perpendicular to the cutting structure 56. Because the cutting structure 56 extends in the first direction I, the flow path of the chemical substance can be unrestricted, or less restricted. Therefore, the chemical substance can be sufficiently introduced between the cutting structures 56 and between the columnar structures P. As a result, the area where the first material layer 51 remains unetched can be reduced.

[0078] Figure 10 is a diagram illustrating a memory system 1000 according to one embodiment of the present disclosure.

[0079] Referring to FIG10, the memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 configured to perform communication between the memory device 1200 and the host 2000.

[0080] The host 2000 can be a device or system configured to store data in or retrieve data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, and erase requests for erase operations. The host 2000 can communicate with the memory system 1000 using at least one interface protocol selected from, for example, Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Form Factor Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0081] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device, or cellular phone. However, the embodiments of the disclosed technology are not limited thereto.

[0082] Controller 1100 can control the overall operation of memory system 1000. Controller 1100 can control memory device 1200 in response to requests from host 2000. Controller 1100 can control memory device 1200 to perform programming, reading, and erasing operations upon request from host 2000. Alternatively, controller 1100 can perform background operations to improve the performance of memory system 1000 without a request from host 2000.

[0083] To control the operation of memory device 1200, controller 1100 can transmit control signals and data signals to memory device 1200. Control signals and data signals can be transmitted to memory device 1200 via different input / output lines. Data signals can include commands, addresses, or data. Control signals can be used to distinguish the time periods of input data signals.

[0084] The memory device 1200 can perform programming, reading, and erasing operations in response to control by the controller 1100. The memory device 1200 may include volatile memory that loses data when power is interrupted, or non-volatile memory that retains data when no power is supplied. The memory device 1200 may be a semiconductor device having the structure described above with reference to Figures 1A to 1D, 2A to 2C, 3A to 3C, and 4A to 4D. The memory device 1200 may be a semiconductor device manufactured by the method described above with reference to Figures 5A and 5B, 6A and 6B, 7A to 7C, and 8A to 8C. According to one embodiment, the semiconductor device may include a gate structure comprising conductive and insulating layers stacked alternately on top of each other, a channel structure extending through the gate structure and arranged in a first direction, a cut structure extending in the first direction and successively passing through the channel structure, and a first slit structure extending through the gate structure and extending in a second direction intersecting the first direction.

[0085] Figure 11 is a diagram illustrating a memory system 30000 according to one embodiment of the present disclosure.

[0086] Referring to Figure 11, the memory system 30000 can be integrated into a cellular phone, smartphone, tablet computer, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 for controlling the operation of the memory device 2200.

[0087] The controller 2100 can control data access operations of the memory device 2200 (e.g., programming, erasing, or reading operations of the memory device 2200) in response to the control of the processor 3100.

[0088] It can respond to the control of the controller 2100 and output the data programmed into the memory device 2200 via the display 3200.

[0089] The radio transceiver 3300 can exchange radio signals via an antenna ANT. For example, the radio transceiver 3300 can convert radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the controller 2100 or the display 3200. The controller 2100 can transmit the signals processed by the processor 3100 to the memory device 2200. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the radio signals to external devices via the antenna ANT. Control signals for controlling the operation of the host or data to be processed by the processor 3100 can be input via an input device 3400, and the input device 3400 may include a pointing device such as a touchpad and computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0090] According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 3100 or as a chip separate from the processor 3100.

[0091] Figure 12 is a diagram illustrating a memory system 40000 according to one embodiment of the present disclosure.

[0092] Referring to Figure 12, the memory system 40000 can be integrated into a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, or MP4 player.

[0093] The memory system 40000 may include a memory device 2200 and a controller 2100 for controlling the data processing operations of the memory device 2200.

[0094] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input via the input device 4200. Examples of the input device 4200 may include a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0095] The processor 4100 can control the overall operation of the memory system 40000 and the control operation of the controller 2100. According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a chip separate from the processor 4100.

[0096] Figure 13 is a block diagram illustrating a memory system 50000 according to one embodiment of the present disclosure.

[0097] Referring to Figure 13, the memory system 50000 can be integrated into an image processor, such as a digital camera, a cellular phone with a digital camera, a smartphone with a digital camera, or a desktop PC with a digital camera.

[0098] The memory system 50000 may include a memory device 2200 and a controller 2100 that controls data processing operations (e.g., programming operations, erasure operations, or read operations) of the memory device 2200.

[0099] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be transmitted to the processor 5100 or the controller 2100. In response to the control of the processor 5100, the converted digital signals can be output via the display 5300 or stored in the memory device 2200 via the controller 2100. In addition, in response to the control of the processor 5100 or the controller 2100, the data stored in the memory device 2200 can be output via the display 5300.

[0100] According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be formed as part of the processor 5100 or as a chip separate from the processor 5100.

[0101] Figure 14 is a diagram illustrating a memory system 70000 according to one embodiment of the present disclosure.

[0102] 14, the memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 2200 , a controller 2100 , and a card interface 7100 .

[0103] The controller 2100 may control the exchange of data between the memory device 2200 and the card interface 7100 . According to one embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0104] The card interface 7100 may interface connect to the data exchange between host 60000 and controller 2100 in accordance with the protocol of host 60000 . According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Card interface 7100 may refer to a hardware capable of supporting a protocol used by a host 60000, a software installed in the hardware, or a signal transmission method.

[0105] When the memory system 70000 is connected to the host interface 6200 of the host 60000, such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box, the host interface 6200 may respond to the control of the microprocessor 6100 for communication with the memory device 22 through the card interface 7100 and the controller 2100 .

[0106] The integration density of semiconductor devices can be improved by resorting to three-dimensional stacked memory units. In addition, semiconductor devices with stable structures and improved reliability can be provided.

[0107] 10: Base 11: Conductive layer 12: Insulating layer 13A: First channel layer / channel layer 13B: Second channel layer / channel layer 14A: First conductive pad 14B: Second conductive pad 15A: First insulating core 15B: Second insulating core 23A: First channel layer 23B: Second channel layer 24A: First conductive pad 24B: Second conductive pad 25A: First insulating core 25B: Second insulating core 50: Base 51: First material layer 52: Second material layer 53: Channel Layer 53A: First Channel Layer 53B: Second Channel Layer 54: Conductive pad 54A: First conductive pad 54B: Second conductive pad 55: Insulating core 55A: First insulating core 55B: Second Insulating Core 56, 56': Cutting structure 57: Third material layer 58: First slit structure 59: Second slit structure 1000: Memory System 1100: Controller 1200: Memory device 2000: Mainframe 2100: Controller 2200: Memory Device 3100: Processor 3200: Monitor 3300: Radio transceiver 3400: Input device 4100: Processor 4200: Input device 4300: Monitor 5100: Processor 5200: Image Sensor 5300: Monitor 6100: Microprocessor 6200: Host Interface 7100: Card Interface 30000: Memory System 40000: Memory System 50000: Memory System 60000: Host 70000: Memory System CS: Cutting Structure CT1: First contact plug CT2: Second contact plug GST: Gate structure IL1, IL11, IL12, IL13: First interconnect IL2, IL21, IL22, IL23: Second interconnects P: Columnar structure P1, P11, P12, P13, P14: First columnar structure P1A, P11A, P12A, P13A, P14A: First sub-column structure P1B, P11B, P12B, P13B, P14B: Second sub-columnar structures P2, P21, P22, P23, P24: Second columnar structure P2A, P21A, P22A, P23A, P24A: First sub-column structure P2B, P21B, P22B, P23B, P24B: Second sub-column structures SLS1: First slit structure SLS2: Second Slit Structure

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising conductive layers and insulating layers alternately stacked on top of each other in a first direction; A channel structure that passes through the gate structure in a first direction and is arranged in a second direction intersecting the first direction; a cutting structure that extends in both the first and second directions and passes through the channel structure in the second direction. And a first slit structure that passes through the gate structure and extends upward on a third party intersecting the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein, Each of the channel structures is separated into a first channel structure and a second channel structure by the cutting structure.

3. The semiconductor device according to claim 2, further comprising: At least one first line, the at least one first line extending in the second direction and coupled to the first channel structure; And at least one second bit line, which extends in the second direction and is coupled to the second channel structure.

4. The semiconductor device according to claim 1, further comprising a second slit structure penetrating the gate structure at a shallower depth than both the first slit structure and the cut structure, the second slit structure extending upward in the third party.

5. The semiconductor device according to claim 4, wherein, The cutting structure is in contact with the second slit structure.

6. The semiconductor device according to claim 1, wherein, The cutting structure includes insulating material.

7. A semiconductor device comprising: A gate structure comprising conductive layers and insulating layers alternately stacked on top of each other in a first direction; A columnar structure passing through the gate structure in the first direction; a cutting structure passing through the columnar structure in the first direction and in a second direction intersecting the first direction, separating each of the columnar structures into a first columnar structure and a second columnar structure; a first slit structure passing through the gate structure in the first direction and extending upward in a third direction intersecting the first and second directions; a first interconnect extending in the second direction and coupled to the first columnar structure; And a second interconnect line extending in the second direction, the second interconnect line being coupled to the second columnar structure.

8. The semiconductor device according to claim 7, further comprising: The first contact plug is coupled to the first columnar structure, and the first contact plug couples the first columnar structure to the first interconnect. And a second contact plug, the second contact plug being coupled to the second columnar structure, the second contact plug coupling the second columnar structure to the second interconnect.

9. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a stacked structure; A channel structure is formed that passes through the stacked structure in a first direction and is arranged in a second direction that intersects the first direction; A cutting structure is formed that passes through the channel structure in the second direction and extends in both the first and second directions; And forming a first slit structure that passes through the stacked structure and extends upward on a third party that intersects the first direction and the second direction.

10. The method according to claim 9, wherein, The step of forming the cut structure includes the following steps: etching the channel structure so that each of the channel structures is separated into a first channel structure and a second channel structure.

11. The method according to request item 10, further comprising the following steps: Form at least one first line that extends in the second direction and is coupled to the first channel structure; And forming at least one second bit line that extends in the second direction and is coupled to the second channel structure.

12. The method according to claim 9, wherein, The steps of forming the cut structure include the following: forming a groove that intersects with at least two channel structures; And to form the cutting structure to include insulating material in the trench.

13. The method according to claim 9, wherein, The step of forming the first slit structure includes the following steps: forming a first slit through the stacked structure comprising alternating stacked first and second material layers, the first slit extending upward in the third; replacing the first material layer with a third material layer via the first slit; and forming the first slit structure in the first slit.

14. The method according to claim 9, further comprising the step of: forming a second slit structure, the second slit structure penetrating the stacked structure at a shallower depth than the first slit structure and extending upward on the third party.

15. The method according to claim 14, wherein, The steps of forming the second slit structure include: forming the second slit by etching the stacked structure and the cut structure; and forming the second slit structure in the second slit.

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