Semiconductor architecture having thermal budget enhanced buried power rail and method of manufacturing the same

Abstract

This invention provides a semiconductor architecture and a method for manufacturing the same. The semiconductor architecture includes: a wafer; a semiconductor device provided on the wafer, the semiconductor device including an epitaxial layer, epitaxial contacts provided on the epitaxial layer, a first via provided on the epitaxial contacts, and a metal line provided on the first via, the metal line being configured to route signals; an oxide layer provided on a first surface of the wafer and adjacent to the semiconductor device; and a buried power rail (BPR) configured to deliver power, at least a portion of the BPR being contained within the wafer, wherein a portion of the BPR contacts the oxide layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a buried power rail (BPR) included in a semiconductor architecture and a method of manufacturing the same, and more particularly, to a thermally enhanced BPR included in a semiconductor architecture and a method of manufacturing the same.

Prior Art

[0002] Compared to a power rail formed at the same horizontal height as a routing metal layer, a semiconductor architecture including a buried power rail (BPR) can reduce resistance in the semiconductor architecture and increase routing flexibility. The size of a semiconductor architecture including a BPR can be reduced compared to a semiconductor architecture including a power rail formed at the horizontal height of a routing metal layer.

[0003] Before providing front-end-of-line (FEOL) layers of a semiconductor architecture including active devices such as an epitaxial layer and gates, a BPR is typically formed in the semiconductor architecture. When forming FEOL layers in the semiconductor architecture, a relatively high temperature greater than about 1000 °C is required. Since the BPR includes a metal material such as cobalt, tungsten, or ruthenium, the BPR can degrade by metal migration or diffusion that occurs when forming the FEOL layer at a high temperature. This metal migration or diffusion of the BPR can cause tool contamination and increase leakage, which can lead to device degradation or failure.

[0004] The information disclosed in this background section has been known to the inventors before implementing the embodiments of the present application or is technical information obtained during the implementation of the embodiments. Therefore, it may contain information that does not form prior art already known to the public.

Summary of the Invention

[0005] One or more example embodiments provide a buried power rail included in a semiconductor architecture and a method of manufacturing the same.

[0006] One or more example embodiments also provide a thermally enhanced buried power rail of a semiconductor architecture and a method of manufacturing the same.

[0007] According to an aspect of an example embodiment, a semiconductor architecture is provided, the semiconductor architecture comprising: a wafer; a semiconductor device provided on the wafer, the semiconductor device comprising an epitaxial layer, an epitaxial contact provided on the epitaxial layer, a first via provided on the epitaxial contact, and a metal wire provided on the first via, and the metal wire being configured to route signals; an oxide layer provided on a first surface of the wafer and adjacent to the semiconductor device; and a buried power rail (BPR) configured to deliver power, at least a portion of the BPR being included inside the wafer, wherein a portion of the BPR contacts the oxide layer.

[0008] According to another aspect of an example embodiment, a method of manufacturing a semiconductor architecture is provided, the method comprising: providing a wafer; patterning fins on the wafer; providing a front-end-of-line (FEOL) layer on the wafer; etching trenches in the wafer; filling the trenches with a metal material to form a buried power rail (BPR); providing a middle-of-line (MOL) layer on the wafer; and providing a back-end-of-line (BEOL) layer on the wafer.

[0009] According to another example embodiment, a method of manufacturing a semiconductor architecture is provided, the method comprising: providing a wafer; patterning fins on the wafer; providing a front-end-of-line (FEOL) layer on the wafer and on the fins; providing trenches in the wafer in a vertical direction to a level lower than the fins; filling the trenches with a metal material to form a buried power rail (BPR) configured to deliver power; providing a middle-of-line (MOL) layer on the wafer connected to the BPR; and providing a back-end-of-line (BEOL) layer on the wafer, the BEOL layer being configured to route signals.

Embodiments

[0011] The example embodiments described herein are examples, and thus, the present disclosure is not limited thereto and may be implemented in various other forms. Each of the example embodiments provided in the following description does not exclude being associated with one or more features of another example or another example embodiment provided herein or not provided herein but consistent with the present disclosure. For example, even if a material described in a particular example or example embodiment is not described in its different examples or example embodiments, unless otherwise mentioned in its description, the material can still be understood to be related to or combined with different examples or embodiments.

[0012] In addition, it should be understood that all descriptions of principles, aspects, examples, and example embodiments are intended to cover their structural and functional equivalents. In addition, such equivalents should be understood to include not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same function regardless of their structure.

[0013] It should be understood that when an element, component, layer, pattern, structure, region, etc. (collectively referred to as "element") of a semiconductor device is referred to as "on", "above", "over", "below", "beneath", "underneath", "connected to", or "coupled to" another element of the semiconductor device, it can be directly on, above, over, below, beneath, underneath, connected to, or coupled to the other element, or there may be intervening elements. In contrast, when an element of a semiconductor device is referred to as "directly on", "directly above", "directly over", "directly below", "directly beneath", "directly underneath", "directly connected to", or "directly coupled to" another element of the semiconductor device, there are no intervening elements. The same reference numerals throughout this disclosure refer to the same elements.

[0014] Spatial relative terms, such as "on", "above", "over", "upper", "below", "beneath", "underneath", "lower", "top", and "bottom" and the like, may be used herein for ease of description to describe the relationship of one element to another as shown in the figures. It should be understood that such spatial relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is flipped over, an element described as "below" or "beneath" other elements will then be oriented "above" the other elements. Thus, the term "below" can cover both an orientation above and below. The semiconductor device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. As used herein, when preceding a list of elements, expressions such as "at least one of..." modify the entire list of elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. As used herein, when the term "same" is used to compare the sizes of two or more than two elements, the term may cover "substantially the same" sizes. It should be understood that although terms such as "first", "second", "third", "fourth", etc. may be used herein to describe various elements, such elements should not be limited by such terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. It should also be understood that even if a step or operation of a manufacturing device or structure is described later than another step or operation, unless the other step or operation is described as being performed after the step or operation, the step or operation may also be performed later than the other step or operation. The example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the example embodiments should not be construed as being limited to the particular shapes of regions shown herein, but should include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in a certain implantation in the region between the buried region and the surface into which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the device regions and are not intended to limit the scope of the present disclosure. Additionally, in the drawings, for clarity, the sizes and relative sizes of layers and regions may be enlarged. For simplicity, the general elements of semiconductor devices may or may not be described in detail herein. FIG. 1 shows a semiconductor architecture including a BPR according to the related art.

[0021] According to related technologies, the semiconductor architecture 1000 includes a wafer 1100 and fins 150 patterned on the wafer 1100. The wafer 1100 and the fins 150 include, for example, silicon (Si). The fins 150 can be individual channel structures of fin field-effect transistors (FinFETs). The semiconductor architecture 1000 further includes an oxide layer 1101 formed on the wafer 1100 and semiconductor devices formed on the wafer 1100. The semiconductor devices can be integrated circuits configured to, for example, route signals, deliver power, and / or operate as part of logic gates. For example, the semiconductor devices include an epitaxial layer 160 grown on the fins 150. The epitaxial layer 160 can form the active regions of the transistors, i.e., the source / drain regions, and can include, for example, Si. The epitaxial layer 160 is included in a front-end-of-line (FEOL) layer formed on the wafer 1100.

[0022] In a middle-of-line (MOL) layer of the semiconductor device, an epitaxial contact 190 is formed to contact the epitaxial layer 160 and extends in a horizontal direction parallel to a first surface of the wafer 1100. A vertical contact 130 is formed on a surface of the epitaxial contact 190 and extends in the oxide layer toward the first surface of the wafer 1100. In a back-end-of-line (BEOL) layer of the semiconductor device, a metal layer 180 configured to route signals is formed, and vias 170 are formed between the metal layers 180 to interconnect the metal layers 180. An additional via 170 is formed between the epitaxial contact 190 and the metal layer 180 to connect the signal wiring layer to the epitaxial layer 160.

[0023] A buried power rail (BPR) 120 is formed to contact the vertical contact 130 and penetrates in a vertical direction into the wafer 1100 to a horizontal height below the fins 150. The BPR is configured to deliver power.

[0024] The epitaxial layer 160 includes a power-tap epitaxial layer and a non-power-tap epitaxial layer. The metal layer 180 is connected to the non-power-tap epitaxial layer of the epitaxial layer 160 for internal signal routing. The BPR 120 is connected to the power-tap epitaxial layer of the epitaxial layer 160. The BPR 120 is configured to deliver power to the epitaxial layer 160, i.e., the active region.

[0025] According to related technologies, the semiconductor architecture 1000 can also include a portion of a BPR capping layer 110 formed on an exposed surface of the BPR 120. The BPR capping layer 110 includes a dielectric material, such as silicon nitride (SiN).

[0026] According to related art, the BPR 120 can be thermally degraded by metal migration or diffusion, and the resistance of the BPR 120 can become relatively high, which may lead to the degradation of the semiconductor device or a failure in the semiconductor device.

[0027] FIGS. 2A to 2H illustrate a method of manufacturing the semiconductor architecture of FIG. 1 according to related art.

[0028] As shown in FIGS. 2A and 2B, the method includes providing a wafer 1100. The wafer 1100 includes, for example, Si.

[0029] The method includes patterning fins 150 on the wafer 1100 and forming an oxide layer 1101 on the wafer 1100. The fins 150 include, for example, Si and form respective channel structures of a FinFET.

[0030] As shown in FIG. 2C, trenches 121 are formed in a vertical direction in the oxide layer 1101 and the wafer 1100 to a horizontal height below the fins 150. Referring to FIG. 2D, the trenches 121 are filled with a metal material 120', such as cobalt (Co), tungsten (W), and ruthenium (Ru).

[0031] As shown in FIGS. 2E to 2G, the metal material 120' is etched to a horizontal height of a first surface of the wafer 1100 to form the BPR 120. A BPR capping layer 110 is formed on an exposed surface of the BPR 120 to insulate the BPR 120. The BPR capping layer 110 includes, for example, silicon nitride (SiN). The space formed by etching the BPR 120 above the BPR capping layer 110 is filled with an oxide material 100'. The oxide layer 1101 and the oxide material 100' can be integrally formed.

[0032] As shown in FIG. 2H, a semiconductor device is formed on the wafer 1100. Forming the semiconductor device includes forming a FEOL layer including an epitaxial layer 160 formed on the fins 150. An MOL layer is formed on the FEOL layer. The MOL layer includes an epitaxial contact 190 that contacts the epitaxial layer 160 and extends in a horizontal direction, and a vertical contact 130 that contacts the epitaxial contact 190 and the BPR 120. A BEOL layer is formed on the MOL layer. The BEOL layer includes a metal layer 180 and vias 170 formed between the metal layers 180 to interconnect the metal layers 180. Another via 170 can also be formed between the epitaxial contact 190 and the metal layer 180 to connect the epitaxial layer 160 to the metal layer 180. The oxide material integrally formed with the oxide layer 10 can be vertically adjacent to the FEOL layer, the MOL layer, and the BEOL layer to the horizontal height of the BEOL layer.

[0033] According to the related art, the BPR 120 is formed before the FEOL layer is formed. Since the formation of the FEOL layer requires a high temperature greater than about 1000 °C, the BPR 120 can be thermally degraded during the formation of the FEOL layer. For example, metal migration or diffusion can occur in the BPR 120. Metal migration or diffusion can cause an increase in the resistance of the BPR 120, which may reduce the performance of the semiconductor device or cause a failure in the semiconductor device.

[0034] FIG. 3 shows a perspective view of a semiconductor architecture including a BPR according to an example embodiment.

[0035] As shown in FIG. 3, the semiconductor architecture 1 includes a wafer 100 and a semiconductor device 200 formed on a first surface of the wafer 100. However, the embodiment is not limited thereto. For example, the semiconductor architecture 1 can be a back side power distribution network (BSPDN) semiconductor architecture, which includes a wafer, a first semiconductor device configured to route signals and formed on a first surface of the wafer, and a second semiconductor device configured to deliver power and formed on a second surface of the wafer opposite to the first semiconductor device.

[0036] Referring to FIG. 3, the wafer 100 includes, for example, a Si substrate, a glass substrate, a sapphire substrate, etc. However, the embodiment is not limited thereto. As shown in FIG. 3, the wafer 100 can be a circular panel, but the shape of the wafer 100 is not limited thereto. For example, the wafer 100 can be a quadrilateral panel. The wafer 100 can include a single layer or multiple layers.

[0037] FIG. 4 shows a cross-sectional view taken along line I-I' of FIG. 3 according to an example embodiment.

[0038] As shown in FIG. 4, the semiconductor architecture 1a includes a wafer 100, fins 50 patterned on the wafer 100, and an oxide layer 10 deposited on the wafer 100. The wafer 100 and the fins 50 include, for example, Si. The fins 50 can be individual channel structures of transistors such as FinFETs, but are not limited thereto. It should be understood that the transistors described below can be one or a combination of FinFETs, nanowire transistors, nanosheet transistors, etc.

[0039] The semiconductor structure 1a also includes semiconductor devices formed on the wafer 100. The semiconductor devices can be integrated circuits configured to route signals and deliver power. The semiconductor devices include a FEOL layer, and the FEOL layer includes an epitaxial layer 60 grown on the fin 50. The epitaxial layer 60 can form the active region of the transistor, that is, the source / drain region, and can include, for example, Si. The semiconductor devices also include a MOL layer, and the MOL layer includes an epitaxial contact 90 that contacts the epitaxial layer 60 and extends in a horizontal direction parallel to the first surface of the wafer 100. The MOL layer can also include a vertical contact 30 that contacts the epitaxial contact 90 and penetrates the oxide layer 10 toward the first surface of the wafer 100. The semiconductor devices also include a BEOL layer, and the BEOL layer includes a metal layer 80 configured to route signals and vias 70 formed between the metal layers 80 to interconnect the metal layers 80. The vias 70 are formed between the metal layer 80 and the epitaxial contact 90 to connect the metal layer 80 to the epitaxial layer 60.

[0040] The BPR 20a is formed to contact the surface of the vertical contact 30 and penetrate into the wafer 100 to a horizontal height below the fin 50. The BPR 20a is included inside the wafer 100 and is configured to deliver power. The width of the BPR 20a can be greater than the width of the vertical contact 30, but the embodiment is not limited thereto.

[0041] The semiconductor structure 1a according to an example embodiment does not include any part of the BPR top layer shown in FIGS. 1 and 2H, and the manufacturing process can be more simplified.

[0042] Compared with the BPR 120 included in the semiconductor structure 1000 according to the related art, the BPR 20a included in the semiconductor structure 1a according to an example embodiment may not be thermally degraded or may reduce thermal degradation. Therefore, the degradation of the semiconductor device can be reduced, or the failure of the semiconductor device can be prevented.

[0043] FIGS. 5A to 5H illustrate a method of manufacturing the semiconductor structure in FIG. 4 according to an example embodiment.

[0044] As shown in FIG. 5A, the method includes providing a wafer 100 and patterning fins 50 on the wafer 100. The wafer 100 and the fins 50 include, for example, Si. Each of the fins 50 can be used as a current channel of a transistor. Although each of the fins 50 is shown as the fin structure of a FinFET in FIGS. 5A to 5H, the fins 50 can be respectively multiple fin structures, such as a combination of nanowires of a nanowire transistor or nanosheets of a nanosheet transistor.

[0045] As shown in FIG. 5B, an oxide layer 10 formed of, for example, SiO can be deposited on the wafer 100.

[0046] As shown in FIG. 5C, the FEOL layer is formed on the wafer 100. For example, the epitaxial layer 60 is grown on the fin 50, and the gate structure 11 is formed on the fin 50 and the wafer 100 adjacent to the oxide layer 10. For example, FIG. 5C shows a cross-sectional view depicting the gate structure 11 formed on the fin 50. Although not shown in FIG. 5C, the oxide layer 10 shown in FIG. 5B can be provided in front of and behind the gate structure 11 in FIG. 5C. The epitaxial layer 60 can form the active region of the transistor, i.e., the source / drain region, and can include, for example, Si.

[0047] As shown in FIG. 5D, the trench 21a is formed in the oxide layer 10 and the wafer 100. The trench 21a is formed in the wafer 100 to a horizontal height below the fin 50 in the vertical direction. The trench 21a is formed by, for example, various types of etching processes, but is not limited thereto.

[0048] As shown in FIGS. 5E and 5F, a metal material 20a', such as Co, W, Ru, etc., can fill the trench 21a. A part of the metal material 20a' is etched to the horizontal height of the first surface of the wafer 100 to form the BPR 20a and the trench 21a'. As shown in FIG. 5G, an oxide material 10' fills the trench 21a' above the BPR 20a. The oxide material 10' can be the same material as that forming the oxide layer 10 and can be formed integrally with the oxide layer 10.

[0049] As shown in FIG. 5H, the MOL layer including the epitaxial contact 90 that includes the epitaxial layer 60 and extends in the horizontal direction parallel to the first surface of the wafer 100 is formed on the FEOL layer. The formation of the MOL layer also includes forming the vertical contact 30 that includes the epitaxial contact 90 and penetrates the oxide layer 10 toward the first surface of the wafer 100 to contact the exposed surface of the BPR 20a. The BEOL layer including the metal layer 80 and the via 70 is formed on the MOL layer. The via 70 interconnects the metal layer 80 and connects the metal layer 80 to the epitaxial contact 90. The oxide material formed integrally with the oxide layer 10 can be adjacent to the FEOL layer, the MOL layer, and the BEOL layer in the vertical direction up to the horizontal height of the BEOL layer.

[0050] According to an example embodiment, the BPR 20a included in the semiconductor architecture 1a is formed after the formation of the FEOL layer (which requires high temperature). Therefore, the thermal degradation of the BPR 20a can be reduced or prevented, thereby preventing or reducing the degradation of the semiconductor device or preventing the failure of the semiconductor device.

[0051] Since the method of manufacturing the semiconductor architecture 1a according to the exemplary embodiments does not include the step of forming the BPR capping layer shown in FIGS. 1 and 2H, the manufacturing process of the semiconductor architecture 1a can be more simplified.

[0052] FIG. 6 shows a semiconductor architecture including a BPR according to another exemplary embodiment.

[0053] According to an exemplary embodiment, the semiconductor architecture 1c includes a wafer 100, fins 50 patterned on the wafer 100, and an oxide layer 10 deposited on the wafer 100. The wafer 100 and the fins 50 may include, for example, Si. The fins 50 may be individual channel structures of transistors such as FinFETs, but are not limited thereto.

[0054] The semiconductor architecture 1c further includes semiconductor devices formed on the wafer 100. The semiconductor devices may be integrated circuits configured to route signals and deliver power. The semiconductor devices include a FEOL layer that includes an epitaxial layer 60 grown on the fins 50. The epitaxial layer 60 may form the active regions of the transistors, i.e., the source / drain regions, and may include, for example, Si. The semiconductor devices also include a MOL layer that includes epitaxial contacts 90 that contact the epitaxial layer 60 and extend in a horizontal direction parallel to a first surface of the wafer 100. The semiconductor devices also include a BEOL layer that includes metal layers 80 configured to route signals and vias 70 formed between the metal layers 80 to interconnect the metal layers 80. The vias 70 are also formed between the metal layers 80 and the epitaxial contacts 90 to connect the epitaxial layer 60 to the metal layers 80 configured to route signals.

[0055] The BPR 20c is formed to contact the epitaxial contacts 90 and penetrates vertically into the wafer 100 to a horizontal height below the fins 50. The BPR 20c is included inside the wafer 100 and is configured to deliver power. The width of the BPR 20c may be greater than the width of the vertical contacts 30, but the embodiments are not limited thereto.

[0056] Compared with the BPR 120 included in the semiconductor architecture 1000 according to the related art, the BPR 20c included in the semiconductor architecture 1c according to the exemplary embodiments may not undergo thermal degradation or may reduce thermal degradation. Therefore, the degradation of the semiconductor devices may be reduced, or the failure of the semiconductor devices may be prevented.

[0057] The semiconductor architecture 1c according to the exemplary embodiment does not include any part of the BPR capping layer shown in FIGS. 1 and 2H, and the manufacturing process can be more simplified. In addition, since the length of the BPR 20c in the vertical direction can be longer than that of the BPR 20a shown in FIG. 4, the resistance of the BPR 20c can be lower than that of the BPR 20a, thereby further improving the device performance.

[0058] FIGS. 7A to 7F illustrate a method of manufacturing the semiconductor architecture in FIG. 6 according to the exemplary embodiment.

[0059] As shown in FIG. 7A, the method includes providing a wafer 100 and patterning fins 50 on the wafer 100. The wafer 100 and the fins 50 may include, for example, Si. Each of the fins 50 can be used as a current channel of a transistor. Although each of the fins 50 is shown as a fin structure of a FinFET in FIGS. 7A to 7F, the fins 50 can be respectively a plurality of fin structures, such as a combination of nanowires of a nanowire transistor or nanosheets of a nanosheet transistor.

[0060] As shown in FIG. 7B, an oxide layer 10 is deposited on the wafer 100. The wafer 100 and the fins 50 may include, for example, Si.

[0061] As shown in FIG. 7C, a FEOL layer is formed on the wafer 100. For example, an epitaxial layer 60 may be grown on the fins 50, and a gate structure 11 may be formed on the wafer 100 adjacent to the oxide layer 10. The epitaxial layer 60 may form the active region of the transistor, i.e., the source / drain region, and may include, for example, Si.

[0062] As shown in FIG. 7D, trenches 21c are formed in the oxide layer 10 and the wafer 100. The trenches 21c may be formed in the wafer 100 in the vertical direction to a horizontal height below the fins 50. The trenches 21c may be formed by, for example, dry etching or CMP. However, the embodiments are not limited thereto.

[0063] As shown in FIG. 7E, a metal material such as Co, W, Ru, etc. is filled in the trenches 21c to form the BPR 20c.

[0064] As shown in FIG. 7F, a MOL layer may be formed on the FEOL layer. The MOL layer includes an epitaxial contact 90 formed to contact the epitaxial layer 60 and the BPR 20c. The BPR 20c extends to the horizontal height of the epitaxial contact 90 and directly contacts the epitaxial contact 90.

[0065] Form a BEOL layer on the MOL layer, which includes a metal layer 80, vias 70 formed between the metal layers 80 to interconnect the metal layers 80, and vias 70 formed between the metal layer 80 and the epitaxial contact 90. The oxidation material integrally formed with the oxide layer 10 can be vertically adjacent to the FEOL layer, the MOL layer, and up to the horizontal height of the BEOL layer.

[0066] According to an exemplary embodiment, the BPR 20a included in the semiconductor architecture 1c is formed after forming the FEOL layer (which requires high temperature). Therefore, the thermal degradation of the BPR 20a can be reduced or prevented, thereby reducing the degradation of the semiconductor device or preventing the failure of the semiconductor device.

[0067] Since the method of manufacturing the semiconductor architecture 1c according to the exemplary embodiment does not include the step of forming the BPR capping layer shown in FIGS. 1 and 2H, the manufacturing process of the semiconductor architecture 1a can be more simplified. In addition, since the length of the BPR 20c in the vertical direction can be longer than that of the BPR 20a shown in FIG. 4, the resistance of the BPR 20c can be lower than that of the BPR 20a, thereby further improving the device performance.

[0068] Since the BPR 20 is in direct contact with the epitaxial contact 90, and the method of manufacturing the semiconductor architecture 1c according to the exemplary embodiment does not include forming a vertical contact between the epitaxial contact 90 and the BPR 20c, the manufacturing method can be more simplified, and the resistance of the semiconductor architecture 1c can be reduced.

[0069] FIG. 8 shows a flowchart of a method of manufacturing a semiconductor architecture according to an exemplary embodiment.

[0070] The method includes providing a wafer and patterning fins on the wafer (S110). The wafer and the fins may include, for example, Si. The fins can be transistor channel structures such as FinFETs. Deposit an oxide layer on the wafer (S120).

[0071] An FEOL layer can be formed on the wafer (S130). For example, an epitaxial layer can be grown on the fins, and a gate structure can be formed on the wafer adjacent to the oxide layer.

[0072] Channels can be formed in the wafer and the oxide layer (S140). The channels can be formed in the wafer in the vertical direction to the horizontal height below the fins. The channels can be formed by, for example, dry etching or CMP. However, the embodiments are not limited thereto.

[0073] Fill the trench with a metal material (S150). The metal material may include, for example, Co, W, Ru, etc. Etch a part of the metal material to the level of the first surface of the wafer to form a BPR (S160).

[0074] Form a MOL layer including vertical contacts on the FEOL layer such that the vertical contacts are in contact with the BPR (S170). The formation of the MOL layer also includes forming epitaxial contacts that contact the vertical contacts and the epitaxial layer. Form a BEOL layer on the MOL layer (S180). The BEOL layer includes metal layers, vias formed between the metal layers to interconnect the metal layers, and vias formed between the metal layer and the epitaxial contacts.

[0075] FIG. 9 shows a flowchart of a method for manufacturing a semiconductor architecture according to an exemplary embodiment.

[0076] The method includes providing a wafer and patterning fins on the wafer (S310). The wafer and the fins may include, for example, Si. Deposit an oxide layer on the wafer (S320).

[0077] Form a FEOL layer on the wafer (S330). For example, an epitaxial layer may grow on the fins, and a gate structure is formed on the wafer adjacent to the oxide layer.

[0078] Form trenches in the oxide layer and the wafer (S340). The trenches may be formed in the wafer in a vertical direction to a level below the fins. The trenches may be formed by, for example, dry etching or CMP. However, the embodiments are not limited thereto.

[0079] Fill the trenches with a metal material to form a BPR (S350). The metal material may include, for example, Co, W, Ru, etc.

[0080] Form a MOL layer on the FEOL layer such that the BPR is in contact with the epitaxial contacts (S360). The epitaxial contacts are formed to contact the epitaxial layer and extend in a horizontal direction.

[0081] Form a BEOL layer on the MOL layer (S370). The BEOL layer includes metal layers, vias formed between the metal layers to interconnect the metal layers, and vias formed between the metal layer and the epitaxial contacts.

[0082] FIG. 10 shows a semiconductor package that may incorporate a semiconductor architecture including a BPR according to an exemplary embodiment. [

[0083] ]Referring to FIG. 10, a semiconductor package 2000 according to an exemplary embodiment may include a processor 2200 and a semiconductor device 2300 mounted on a substrate 2100. The processor 2200 and / or the semiconductor device 2300 may include one or more of the semiconductor architectures described in the above exemplary embodiments. [

[0084] ]FIG. 11 shows a schematic block diagram of an electronic system according to an exemplary embodiment. [

[0085] ]Referring to FIG. 11, an electronic system 3000 according to an embodiment may include a microprocessor 3100, a memory 3200, and a user interface 3300 that perform data communication using a bus 3400. The microprocessor 3100 may include a central processing unit (CPU) or an application processor (AP). The electronic system 3000 may further include a random access memory (RAM) 3500 that communicates directly with the microprocessor 3100. The microprocessor 3100 and / or the RAM 3500 may be implemented in a single module or package. The user interface 3300 can be used to input data into the electronic system 3000 or output data from the electronic system 3000. For example, the user interface 3300 may include, without limitation, a keyboard, a touchpad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, an illumination system, or various other input / output devices. The memory 3200 may store the operation code of the microprocessor 3100, the data processed by the microprocessor 3100, or the data received from an external device. The memory 3200 may include a memory controller, a hard disk, or a solid state drive (SSD). [

[0086] ]At least the microprocessor 3100, the memory 3200, and / or the RAM 3500 in the electronic system 3000 may include the semiconductor architecture as described in the above exemplary embodiments.

[0087] According to an example embodiment, a BPR included in a semiconductor architecture is formed after forming a FEOL layer (which requires high temperature). Accordingly, thermal degradation of the BPR can be reduced or prevented, thereby preventing or reducing device degradation or device failure and improving device performance.

[0088] It should be understood that the example embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. Generally, the description of features or aspects within each example embodiment should be considered as available for other similar features or aspects in other embodiments.

[0089] Although example embodiments have been described with reference to the drawings, those of ordinary skill in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Brief Description of the Drawings

[0010] The above and / or other aspects, features, and advantages of the example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 shows a semiconductor architecture including a BPR according to a related embodiment. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H show a method of manufacturing the semiconductor architecture including the BPR in FIG. 1 according to a related embodiment. FIG. 3 shows a perspective view of a semiconductor architecture including a BPR according to an example embodiment. FIG. 4 shows a cross-sectional view taken along line I-I' of FIG. 3 according to an example embodiment. FIGS. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H show a method of manufacturing the semiconductor architecture in FIG. 4 according to an example embodiment. FIG. 6 shows a cross-sectional view taken along line I-I' of FIG. 3 according to another example embodiment. FIGS. 7A, 7B, 7C, 7D, 7E, and 7F show a method of manufacturing the semiconductor architecture in FIG. 6 according to an example embodiment. FIG. 8 shows a flowchart of a method of manufacturing a semiconductor architecture including a BPR according to an example embodiment. FIG. 9 shows a flowchart of a method of manufacturing a semiconductor architecture including a BPR according to another example embodiment. FIG. 10 shows a semiconductor package that can incorporate a semiconductor architecture including a BPR according to an example embodiment. FIG. 11 shows a schematic block diagram of an electronic system that can incorporate a semiconductor architecture including a BPR according to an example embodiment.

Claims

1. A semiconductor architecture, comprising: wafers; Fins are patterned on the wafer; A semiconductor device is provided on the wafer, the semiconductor device comprising: an epitaxial layer; an epitaxial contact provided on the epitaxial layer; a first via provided on the epitaxial contact; and a metal line provided on the first via, the metal line being configured to route signals; an oxide layer provided on a first surface of the wafer and adjacent to the semiconductor device; and a buried power rail (BPR) configured to deliver power, at least a portion of the buried power rail being located inside the wafer, wherein a portion of the buried power rail contacts the oxide layer, wherein a first end of the buried power rail extends vertically in the wafer to a horizontal height below the fins, and wherein a second end of the buried power rail opposite to the first end of the buried power rail extends to a horizontal height above the top of the epitaxial layer.

2. The semiconductor architecture as claimed in claim 1, wherein the second end of the embedded power rail extends to the horizontal height of the epitaxial contact.

3. The semiconductor architecture as described in claim 2, wherein a portion of the side surface of the embedded power rail directly contacts the epitaxial contact.

4. The semiconductor architecture as described in claim 1, wherein the fins are channel structures of field-effect transistors (FinFETs).

5. A method for manufacturing a semiconductor architecture, the method comprising: Provide wafers; The fins are patterned on the wafer; An oxide layer is provided on the wafer and adjacent to the fins; A front-end process (FEOL) layer is provided on the wafer and the fins; a trench is provided in the oxide layer and the wafer such that a first end of the trench is at a vertical height below the horizontal level of the wafer above the fins; the trench is filled with a metal material and the metal material filled in the trench is etched to the horizontal level of a first surface of the wafer to form a buried power rail (BPR) configured to deliver power; the space in the trench formed above the buried power rail is filled with an oxide material; a mid-end process (MOL) layer is provided on the wafer; and a back-end process (BEOL) layer is provided on the wafer, wherein providing the front-end process layer includes providing epitaxial layers on the fins respectively.

6. The method of manufacturing a semiconductor architecture as described in claim 5, wherein providing the mid-process layer comprises: Epitaxial contacts are provided on the epitaxial layer; And provides vertical contacts for contacting the epitaxial contacts and the embedded power rail.

7. The method of manufacturing a semiconductor architecture as described in claim 6, wherein providing the back-end process layer comprises: A first through-hole is provided on the epitaxial contact; A metal layer is provided on the first via, the metal layer being configured to route signals.

8. The method of manufacturing a semiconductor architecture as claimed in claim 5, wherein providing the trench includes providing a second end of the trench to a horizontal height of the epitaxial layer in the vertical direction.

9. A method for manufacturing a semiconductor architecture, the method comprising: Provide wafers; The fins are patterned on the wafer; An oxide layer is provided on the wafer and adjacent to the fins; An epitaxial layer is provided on the fin; A trench is provided in the oxide layer and the wafer, such that a first end of the trench is formed in the wafer at a horizontal height below the fin in the vertical direction; the trench is filled with a metallic material to a horizontal height above the top of the epitaxial layer to form a buried power rail (BPR) configured to deliver power; a mid-process (MOL) layer connected to the buried power rail is provided on the wafer; and a back-end process (BEOL) layer is provided on the wafer, the back-end process layer being configured to route signals.

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