Power gating switch tree structure and method for reduced wake-up time and power leakage

Abstract

One aspect relates to an apparatus comprising: first and second power rails; a first set of power switching units coupled to the first and second power rails, the first set of power switching units being cascaded from an output of a control circuit to an input of the control circuit; and a second set of power switching units coupled to the first and second power rails, the second set of power switching units being coupled to one of: a pair of units in the first set, a first output of the control circuit, and a first input of the control circuit. Another aspect relates to a method comprising: propagating a control signal via a first set of cascaded power switching units to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switching units coupled between a pair of units in the first set.

Description

[Technical Field]

[0001] Various aspects of this disclosure generally relate to power gate circuitry, and more specifically to power gate switch tree structures for reducing wake-up time and power leakage. [Previous Technology]

[0002] Integrated circuits (ICs) typically include multiple cores, such as central processing unit (CPU) cores, graphics processing unit (GPU) cores, modem cores, imaging (camera) cores, memory cores, etc. Power management integrated circuits (PMICs) can provide power to the IC (e.g., provide voltage and current); and more specifically, provide power to the IC's global power rails for further distribution of power. The IC may also include power gating circuitry for selectively coupling the global power rails to regional power rails coupled to the various cores. The power gating circuitry should be configured to selectively couple the global power rails to the regional power rails without significantly affecting the IC cores already coupled to the global power rails. [Summary of the Invention]

[0003] The following is a simplified summary of one or more embodiments to provide a basic understanding of such embodiments. This summary is not a broad overview of all conceived embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to define the scope of any or all embodiments. Its sole purpose is to introduce some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description provided below.

[0004] One aspect of this disclosure relates to an apparatus. The apparatus includes: a first power rail; a second power rail; a control circuit including a first input and a first output; a first set of power switching units coupled to the first and second power rails, wherein the first set of power switching units is cascaded from the first output of the control circuit to the first input of the control circuit; and a second set of at least one power switching unit coupled to the first and second power rails, wherein the second set of at least one power switching unit is coupled to one of: a first node between a first pair of power switching units in the first set, a first output of the control circuit, and a first input of the control circuit.

[0005] Another aspect of this disclosure provides a method. The method includes: propagating a first control signal via a first group of cascaded power switch units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and propagating the first control signal via at least one power switch unit of a second group coupled between a first pair of power switch units in the first group to couple the first power rail to the second power rail.

[0006] Another aspect of this disclosure relates to an apparatus. The apparatus includes: means for transmitting a first control signal via a first set of cascaded power switch units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and means for transmitting the first control signal via at least one power switch unit of a second set coupled between a first pair of power switch units in the first set to couple the first power rail to the second power rail.

[0007] Another aspect relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; a signal processing core coupled to the transceiver; a first power rail; a second power rail coupled to the signal processing core; a control circuit including a first input and a first output; a first set of cascaded power switch units coupled to the first and second power rails, wherein the first set of power switch units is cascaded from a first output of the control circuit to a first input of the control circuit; and a second set of at least one power switch unit coupled to the first and second power rails, wherein the second set of at least one power switch unit is coupled to one of the following: a first node between a first pair of power switch units in the first set, a first output of the control circuit, and a first input of the control circuit.

[0008] To achieve the foregoing and related objectives, the one or more embodiments include features fully described below and specifically pointed out in the claims. The following description and drawings illustrate certain exemplary aspects of the one or more embodiments. However, these aspects only indicate a few of the various ways in which the principles of various embodiments can be employed, and the described embodiments are intended to encompass all such aspects and their equivalents.

Implementation Method

[0022] The detailed descriptions following the diagrams are intended to describe various configurations, and not to represent only the configurations in which the concepts described herein can be practiced. The detailed descriptions include specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, known structures and components are shown in block diagram form to avoid making such concepts difficult to understand.

[0023] FIG1A shows a block diagram of an exemplary integrated circuit (IC) power system 100 according to one aspect of the present disclosure. The IC power system 100 includes a power management integrated circuit (PMIC) 110, a printed circuit board (PCB) 120, and an integrated circuit (IC) package 130 surrounding the integrated circuit (IC) 140.

[0024] PMIC 110 can be configured to generate an external power supply voltage Vext. PCB 120 includes a metallized trace 122 configured to route the external power supply voltage Vext from PMIC 110 to IC package 130. IC package 130 may include internal electrical routing methods (e.g., pins, pads, wire bonding, etc.) to further route the power supply voltage Vext to global power rail 142 of IC 140. As shown in FIG1A, the metallized trace 122 of PCB 120 and the internal route 132 of IC package 130 can be modeled as an inductor L coupled in series with a resistor R. Accordingly, there will be current resistance (IR) losses via PCB metallized trace 122 and internal route 132 of package, such that the power supply voltage Vdd at global power rail 142 is less than the external power supply voltage Vext (e.g., Vdd < Vext).

[0025] IC 140 includes a first global power rail 144 coupled to a first IC core 148 (e.g., a central processing unit (CPU) core, which may also be referred to herein as a "power-on core"). IC 140 also includes a second regional power rail 146 coupled to a second IC core 150 (e.g., an imaging or camera core, which may also be referred to herein as a "power-on core"). IC 140 may also include a power gate circuit, which may collectively include a control circuit 152, a first set of power switching units SW11 to SW1M, and a second set of power switching units SW21 to SW2N (where M and N are integers). The first set of power switching units SW11 to SW1M, in response to a first control signal generated by the control circuit 152, selectively couples the global power rail 142 to the first regional power rail 144. Similarly, the second set of power switching units SW21 to SW2N, in response to a second control signal generated by the control circuit 152, selectively couples the global power rail 142 to the second regional power rail 146.

[0026] Therefore, when the first core 148 is to be started, as specified by the power-on signal (PWR_ON) provided to the control circuit 152, the control circuit 152 generates a first control signal to close the first set of power switch units SW11 to SW1M, thereby coupling the global power rail 142 to the first regional power rail 144, and thus providing a power supply voltage Vdd1 to the first core 148. Since there may be some IR loss in the first set of power switch units SW11 to SW1M, the power supply voltage Vdd1 at the first regional power rail 144 may be slightly lower than the power supply voltage Vdd at the global power rail 142.

[0027] Similarly, when the second core 150 is to be started as specified by the PWR_ON signal, the control signal 152 generates a second control signal to close the second set of power switch units SW21 to SW2N, thereby coupling the global power rail 142 to the second regional power rail 146, and thus providing a power supply voltage Vdd2 to the second core 150. Since there may be some IR loss in the second set of power switch units SW21 to SW2N, the power supply voltage Vdd2 at the second regional power rail 146 may be slightly lower than the power supply voltage Vdd at the global power rail 142.

[0028] In some cases, the first core 148 may have already been activated, for example, when the CPU core is one of the first cores to be activated in IC 140. Later, at a subsequent time, the second core 150 may be activated, for example, when an imaging or camera core is used to capture images or video. Before activating the second core 150, the first set of power switch units SW11 to SW1M may be in their closed state, and the second set of power switch units SW21 to SW2N may be in their open state. When the second core 150 is about to be activated, the control circuit 152 generates a second control signal that closes the second set of power switch units SW21 to SW2N. If, for example, the first core 148 has a significantly lower capacitive load than the second core 150, and the second set of power switch units SW21 to SW2N is suddenly closed, then the second core 150 will draw current I1 from the first core 148 and interfere with the power supply voltage Vdd1 at the first region power rail 144. This could cause incorrect operation of the first core 148, potentially leading to bit errors and / or circuit failures.

[0029] Figure 1B shows a graph depicting the current and voltage time response associated with the IC power system 100 according to another aspect of this disclosure. The x-axis or horizontal axis of the graph represents time. The upper portion of the y-axis or vertical axis represents the current I2 drawn by the second core 150. The lower portion of the y-axis or vertical axis represents the power supply voltage Vdd1 at the first regional power rail 144. As illustrated in the graph, at time t1, the control circuit 152 turns on (closes) the second set of power switching units SW21 to SW2N, causing the current I2 drawn by the second core 150 to rise rapidly. As discussed, the consequence of this is that the second core 150 draws current I1 from the first power rail 144 via the global power rail 142. Therefore, the power supply voltage Vdd1 drops, as illustrated in the graph. The current I2 and voltage Vdd1 responses can be underdamped and can include overshoot, undershoot, and oscillations toward a steady-state level.

[0030] At a later time t2, the current I2 drawn by the second core 150 essentially reaches a steady-state current, and the power supply voltage Vdd1 at the first power rail 144 essentially recovers to the voltage level before the second core 150 was started. As shown in the graph, between times t1 and t2 (also known as the "wake-up" time), the power supply voltage Vdd1 may drop to a minimum voltage, which may be lower than the safe minimum voltage threshold Vth (e.g., 10% lower than the specified level of Vdd1). In such a case, a power supply voltage Vdd1 below the safe voltage threshold Vth may cause operational problems with the first core 148, which may in turn lead to bit errors or circuit failures. Therefore, turning on the second set of power switching units SW21 to SW2N can reduce the drop in power supply voltage Vdd1 and keep the power supply voltage Vdd1 above the safe threshold Vth when the second core 150 is started.

[0031] Figure 2A shows a block diagram of an exemplary power gate circuit 200 according to another aspect of this disclosure. The power gate circuit 200 is configured to progressively couple a global power rail Vdd to a regional power rail Vdd2, such that the power supply voltage at other regional power rails Vdd2 already coupled to the global power rail Vdd is not disturbed in a way that causes it to drop below a safe voltage threshold Vth. For ease of illustration and explanation, the global power supply voltage and the global power rail are referred to as Vdd, and the regional power supply voltage and the regional power rail are referred to as Vdd2.

[0032] More specifically, the power supply control circuit 200 includes a set of power switch units SW1 to SW32 (e.g., 32 in this example, but may have a different number of units). This set of power switch units SW1 to SW32 is coupled between the global power rail Vdd and the regional power rail Vdd2. From a signal propagation perspective, this set of power switch units SW1 to SW32 is cascaded from a pair of outputs Iw and Is of the control circuit 210 to a pair of inputs Rw and Rs of the control circuit 210.

[0033] Cascading means that power switch units SW1 to SW31 (excluding the last power switch unit SW32, which includes one or more outputs coupled to control circuit 210) include outputs that are respectively coupled to the inputs of subsequent power switch units SW2 to SW32 in a daisy chain-like manner. In other words, cascading means that power switch units SW2 to SW32 (excluding the first SW1, which includes one or more inputs coupled to control circuit 210) include inputs that are respectively coupled to the outputs of preceding power switch units SW1 to SW31 in a daisy chain-like manner.

[0034] As discussed in more detail herein, each of the power switching units SW1 through SW32 includes two independent inputs and two independent outputs. Each power switching unit propagates a weak (W) control signal along the cascaded set of power switching units SW1 through SW32 via a first input / output, simultaneously closing or turning on a relatively smaller switching device (e.g., a field-effect transistor (FET)) that couples the global power rail Vdd to the regional power rail Vdd2. Each power switching unit propagates a strong (S) control signal along the cascaded set of power switching units SW1 through SW32 via a second input / output, simultaneously closing or turning on a relatively larger switching device (e.g., a FET) that couples the global power rail Vdd to the regional power rail Vdd2. As an example, the relatively larger switching FET device may have a channel width-to-length (W / L) ratio that is 1000 times that of the relatively smaller switching FET device.

[0035] In operation, in response to the power-on (PWR_ON) signal, the control circuit 210 can generate a weak (W) control signal at the Iw output (making it active). The weak (W) control signal then propagates to the first power switch unit SW1, turning on its relatively small switching device and coupling the global power rail Vdd to the regional power rail Vdd2. The weak (W) control signal then propagates to the second power switch unit SW2, turning on its relatively small switching device and further coupling the global power rail Vdd to the regional power rail Vdd2. The weak (W) control signal then propagates to the third power switch unit SW3, turning on its relatively small switching device and further coupling the global power rail Vdd to the regional power rail Vdd2. In a similar manner, the propagation of the weak (W) control signal continues through power switch units SW4 to SW32, sequentially further coupling the global power rail Vdd to the regional power rail Vdd2, until the weak (W) control signal reaches the first input RW of the control circuit 210.

[0036] In response to receiving a weak (W) control signal at the first input RW, the control circuit 210 can generate a strong (S) control signal at the Is output (making it active). The strong (S) control signal then propagates to the first power switch unit SW1, thereby turning on its relatively large switching device and further coupling the global power rail Vdd to the regional power rail Vdd2. The strong (S) control signal then propagates to the second power switch unit SW2, turning on its relatively large switching device and further coupling the global power rail Vdd to the regional power rail Vdd2. The strong (S) control signal then propagates to the third power switch unit SW3, turning on its relatively large switching device and further coupling the global power rail Vdd to the regional power rail Vdd2. In a similar manner, the propagation of the strong (S) control signal continues through power switch units SW4 to SW32, sequentially further coupling the global power rail Vdd to the regional power rail Vdd2, until the strong (S) control signal reaches the second input RS of the control circuit 210.

[0037] Figure 2B shows a graph depicting the response of the weak (W) control signal and the strong (S) control signal, the current I2, and the voltage Vdd1 associated with the power gate circuit 200 relative to time, according to another aspect of this disclosure. The x-axis or horizontal axis of the graph represents time. The top portion of the y-axis or vertical axis represents the weak (W) control signal. The second portion from the top portion represents the strong (S) control signal. The third portion from the top portion represents the current I2 drawn by the core coupled to the regional power rail Vdd2. The bottom portion represents the power supply voltage Vdd1 at the regional power rail that is coupled to the global power rail Vdd.

[0038] As shown in the graph, before time t1, neither the weak (W) control signal nor the strong (S) control signal is active (in this example, a logic high voltage). Therefore, the power switch units SW1 to SW32 are in their off state; consequently, the global power rail Vdd is not coupled to the regional power rail Vdd2. Accordingly, since there is no power supply voltage on the regional power rail Vdd2, the current I2 drawn by the core coupled to the regional power rail Vdd2 is essentially zero (e.g., there may be some leakage current through the switching devices of the power switch units SW1 to SW32). Moreover, before time t1, the power supply voltage Vdd1 at the other regional power rails is within specifications, for example, exceeding the safety threshold voltage Vth by a specified limit.

[0039] At time t1, the PWR_ON signal is set to initiate coupling to the core of the regional power rail Vdd2. In response to the PWR_ON signal, control circuit 210 activates a weak (W) control signal (e.g., sets it to logic low). As discussed, the weak (W) control signal propagates through the power switch units SW1 to SW32, sequentially and gradually coupling the entire power rail Vdd to the regional power rail Vdd2. At time t2, the weak (W) control signal arrives at the RW input of control circuit 210; thus ending the weak (W) power rail coupling phase. As illustrated, during the weak (W) coupling phase, the current I2 drawn from the core coupled to the regional power rail Vdd2 gradually increases, thereby reducing or minimizing the impact on the power supply voltage Vdd1 at other regional power rails. Therefore, the power supply voltage Vdd1 decreases slightly, but does not fall below the safety threshold voltage Vth.

[0040] At time t2, in response to receiving a weak (W) control signal at the RW input, control circuit 210 activates a strong (S) control signal (e.g., sets it to logic low). As discussed, the strong (S) control signal propagates through the power switch units SW1 to SW32, sequentially and gradually coupling the global power rail Vdd to the regional power rail Vdd2. At time t3, the strong (S) control signal arrives at the RS input of control circuit 210; thus ending the strong (S) power rail coupling phase. As illustrated, during the strong (S) coupling phase, the slope of the current I2 drawn from the core coupled to the regional power rail Vdd2 increases significantly and may include overshoot and oscillations toward steady-state current. As a result of the strong (S) coupling, the complete coupling of the global power rail Vdd to the regional power rail Vdd2 is accelerated. Since the core coupled to the regional power rail Vdd2 is already drawing current I2 due to the weak (W) coupling phase, the rate at which current I2 is drawn after time t2 does not significantly affect the power supply voltage Vdd1. Therefore, the power supply voltage Vdd1 remains above the safe threshold voltage Vth.

[0041] FIG3 shows a schematic diagram of an exemplary power switch unit 300 according to another aspect of the present disclosure. The power switch unit 300 may be an exemplary implementation of each of the power switch units SW1 to SW32 of the power gate circuit 200.

[0042] Regarding the weak (W) control signal propagation path, the power switch unit 300 includes a first input buffer or inverter 310, a first FET M1 (which may be implemented as an n-channel metal-oxide-semiconductor (NMOS) FET or a p-channel metal-oxide-semiconductor (PMOS) FET), and a first output buffer or inverter 320. The first input buffer or inverter 310 includes an input serving as the weak (W) control signal input Win of the power switch unit 300. The first FET M1 is coupled between the global power rail Vdd (via the drain / source terminal) and the regional power rail Vdd2 (via the drain / source terminal) and includes a gate coupled to the output of the first input buffer or inverter 310. The first output buffer or inverter 320 includes an input coupled to the gate of the first FET M1 and an output serving as the weak (W) control signal output Wout of the power switch unit 300.

[0043] Regarding the strong (S) control signal propagation path, the power switch unit 300 includes a second input buffer or inverter 330, a second FET M2 (which may be implemented as an NMOS FET or a PMOS FET), and a second output buffer or inverter 340. The second input buffer or inverter 330 includes an input that serves as the strong (S) control signal input Sin of the power switch unit 300. The second FET M2 is coupled between the global power rail Vdd (via the drain / source terminal) and the regional power rail Vdd2 (via the drain / source terminal), and includes a gate coupled to the output of the second input buffer or inverter 330. The second output buffer or inverter 340 includes an input coupled to the gate of the second FET M2 and an output that serves as the strong (S) control signal output Sout of the power switch unit 300. As discussed, the second FET M2 may be larger than the first FET M1.

[0044] In operation, when an effective weak (W) control signal (e.g., at a logic low voltage) propagates to the weak input Win of the power switching unit 300, the first input inverter 310 inverts the weak (W) control signal to generate a logic high voltage. This logic high voltage is applied to the gate of the first NMOS FET M1; thereby turning on the first FET M1 and coupling the global power rail Vdd to the regional power rail Vdd2. The first output inverter 320 inverts the logic high voltage at the gate of the first NMOS FET M1, thereby outputting an effective logic low weak (W) control signal for the subsequent power switching unit or the input Rw of the control circuit 210.

[0045] Similarly, when an active strong (S) control signal (e.g., at a logic low voltage) propagates to the strong input Sin of the power switching unit 300, the second input inverter 330 inverts the strong (S) control signal to generate a logic high voltage. This logic high voltage is applied to the gate of the second NMOS FET M2; thereby turning on the second FET M2 and coupling the global power rail Vdd to the regional power rail Vdd2. The second output inverter 340 inverts this logic high voltage at the gate of the second NMOS FET M2, thereby outputting an active logic low strong (S) control signal for the subsequent power switching unit or the input Rs of the control circuit 210.

[0046] Although the power gate circuit 200 provides an efficient method to start the core coupled to the regional power rail Vdd2 without significantly affecting the power supply voltage Vdd1 at other regional power rails (e.g., keeping Vdd1 above the safe threshold voltage Vth), the power gate circuit 200 may take a considerable amount of time to fully couple the global power rail Vdd to the regional power rail Vdd2 due to the cascaded arrangement of the power switching units (e.g., the wake-up time may be relatively long). Furthermore, since each power switching unit includes two (2) input buffers or inverters and two (2) output buffers or inverters, there may be significant current leakage associated with this group of power switching units, thereby reducing the power efficiency of the power gate circuit 200. The buffers or inverters may also occupy a significant portion of the IC coverage area.

[0047] Figure 4 shows a block diagram of another exemplary power gate circuit 400 according to another aspect of the present disclosure. The power gate circuit 400 can be configured to provide a faster wake-up time compared to the power gate circuit 200 to fully couple the global power rail Vdd to the regional power rail Vdd2, while keeping the power supply voltage Vdd1 at other regional power rails coupled to the global power rail Vdd above a safe threshold voltage Vth. Furthermore, the power gate circuit 400 can also be configured to have lower current leakage compared to the power gate circuit 200, to reduce power consumption or to operate the power gate circuit 400 in a more power-efficient manner. Additionally, the power gate circuit 400 can occupy a significantly smaller IC coverage area compared to the power gate circuit 200. As further discussed herein, the power gate circuit 400 can have a “binary” power switch tree structure.

[0048] Specifically, the power damming circuit 400 includes a first group of power switching units SW11 to SW14 to SW24 to SW84 cascaded from the Iw and Is outputs of the control circuit 410 to the Rw and Rs inputs of the control circuit 410, respectively. The power damming circuit 400 also includes multiple cascaded power switching units SW21 to SW81, SW22 to SW82, and SW23 to SW83, respectively coupled to nodes between different pairs of power switching units SW11 / SW12, SW12 / SW13, and SW13 / SW14 in the first group, or extending from such nodes. In this example, the multiple power switching units SW21 to SW81, SW22 to SW82, and SW23 to SW83 do not terminate at the control circuit 410. As discussed in more detail herein, the multiple sets of power switching units SW21 to SW81, SW22 to SW82, and SW23 to SW83 include corresponding non-driven or terminal power switching units SW81 to SW83, which are shown in black shades because they do not include output buffers or inverters, as they do not drive subsequent power switching units.

[0049] It should be noted that the first subset of the first group of power switch units, SW11 to SW14, extends substantially orthogonally to the direction in which the extensions of the multiple groups of power switch units, SW21 to SW81, SW22 to SW82, and SW23 to SW83, are directed. Furthermore, it should be noted that the second subset of the first group of power switch units, SW24 to SW84, extends substantially parallel to the direction in which the extensions of the multiple groups of power switch units, SW21 to SW81, SW22 to SW82, and SW23 to SW83, are directed.

[0050] The power supply control circuit 400 further includes non-driven or terminal power switch units SW1 to SW71 (indicated by black shading) respectively coupled to different pairs of SW21 / SW41, SW41 / SW61, and SW61 / SW81 in a set of cascaded power switch units SW21 to SW81. The power supply control circuit 400 also includes non-driven or terminal power switch units SW32 to SW72 (indicated by black shading) respectively coupled to different pairs of SW22 / SW42, SW42 / SW62, and SW62 / SW82 in a set of cascaded power switch units SW22 to SW82. In addition, the power supply control circuit 400 also includes non-driven or terminal power switch units SW33 to SW73 (indicated by black shading) respectively coupled to different pairs of SW23 / SW43, SW43 / SW63, and SW63 / SW83 in a set of cascaded power switch units SW23 to SW83. Furthermore, in this example, the power dam circuit 400 also includes undriven or terminal power switch units SW34 to SW74 (indicated by black shading) that are respectively coupled to different pairs of SW24 / SW44, SW44 / SW64, and SW64 / SW84 in a set of cascaded power switch units SW24 to SW84. All power switch units of the power dam circuit 400 are coupled between the global power rail Vdd and the regional power rail Vdd2.

[0051] The power gate circuit 400 can provide a faster wake-up time than the power gate circuit 200 because multiple power switch units are turned on substantially simultaneously in the power gate circuit 400. Assuming that each of the power switch units has substantially the same signal delay (D), then after propagation through the power switch unit SW11, the control signal (weak or strong) turns on the power switch units SW12 and SW21 substantially simultaneously; then turns on the power switch units SW13, SW22, SW41 and SW31 substantially simultaneously; then turns on the power switch units SW14, SW23, SW42, SW32, SW61 and SW51 substantially simultaneously; and so on. With the help of this tree structure (which can be called a “binary” tree structure because the number of units that are started simultaneously increases and decreases in a manner similar to the increase and decrease of a binary number (1), the turn-on process is as follows: 1 unit, 2 units, 4 units, 6 units, 7 units, 6 units, 4 units and 2 units, with an 8-unit delay (D). The power gate circuit 200 requires a delay of 32 units (D) to complete the propagation of a single control signal. Therefore, using the power gate circuit 400 significantly reduces the wake-up time.

[0052] FIG5 shows a schematic diagram of another exemplary power switch unit 500 according to another aspect of the present disclosure. The power switch unit 500 may be an exemplary embodiment of any of the non-driven or terminal power switch units SW31 to SW71, SW81, SW32 to SW72, SW82, SW33 to SW73, SW83, SW34 to SW74 and SW84 of the power gate circuit 400.

[0053] Regarding the weak (W) control signal path, the power switch unit 500 includes a first input buffer or inverter 510 and a first FET M1 (which may be implemented as an NMOS FET or a PMOS FET). The first input buffer or inverter 510 includes an input that serves as the weak (W) control signal input Win of the power switch unit 500. The first FET M1 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the first input buffer or inverter 510. Since the non-driven or terminal power switch unit 500 is not preceding other power switch units, it need not include an output buffer or inverter in the weak (W) control signal path. Therefore, the power switch unit 500 can be described as having a floating weak (W) control signal output Wout.

[0054] Regarding the strong (S) control signal path, the power switching unit 500 includes a second input buffer or inverter 530 and a second FET M2 (which may be implemented as an NMOS FET or a PMOS FET). The second input buffer or inverter 530 includes an input that serves as the strong (S) control signal input Sin for the power switching unit 500. The second FET M2 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the second input buffer or inverter 530. As discussed, the second FET M2 may be larger than the first FET M1. Since the non-driven or terminal power switching unit 500 is not preceding other power switching units, it need not include an output buffer or inverter in the strong (S) control signal path. Therefore, the power switching unit 500 can be described as also having a floating strong (S) control signal output Sout.

[0055] Output buffers or inverters in power switching units are potential sources of current leakage. Accordingly, power switching unit 500 can have less current leakage than power switching unit 300, which includes output buffers or inverters 320 and 340. Comparing power gate circuit 400 to power gate circuit 200, all power switching units SW1 to SW32 in power gate circuit 200 include output buffers or inverters, while in power gate circuit 400, only 17 out of 32 power switching units have output buffers or inverters. Therefore, power gate circuit 400 can have a 50% improvement in power efficiency compared to power gate circuit 200. In addition, output buffers or inverters also occupy IC coverage area. By having non-driven or terminal power switching units, power gate circuit 400 can also have a smaller IC coverage area compared to power gate circuit 200.

[0056] Figure 6 shows a block diagram of yet another exemplary power gate circuit 600 according to another aspect of this disclosure. The power gate circuit 600 can also be configured to provide a faster wake-up time compared to the power gate circuit 200 to fully couple the global power rail Vdd to the regional power rail Vdd2, while keeping the power supply voltage Vdd1 at other regional power rails (coupled to the global power rail Vdd) above a safe threshold voltage Vth. Furthermore, the power gate circuit 600 can also be configured to have lower current leakage compared to the power gate circuit 200, thereby reducing power consumption or enabling the power gate circuit 600 to operate in a more power-efficient manner. Additionally, the power gate circuit 600 can be implemented using a smaller IC coverage area compared to the power gate circuit 200.

[0057] As discussed in more detail herein, the power supply control circuit 600 includes a power switch unit tree structure, which may be referred to as a “dangling” tree structure because it includes power switch units coupled in parallel with each power switch unit in the cascaded group. That is, from a top view of the tree structure, the parallel power switch units appear to “dangle” out from their corresponding cascaded power switch units.

[0058] Specifically, the power supply control circuit 600 includes a first set of power switch units SW1 to SW12 cascaded from the Iw and Is outputs of the control circuit 610 to the Rw and Rs inputs of the control circuit 610, respectively. The first set of power switch units SW1 to SW12 are coupled between the global power rail Vdd and the regional power rail Vdd2, as discussed above.

[0059] The power control circuit 600 may further include a group of power switching units coupled in parallel with each of the power switching units SW1 to SW12 in the first group. For example, the first group of power switching units SW11 to SW1K is coupled in parallel with the power switching unit SW1 in the first group. The second group of power switching units SW21 to SW2K is coupled in parallel with the power switching unit SW2 in the first group. The third group of power switching units SW31 to SW3K is coupled in parallel with the power switching unit SW3 in the first group; and so on, such that multiple groups of power switching units SW41-SW4K to SW121-SW12K are coupled in parallel with the power switching units SW4 to SW12 in the first group, respectively. The parallel power switching units are also coupled between the global power rail Vdd and the regional power rail Vdd2.

[0060] Since the multiple sets of power switching units SW11-SW1K to SW121-SW12K are not preceding or driving other power switching units, each power switching unit can be implemented as a non-driving or terminal power switching unit, for example, power switching unit 500. Since power switching unit 500 does not include output buffers or inverters as discussed above, power switching unit 500 is less prone to current leakage and can have a smaller IC coverage area compared to power switching unit 300, which includes output buffers or inverters. As an example, if K equals two (2), then power gate circuit 600 includes 36 power switching units, of which only 12 include output buffers or inverters, while power gate circuit 200 has 32 power switching units, all of which have output buffers or inverters. Thus, power gate circuit 600 can have approximately 67% greater power efficiency and 3% smaller IC coverage area compared to power gate circuit 200.

[0061] Regarding the wake-up time, the multiple sets of parallel power switch units SW1-SW1K to SW12-SW12K are essentially woken up simultaneously by the corresponding control signals (weak (W) or strong (S)). Since there are 12 power switch units SW1 to SW12 cascaded from the Iw and Is outputs of control circuit 610 to the Rw and Rs inputs, the wake-up time of power gate circuit 600 is 2*12*D or 24D, where D is the control signal delay for each power switch unit (assuming the delay D is essentially the same for all power switch units). Compared to power gate circuit 200, power gate circuit 200 includes 32 power switch units SW1 to SW32 cascaded from the Iw and Is outputs of control circuit 210 to the Rw and Rs inputs. Therefore, the wake-up time of power gate circuit 200 is 2*32*D or 64D, which is much longer than the 24D wake-up time of power gate circuit 600.

[0062] Figure 7A shows a block diagram of another exemplary power gate circuit 700 (weak (W) signal routing) according to another aspect of this disclosure. In the power gate circuits 200, 400, and 600 discussed above, the routing or unit-to-unit interconnection between power switch units is the same for both the weak (W) control signal and the strong (S) control signal, although they are connected in parallel. However, it should be understood that the routing or unit-to-unit interconnection between power switch units can be different for the weak (W) control signal and the strong (S) control signal. Power gate circuit 700 is an example of such an implementation. Figure 7A shows the routing or interconnection of power switch units for the weak (W) control signal; while Figure 7B, which will be discussed further herein, shows the routing or interconnection of power switch units for the strong (S) control signal.

[0063] More specifically, the power gate circuit 700 includes a first set of power switch units SW1 to SW8 cascaded from the Iw output of the control circuit 710, similar to the cascaded implementation of the power gate circuit 200. The power gate circuit 700 also includes a second set of power switch units SW9 to SW20 cascaded from the weak (W) control signal output Wout of the power switch unit SW8 to the Rw input of the control circuit 710. Similar to the "dangling" tree structure of the power gate circuit 600, the power gate circuit 700 also includes sets of power switch units SW91-SW9K to SW201-SW20K respectively coupled in parallel with the power switch units SW9 to SW20. Similar to other power gate circuits, all power switch units of the power gate circuit 700 are coupled between the global power rail Vdd and the regional power rail Vdd2. Since the multiple sets of power switch units SW91-SW9K to SW201-SW20K do not precede or drive the subsequent power switch units, they can all be implemented as non-driving or end power switch units, for example, power switch unit 500.

[0064] In operation, in response to the PWR_ON signal received by the power gate circuit 700 to activate the core coupled to the regional power rail Vdd2, the control circuit 710 generates a weak (W) control signal (to activate it). The weak (W) control signal propagates through the first set of power switch units SW1 to SW8, thereby coupling the entire power rail Vdd sequentially to the regional power rail Vdd2. Subsequently, the weak (W) control signal propagates through the second set of power switch units SW9 to SW20, and to multiple sets of parallel power switch units SW91-SW9K to SW201-SW20K, thereby coupling the entire power rail Vdd sequentially to the regional power rail Vdd2, until the weak (W) control signal is received by the RW input of the control circuit 710.

[0065] Figure 7B shows a block diagram of a power gate circuit 700 with strong (S) control signal routing or cell-to-cell interconnection according to another aspect of this disclosure. The routing or cell-to-cell interconnection for the strong (S) control signal is based on a binary tree structure similar to the tree structure of the power gate circuit 400 discussed above.

[0066] More specifically, the control circuit 710 includes a strong (S) control signal output Is coupled to the strong (S) control signal input of the power switch unit SW5. The strong (S) control signal is routed via a portion of the first group of power switch units, namely power switch units SW5 to SW9. Subsequently, the strong (S) control signal is routed from the strong (S) control signal output Sout of the power switch unit SW8 via the second group of power switch units SW9, SW16 and SW17 to the strong (S) control signal input Rs of the control circuit 710.

[0067] The strong (S) control signal is also routed from the strong (S) control signal output Sout of power switch unit SW5 via a set of cascaded power switch units SW12, SW13, SW20, and SW201. As indicated by its black shading, power switch unit SW201 can be a non-driven or terminal power switch unit, similar to power switch unit 500 discussed above. Furthermore, the strong (S) control signal is also routed from the strong (S) control signal output Sout of power switch unit SW6 via a set of cascaded power switch units SW11, SW14, SW19, and SW191. As indicated by its black shading, power switch unit SW191 can be a non-driven or terminal power switch unit, similar to power switch unit 500 discussed above. Furthermore, the strong (S) control signal is also routed from the strong (S) control signal output Sout of power switch unit SW7 via a set of cascaded power switch units SW10, SW15, SW18, and SW181. As indicated by its black shading, the power switch unit SW181 may be a non-driven or terminal power switch unit, similar to the power switch unit 500 discussed above.

[0068] The strong (S) control signal is also routed from the strong (S) control signal output Sout of power switch units SW9 to SW13 via power switch units SW91, SW101, SW111, SW121, SW131, SW141, SW151 and SW161. As indicated by their black shading, power switch units SW91, SW101, SW111, SW121, SW131, SW141, SW151 and SW161 can be non-driven or terminal power switch units, similar to the power switch unit 500 discussed above.

[0069] In operation, in response to receiving a weak (W) control signal at input Rw, control circuit 710 generates a strong (S) control signal (making it active). The strong (S) control signal propagates through the power switch units SW5 to SW9, SW16 and SW17 to the Rs input of control signal 710, thereby causing each power switch unit to sequentially couple the global power rail Vdd to the regional power rail Vdd2. The strong (S) control signal also propagates along multiple power switch units SW12, SW13, SW20 and SW201, SW11, SW14, SW19 and SW191 and SW10, SW15, SW18 and SW181, thereby sequentially coupling the global power rail Vdd to the regional power rail Vdd2. The strong (S) control signal is also propagated to the non-drive or end power switch units SW91, SW101, SW111, SW121, SW131, SW141, SW151 and SW161, thereby further coupling the global power rail Vdd to the regional power rail Vdd2.

[0070] Figure 8 shows a schematic diagram of yet another exemplary power switching unit 800 according to another aspect of the present disclosure. In power gate control circuits where the weak (W) control signal has a different unit-to-unit route than the strong (S) control signal (e.g., in the case of power gate control circuit 700), there may be one or more power switching units that precede or drive the subsequent power switching unit relative to the weak (W) control signal, but not relative to the strong (S) control signal. Such one or more power switching units need not include an output buffer or inverter relative to the strong (S) control signal. Power switching unit 800 is an exemplary detailed embodiment of such one or more power switching units.

[0071] Specifically, relative to the weak (W) control signal propagation path, the power switching unit 800 includes a first input buffer or inverter 810, a first FET M1 (which may be implemented as an NMOS FET or a PMOS FET), and an output buffer or inverter 820. The first input buffer or inverter 810 includes an input that serves as the weak (W) control signal input Win of the power switching unit 800. The first FET M1 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the first input buffer or inverter 810. The output buffer or inverter 820 includes an input coupled to the gate of the first FET M1, and an output that serves as the weak (W) control signal output Wout of the power switching unit 800.

[0072] Relative to the strong (S) control signal path, the power switching unit 800 includes a second input buffer or inverter 830 and a second FET M2 (which may be implemented as an NMOS FET or a PMOS FET). The second input buffer or inverter 830 includes an input that serves as the strong (S) control signal input Sin for the power switching unit 800. The second FET M2 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the second input buffer or inverter 830. As discussed, the second FET M2 may be larger than the first FET M1. Since the power switching unit 800 is not preceding other power switching units relative to the strong (S) control signal, it need not include an output buffer or inverter in the strong (S) control signal path. Therefore, the power switching unit 800 can be described as also having a floating strong (S) control signal output Sout.

[0073] Figure 9 shows a schematic diagram of yet another exemplary power switching unit 900 according to another aspect of the present disclosure. Similarly, in a power gate circuit where the weak (W) control signal has a different unit-to-unit route than the strong (S) control signal, there may be one or more power switching units that precede or drive the subsequent power switching unit relative to the strong (S) control signal, but not relative to the weak (W) control signal. Such one or more power switching units need not include an output buffer or inverter relative to the weak (W) control signal. Power switching unit 900 is an exemplary detailed embodiment of such one or more power switching units.

[0074] Specifically, relative to the weak (W) control signal path, the power switching unit 900 includes a first input buffer or inverter 910 and a first FET M1 (which may be implemented as an NMOS FET or a PMOS FET). The first input buffer or inverter 910 includes an input that serves as the weak (W) control signal input Win of the power switching unit 900. The first FET M1 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the first input buffer or inverter 910. Since the power switching unit 900 is not preceding other power switching units relative to the weak (W) control signal, it need not include an output buffer or inverter in the weak (W) control signal path. Therefore, the power switching unit 900 can be described as having a floating weak (W) control signal output Wout.

[0075] Relative to the strong (S) control signal path, the power switching unit 900 includes a second input buffer or inverter 930, a second FET M2 (which may be implemented as an NMOS FET or a PMOS FET), and an output buffer or inverter 940. The second input buffer or inverter 930 includes an input that serves as the strong (S) control signal input Sin of the power switching unit 900. The second FET M2 is coupled between the global power rail Vdd and the regional power rail Vdd2, and includes a gate coupled to the output of the second input buffer or inverter 930. As discussed, the second FET M2 may be larger than the first FET M1. The output buffer or inverter 940 includes an input coupled to the gate of the second FET M2, and an output that serves as the strong (S) control signal output Sout of the power switching unit 900.

[0076] Figure 10 shows a flowchart of an exemplary method 1000 for supplying power to a circuit (core) according to another aspect of this disclosure. Method 1000 includes propagating a first control signal via a first set of cascaded power switching units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit (block 1010). Examples of means for propagating the first control signal via the first set of cascaded power switching units to sequentially couple the first power rail to the second power rail include any one of the first set of power switching units SW11 to SW84 of power gate circuit 400, the first set of power switching units SW1 to SW12 of power gate circuit 600, the first set of power switching units SW1 to SW20 of power gate circuit 700 for a weak (W) control signal, and the first set of power switching units SW5 to SW9, SW16, and SW17 of power gate circuit 700 for a strong (S) control signal.

[0077] Method 1000 further includes propagating a first control signal via at least one power switch unit of a second group coupled between the first pair of power switch units in the first group to couple the first power rail to the second power rail (block 1020). Examples of components for propagating the first control signal via at least one power switch unit of a second group coupled between the first pair of power switch units in the first group include any of a plurality of power switch units such as SW21 to SW81, SW22 to SW82 and SW23 to SW83 of power gate circuit 400, SW11-SW1K to SW121-SW12K of power gate circuit 600, SW91-SW9K to SW201-SW20K of power gate circuit 700 for weak (W) control signals and SW12, SW13 and SW20, SW11, SW14 and SW19 and SW10, SW15 and SW18 of power gate circuit 700 for strong (S) control signals.

[0078] According to method 1000, the propagation of the first control signal may include propagating the first control signal from a first output of the control circuit to a first input of the control circuit. Examples of components for propagating the first control signal from the first output of the control circuit to the first input of the control circuit include any of a plurality of sets of power switch units cascaded from the output (e.g., Iw and / or Is) of any control circuit described herein to its input (e.g., Rw and / or Rs). Method 1000 may also include propagating a second control signal from a second output of the control circuit to a second input of the control circuit via a first set of cascaded power switch units, thereby sequentially coupling a first power rail to a second power rail. Examples of components for propagating the second control signal from the second output of the control circuit to the second input of the control circuit via a first set of cascaded power switch units include any of a plurality of sets of power switch units cascaded from the output (e.g., Iw and / or Is) of any control circuit described herein to its input (e.g., Rw and / or Rs).

[0079] According to method 1000, propagating the first control signal via at least one power switch unit in the second group includes propagating the first control signal via the second group of cascaded power switch units to sequentially couple the first power rail to the second power rail. Examples of components for propagating the first control signal via the second group of cascaded power switch units to sequentially couple the first power rail to the second power rail include any one of multiple groups of cascaded power switch units coupled between a pair of power switch units in the first group. Furthermore, method 1000 may also include propagating the first control signal via a second group of parallel power switch units to couple the first power rail to the second power rail. Examples of components for propagating the first control signal via the second group of parallel power switch units to couple the first power rail to the second power rail include any one of the parallel power switch units of power gate circuits 600 and 700.

[0080] Figure 11 shows a block diagram of an exemplary wireless communication device 1100 according to another aspect of this disclosure. The wireless communication network 1100 includes an integrated circuit (IC) 1110, which can be configured as a system-on-a-chip (SOC). The SOC 1110 includes a first core 1130, a power gate circuit 1120, and a second core 1140. The power gate circuit 1120 can be implemented according to any of the power gate circuits 400, 600, and 700 described above. Accordingly, the power gate circuit 1120 is coupled to a global power rail Vdd, a first regional power rail Vdd1, and a second regional power rail Vdd2.

[0081] A first regional power rail Vdd1 and a second regional power rail Vdd2 are coupled to a first core 1130 and a second core 1140, respectively. A power gate circuit 1120 is configured to receive a power-on signal (PWR_ON) for selectively coupling the global power rail Vdd to one or both of the regional power rails Vdd1 and Vdd2 to selectively enable the first and / or second cores 1130 and 1140. As an example, the first core 1130 may be implemented as a central processing unit (CPU) core, and the second core 1140 may be implemented as a modem core. Accordingly, the second core 1140 may include one or more signal processing cores configured to process baseband (BB) signals.

[0082] The wireless communication device 1100 also includes a transceiver 1150 and at least one antenna 1160 (e.g., an antenna array). According to signal transmission operations, the one or more digital signal processing cores 1140 generate a BB transmit signal and provide the BB transmit signal to the transceiver 1150. The transceiver 1150 is configured to generate a radio frequency (RF) transmit signal based on the BB transmit signal (e.g., upsampling, RF filtering, preamplification, phase shifting, power amplification, etc.). The transceiver 1150 provides the RF transmit signal to at least one antenna 1160 for wireless transmission to one or more remote wireless communication devices.

[0083] According to the signal reception operation, at least one antenna 1160 receives an RF signal from one or more remote wireless communication devices. A transceiver 1150 is configured to generate a BB received signal based on the received RF signal (e.g., RF filtering, low-noise amplification (LNA), down-conversion, phase shifting, IF, and / or BB amplification, etc.). Subsequently, one or more digital signal processing cores 1140 process the BB received signal to recover data from it.

[0084] An overview of various aspects of this disclosure will be provided below:

[0085] Aspect 1: An apparatus comprising: a first power rail; a second power rail; a control circuit including a first input and a first output; a first set of power switch units coupled to the first and second power rails, wherein the first set of power switch units is cascaded from a first output of the control circuit to a first input of the control circuit; and a second set of at least one power switch unit coupled to the first and second power rails, wherein the second set of at least one power switch unit is coupled to one of: a first node between a first pair of power switch units in the first set, a first output of the control circuit, and a first input of the control circuit.

[0086] Aspect 2: The apparatus according to aspect 1, wherein the second group of at least one power switch unit includes a second group of cascaded power switch units extending from one of the following: a first node, a first output of a control circuit and a first input of a control circuit.

[0087] Aspect 3: According to the apparatus of aspect 2, a first subset of the first group of cascaded power switch units extends in a direction substantially orthogonal to the direction in which the second group of cascaded power switch units extend.

[0088] Aspect 4: According to the apparatus of aspect 3, the second subset of the first group of cascaded power switch units extends in a direction substantially parallel to the direction in which the second group of cascaded power switch units extend.

[0089] Aspect 5: The apparatus according to any one of aspects 1-4 further includes at least one power switch unit of a third group coupled to the first and second power rails, wherein the at least one power switch unit of the third group is coupled to a second node between the second pair of power switch units in the first group.

[0090] Aspect 6: The apparatus according to aspect 5, wherein at least one power switch unit of the third group includes a third group of cascaded power switch units extending from the second node.

[0091] Aspect 7: The apparatus according to any one of aspects 2-6 further includes at least one power switch unit of a third (or fourth) group coupled to the first and second power rails, wherein the at least one power switch unit of the third (or fourth) group is coupled to a second node between the second pair of power switch units in the second group.

[0092] Aspect 8: The apparatus according to aspect 7, wherein at least one power switch unit of the third (or fourth) group is not preceding other power switch units.

[0093] Aspect 9: The apparatus according to aspect 8, wherein the third group of at least one power switching unit comprises: a first buffer or inverter including a first input coupled to a first output of a power switching unit in the second group of cascaded power switching units; a first field-effect transistor (FET) coupled between the first and second power rails, wherein the first FET includes a first gate coupled to the first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to a second output of a power switching unit in the second group of cascaded power switching units; and a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to the second output of the second buffer or inverter, and wherein the second FET is larger than the first FET.

[0094] Aspect 10: The apparatus according to any one of aspects 2-9, wherein the second group of cascaded power switch units includes a power switch unit that is not preceding the other power switch units.

[0095] Aspect 11: An apparatus according to any one of aspects 1-10, wherein each cascaded power switch unit in the first group of cascaded power switch units includes: a first buffer or inverter including a first input coupled to one of: a first output of a preceding power switch unit in the first group of cascaded power switch units and a first output of a control circuit; a first field-effect transistor (FET) coupled between first and second power rails, wherein the first FET includes a first gate coupled to the first output of the first buffer or inverter; a second buffer or inverter including a second input coupled to one of: a second output of a preceding power switch unit in the first group of cascaded power switch units and a second output of a control circuit; A second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of a second buffer or inverter, and wherein the second FET is larger than the first FET; a third buffer or inverter including a third input and a third output, the third input being coupled to a first gate of the first FET, the third output being coupled to one of the following: a first input of a subsequent power switch unit in the first set of cascaded power switch units and a first input of a control circuit; and a fourth buffer or inverter including a fourth input and a fourth output, the fourth input being coupled to a second gate of the second FET, the fourth output being coupled to one of the following: a second input of a subsequent power switch unit in the first set of cascaded power switch units and a second input of a control circuit.

[0096] Aspect 12: An apparatus according to any one of aspects 1-10, wherein at least one power switch unit in the first group of cascaded power switch units or at least one power switch unit in the second group of at least one power switch unit comprises: a first buffer or inverter including a first input coupled to one of: a first output of a preceding power switch unit and a first output of a control circuit; a first field-effect transistor (FET) coupled between first and second power rails, wherein the first FET includes a first gate coupled to the first output of the first buffer or inverter; and a second buffer or inverter including a second input. The second input is coupled to one of the following: a second output of a preceding power switch unit or other preceding power switch unit and a second output of a control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of a second buffer or inverter, and wherein the second FET is larger than the first FET; and a third buffer or inverter including a third input and a third output, the third input being coupled to one of the following: a first gate of a first FET, the third output being coupled to a first input of a subsequent power switch unit and a first input of a control circuit, wherein the second gate is coupled to a floating output.

[0097] Aspect 13: An apparatus according to any one of aspects 1-10, wherein at least one power switch unit in the first group of cascaded power switch units or at least one power switch unit in the second group of at least one power switch unit comprises: a first buffer or inverter including a first input coupled to one of: a first output of a preceding power switch unit and a first output of a control circuit; a first field-effect transistor (FET) coupled between first and second power rails, wherein the first FET includes a first gate coupled to the first output of the first buffer or inverter; a second buffer or inverter including a second input, the second input... The input is coupled to one of the following: a second output of a pre-power switching unit or other pre-power switching unit and a second output of a control circuit; a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of a second buffer or inverter, and wherein the second FET is larger than the first FET; and a third buffer or inverter including a third input and a third output, the third input being coupled to a second gate of the second FET, the third output being coupled to one of the following: a first input of a subsequent power switching unit or other power switching unit and a second input of a control circuit, wherein the first gate is coupled to a floating output.

[0098] Aspect 14: The apparatus according to any one of aspects 1-13, wherein the second group of at least one power switch unit comprises a group of power switch units in parallel.

[0099] Aspect 15: According to the apparatus of aspect 14, each of the parallel power switch units in a group of parallel power switch units is not preceding the other power switch units.

[0100] Aspect 16: According to the apparatus of aspect 15, each of the parallel power switching units in a group of parallel power switching units includes: a first buffer or inverter including a first input coupled to one of: a first output of the preceding power switching unit in the first group and a first output of the control circuit; a second buffer or inverter including a second input coupled to one of: a second output of the preceding power switching unit and a second output of the control circuit; and a second FET coupled between the first and second power rails, wherein the second FET includes a second gate coupled to a second output of the second buffer or inverter, and wherein the second FET is larger than the first FET.

[0101] Aspect 17: An apparatus according to any one of aspects 1-16, wherein each power switch unit in the first group of power switch units includes: a first input coupled to a first output of a control circuit and a first input of a preceding power switch unit in the first group; a first output coupled to a first input of a control circuit and a first input of a subsequent power switch unit in the first group; a second input coupled to a second output of a control circuit and a second input of a preceding power switch unit in the first group; and a second output coupled to a second input of a control circuit and a second input of a subsequent power switch unit in the first group.

[0102] Aspect 18: An apparatus according to any one of aspects 1-16, wherein at least one power switch unit in the first group of power switch units includes: a first input coupled to a first output of a control circuit and a first output of a preceding power switch unit in the first group; a first output coupled to a first input of a control circuit and a first input of a subsequent power switch unit in the first group; a second input coupled to a second output of a control circuit, a second output of a preceding power switch unit in the first group and a third output of a first power switch unit not in the first group; and a second output coupled to a second input of a control circuit, a second input of a subsequent power switch unit in the first group and a third input of a second power switch unit not in the first group.

[0103] Aspect 19: An apparatus according to any one of aspects 1-18, wherein at least one of the second group of power switch units includes: a first input coupled to a first output of a control circuit, a first output of a first power switch unit in the first group and a second output of a first power switch unit in the second group; and a second input coupled to a second output of a control circuit, a second output of a first power switch unit in the first group and a third output of a first power switch unit in the second group.

[0104] Aspect 20: A method comprising: propagating a first control signal via a first group of cascaded power switch units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and propagating the first control signal via at least one power switch unit of a second group coupled between a first pair of power switch units in the first group to couple the first power rail to the second power rail.

[0105] Aspect 21: According to the method of aspect 20, the propagation of the first control signal includes propagating the first control signal from a first output of the control circuit to a first input of the control circuit.

[0106] Aspect 22: The method according to aspect 21 further includes transmitting a second control signal from the second output of the control circuit to the second input of the control circuit via a first set of cascaded power switch units, so as to sequentially couple the first power rail to the second power rail.

[0107] Aspect 23: The method according to any one of aspects 20-22, wherein the second group of at least one power switch unit includes a second group of cascaded power switch units, and wherein propagating the first control signal via the second group of at least one power switch unit includes propagating the first control signal via the second group of cascaded power switch units to sequentially couple the first power rail to the second power rail.

[0108] Aspect 24: The method according to any one of aspects 20-23, wherein the second group of at least one power switch unit includes a group of parallel power switch units, and wherein propagating the first control signal via the second group of at least one power switch unit includes propagating the first control signal via the group of parallel power switch units to sequentially couple the first power rail to the second power rail.

[0109] Aspect 25: An apparatus comprising: means for transmitting a first control signal via a first set of cascaded power switch units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and means for transmitting the first control signal via at least one power switch unit of a second set coupled between a first pair of power switch units in the first set to couple the first power rail to the second power rail.

[0110] Aspect 26: The apparatus according to aspect 25, wherein the component for propagating the first control signal includes a component for propagating the first control signal from a first output of the control circuit to a first input of the control circuit.

[0111] Aspect 27: The apparatus according to aspect 25 or 26, wherein the second group of at least one power switch unit includes a second group of cascaded power switch units, and wherein the means for transmitting a first control signal via the second group of at least one power switch unit includes means for transmitting the first control signal via the second group of cascaded power switch units to sequentially couple the first power rail to the second power rail.

[0112] Aspect 28: An apparatus according to any one of aspects 25-27, wherein the second group of at least one power switch unit comprises a group of parallel power switch units, and wherein the means for transmitting a first control signal via the second group of at least one power switch unit comprises means for transmitting the first control signal via the second group of parallel power switch units to sequentially couple the first power rail to the second power rail.

[0113] Aspect 29: A wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; a signal processing core coupled to the transceiver; a first power rail; a second power rail coupled to the signal processing core; a control circuit including a first input and a first output; a first set of cascaded power switch units coupled to the first and second power rails, wherein the first set of power switch units is cascaded from a first output of the control circuit to a first input of the control circuit; and a second set of at least one power switch unit coupled to the first and second power rails, wherein the second set of at least one power switch unit is coupled to one of: a first node between a first pair of power switch units in the first set, a first output of the control circuit, and a first input of the control circuit.

[0114] Aspect 30: A wireless communication device according to aspect 29, wherein the second group of at least one power switch unit includes a second group of cascaded power switch units extending from one of the following: a first node, a first output of a control circuit and a first input of a control circuit.

[0115] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but rather to be given the widest scope consistent with the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0009] Figure 1A shows a block diagram of an exemplary integrated circuit (IC) power supply system according to one aspect of the present disclosure.

[0010] Figure 1B shows a graph depicting the current and voltage time response associated with the IC power system of Figure 1A according to another aspect of this disclosure.

[0011] Figure 2A shows a block diagram of an exemplary power gate circuit according to another aspect of the present disclosure.

[0012] Figure 2B shows a graph depicting the control signal, current, and voltage response relative to time in relation to the power supply gate circuit of Figure 2A, according to another aspect of this disclosure.

[0013] Figure 3 shows a schematic diagram of an exemplary power switch unit according to another aspect of the present disclosure.

[0014] Figure 4 shows a block diagram of another exemplary power gate circuit according to another aspect of the present disclosure.

[0015] Figure 5 shows a schematic diagram of another exemplary power switch unit according to another aspect of the present disclosure.

[0016] Figure 6 shows a block diagram of yet another exemplary power gate circuit according to another aspect of the present disclosure.

[0017] Figures 7A to 7B collectively show block diagrams of yet another exemplary power gate circuit according to another aspect of the present disclosure.

[0018] Figure 8 shows a schematic diagram of yet another exemplary power switch unit according to another aspect of the present disclosure.

[0019] Figure 9 shows a schematic diagram of yet another exemplary power switch unit according to another aspect of the present disclosure.

[0020] Figure 10 shows a flowchart of an exemplary method for supplying power to a circuit according to another aspect of this disclosure.

[0021] FIG11 shows a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure.

Claims

1. An apparatus for reducing wake-up time and power leakage, comprising: First power rail; Second power rail; control circuit, including first input and first output; A first set of power switch units is coupled to the first power rail and the second power rail, wherein the first set of power switch units is cascaded to propagate a control signal from the first output to the first input of the control circuit, wherein the first set of power switch units responds to the control signal to electrically couple the first power rail to the second power rail. A second group of at least one power switch unit is coupled to the first power rail and the second power rail, wherein the second group of at least one power switch unit is coupled to one of the following: a first node between a first pair of power switch units in the first group, the first output of the control circuit, and the first input of the control circuit, wherein the second group of at least one power switch unit responds to the control signal to electrically couple the first power rail to the second power rail, wherein the second group of at least one power switch unit includes a second group of cascaded power switch units extending from one of the following: the first node, the first output of the control circuit, and the first input of the control circuit; And a third group of at least one power switch unit coupled to the first power rail and the second power rail, wherein the third group of at least one power switch unit is coupled to a second node between the second pair of power switch units in the second group.

2. The apparatus according to claim 1, wherein a first subset of the first set of cascaded power switch units extends in a direction substantially orthogonal to the direction in which the second set of cascaded power switch units extend.

3. The apparatus according to claim 2, wherein the second subset of the first set of cascaded power switch units extends in a direction substantially parallel to the direction in which the second set of cascaded power switch units extend.

4. The apparatus according to claim 1 further includes a third group of at least one power switch unit coupled to the first power rail and the second power rail, wherein the third group of at least one power switch unit is coupled to a second node between the second pair of power switch units in the first group.

5. The apparatus according to claim 4, wherein the third group of at least one power switch unit comprises a third group of cascaded power switch units extending from the second node.

6. The apparatus according to claim 1, wherein the third group of at least one power switch unit is not preceding the other power switch units.

7. The apparatus according to claim 1, wherein the second set of cascaded power switch units includes a power switch unit that is not preceding other power switch units.

8. A method for reducing wake-up time and power leakage, comprising: A first control signal is transmitted via a first set of cascaded power switch units to sequentially couple the first power rail to the second power rail, wherein the second power rail is coupled to the circuit. The first control signal is transmitted via at least one power switch unit in a second group coupled between the first pair of power switch units in the first group to couple the first power rail to the second power rail.

9. The method according to claim 8, wherein propagating the first control signal includes propagating the first control signal from a first output of the control circuit to a first input of the control circuit.

10. The method according to claim 9 further includes propagating a second control signal from a second output of the control circuit to a second input of the control circuit via the first set of cascaded power switch units, so as to sequentially couple the first power rail to the second power rail.

11. The method according to claim 8, wherein the second group of at least one power switch unit comprises a second group of cascaded power switch units, and wherein propagating the first control signal via the second group of at least one power switch unit comprises: The first control signal is transmitted via the second set of cascaded power switch units to sequentially couple the first power rail to the second power rail.

12. An apparatus for reducing wake-up time and power leakage, comprising: A component for transmitting a first control signal via a first set of cascaded power switch units to sequentially couple a first power rail to a second power rail, wherein the second power rail is coupled to a circuit; and a component for transmitting the first control signal via at least one power switch unit in a second set coupled between a first pair of power switch units in the first set to couple the first power rail to the second power rail.

13. The apparatus according to claim 12, wherein the component for transmitting the first control signal comprises: A component for propagating the first control signal from the first output of the control circuit to the first input of the control circuit.

14. The apparatus according to claim 12, wherein the second group of at least one power switch unit comprises a second group of cascaded power switch units, and wherein the component for transmitting the first control signal via the second group of at least one power switch unit comprises: A component for transmitting the first control signal via the second set of cascaded power switch units to sequentially couple the first power rail to the second power rail.

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