Flip-chip ball grid array-type integrated circuit package for very high frequency operation, and printed circuit board comprising the same

Abstract

This invention relates to a ball array flip-chip integrated circuit package (2), wherein: the lower side of the package includes a plurality of receiver pads (15, 26) for signal, ground and solder balls; a stack of signal vias (11, 13) and ground vias (22) electrically connected to the respective receiver pads vertically passes through the dielectric (6) of the package, thereby forming a quasi-coaxial structure. In an upper portion of the package: the signal vias (11, 13) are electrically connected to a small number of signal conductive bumps (9) protruding from the upper surface of the dielectric of the package; and at least two ground vias (22) are connected to the respective ground conductive bumps (20) by means of conductive protrusions (30), thereby forming a ring around the signal conductive bumps (9).

Description

[Technical Field]

[0001] Field of Invention

[0002] This invention belongs to the field of integrated circuit packaging. More specifically, it relates to a flip-chip ball grid array (FCBGA) type package, that is, a package suitable for carrying flip-chip (FC) and connecting to a printed circuit board via an array of solder balls called a ball grid array (BGA). [Previous Technology]

[0003] Background of the Invention

[0004] Ball grid array (BGA) is a type of surface-mount package used for integrated circuits. BGA packages have more interconnect leads than flat or dual in-line packages (DIPs) because the entire bottom surface of the device, not just the periphery, can be used for interconnection. Interconnects can also be shorter than in other package types, resulting in lower parasitic inductance and thus better high-frequency performance.

[0005] Flip die (FC) technology is a process for interconnecting integrated circuits (or "electronic chips") to external circuits by means of solder bumps deposited on pads located on the upper surface of a wafer. Solder bumps are deposited on the wafer pads during the final stage of wafer fabrication. The wafer is then flipped so that its top side is facing down and aligned so that the bumps are aligned with corresponding pads on the external circuitry; the bumps are then melted to complete the interconnection. This contrasts with wire bonding, in which the wafer is mounted vertically and wires are used to interconnect the wafer pads to the external circuitry. Compared to conventional bridging techniques, this method allows for further miniaturization and reduction of parasitic inductance, resulting in better high-frequency performance.

[0006] The FCBGA package combines two technologies: on its lower side, it carries an array of solder balls to allow interconnection to external circuitry (typically a printed circuit board), and on its upper side, it has conductive bumps to interconnect to flip-chip.

[0007] The spacing of flip-chip interconnect bumps is much smaller than the spacing of solder balls in a BGA array. The FCBGA package must manage this step change without causing impedance interruptions that would be detrimental to proper operation at extremely high frequencies (1 GHz or higher, or even 10 GHz or higher).

[0008] US 9,059,490 relates to an FCBGA package designed to operate at up to 60 GHz. The package carries "signal" balls surrounded by "ground" balls on its lower side; these signal balls are connected to the center conductor of a microstrip transmission line carried by a printed circuit board, and the ground balls are connected to their ground conductors. Vertical interconnects ("vias") passing through the dielectric of the package and exposed on its upper surface connect to the balls; a set of vias thus forms a quasi-coaxial structure well-suited for transmitting microwave signals. The center via connects to the signal conductor of the stripline transmission line carried by a ceramic substrate, and the peripheral vias connect to the ground plane of this transmission line. Another smaller-diameter quasi-coaxial structure through the vias in the ceramic substrate connects this line to a flip-chip fixed to the lower side of the ceramic substrate, which protrudes laterally from the dielectric of the package. The use of a transmission line interconnecting the two quasi-coaxial structures of the vias allows for adjustment of the spacing between the BGA array and the flip-chip, but at the cost of some manufacturing complexity and relatively significant size.

[0009] US 6,891,266 and US 2006 / 0038633 relate to FCBGA packages with quasi-coaxial structures including through-holes that connect an array of solder balls on the lower side of the package to planar transmission lines on the upper surface of the package. Similarly, the need to provide planar transmission lines on the upper surface of the package increases the package size.

[0010] The present invention aims to completely or partially overcome the aforementioned disadvantages of the prior art. More specifically, it aims to provide a simpler and / or smaller FCBGA package while ensuring operation at frequencies that may exceed 10 GHz or even 20 GHz, for example up to 59 GHz. [Summary of the Invention]

[0011] Summary of the Invention

[0012] According to the present invention, this objective is achieved by using a quasi-coaxial structure with vias of reduced diameter in the upper portion of the package to correspond to the spacing between the interconnect bumps of the flip chip. Furthermore, signals are carried by a plurality of vias at the center of the structure, the number of which and the diameter of the vias are simultaneously reduced, thus maintaining constant impedance. In this way, the variation in spacing occurs within a set of vias without traversing transmission lines, thereby reducing the complexity and size of the package while maintaining good performance at extremely high frequencies.

[0013] According to a first aspect of this disclosure, a flip-chip ball grid array type integrated circuit package is provided, comprising a dielectric having an upper surface and a lower surface, wherein: the lower surface of the dielectric includes a plurality of receiving pads for connection purposes, including a central signal receiving pad and a peripheral ground receiving pad surrounding the signal receiving pad; a plurality of stacked signal vias electrically connected to the signal receiving pads and vertically passing through the dielectric; a plurality of stacked ground vias electrically connected to ground receiving pads, vertically passing through the dielectric and forming a ring around the signal vias; characterized in that, in the upper portion of the dielectric: the signal vias are electrically connected to a smaller number of signal conductive bumps protruding from the upper surface of the dielectric; and at least two ground vias are connected to respective ground conductive bumps via conductive protrusions, the ground conductive bumps protruding from the upper surface of the dielectric and forming a ring around the signal conductive bumps.

[0014] The number of signal conductive bumps protruding from the upper surface of the dielectric can be less than the number of signal vias stacked through the dielectric.

[0015] The conductive protrusions may extend from at least two grounding vias toward the signal vias.

[0016] A smaller number of signal conductive bumps may include one or more signal conductive bumps.

[0017] According to a specific embodiment of the present invention:

[0018] The dielectric may be composed of stacked dielectric layers.

[0019] Conductive ground planes may be disposed among at least some of the dielectric layers, the ground planes having openings having substantially the same diameter and aligned in a vertical direction perpendicular to the ground planes; a stack of signal vias electrically connected to a signal receiving area may pass vertically through the dielectric layers corresponding to the central area of ​​the openings of the ground planes; a stack of ground vias electrically connected to a ground receiving pad may pass vertically through the dielectric layers outside the openings of the ground planes; and ground vias connected to individual conductive bumps by means of conductive protrusions may be located on either side of the openings of the ground planes. In this case, all ground vias may be connected by means of the conductive protrusions to individual conductive bumps located inside the openings.

[0020] Signal vias can be interconnected by conductive bridges.

[0021] The stack of ground vias may not extend through the lower portion of the package, and the electrical connection to the ground receiving pad is provided by other stacks of vias, thereby forming a ring around the signal via with a diameter larger than the ring formed by the ground via.

[0022] The dielectric can be made of ceramic or organic materials.

[0023] The package may include a single signal conductive bump.

[0024] The diameter of the opening of the ground plane, the number of signal vias stacked, the diameter of the ring around the signal via, the number of ground conductive bumps, and the diameter of the ring formed by these final shapes around the signal bumps can be selected to ensure impedance continuity between the receiving pad for the solder ball and the conductive bump protruding from the upper surface of the self-dielectric.

[0025] The package can carry a semiconductor flip-chip, which is electrically connected to a conductive bump protruding from the upper surface of the self-dielectric.

[0026] According to another aspect of this disclosure, a printed circuit board is provided, which includes a signal conductor and at least one ground plane to form a transmission line for microwave signals. The integrated circuit board carries a package according to the first aspect, wherein the signal receiving pad of the package is connected to the signal conductor by means of solder balls, and the ground receiving pad of the package is also connected to the ground plane by means of solder balls.

Implementation Method

[0037] Detailed Description of Preferred Embodiments

[0038] Figure 1 shows an FCBGA package 2, which is mounted on a printed circuit board (PCB) 5 by means of a solder ball array 4 on its lower side and carries a flip-chip 1 on its upper surface.

[0039] Figures 2, 3 and 4 show three cross-sectional views of the package 2 made of ceramic material according to the first embodiment, respectively, according to sections AA, BB and CC. Figure 5 is a transparent view of the same package 2.

[0040] The PCB 5 includes a dielectric 7, inside which a signal line 18 is disposed. The signal line is positioned between an upper ground plane 29a on the upper surface of the PCB and a lower ground plane 29b on the bottom surface of the PCB, and is framed by a shielded via 21 connecting the two ground planes. The signal line 18 is connected via a microvia 17 to an interconnect area ("pad") 19 located on the upper surface of the PCB and insulated from the ground planes; a so-called "signal" solder ball 16 is disposed on this interconnect pad 19. A so-called "ground" solder ball 27 is disposed on the upper ground plane 29a to surround the signal ball 16. Corresponding to the ground ball 27, a ground via 28 connects the upper ground plane 29a to the lower ground plane 29b.

[0041] The main body of package 2 is composed of a stack of dielectric layers (ceramic material in the embodiments of Figures 2 to 4). Optionally, all or some of these dielectric layers, especially the upper dielectric layer of the stack, carry a conductive ground plane 23 on its upper surface. These conductive ground planes have a vertically aligned central opening 31. The lower side of package 2 carries conductive receiving pads corresponding to solder balls: a central signal receiving pad 15 for interconnection with signal balls 19 and a peripheral ground receiving pad 26 surrounding the signal receiving area 15 intended for interconnection with ground balls 27. The upper surface of the package carries conductive bumps 9, 20 intended to allow interconnection with the working surface 8 of flip-chip 1. More specifically, one or more signal conductive bumps 9 are surrounded by ground conductive bumps 20. Through-holes extending through the dielectric stack connect one or more signal conductive bumps 9 to the signal receiving pad 15 on the lower side and connect the ground conductive bumps 20 to the ground receiving pads 26. The space between the upper surface of package 2, the conductive bumps and the chip 1 is filled with "underfill" resin 10.

[0042] Signals propagating along signal lines 18 are vertically and directly transmitted to the wafer 1 via a plurality of stacked signal vias 11. In the illustrated embodiment, two stacked signal vias are interconnected by means of conductive bridges 12. In the upper portion of the stack (i.e., in the upper dielectric layer), these vias, identified by reference numeral 13, have a reduced radius for feasibility reasons.

[0043] The use of unnecessary bridges 12 increases the resonant frequency that limits the interconnect RF bandwidth. This resonance is generated by signal bounce between potential impedance faults at the intersection of the PCB package interface and the package chip interface, and then functions as a resonant cavity via surface current density markers rotating about a horizontal axis inside multiple signal vias 11. In effect, these bridges reduce the volume of the resonant cavity and thus the wavelength of the resonant frequency, thereby increasing the maximum operating frequency of the package.

[0044] The stack of signal vias 11 is surrounded by an ideal concentric ring, which consists of a plurality of stacked ground vias 22, eight of which are shown in the illustrated embodiment. The number of stacks of signal vias 11 and the diameter (more generally, the lateral dimension) of the ring of stacked ground vias 22 are selected such that the characteristic impedance of the quasi-coaxial structures 11, 22 is substantially the same as the impedance of the transmission lines 18, 29a, 29b, typically 50 ohms. More specifically, for a given value of characteristic impedance, the higher the number of stacks of signal vias 11, the farther apart the stacks of ground vias 22 should be.

[0045] If the dielectric layer of the package carries a ground plane 23 having a center opening 31 , then the stack of grounding through holes 22 is located outside of such openings, such as in positions tangent to their edges. On the other hand, the stacking of signal through holes 11 can be seen in the center of those openings.

[0046] The separation between the conductive ground bumps 20 corresponding to the lining on the action surface 8 of the chip 1 (not shown) is usually more closely spaced than the stacks of the ground through holes 22 . If this is not the case, the surface area of ​​the wafer will have to increase unnecessarily, which will increase the cost. As can be seen in Fig. 3 , the stacking of ground through holes 22 stops before reaching the top layer (or more generally, the group of top layers) of the dielectric stack. This last layer is traversed by a ground through hole 24 which also forms a ring around the signal through hole 11 , but having a smaller diameter to correspond to the positioning of the respective linings on the action surface 8 of the wafer 1 . More specifically, the via 24 is located inside the opening 31 of the ground plane 23, between the upper dielectric layer and the dielectric layer immediately below it, and is connected to this ground plane (or to the upper end of the stack connected to the via 22) by conducting protrusions 30 . The ground conducting bump 20 is configured corresponding to the upper end of the through hole 24 .

[0047] The narrowing of the torus of the ground through hole tends to reduce the characteristic impedance of the quasi-coaxial structure. To avoid impedance breakdown, a single signal conducting bump 9 is placed on the bridge 12 of the top layer (more usually, a smaller number of signal bumps 9 will be present compared to the stacking of signal through holes 11 ).

[0048] The decoupling of the radius of the ring of the ground through hole 24 on the upper portion of the body of the package and the radius of the ring of the ground through hole 22 on the center portion of the body of the package thus makes it possible to avoid impedance faults near the interconnects of the wafer. It should be noted that the electrical connection between the ground through hole 22 and the ground through hole 24 is formed by small width copper (protrusion 30 ) to avoid creating a capacitive fault (reduced capacitive impedance) that will result from the narrowing of the opening 31 and thus the proximity between the ground plane 23 and the signal through hole 11 .

[0049] In the lower portion of the package, the ring of the ground through hole 22 of the center portion gives way to another ring of the ground through hole 25 having a larger diameter. On the one hand, this enables alignment relative to the spacing of the grounding earth 27 and, on the other hand, compensates for the capacitive failure caused by the proximity between the receiving lining 26 of the grounding earth and the receiving lining 15 of the signal ball;

[0050] Figures 6 and 7 show two cross-sectional views of the package 2 made of organic material according to the second embodiment, respectively, according to sections AA and BB. Figure 8 is a transparent view of the same package.

[0051] As in the case of the ceramic package shown in Figures 2 to 5, the main body of the package is composed of a stack of dielectric layers, this time made of organic materials. More specifically, it is possible to distinguish between a central portion 34 composed of a thicker layer or even a single thick layer and an upper end portion and a lower end portion 33 composed of thinner layers. The solder mask layer 32 may cover the upper and lower surfaces, exposing only the electrical interconnection areas.

[0052] Compared to the embodiment made of ceramic material, the package made of organic material in Figures 6 to 8 may have receiving pads 15, 26 for smaller solder balls. For this reason, it is not necessary to provide an enlarged ring of ground vias in the lower portion of the package. In the upper portion of the package, signals can be transmitted via a single stack of vias 13.

[0053] The vias 22, 11 through the package made of organic material can be produced by laser ablation (as described) or mechanically. Various stacks of ground vias 25, 24 and signal vias 13, 11 can be decomposed so that the vias are not strictly stacked, but slightly offset relative to their counterparts in the top and / or bottom layers, ideally offset by the diameter of the capture pad, to improve assembly reliability and, more specifically, improve thermomechanical stress resistance. Figure 9 illustrates such a stacking structure of vias 200 (which may include a stack of ground vias 25, 24 and / or signal vias 13, 11).

[0054] Certain features of the package shown in Figures 6 to 8 are not directly derived from the use of organic materials, but rather constitute design choices. Essentially, this involves larger, square openings in the ground plane, and specifically, only some ground solder bumps are closer to the signal solder bumps, while other ground solder bumps form rings with the same lateral dimensions as the quasi-coaxial structure of via 22. More specifically, three ground solder bumps on either side of signal bump 9 are positioned closer to signal bump 9 (it would be preferable to "split" [or duplicate] one ground solder bump to provide a path for the signal line, rather than simply placing two ground solder bumps together). The size of the interconnects (determining the number of ground bumps closer to the signal bump and the precise location of the ground bumps) must be set in a manner that ensures the continuity of characteristic impedance between the PCB and the flip-chip.

[0055] The invention has been described with reference to two specific embodiments, but variations are possible. Different dielectric and conductive materials can be implemented, and different manufacturing techniques can be employed. The number, spacing, and relative positions of signal and ground vias in the various parts (lower, center, and upper) of the package can be determined by the designer according to the specific constraints of each application, while ensuring that there are no impedance faults throughout the interconnection process. Furthermore, the dielectric of the package can be solid, but a multilayer structure is generally preferred. Additionally, the package may not be intended to be connected to a printed circuit board via solder balls, but rather placed in an adapter "receptacle," in which case the receiving pads 15 and 26 contact the spring connector. [Simplified Explanation of the Diagram]

[0027] Other features, details and advantages of the invention will become apparent upon reading the description given with reference to the accompanying drawings, which are provided by way of example and respectively illustrate:

[0028] Figure 1 is a perspective view of the package according to an embodiment;

[0029] FIG2 is a first cross-sectional view of the package in FIG1 based on ceramic technology according to a first embodiment of the present invention;

[0030] FIG3 is a second cross-sectional view of the package in FIG1 according to the first embodiment of the present invention;

[0031] FIG4 is a third cross-sectional view of the package in FIG1 according to the first embodiment of the present invention;

[0032] FIG5 is a transparent view of the package in FIG1 according to the first embodiment of the present invention;

[0033] FIG6 is a first cross-sectional view of the package in FIG1 based on organic technology according to a second embodiment of the present invention;

[0034] FIG7 is a second cross-sectional view of the package in FIG1 according to the second embodiment of the present invention;

[0035] FIG8 is a transparent view of the encapsulation in FIG1 according to the second embodiment of the present invention; and

[0036] Figure 9 is a detailed view of the stack of through holes according to the second embodiment of the present invention.

Claims

1. A flip-chip ball grid array type integrated circuit package (2) comprising a dielectric (6) having an upper surface and a lower surface, wherein: The lower side of the dielectric includes a plurality of receiving pads (15, 26) for connecting members (16, 27), including a central signal receiving pad (15) and several peripheral ground receiving pads (26) surrounding the signal receiving pad (15); a plurality of stacked signal vias (11, 13) electrically connected to the signal receiving pads (15) and vertically passing through the dielectric (6); a plurality of stacked ground vias (22) electrically connected to the ground receiving pads (26), vertically passing through the dielectric (6) and forming a ring around the signal vias; wherein, in the upper portion of the dielectric: The signal vias (11, 13) are electrically connected to a smaller number of signal conductive bumps (9) protruding from the upper surface of the dielectric; and at least two ground vias (22) are connected to a separate number of ground conductive bumps (20) by means of a number of conductive protrusions (30), which protrude from the upper surface of the dielectric and form a ring around the signal conductive bumps (9); wherein the dielectric is composed of one of a number of dielectric layers stacked; wherein: a number of conductive ground planes (23) are disposed between at least some of the dielectric layers, the ground planes having a number of openings (31) having substantially the same diameter and aligned in a vertical direction perpendicular to one of the ground planes; The stacks of signal vias (11, 13) electrically connected to the signal receiving pad (15) vertically pass through the dielectric layer (6) corresponding to the central region of one of the openings (31) of the ground planes (23); the stacks of ground vias (22) electrically connected to the ground receiving pads (26) vertically pass through the dielectric layer (6) outside the openings (31) of the ground planes (23); and the ground vias (22) connected to the respective conductive bumps (20) by means of the conductive protrusions (30) are located on either side of the opening (31) of the ground plane; and all of the ground vias (22) are connected to the respective conductive bumps (20) located inside the opening by means of the conductive protrusions (30).

2. The package (2) of claim 1, wherein the signal vias (11) are interconnected by a plurality of conductive bridges (12).

3. The package (2) of claim 1 or 2, wherein the stack of the ground vias (22) does not extend through the lower portion of the package, and the electrical connection with the ground receiving pads (26) is provided by other stacks of vias (25) to form a ring around the signal vias (11), the diameter of the ring being larger than the diameter of the ring formed by the stack of the ground vias (22).

4. The package (2) as requested in item 3, wherein the dielectric (6) is made of ceramic material.

5. The package (2) as requested in item 1, wherein the dielectric (6) is made of an organic material.

6. The package (2) of claim 1 includes a single signal conductive bump (9).

7. The package (2) of claim 1, wherein the diameter of the openings (31) of the ground planes (23), the number of stacks of the signal vias (11), the diameter of the ring of the ground vias (22, 25) surrounding the signal vias, the number of ground conductive bumps (20), and the diameter of the ring formed by the ground conductive bumps (20) surrounding one or more signal bumps (9) are selected to ensure impedance continuity between the pads (15, 26) for the solder balls and the conductive bumps (9, 20) protruding from the upper surface of the dielectric.

8. The package (2) of claim 1 carries a flip semiconductor wafer (1) electrically connected to conductive bumps (9, 20) protruding from the upper surface of the dielectric.

9. A printed circuit board (5) comprising a signal conductor (18) and at least one ground plane (29a, 29b) to form a transmission line for a microwave signal, the printed circuit board carrying a package (2) as claimed in claim 1, wherein the signal receiving pad (15) of the package is connected to the signal conductor by means of a solder ball (16), and the ground receiving pads (26) of the package are also connected to the ground plane by means of a plurality of solder balls (27).

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