Host device, storage device, and electronic device

Abstract

This invention relates to a host device, a storage device, and an electronic device. The electronic device includes: a host device comprising: an application that requests to write data; and a file system that, in response to the application's request, generates records regarding data attributes and allocates partitions corresponding to the data based on the records; and a storage device comprising: a memory device including a plurality of memory chips; and a memory controller that receives data and records of data from the host device and controls the memory device to sequentially store data in physical regions within the memory device corresponding to partitions, wherein the memory controller can allocate superblocks including physical regions based on records, and superblocks can include a plurality of first physical regions or a plurality of second physical regions based on records, wherein a first physical region includes one or more memory blocks within a memory chip, and a second physical region includes a portion of each memory block included in different memory chips.

Description

[Technical Field]

[0001] This invention relates to an electronic device, and more specifically, to a host device, a storage device, and an electronic device. [Previous Technology]

[0002] The storage device translates logical addresses received from the host device into physical addresses and uses them; therefore, the logical regions in the host device and the physical regions of the storage device are interconnected. Therefore, in order to improve the performance of electronic devices, a new device or method is needed that can complementaryly control the host device and the storage device. [Summary of the Invention]

[0003] Embodiments of the present invention provide a host device, storage device, and electronic device capable of effectively managing each piece of data according to its characteristics.

[0004] An electronic device according to an embodiment of the present invention may include: a host device including: an application requesting to write data; and a file system that, in response to the request of the application, generates a record regarding the attributes of the data and allocates a partition corresponding to the data based on the record; and a storage device including: a memory device including a plurality of memory chips; and a memory controller receiving the data and a record of the data from the host device and controlling the memory device to sequentially store the data in physical regions in the memory device corresponding to the partitions, wherein the memory controller may allocate a superblock including the physical regions based on the record, the superblock may include a plurality of first physical regions or a plurality of second physical regions based on the record, the first physical regions including one or more memory blocks in a memory chip, and the second physical regions including a portion of each memory block included in different memory chips.

[0005] A host device according to an embodiment of the present invention may include: an application that requests to write data; and a file system that, in response to the application's request, generates a record regarding the attributes of the data and allocates a partition corresponding to the data based on the record, wherein the file system may determine a partition group including the partition based on the record, the partition group may be one or more first partition groups or one or more second partition groups, in the first partition group any one of the empty partitions in the partition group is allocated as a new partition regardless of the partition order in the partition group, and in the second partition group a new partition is allocated according to the partition order in the partition group.

[0006] A storage device according to an embodiment of the present invention may include: a memory device including a plurality of memory chips; and a memory controller, which receives data and records of the data from an external host, allocates superblocks for storing data in the memory device, and controls the memory device to sequentially store the data in physical regions included in the superblocks, wherein the superblocks may include a plurality of first physical regions or a plurality of second physical regions based on the records, the first physical regions including one or more memory blocks in a memory chip, and the second physical regions including a portion of each memory block included in different memory chips.

[0007] According to an embodiment of the present invention, the file system can respond to the application's request, generate a record about the data attributes, and allocate a partition corresponding to the data based on the record. The file system can determine a partition group including the partition based on the record. The partition group can be one or more first partition groups or one or more second partition groups. In the first partition group, any one of the empty partitions in the partition group is allocated as a new partition regardless of the partition order in the partition group. In the second partition group, a new partition is allocated according to the partition order in the partition group.

[0008] The operation method of the controller according to an embodiment of the present invention may include the steps of controlling a memory device to store first data in a first superblock and storing second data in a second superblock, wherein the first superblock may include a plurality of first regions, each first region being formed by memory blocks belonging to different memory planes disposed in a chip, the first regions being mapped to each logical region in a first logical region group arbitrarily allocated for the first data, and the second superblock may include a plurality of second regions, each second region being formed by pages belonging to different storage blocks disposed across a plurality of chips, the second regions being mapped to each logical region in a second logical region group sequentially allocated for the second data.

[0009] This technology provides a host device, storage device, and electronic device that can effectively manage each piece of data according to its characteristics.

Implementation Method

[0011] The specific structural or functional descriptions of embodiments of the present invention disclosed in this specification or application are merely illustrative of embodiments of the present invention. Embodiments of the present invention may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0012] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention.

[0013] Referring to Figure 1, the storage device 50 may include a memory device 100 and a memory controller 200. The storage device 50 may be a device that stores data under the control of a host 400, such as a mobile phone, smartphone, MP3 player, portable computer, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system. Alternatively, the storage device 50 may be a device that stores large amounts of data in one location under the control of the host 400, such as a server or data center.

[0014] Depending on the host interface used as the communication method with the host 400, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC, micro-MMC multimedia cards; SD, mini-SD, micro-SD secure digital cards; USB (Universal Serial Bus) storage devices, UFS (Universal Flash Storage) devices, PCMCIA (Personal Computer Memory Card International Association) card storage devices; PCI (Peripheral Component Interconnection) card storage devices; PCI-E (PCI-Express) card storage devices; CF (Compact Flash) cards; smart media cards; and memory sticks.

[0015] The storage device 50 can be manufactured in any of the various types of packages. For example, the storage device 50 can be manufactured in any of the various types of packages such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), and WSP (wafer-level stack package).

[0016] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0017] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0018] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0019] In embodiments, the memory device 100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, RRAM (resistive random access memory), PRAM (phase-change RAM), MRAM (magnetoresistive random access memory), or FRAM (ferroelectric random access memory). Memory devices include NAND flash memory, STT-RAM (spin transfer torque random access memory), etc. For ease of explanation, this specification assumes that memory device 100 is NAND flash memory.

[0020] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access a region selected according to the address in the memory cell array. The memory device 100 can perform operations instructed by the commands for the region selected according to the address. For example, the memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, the memory device 100 programs data into the region selected according to the address. During a read operation, the memory device 100 reads data from the region selected according to the address. During an erase operation, the memory device 100 erases the data stored in the region selected according to the address.

[0021] The memory controller 200 can control the overall operation of the storage device 50.

[0022] In this embodiment, the memory controller 200 may receive data and a logical address (LA) from the host 400. The memory controller 200 may include firmware (not shown) capable of converting the logical address (LA) into a physical address (PA), which indicates the address of a memory cell in the memory device 100 where data will be stored. Additionally, the memory controller 200 may store a logical-physical address mapping table that constitutes the mapping relationship between the logical address (LA) and the physical address (PA) in a buffer memory.

[0023] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, or erase operations according to the request of the host 400. During a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, physical addresses, and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and physical addresses. During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and physical addresses. Alternatively, the memory controller 200 can open or close a physical zone in the memory device 100 according to the request of the host 400. Opening a physical zone can be represented as creating a logical address group corresponding to that physical zone, for example, creating a mapping table for logical addresses corresponding to partitions allocated to data by the host. Closing a physical zone can indicate that no write request to store data in that physical zone will occur until an open request for that physical zone is received again. The host 400 can provide such requests to open or close physical zones as separate requests, or it can provide them together with other requests such as write requests.

[0024] In this embodiment, the memory controller 200 can generate commands, addresses, and data independently, regardless of requests from the host 400, and transmit the generated commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing programming operations, read operations, and erase operations that accompany wear leveling, read reclaim, garbage collection, etc.

[0025] In an embodiment, the memory controller 200 may include a flash translation layer. The flash translation layer can convert a logical address (LA) corresponding to a request received from the host 400 into a physical address (PA), and output the converted physical address (PA) to the memory device 100.

[0026] For example, as described above, the flash translation layer can convert a logical address (LA) corresponding to a programming request into a physical address (PA), or it can convert a logical address (LA) corresponding to a read request into a physical address (PA), or it can convert a logical address (LA) corresponding to an erase request into a physical address (PA). The flash translation layer can output the converted physical address (PA) to the memory device 100, and the memory device 100 can perform operations on the page or memory block corresponding to the physical address (PA).

[0027] In this embodiment, the memory controller 200 can receive logical addresses from the file system 420 and convert the received logical addresses into consecutive physical addresses. When consecutive physical addresses are output to the memory device 100, the memory device 100 can perform consecutive operations corresponding to the consecutive physical addresses. At this time, the consecutive physical addresses can be determined according to the type of the allocated physical region. The type of physical region will be described in more detail with reference to FIGS. 4, 12, and 13.

[0028] In an embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 400 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 400 in the buffer memory and then transfer the data temporarily stored in the buffer memory to the memory device 100.

[0029] In various embodiments, the buffer memory can serve as both operational memory and fast buffer memory of the memory controller 200. The buffer memory can store code or commands executed by the memory controller 200. Alternatively, the buffer memory can store data processed by the memory controller 200.

[0030] In an embodiment, the buffer memory may be implemented as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Memory Bus Dynamic Random Access Memory).

[0031] In various embodiments, the buffer memory may be connected to the storage device 50 externally. In this case, a volatile memory device connected to the storage device 50 externally may serve as the buffer memory.

[0032] In this embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interleaved manner to improve operational performance. The interleaved manner can be a manner in which the operations of at least two memory devices 100 overlap. Alternatively, the interleaved manner can be a manner in which the operations of multiple groups divided within a memory device 100 overlap. In this case, a group can be one or more memory die units or one or more memory plane units.

[0033] The host 400 can utilize technologies such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), and RDIMM (Registered Dual In-line Memory Module). The storage device 50 communicates with at least one of various communication methods, including DIMM (Load Reduced DIMM) and LRDIMM (Load Reduced DIMM).

[0034] In this embodiment, host 400 may include application 410. Application 410 is also referred to as an application program and may be software that executes within an operating system (OS). Application 410 may process data in response to user input. For example, application 410 may process data in response to user input and transmit a request to file system 420 for storing the processed data in memory device 100 of storage device 50.

[0035] The file system 420 can respond to a request transmitted from the application to allocate logical addresses (LAs) for the data to be stored. In an embodiment, the file system 420 can be a Log structure File System (LFS). A Log structure File System (LFS) can generate records taking into account the attributes of the input data and can allocate partitions corresponding to the data based on the records. In this case, a partition can be a set of logical addresses. Therefore, allocating a partition can represent allocating logical addresses corresponding to the corresponding data. The data in the allocated partition can be stored sequentially in the storage area of ​​the memory device 100 corresponding to the partition. For example, the Log structure File System (LFS) can be a flash-friendly file system (F2FS). A Flash-Friendly File System (F2FS) is a record-based file system designed with consideration of the characteristics of Solid State Drives (SSDs), which can increase the parallelism within the SSD by using multi-head records. Different partitions can be allocated for data that generate different records. A Log structure File System (LFS) cannot overwrite data. When data is modified, the Record Structure File System (LFS) can reallocate the logical address corresponding to the data to be modified and write the data to the corresponding physical area.

[0036] Data requested to be written by application 410 can be stored in host memory (not shown) in the host and can be flushed to storage device 50 via device interface (not shown) according to requests from the application. Host memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM.

[0037] Figure 2 is a diagram used to illustrate the memory device of Figure 1.

[0038] Referring to FIG2, the memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0039] The memory cell array 110 includes multiple memory blocks (BLK1~BLKi). The multiple memory blocks (BLK1~BLKi) are connected to the address decoder 130 via row lines (RL). The multiple memory blocks (BLK1~BLKi) are connected to the input / output circuitry 140 via column lines (CL). In an embodiment, the row lines (RL) may include word lines, source select lines, and drain select lines. In an embodiment, the column lines (CL) may include bit lines.

[0040] In an embodiment, the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes, each plane including one or more memory blocks.

[0041] Furthermore, the multiple memory blocks (BLKs) included in the memory cell array 110 can be divided into two or more super blocks (SBs). A super block (SB) can be a unit used by the control logic 150 to manage the multiple memory blocks (BLKs) included in the memory cell array 110. A super block (SB) can be a set of memory blocks (BLKs) that perform read and / or write operations simultaneously or within the same time period, or perform read and / or write operations in combination or in association; or a super block (SB) can be a set of memory blocks (BLKs) that perform read and / or write operations for a single command; or a super block (SB) can be a set of memory blocks (BLKs) that perform read and / or write operations in combination or simultaneously within the memory cell array 110. Additionally, a group of memory blocks (BLKs) that differ from each other in terms of management or operation can be referred to as a super block (SB). Each of two or more superblocks (SBs) can be the same size. That is, each of two or more superblocks (SBs) can contain the same number of memory blocks (BLKs). Alternatively, at least one of two or more superblocks (SBs) can have a different size than the others. That is, at least one superblock (SB) can contain a different number of memory blocks (BLKs) than the others. Furthermore, each of two or more superblocks (SBs) can contain two or more memory blocks (BLKs) located on the same memory chip. In contrast, each of two or more superblocks (SBs) can contain two or more memory blocks (BLKs) located on two or more different memory chips.

[0042] Each of the plurality of memory blocks (BLK1~BLKi) includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each memory cell of the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0043] In this embodiment, the voltage generation unit 120, the address decoder 130, and the input / output circuit 140 can be collectively referred to as the peripheral circuit. The peripheral circuit can drive the memory cell array 110 under the control of the control logic 150. The peripheral circuit can drive the memory cell array 110 to perform programming operations, read operations, and erase operations.

[0044] The voltage generating unit 120 is configured to generate multiple operating voltages using the external power supply voltage supplied to the memory device 100. The voltage generating unit 120 operates in response to the control of the control logic 150.

[0045] In this embodiment, the voltage generating unit 120 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generating unit 120 is used as the operating voltage of the memory device 100.

[0046] In this embodiment, the voltage generating unit 120 can generate multiple operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generating unit 120 can be configured to generate various voltages required by the memory device 100. For example, the voltage generating unit 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0047] The voltage generating unit 120 includes a plurality of pumping capacitors that receive internal power supply voltage to generate a plurality of operating voltages with different voltage levels, and the voltage generating unit 120 can selectively activate the plurality of pumping capacitors to generate a plurality of operating voltages in response to the control of the control logic 150.

[0048] The generated operating voltages can be supplied to the memory cell array 110 through the address decoder 130.

[0049] Address decoder 130 is connected to memory cell array 110 via row lines (RL). Address decoder 130 is configured to operate in response to control of control logic 150. Address decoder 130 can receive addresses (ADDR) from control logic 150. Address decoder 130 can decode block addresses in the received address (ADDR). Address decoder 130 selects at least one memory block from memory blocks (BLK1~BLKi) based on the decoded block addresses. Address decoder 130 can decode row addresses in the received address (ADDR). Address decoder 130 can select at least one word line from the word lines of the selected memory block based on the decoded row addresses. In an embodiment, address decoder 130 can decode column addresses in the received address (ADDR). Address decoder 130 can connect input / output circuitry 140 and memory cell array 110 based on the decoded column addresses.

[0050] For example, address decoder 130 may include elements such as row decoder, column decoder, address buffer.

[0051] The input / output circuit 140 may include multiple page buffers. These page buffers can be connected to the memory cell array 110 via bit lines. During programming operations, data can be stored in selected memory cells based on the data stored in the multiple page buffers.

[0052] During a read operation, data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0053] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuit 140. Control logic 150 can operate in response to commands (CMDs) transmitted from external devices. Control logic 150 can generate control signals in response to commands (CMDs) and addresses (ADDRs) to control peripheral circuits.

[0054] Figure 3 is a diagram used to illustrate the memory cell array of Figure 2.

[0055] Referring to Figure 3, the memory cell array 110 may include more than one memory chip, and each memory chip may include more than one plane, which includes more than one memory block. Although Figure 3 shows the memory cell array 110 including four memory chips (DIE#0, DIE#1, DIE#2, DIE#3), the number of memory chips is not limited to this. Multiple memory chips can transmit to or receive from the memory controller through multiple channels, and each channel can be connected to more than one memory chip. For example, if a channel is connected to a memory chip, a memory chip can receive one command at a time, and the planes included in a memory chip can process the commands received by the memory chip in parallel.

[0056] FIG4 is a diagram illustrating the partition allocation in a host device and the physical zone allocation in a storage device according to an embodiment of the present invention.

[0057] Referring to FIG4, the file system 420 of the host device can generate a record of data attributes in response to a request to write data from application 410, and allocate a partition corresponding to the data based on the record. A partition can be a group of multiple logical addresses, and allocating a partition corresponding to data can mean allocating some or all of the multiple logical addresses included in the partition to the data. In one embodiment, the multiple logical addresses corresponding to a partition can be consecutive logical addresses. Alternatively, the multiple logical addresses corresponding to a partition can be non-consecutive, but information about the logical addresses included in each partition can be stored in the host's memory or the memory of a storage device, and the logical addresses of each partition can be managed. Furthermore, the file system 420 can determine a partition group including partitions based on the record allocated to the data. A partition group can include multiple partitions, and the logical addresses included in the partitions within a partition group can be consecutive. Alternatively, the logical addresses included in the partitions within a partition group can be non-consecutive, but information about the logical addresses included in each partition group can be stored in the host's memory or the memory of a storage device, and the logical addresses of each partition can be managed. In one embodiment, a partition group may include a first partition group and a second partition group. In the first partition group, the file system allocates any empty partition in the partition group as a new partition, regardless of the partition order in the partition group. In the second partition group, the file system allocates new partitions according to the partition order in the partition group.

[0058] Additionally, the host 400 can provide data allocated by the file system 420 to the storage device 50, including records and partitions. In one example, data can be provided to the storage device 50 through a device interface (not shown) in the host 400. The file system 420 can divide and manage the memory device 100 in the storage device 50 into multiple areas. In one embodiment, the file system 420 can divide the storage space in the memory device 100 into a checkpoint area, a segment information table (SIT), a node address table (NAT), a segment summary area (SSA), and a main area. The checkpoint area can store checkpoints. A checkpoint is data that saves the state of the system up to the logical break point when a system interruption event such as a sudden power off occurs during the operation of the computing system, and data can be recovered using the checkpoint. The segment information table (SIT) can include valid page information for each segment. The Node Address Table (NAT) may include the identifier of each node in the index tree of the files stored in the memory device 100 and the physical address corresponding to each node identifier. The Segment Summary Area (SSA) may include summary information of each segment of the main area, as described later. The main area may be a space for storing various directory information, data, file information, etc., used by actual users. In this specification, all data and information stored in the main area are defined as data. At this time, the data stored in the main area can be classified as nodes or data according to their type. A node may represent an inode or an index, while data may represent a directory or user file data. In addition, the stored data can be classified according to temperature, and the temperature of the data can be classified as hot, warm, and cold. Therefore, the file system 420 can classify the data as hot nodes, warm nodes, cold nodes, hot data, warm data, cold data, etc., and the data can be stored in the main area after being allocated records. Therefore, the main area can be divided into virtual areas corresponding to the partitions allocated by the file system 420, and each virtual area can be allocated specific records. Furthermore, such virtual regions can be grouped and classified into virtual region groups corresponding to partition groups determined by the file system 420. Additionally, each virtual region can include multiple segments, and data can be stored sequentially within each segment. In this case, a segment can correspond to one or more logical addresses.Such virtual regions can be physically implemented in host memory (not shown) or buffer memory devices (not shown) of storage devices, or logically implemented by managing information about the logical addresses included in each partition and each group of partitions in host memory or buffer memory devices.

[0059] The storage device 50 may include a memory controller 200 and a memory device 100, and the memory controller 200 may include a region management unit 210 and a flash conversion layer 220.

[0060] The memory controller 200 can receive data from the host 400. The data can be data that has been allocated records and partitioned by the file system 420. The region management unit 210 can allocate superblocks for storing data based on the records of the received data. A superblock can include multiple physical regions. Since the form of the physical regions included therein varies depending on the type of superblock, allocating a superblock can determine the form of the physical regions for storing data. That is, it can be determined which physical region should be included in a first physical region that includes more than one memory block in a memory chip and a second physical region that includes a portion of each memory block included in different memory chips. At this time, a superblock that includes multiple first physical regions can be called a first superblock, and a superblock that includes multiple second physical regions can be called a second superblock. At this time, the data stored in the first superblock can be data that has been allocated partitions in a first partition group by the file system 420, and the data stored in the second superblock can be data that has been allocated partitions in a second partition group.

[0061] The area management unit 210 may provide information about the type of physical area where data is to be stored to the flash conversion layer 220, and the flash conversion layer 220 may convert the logical address of the data in the allocated partition into a physical address based on this. In one embodiment, the data in the allocated partition may be assigned logical addresses included in the partition, and the flash conversion layer 220 may convert the logical address of the data to be stored into a consecutive physical address in the physical area determined by the area management unit 210.

[0062] The flash conversion layer 220 can transmit the converted entity address to the area management unit 210, and the area management unit 210 can control the memory device 100 to store the data in the received entity address.

[0063] Figure 5 is a diagram illustrating the structure of partitions allocated by the file system.

[0064] Referring to Figure 5, a partition may include multiple logical addresses. The logical addresses included in a partition may be consecutive or non-consecutive addresses. Allocating a partition to data may indicate that logical addresses within the partition have been allocated. Information about the addresses included in each partition may be included in the memory of the host or the memory of the storage device. Logical addresses may be allocated sequentially according to the size of the data to be written. For example, when there is a write request for data D1 and D2 of a specific size and the partitions in Figure 5 are allocated to data D1 and D2, logical addresses LA1 to LA3 may be allocated to D1, and logical addresses LA4 and LA5 may be allocated to D2.

[0065] Figure 6 is a diagram illustrating the allocation process of a new partition in a first partition group according to an embodiment of the present invention.

[0066] Referring to Figure 6, a partition group in which new partitions can be allocated regardless of the partition order within the partition group can be defined as a first partition group 421a. In this case, the logical addresses of the partitions included in the partition group can be contiguous, and the logical addresses can increase as the partition number in the partition group increases. Therefore, the partition order can represent the partition number order within the partition group, which can represent the order in which the logical addresses increase. Alternatively, the logical addresses of the partitions included in the partition group can be discontinuous. In this case, the partition order can be determined based on the partitions stored in separate memory and information about the logical addresses included in each partition group. In the case of the first partition group 421a, since partitions and logical addresses can be allocated regardless of the partition order, the third partition (partition #3) can be allocated first, and all logical addresses in the third partition can be allocated, so that the first partition (partition #1) can be allocated after the partition becomes a full section, and logical addresses for new data can be allocated. When all logical addresses of the first partition, which is an open section, are allocated to data and the first partition becomes a full partition, the file system 420 can allocate either the zeroth partition (partition #0) or the second partition, which is an empty section, as a new partition, and can allocate the logical addresses included therein to data.

[0067] Figures 7A and 7B are diagrams illustrating the allocation process of new partitions in a second partition group according to an embodiment of the present invention.

[0068] Referring to Figures 7A and 7B, a partition group that allocates new partitions according to the partition order in the partition group can be defined as a second partition group 421b. As shown in Figure 7A, in the second partition group, the zeroth partition (partition #0) can be opened first, and the logical addresses included therein can be allocated to data. When the zeroth partition becomes a full partition, the first partition (partition #1), which is the next partition in the order, can be allocated as a new partition to store data. As shown in Figure 7B, when all partitions in the second partition group 421b are full partitions, the file system 420 can allocate the zeroth partition (partition #0), which is the first partition in the new second partition group, as a new partition after allocating the new second partition group 421b, and can allocate the logical addresses included therein to data. At this time, in the case of the second partition group 421b, partitions can be allocated according to the partition order in the partition group. When the third partition (partition #3), which is the last partition, is a full partition, there cannot be empty partitions in the partitions before it. Therefore, in the case of the second partition group 421b, there is no need to search for an empty partition in the partition group. If there is no next-order partition in the second partition group 421b, the file system 420 allocates a new second partition group 421b.

[0069] Figure 8 is a diagram illustrating the reset process of the first partition group according to an embodiment of the present invention.

[0070] Referring to Figure 8, in the first partition group 421a, 1) when the zeroth partition (partition #0) is reset, 2) by discarding all data corresponding to the logical addresses in the zeroth partition, the zeroth partition becomes an empty partition, completing the reset operation. Additionally, 3) when the first partition (partition #1) is reset, 4) by discarding all data corresponding to the logical addresses in the first partition, the first partition becomes an empty partition, completing the reset operation. Additionally, 5) when the second partition (partition #2) is reset, 6) by discarding all data corresponding to the logical addresses in the second partition, the second partition becomes an empty partition, completing the reset operation. That is, when a reset operation is performed on a partition included in the first partition group 421a, in response, the data corresponding to the logical addresses in that partition is discarded, so that the partition can immediately become an empty partition, thus completing the reset operation. At this time, discarding the data corresponding to the logical addresses can represent releasing the mapping relationship between logical addresses and data. A reset operation is performed when all data corresponding to logical addresses in a specific partition becomes invalid. If valid data exists, it is mapped to logical addresses in another partition. A reset operation can also be performed after invalidating the data corresponding to the relevant logical addresses. The logical addresses included in the reset partition can then be reassigned to new data. Such a reset operation can be performed by the file system.

[0071] FIG9 is a diagram illustrating the reset process of the second partition group according to an embodiment of the present invention.

[0072] Referring to Figures 4 and 9, in the second partition group 421b, 1) when the zeroth partition (partition #0) is reset, 2) the data corresponding to the logical addresses in the zeroth partition is not immediately discarded, and information indicating that the zeroth partition is ready to be reset is stored in the bitmap. Additionally, 3) when the first partition (partition #1) is reset, 4) the data corresponding to the logical addresses in the first partition is not immediately discarded, and information indicating that the first partition is ready to be reset is stored in the bitmap. Additionally, 5) when the second partition (partition #2) is reset, 6) the data corresponding to the logical addresses in the second partition is not immediately discarded, and information indicating that the second partition is ready to be reset is stored in the bitmap. Additionally, 7) when the third partition (partition #3) is reset, 8) the data corresponding to the logical addresses in the third partition is not immediately discarded, and information indicating that the third partition is ready to be reset is stored in the bitmap. 9) Therefore, when the information indicating that all partitions in the second partition group 421b are ready to be reset is stored in the bitmap, all data corresponding to all logical addresses in all said partitions is discarded, and all partitions in the second partition group 421b become empty partitions at once, thereby completing the reset operation. That is, in the case of the second partition group 421b, when only a portion of the partitions are reset, the data is not immediately discarded, so the partitions do not become empty partitions. After the reset operation is performed on all partitions in the second partition group 421b, that is, after the information indicating that all partitions are ready to be reset is stored, the data corresponding to the logical addresses of all partitions included in the second partition group 421b is discarded, so all partitions in the second partition group 421b can become empty partitions simultaneously. When the reset operation is completed, the information indicating that all partitions in the second partition group 421b are ready to be reset can be deleted. At this time, the bitmap storing the information indicating that the reset is ready can be included in any location in the storage device. At this time, discarding the data corresponding to the logical address can represent releasing the mapping relationship between the logical address and the data. When all data corresponding to logical addresses in a specific partition becomes invalid, a reset operation is performed. If valid data exists, it is mapped to logical addresses in another partition. After the data corresponding to that logical address is invalidated, a reset operation can be performed. The logical addresses included in the reset partition can then be reallocated to new data. Such a reset operation can be performed by the file system.

[0073] Figure 10 is a diagram illustrating the classification of data according to an embodiment of the present invention.

[0074] In one embodiment, data written by an application request can be classified as nodes or data according to its type, and can be classified as hot, warm, or cold according to its temperature. Therefore, the file system 420 can generate records of hot nodes, warm nodes, cold nodes, hot data, warm data, cold data, etc., for the data according to the data's attributes. For example, a hot node can be an inode or a direct node block of a directory; therefore, a hot node can be data that is overwritten or updated very frequently and has a high probability of becoming a garbage collection object. A warm node can be an inode or a direct node block of a regular file; therefore, a warm node can be data that is overwritten or updated frequently and has a fairly high probability of becoming a garbage collection object. A cold node can be an indirect node block; therefore, a cold node can be data that is overwritten and updated infrequently but has a very high probability of becoming a garbage collection object. Hot data can be a directory entry block, quota, or small file data with a size of less than 64KB; therefore, hot data can be data that is overwritten or updated more frequently than other data and has a high probability of becoming a garbage collection object. Warm data can be user-created data blocks, such as large files larger than 64KB. Therefore, warm data can be data that is frequently updated but has a low probability of becoming garbage collected. Cold data can be data moved through cleaning or garbage collection, data blocks classified as cold data by the user, or files with a specific format (ex, .db, .jpg, etc.), such as multimedia files. Therefore, cold data can be data with a low overwriting frequency and a low probability of becoming garbage collected. However, this classification of data is not limited to this method and can be modified to various standard methods including those shown in Figure 11 below. In this specification, file system cleaning can mean, from the host's perspective, ensuring an empty partition by allocating another partition to valid data corresponding to a logical address in the sacrifice partition, and then severing the relationship between the logical address in the sacrifice partition and its corresponding data. Garbage collection can mean, from the storage device's perspective, ensuring an empty physical area or empty memory block by moving valid data from the data stored in the sacrifice physical area of ​​the storage device to another physical area, and then erasing that physical area.

[0075] Referring to Figure 10, the partitions included in the first partition group can be assigned to hot nodes, warm nodes, cold nodes, and hot data, and the partitions included in the second partition group can be assigned to warm data and cold data. At this time, the hot nodes, warm nodes, cold nodes, and hot data assigned to the first partition included in the first partition group can be defined as first-class data, and the warm data and cold data assigned to the second partition included in the second partition group can be defined as second-class data. However, the classification of each data included in the first and second partition groups is not limited to that shown in Figure 10, and the data can be classified in various ways according to the settings. Preferably, the first-class data can be data with a smaller capacity, or data with a high probability of being updated or overwritten. Conversely, the second-class data can be data with a larger capacity, or data with a low probability of being updated or overwritten. Therefore, the second-class data can be data that is relatively more affected by input / output performance than the first-class data. At this time, for data classified as first-class data, a partition in the first partition group can be assigned regardless of the specific attributes of the data. Alternatively, even for the same type of data (Category I), different partitions within a single Category I partition group can be assigned depending on the data type (node ​​or data) or temperature (hot, warm, cold) attributes. Similarly, for data classified as Category II, a single partition within a single Category II partition group can be assigned regardless of the data's specific attributes. Or, even for the same type of data (Category II), different partitions within a single Category II partition group can be assigned depending on the data type (node ​​or data) or temperature (hot, warm, cold) attributes.

[0076] Figure 11 is a diagram illustrating the classification of data according to another embodiment of the present invention.

[0077] Referring to Figure 11, data can be classified according to a classification standard different from that in Figure 10. In the case of Figure 11, data is classified into hot nodes, warm nodes, hot data, warm data, and cold data. Hot nodes may include directory index nodes, file index nodes, and direct nodes; warm nodes may include indirect nodes, directory entry blocks, and allocation quantities. In addition, hot data may include small file data, warm data may include medium file data, and cold data may be large file data or file data of any size with a specific format. That is, the data classification shown in Figure 11 can be based on data type, data size, data occurrence frequency, coverage frequency, etc., to reclassify data with various attributes to be more suitable for partition groups and superblocks. Therefore, the classified hot nodes, warm nodes, and hot data can be classified as first-class data and can be assigned partitions in the first partition group, and the classified warm data and cold data can be classified as second-class data and can be assigned partitions in the second partition group. However, the data classification standard is not limited to the content described with reference to Figure 10 and the content shown in Figure 11.

[0078] FIG12 is a diagram illustrating memory block management of a storage device according to an embodiment of the present invention.

[0079] Referring to Figures 3, 4, and 12, the memory cell array 110 may include multiple memory chips, for example, it may include four memory chips (DIE#0 to DIE#3). Additionally, each memory chip may include multiple planes, and each plane may include multiple memory blocks, for example, it may include four planes (PLANE#0 to PLANE#3). The region management unit 210 may classify and manage the multiple memory blocks in the memory cell array into super blocks. A super block may include more than one physical region. A super block may be formed across multiple memory chips; for example, as shown in Figure 12, a super block may be formed across all memory chips. A super block may be divided into a first super block 111a and a second super block 111b based on the shape of the included physical regions.

[0080] The first physical region 112a included in the first super block 111a may include more than one block in a memory chip. For example, as shown in FIG12, for each memory chip, the region including one memory block included in plane 0 to plane 3 can be designated as a physical region. Therefore, the first super block 111a may include four first physical regions 112a, and each memory chip forms one first physical region 112a.

[0081] The second physical region 112b included in the second superblock 111b may include a portion of each block included in different memory chips. For example, as shown in FIG12, the second physical region 112b may be formed across all four memory chips (DIE#0~DIE#3) and may include only a portion of each memory block included in each plane. For example, as shown in FIG12, it may include only 1 / 4 of the page of each memory block included in each plane. Therefore, the second superblock 111b may be formed across all memory chips and may include four second physical regions 112b formed to include only a portion of the page of each memory block.

[0082] In one embodiment, the first superblock 111a and the second superblock 111b can be the same size. That is, the first superblock 111a and the second superblock 111b can include the same number of memory blocks. Additionally, the first physical region 112a and the second physical region 112b can be the same size. That is, the number of pages included in the first physical region 112a and the second physical region 112b can be the same. The first physical region 112a can be formed in one memory chip, while the second physical region 112b can be formed across multiple memory chips. Therefore, in the case of the second physical region 112b, it can operate in a die-interleaved manner; specifically, as shown in FIG12, when the second physical region 112b is formed across all memory chips, it can operate in a full-die interleaved manner. However, different second physical regions 112b cannot be allocated and programmed simultaneously. Furthermore, since the second physical region only includes a portion of each memory block, it cannot be erased immediately when a specific physical region needs to be erased. The physical region can only be erased when all pages of each memory block partially included in that physical region can be erased—that is, when all physical regions of the superblock including that physical region can be erased. Therefore, while the second physical region offers the advantage of interleaved operation at the memory chip level, it may not be suitable for storing data with high input / output frequencies due to limitations in programming and erasing. Therefore, by simultaneously using the first and second superblocks, smaller capacity or higher input / output frequency data can be stored in the first physical region of the first superblock, and larger capacity or lower input / output frequency data can be stored in the second physical region of the second superblock, thereby improving the performance of the electronic device.

[0083] FIG13 is a diagram illustrating the memory block management process of an electronic device according to an embodiment of the present invention.

[0084] Referring to Figures 4, 12, and 13, the file system 420 of the host 400 generates records for data requested to be written by the application 410 based on the attributes of the data, and classifies the data accordingly and determines partition groups including partitions to be allocated to the data. According to various criteria, the data can be divided into a first type of data allocated to a first partition 422a in a first partition group 421a and a second type of data allocated to a second partition 422b in a second partition group 421b. The data allocated by the file system to the first partition 422a in the first partition group 421a can be stored in a first physical region 112a in a first superblock 111a of the memory device 100 under the control of the memory controller 200, and the data allocated by the file system to the second partition 422b in the second partition group 421b can be stored in a second physical region 112b in a second superblock 111b of the memory device 100. The first partition group 421a corresponds to the first superblock 111a; therefore, the first partition 422a corresponds to the first physical region 112a. The characteristics of the first partition 422a, which can be assigned as a new partition regardless of the partition order in the partition group, conform to the characteristics of the first physical region 112a managed per memory chip. Furthermore, the first partition and the first physical region share the same characteristic: both can be reset or erased on a per-partition or per-physical-region basis. Similarly, the characteristics of the second partition 422b, which is assigned as a new partition according to the partition order in the partition group, conform to the characteristics of the second physical region 112b formed across multiple memory chips. The second partition and the second physical region share the same characteristic: neither can be reset or erased on a per-partition or per-physical-region basis. Reset or erase operations are performed on a per-partition or per-physical-region basis only after their respective second partition groups and second superblocks are in a reset or eraseable state.

[0085] The first partition 422a in the first partition group 421a can be allocated regardless of the partition order, and in response to a physical region allocation request from the host 400 to store data of the allocated partition, the region management unit 210 can allocate a first physical region 112a that forms a region in a memory chip. The second partition 422b in the second partition group 422b can be allocated according to the partition order, and in response to a physical region allocation request from the host 400 to store data of the allocated partition, the region management unit 210 can allocate a second physical region 112b that forms a region including a part of a memory block in multiple memory chips. In response to a physical region allocation request from the host 400, when the region management unit 210 replies with information that there is no additional allocable physical region in the currently used superblock, the file system 420 can allocate a partition in the new partition group after allocating the new partition group. In response, the region management unit 210 can store the data of the newly allocated partition after allocating the new superblock and the new physical region included therein. Alternatively, the file system 420 may not receive information about superblocks and entity regions from the region management unit 210, and may automatically allocate new partition groups and the partitions included in them.

[0086] FIG14 is a flowchart illustrating the process of determining the sacrificial partition for cleaning according to an embodiment of the present invention.

[0087] Referring to Figures 4 and 14, in step S1401, the cost of the candidate partitions can be calculated. The cost can be calculated using the method previously used to select the sacrifice partition. For example, it can be performed using a greedy method or a cost-benefit method. The greedy method sets a smaller cost value when the number of valid blocks corresponding to the logical addresses in the partition is minimized, and selects the partition with the fewest valid blocks as the sacrifice partition. The cost-benefit method sets the cost value by considering the modification time of the data corresponding to the logical addresses in each partition and the number of valid blocks corresponding to the logical addresses in the partition. If the modification time of the partition is long or the number of valid blocks in the partition is small, a lower cost is assigned, and such a partition can be selected as the sacrifice partition. In one embodiment, in the case of foreground cleanup, the cost of the sacrifice partition can be calculated using a greedy method, and in the case of background cleanup, the cost of the sacrifice partition can be calculated using a cost-benefit method.

[0088] In step S1403, the partition type of the candidate partition for calculating the cost can be confirmed. That is, it can be confirmed whether the partition belongs to the first partition of the first partition group or the second partition of the second partition group.

[0089] When it is determined in step S1405 that it is not the second partition, that is, when it is determined to be the first partition, as shown in step S1411, the cost calculated in step S1401 can be kept unchanged. On the other hand, when it is determined in step S1405 that it is the second partition, as in steps S1407 and S1409, the cost can be modified based on the number of partitions storing information about being ready to reset (“Ready to Reset”). The state in which a reset operation is to be performed on a specific partition belonging to the second partition group, but the reset operation cannot be completed because there are other partitions in the partition group that are not yet ready to perform the reset operation, can be defined as a ready-to-reset state. At this time, the partitions in the ready-to-reset state can store information indicating the ready-to-reset state in a separate bitmap. In step S1407, the number of all partitions ready to be reset in all partitions allocated by the file system 420 can be considered. For example, when the number of partitions ready to be reset in all partitions exceeds a threshold, the probability of the candidate partitions included in the second partition group being selected as the sacrifice partition can be increased by reducing the cost, and when it does not exceed the threshold, the cost can be maintained. Alternatively, different weights can be assigned based on the number of partitions to be reset across all partitions. Alternatively, when the number of partitions to be reset across all partitions exceeds a threshold, in step S1409, the number of partitions to be reset in the second partition group to which the partition belongs can be confirmed. When the number of partitions to be reset across all partitions does not exceed the threshold, step S1409 can be omitted. In step S1409, when the number of partitions to be reset in the second partition group to which the partition belongs exceeds the threshold, the probability of the partition being selected as a sacrifice partition can be increased by reducing the cost, and the cost can be maintained when it does not exceed the threshold. Alternatively, different weights can be assigned based on the number of partitions to be reset in the second partition group. In this case, steps S1407 and S1409 can be executed, or only one of the two steps can be executed.

[0090] After calculating and modifying the cost, the final cost value can be compared in step S1413, and the sacrifice partition used for cleaning up the partition can be determined.

[0091] In one embodiment, when performing cleanup, the timing of the next cleanup execution can be adjusted by considering the ratio of logical addresses corresponding to invalid data in all partitions. In the case of the second partition group, the logical addresses included in the partition to be reset are not logical addresses that can be allocated to new data. Therefore, the data corresponding to the logical addresses in the partition to be reset can be considered invalid data, and the timing of the next cleanup execution can be adjusted.

[0092] FIG15 is a diagram illustrating the process of allocating a new partition to valid data corresponding to a logical address in the sacrifice partition during cleanup according to an embodiment of the present invention.

[0093] Referring to Figure 15, when a sacrificial partition is selected using the same process as in Figure 14, a new partition can be assigned to the valid data corresponding to the logical address in the sacrificial partition. At this time, the new partition assigned to the valid data can be a partition included in a partition group of the same type as the partition group that includes the previously assigned partition. For example, as shown in Figure 15, hot nodes, warm nodes, cold nodes, and hot data, data classified as first-class data and assigned to the first partition in the first partition group are also assigned to the first partition in the first partition group. If there is no first partition to be assigned in the first partition group, then after assigning a new first partition group, any partition included in it can be assigned to the valid data corresponding to the logical address in the sacrificial partition. Similarly, as shown in Figure 15, warm data and cold data, data classified as second-class data and assigned to the second partition in the second partition group are also assigned to the second partition in the second partition group. If there is no second partition to be assigned in the second partition group, then after assigning a new second partition group, any partition included in it can be assigned to the valid data corresponding to the logical address in the sacrificial partition.

[0094] FIG16 is a diagram showing another embodiment of the memory controller of FIG1.

[0095] Referring to FIG16, the memory controller 1000 may include a processor 1010, internal memory 1020, error correction code circuit 1030, host interface 1040, buffer memory interface 1050 and memory interface 1060.

[0096] The processor 1010 can perform various operations for controlling the memory device 100 or generate various commands. When the processor 1010 receives a request from the host 400, the processor 1010 can generate commands according to the received request and transmit the generated commands to the queue controller (not shown). In addition, the processor 1010 can respond to a physical region allocation request from the host 400, allocate a superblock and the physical regions included therein in the memory device to store data received from the host, and can manage the allocated superblock and physical regions.

[0097] The internal memory 1020 can store various information required for the operation of the memory controller 1000. For example, the internal memory 1020 may include a logical and physical address mapping table. The internal memory 1020 can be configured as at least one of RAM (Random Access Memory), Dynamic RAM (DRAM), Static RAM (SRAM), cache, and tightly coupled memory (TCM).

[0098] The error correction code circuit 1030 is configured to detect and correct errors in data received from the memory device 100 using error correction codes (ECC). The processor 1010 can control the memory device 100 to adjust the read voltage and perform a reread based on the error detection result of the error correction code circuit 1030. In an exemplary embodiment, an error correction block may be provided as an element of the memory controller 1000.

[0099] The host interface 1040 can exchange commands, addresses, and data between the memory controller 1000 and the host 400. For example, the host interface 1040 can receive requests, addresses, data, etc. from the host 400, and can output data read from the memory device 100 to the host 400. The host interface 1040 can use interfaces such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect), PCIe (PCI express), NVMe (NonVolatile Memory Express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), and LRDIMM. The host interface 1040 communicates with the host 400 using protocols such as Load Reduced DIMM, ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics). The host interface 1040 can receive requests to allocate physical regions corresponding to partitions allocated to data by the host 400.

[0100] The buffer memory interface 1050 can transfer data between the processor 1010 and the buffer memory. The buffer memory can serve as operational memory or fast buffer memory of the memory controller 1000, and can store data used in the storage device 50. Through the processor 1010, the buffer memory interface 1050 can use the buffer memory as a read buffer, write buffer, mapping buffer, etc. According to embodiments, the buffer memory may include DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), or RDRAM (Memory Bus Dynamic Random Access Memory). When the buffer memory is included inside the memory controller 1000, the buffer memory interface 1050 can be omitted.

[0101] The memory interface 1060 can exchange commands, addresses, and data between the memory controller 1000 and the memory device 100. For example, the memory interface 1060 can transmit commands, addresses, data, etc. to the memory device 100 through a channel, and can also receive data from the memory device 100. The memory interface 1060 can transmit commands, addresses, and data to or receive commands, addresses, and data from the memory device 100 based on superblocks and physical regions allocated and managed by the processor 1010.

[0102] FIG17 is a block diagram showing a memory card system using a storage device according to an embodiment of the present invention.

[0103] Referring to FIG17, the memory card system 2000 includes a memory controller 2100, a memory device 2200 and a connector 2300.

[0104] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 may be configured to control read, program, erase, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and the host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory controller 2100 may be implemented in the same manner as memory controller 200 described with reference to FIG1. ​​For example, memory controller 2100 may allocate physical regions and superblocks including the physical regions in memory device 2200, and may control memory device 2200 on a unit basis of physical regions and superblocks.

[0105] For example, the memory controller 2100 may include components such as RAM (random access memory), processing unit, host interface, memory interface, and error correction unit.

[0106] The memory controller 2100 can communicate with an external device via the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 can be configured to communicate with external devices via at least one of various communication standards such as USB (Universal Serial Bus), MMC (MultiMedia Card), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCI express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the aforementioned communication standards.

[0107] For example, the memory device 2200 may be configured as a variety of non-volatile storage devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), and STT-MRAM (Spin Transfer Torque Magnetic RAM).

[0108] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), or a universal flash storage (UFS).

[0109] FIG18 is a block diagram illustrating a solid state drive (SSD) system using a storage device according to an embodiment of the present invention.

[0110] Referring to Figure 18, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 transmits signals to and receives signals from the host 3100 through a signal connector 3001, and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memory modules 3221-322n, an auxiliary power supply device 3230, and a buffer memory module 3240.

[0111] According to an embodiment of the present invention, the SSD controller 3210 can perform the functions of the memory controller 200 described with reference to FIG1.

[0112] The SSD controller 3210 can control multiple flash memory modules 3221~322n in response to signals received from the host 3100. The SSD controller 3210 can control multiple flash memory modules through multiple channels CH1~CHn. More than one memory chip can be connected to each channel. For example, the signal can be a signal based on the interface between the host 3100 and the SSD 3200. For example, a signal can be a signal defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (MultiMedia Card), eMMC (embedded MMC), PCI (Peripheral Component Interconnect), PCI-E (PCI express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, and NVMe.

[0113] The auxiliary power supply unit 3230 is connected to the host 3100 via a power connector 3002. The auxiliary power supply unit 3230 can receive power from the host 3100 and charge it. When the power supply from the host 3100 is unreliable, the auxiliary power supply unit 3230 can supply power to the SSD 3200. For example, the auxiliary power supply unit 3230 can be located inside or outside the SSD 3200. For example, the auxiliary power supply unit 3230 can be located on the motherboard to supply auxiliary power to the SSD 3200.

[0114] Buffer memory 3240 operates as buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memories 3221-322n, or buffer memory 3240 may temporarily store metadata (e.g., mapping tables) of flash memories 3221-322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM.

[0115] FIG19 is a block diagram showing a user system using a storage device according to an embodiment of the present invention.

[0116] Referring to Figure 19, the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0117] The application processor 4100 can drive components, operating systems (OS), user programs, or file systems included in the user system 4000. For example, the application processor 4100 may include controllers, interfaces, and graphics engines that control components included in the user system 4000. The application processor 4100 may be provided as a system-on-a-chip (SoC). The application processor 4100 can generate records for data requested to be written by the user, allocate partition groups and partitions based on the records, and provide the partitioned data to the storage module 4400.

[0118] The memory module 4200 can operate as the main memory, operating memory, buffer memory, or fast buffer memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM. For example, the application processor 4100 and the memory module 4200 may be based on POP (Package on Package) packaging and may be provided as a single semiconductor package.

[0119] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (Time Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 can be included in the application processor 4100.

[0120] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can transfer data stored in storage module 4400 to application processor 4100. For example, storage module 4400 can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash memory, NOR flash memory, or three-dimensional NAND flash memory. For example, storage module 4400 can be provided as a memory card of user system 4000 or a removable drive of an external drive.

[0121] For example, storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as memory device 100 described with reference to FIG1. ​​Storage module 4400 may operate in the same manner as storage device 50 described with reference to FIG1.

[0122] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. For example, user interface 4500 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touchpads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements. User interface 4500 may include user output interfaces such as LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) displays, AMOLED (Active Matrix OLED) displays, LEDs, speakers, and monitors.

[0123] Although the technical concept of this disclosure has been specifically described with reference to the above embodiments, it should be noted that the above embodiments are for descriptive purposes only and not for limitation. Furthermore, those skilled in the art will understand that various embodiments can be made within the scope of the technical concept of this disclosure and the appended claims. In addition, embodiments can be combined to form additional embodiments. [Simplified Explanation of the Diagram]

[0010] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention. FIG2 is a diagram illustrating the memory device of FIG1. ​​FIG3 is a diagram illustrating the memory cell array of FIG2. FIG4 is a diagram illustrating partition allocation in a host device and physical region allocation in a storage device according to an embodiment of the present invention. FIG5 is a diagram illustrating the structure of partitions allocated by a file system. FIG6 is a diagram illustrating the allocation process of new partitions in a first partition group according to an embodiment of the present invention. FIG7A and FIG7B are diagrams illustrating the allocation process of new partitions in a second partition group according to an embodiment of the present invention. FIG8 is a diagram illustrating the reset process of a first partition group according to an embodiment of the present invention. FIG9 is a diagram illustrating the reset process of a second partition group according to an embodiment of the present invention. FIG10 is a diagram illustrating data classification according to an embodiment of the present invention. FIG11 is a diagram illustrating data classification according to another embodiment of the present invention. FIG12 is a diagram illustrating memory block management of a storage device according to an embodiment of the present invention. FIG13 is a diagram illustrating the memory block management process of an electronic device according to an embodiment of the present invention. FIG14 is a flowchart illustrating the process of determining the sacrificial partition for cleanup according to an embodiment of the present invention. Figure 15 is a diagram illustrating the process of allocating new partitions to valid data corresponding to logical addresses in the sacrifice partition during cleanup, according to an embodiment of the present invention. Figure 16 is a diagram showing another embodiment of the memory controller of Figure 1. Figure 17 is a block diagram showing a memory card system using a storage device according to an embodiment of the present invention. Figure 18 is a block diagram showing a solid-state drive (SSD) system using a storage device according to an embodiment of the present invention. Figure 19 is a block diagram showing a user system using a storage device according to an embodiment of the present invention.

Claims

1. An electronic device comprising: A host device includes: an application that requests to write data; and a file system that, in response to the application's request, generates records about the attributes of the data and allocates partitions corresponding to the data based on the records; and a storage device including: a memory device including a plurality of memory chips; and a memory controller that receives the data and records of the data from the host device and controls the memory device to sequentially store the data in physical regions in the memory device corresponding to the partitions, the memory controller allocating superblocks including the physical regions based on the records, the superblocks including a plurality of first physical regions or a plurality of second physical regions based on the records, the first physical regions including more than one memory block in a memory chip, and the second physical regions including a portion of each memory block included in different memory chips.

2. The electronic device as claimed in claim 1, wherein, The file system determines, based on the record, a partition group including the allocated partition, the partition group being either a first partition group or a second partition group, the first partition group including a first partition allocated to data stored in the first physical area, and the second partition group including a second partition allocated to data stored in the second physical area.

3. The electronic device as claimed in claim 2, wherein, The records are assigned according to the type and temperature of the data.

4. The electronic device as claimed in claim 3, wherein, The data stored in the first physical area has a smaller capacity or a higher input / output frequency than the data stored in the second physical area.

5. The electronic device as claimed in claim 4, wherein, The data stored in the first entity region is any one of hot nodes, warm nodes, cold nodes, and hot data.

6. The electronic device as claimed in claim 4, wherein, The data stored in the second physical area is either warm data or cold data.

7. A host device, comprising: The application requests to write data; The file system, in response to the application's request, generates a record of the data attributes and allocates a partition corresponding to the data based on the record. The file system determines a partition group including the partition based on the record. The partition group is one or more first partition groups or one or more second partition groups. In the first partition group, any one of the empty partitions in the partition group is allocated as a new partition regardless of the partition order in the partition group. In the second partition group, a new partition is allocated according to the partition order in the partition group.

8. The host device as described in claim 7, wherein, When all the data corresponding to a specific partition becomes invalid, the file system performs a reset operation to convert the partition into an empty partition.

9. The host device as described in claim 8, wherein, When all the data corresponding to a specific partition included in the first partition group becomes invalid, the file system discards all the data, thereby completing the reset operation.

10. The host device as claimed in claim 9, wherein, When all data corresponding to a specific partition included in the second partition group becomes invalid, the file system stores information indicating that the specific partition is ready to be reset. After storing information indicating that all partitions included in the second partition group are ready to be reset, all data corresponding to all partitions is discarded, thereby completing the reset operation.

11. The host device as claimed in claim 10, wherein, The file system performs cleanup to ensure empty partitions, during which sacrificial partitions are identified and the reset operation is performed on the sacrificial partitions.

12. The host device as claimed in claim 11, wherein, The number of partitions storing information indicating the readiness to reset is used to determine the sacrifice partition.

13. The host device as claimed in claim 12, wherein, The valid data in the data corresponding to the sacrifice partition is allocated to a partition in a partition group of the same type as the partition group that includes the sacrifice partition.

14. A storage device, comprising: Memory device, comprising multiple memory chips; The system also includes a memory controller that receives data and records of the data from an external host, allocates superblocks in the memory device for storing data, and controls the memory device to sequentially store the data in physical regions included in the superblocks. The superblocks may include multiple first physical regions or multiple second physical regions based on the records. The first physical regions may include more than one memory block in a memory chip, and the second physical regions may include a portion of each memory block included in different memory chips.

15. The storage device as claimed in claim 14, wherein, The memory controller receives a record of the data to be stored from the external host and allocates the superblock based on the record.

16. The storage device as claimed in claim 15, wherein, When a write request for data is received from the host, the memory controller converts the logical address corresponding to the data into a continuous physical address within the physical region included in the superblock, based on the allocated superblock.

17. The storage device as claimed in claim 14, wherein, The second physical region is formed across all memory chips.

18. The storage device as claimed in claim 14, wherein, The number of pages included in the first entity region is the same as the number of pages included in the second entity region.

19. The storage device as claimed in claim 14, wherein, The superblock is either a first superblock that includes multiple first entity regions or a second superblock that includes multiple second entity regions, wherein the number of memory blocks included in the first superblock and the second superblock is the same.

20. The storage device as claimed in claim 19, wherein, The first superblock and the second superblock are formed across all memory chips and include one or more memory blocks included in each of the memory chips.

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