Semiconductor device with NANO sheet transistor and method for fabricating the same

Abstract

A semiconductor device capable of improving gate controllability and a method for manufacturing the same, the semiconductor device comprising: a substrate including a first buried source / drain layer and a second buried source / drain layer; a first nanosheet stack including a plurality of first nanosheets stacked in a direction perpendicular to the substrate; a second nanosheet stack including a plurality of second nanosheets stacked in a direction perpendicular to the substrate; an isolation wall disposed between the first nanosheet stack and the second nanosheet stack; a first gate covering a portion of the first nanosheet stack and extending in a direction perpendicular to the substrate; a second gate covering a portion of the second nanosheet stack and extending in a direction perpendicular to the substrate; a first common source / drain layer connected to an end of the first nanosheet and the first buried source / drain layer; and a second common source / drain layer connected to an end of the second nanosheet and the second buried source / drain layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising a nanosheet transistor and a method for manufacturing the same. Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0089089, filed on July 7, 2021, the entirety of which is incorporated herein by reference. Prior Technology

[0003] With the increasing integration of semiconductor devices, research is actively underway on semiconductor devices including multi-gate (e.g., three-gate) devices in order to further improve transistor performance. Summary of the Invention

[0004] Various embodiments of the present invention provide a semiconductor device and a method for manufacturing the same that can improve gate controllability.

[0005] A semiconductor device according to an embodiment of the present invention includes: a substrate including a first buried source / drain layer and a second buried source / drain layer; a first nanosheet stack including a plurality of first nanosheets stacked in a direction perpendicular to the substrate; a second nanosheet stack including a plurality of second nanosheets stacked in a direction perpendicular to the substrate; an isolation wall disposed between the first nanosheet stack and the second nanosheet stack; a first gate covering a portion of the first nanosheet stack and extending in a direction perpendicular to the substrate; a second gate covering a portion of the second nanosheet stack and extending in a direction perpendicular to the substrate; a first common source / drain layer connected to an end of the first nanosheet and the first buried source / drain layer; and a second common source / drain layer connected to an end of the second nanosheet and the second buried source / drain layer.

[0006] A semiconductor device according to an embodiment of the present invention includes: a substrate; a first nanoplatelet transistor array including a plurality of silicon nanoplatelets stacked in a direction perpendicular to the substrate; a second nanoplatelet transistor array including a plurality of silicon-germanium nanoplatelets stacked in a direction perpendicular to the substrate; and an isolation wall disposed between the first nanoplatelet transistor array and the second nanoplatelet transistor array, wherein the silicon nanoplatelets and the silicon-germanium nanoplatelets are disposed at different horizontal heights.

[0007] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: forming an alternating stack of a first semiconductor material and a second semiconductor material alternately disposed on a substrate; forming a first wafer stack and a second wafer stack by etching the alternating stack; forming an isolation wall between the first wafer stack and the second wafer stack; forming a buried source / drain layer in the substrate to align with the first wafer stack and the second wafer stack; removing the second semiconductor material from the first wafer stack to form a first nanosheet stack of the first semiconductor material; removing the first semiconductor material from the second wafer stack to form a second nanosheet stack of the second semiconductor material; forming a first gate and a second gate on the first nanosheet stack and the second nanosheet stack, respectively; and forming a first common source / drain layer and a second common source / drain layer respectively connected to the first nanosheet stack and the second nanosheet stack.

[0008] This invention vertically stacks nanosheet channels and forms gates around at least three surfaces of the nanosheet channels. Therefore, short-channel effects can be suppressed by improving gate controllability.

[0009] This invention vertically stacks three-dimensional nanosheet channels. Therefore, the transistors according to this invention can have a larger drive current than two-dimensional transistors. Simple Explanation of the Diagram

[0010] [Figure 1A] is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present invention.

[0011] [Figure 1B] is a schematic plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0012] [Figure 2A] is a cross-sectional view taken along line A-A' in Figure 1B.

[0013] [Figure 2B] is a cross-sectional view taken along line B-B' in Figure 1B.

[0014] [Figure 2C] is a cross-sectional view taken along line C-C' of Figure 1B.

[0015] [Figure 2D] is a detailed view of the dual-channel nanosheet.

[0016] Figures 3A to 3D are diagrams illustrating dual-channel nanosheets according to other embodiments of the present invention.

[0017] Figures 4 through 18 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] [Figure 19] is a diagram illustrating a semiconductor device according to an embodiment of the present invention. Implementation

[0019] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which serve as schematic representations of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. The various embodiments of the invention are not limited to the specific structures shown in the drawings, but include any structural variations that may arise from the manufacturing process. Furthermore, the shapes of any regions shown in the schematic drawings are intended to illustrate specific examples of the regional structures of various elements and are not intended to limit the scope of the invention.

[0020] Figure 1A is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present invention. Figure 1B is a schematic plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 2A is a cross-sectional view taken along line A-A' of Figure 1B. Figure 2B is a cross-sectional view taken along line B-B' of Figure 1B. Figure 2C is a cross-sectional view taken along line C-C' of Figure 1B. Figure 2D is a detailed view of a dual-channel nanosheet.

[0021] Referring to Figures 1A to 2D, the semiconductor device 100 may include: a substrate 101, a first transistor array TR1, and a second transistor array TR2. The first transistor array TR1 and the second transistor array TR2 may be formed on the substrate 101.

[0022] The first transistor array TR1 and the second transistor array TR2 can be spaced apart from each other by an isolation wall 110. The isolation wall 110 can extend along a first direction D1 perpendicular to the top of the substrate 101. The first transistor array TR1 and the second transistor array TR2 can be disposed along a second direction D2, with the isolation wall 110 interposed between them. The isolation wall 110 can extend relatively long along a third direction D3 to space the first transistor array TR1 and the second transistor array TR2. The isolation wall 110 is a dielectric isolation wall. For example, the isolation wall 110 can comprise silicon oxide, silicon nitride, or a combination thereof.

[0023] The first transistor array TR1 may include a plurality of first transistors. The first transistor array TR1 may include a first nanosheet stack 120N and a first gate 140. The first nanosheet stack 120N may include a plurality of first nanosheets 120.

[0024] The first nanosheet 120 can be stacked vertically on the substrate 101 in a first direction D1. That is, the first nanosheet stack 120N is a first vertically stacked nanosheet comprising a plurality of first nanosheets 120 stacked in a first direction D1 perpendicular to the substrate 101. The first gate 140 can extend vertically along the first direction D1 and cover a portion of the first nanosheet 120 (e.g., a channel). The first gate 140 can be referred to as the first vertical gate. The first gate 140 can be configured to surround (or may cover) at least three surfaces of the first nanosheet 120. Referring to Figures 2A and 2D, a single first nanosheet 120 may include four surfaces, for example, an upper surface F1, a lower surface F2 opposite to the upper surface F1, a first side surface F3, and a second side surface F4 opposite to the first side surface F3. The first gate 140 may cover the upper surface F1, the lower surface F2, and the first side surface F3 of the first nanosheet 120. The second side F4 of the first nanosheet 120 can directly contact the isolation wall 110 and may not be covered by the first gate 140. The first gate 140 may be referred to as a tri-gate or a ring gate. The tri-gate and ring gate may have structures different from those of the full-ring gate. For example, the full-ring gate has a structure that surrounds all surfaces of the nanosheet, while the tri-gate and ring gate have a structure that covers three surfaces of the nanosheet. The first transistor array TR1 may be a tri-gate nanosheet transistor array.

[0025] The first nanosheet 120 may be a single-crystal material. The first nanosheet 120 may be a semiconductor material formed by epitaxial growth. The first nanosheet 120 may include a silicon layer or a silicon-germanium layer. The first nanosheet 120 may include an oxide semiconductor material such as IGZO. Each first nanosheet 120 may have a thickness of 50 Å to 300 Å.

[0026] The first gate 140 may include a conductive stack comprising a variety of conductive materials. For example, the first gate 140 may include a stack of a first annular gate layer 141, a first inner gate liner layer 142, and a first low-resistivity gate layer 143. The first annular gate layer 141 may cover the upper surface F1, the lower surface F2, and the first side surface F3 of the first nanosheet 120. The first annular gate layer 141, the first inner gate liner layer 142, and the first low-resistivity gate layer 143 may include semiconductor materials, metallic materials, metal nitrides, metal silicides, or combinations thereof. The first annular gate layer 141 may include TiN, TiSiN, TiAlN, TiCN, TaN, TaSiN, TaAlN, or TaCN. In one embodiment, the first annular gate layer 141 may include titanium nitride, the first inner gate liner layer 142 may include polycrystalline silicon, and the first low-resistivity gate layer 143 may include tungsten. In another embodiment, the first ring gate layer 141 may include a low work function material or an N-type work function material with a work function of less than about 4.5 eV.

[0027] A first gate dielectric layer 144 may be formed between the first gate 140 and the first nanosheet 120. The first gate dielectric layer 144 may cover the surface of the substrate 101. The first gate dielectric layer 144 may include a multilayer structure disposed between the first nanosheet 120 and the first annular gate layer 141. For example, the first gate dielectric layer 144 may be a stack of a first interface layer 144A, a first high-k layer 144B, and a dipole sensing layer 144C. The first interface layer 144A may directly contact the first nanosheet 120, while the dipole sensing layer 144C may directly contact the first annular gate layer 141. A dipole may be generated between the first interface layer 144A and the first high-k layer 144B through the dipole sensing layer 144C. The first gate dielectric layer 144 may be formed to include a dipole because the first gate dielectric layer 144 includes the dipole sensing layer 144C as described above. The first interface layer 144A may include silicon oxide or silicon oxynitride, while the first high-k layer 144B may include a hafnium-based material. The first high-k layer 144B may include: HfO₂, HfON, HfSiO, HfSiON, HfZrO, or HfZrON. The dipole sensing layer 144C may include lanthanum oxide or magnesium oxide.

[0028] The first transistor array TR1 may further include a first buried source / drain layer 160 formed in the substrate 101. The first buried source / drain layer 160 may be formed on both sides of the first nanosheet stack 120N in the third direction D3 in the substrate 101. The first transistor array TR1 may further include a first common source / drain layer 160S commonly connected to both ends of the first nanosheet 120. The first common source / drain layer 160S may extend perpendicularly along the first direction D1 to connect to the first buried source / drain layer 160. In another embodiment, the first common source / drain layer 160S may extend perpendicularly through the ends of the first nanosheet 120. In another embodiment, the first common source / drain layer 160S may include an epitaxial silicon layer epitaxially grown from the ends of the first nanosheet 120. The first common source / drain layer 160S may be respectively connected to the two ends of the first nanosheet 120. The first buried source / drain layer 160 and the first common source / drain layer 160S may comprise semiconductor materials, metals, metal nitrides, metal silicides, or combinations thereof. In one embodiment, the first buried source / drain layer 160 may comprise cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, or molybdenum silicide. In one embodiment, the first common source / drain layer 160S may comprise polycrystalline silicon.

[0029] The second transistor array TR2 may include a plurality of second transistors. The second transistor array TR2 may include a second nanosheet stack 130P and a second gate 150, and the second nanosheet stack 130P may include a plurality of second nanosheets 130.

[0030] The second nanosheet 130 can be stacked perpendicularly on the substrate 101 along the first direction D1. That is, the second nanosheet stack 130P can also be referred to as the second vertically stacked nanosheet, which includes a plurality of second nanosheets 130 stacked in the first direction D1 perpendicular to the substrate 101. The second gate 150 can extend perpendicularly along the first direction D1 and cover a portion of the second nanosheet 130 (e.g., a channel). The second gate 150 can be referred to as the second vertical gate. The second gate 150 can cover at least three surfaces of the second nanosheet 130. Referring back to Figures 2A and 2D, each second nanosheet 130 can have four surfaces, for example, an upper surface F1, a lower surface F2 opposite to the upper surface F1, a first side surface F3, and a second side surface F4 opposite to the first side surface F3. The second gate 150 can cover the upper surface F1, the lower surface F2, and the first side surface F3 of the second nanosheet 130. The second side F4 of the second nanosheet 130 can directly contact the isolation wall 110 and is not covered by the second gate 150. The second gate 150 can be called a three-gate or ring gate. The second transistor array TR2 can be a three-gate nanosheet transistor array.

[0031] The second nanosheet 130 can be made of a single-crystal material. The second nanosheet 130 can be a semiconductor material formed by epitaxial growth. The second nanosheet 130 may include a silicon layer or a silicon-germanium layer. The second nanosheet 130 may include an oxide semiconductor material such as IGZO. Each second nanosheet 130 can have a thickness of 50 Å to 300 Å. In one embodiment, the first nanosheet 120 can be a silicon nanosheet, and the second nanosheet 130 can be a silicon-germanium nanosheet.

[0032] The second gate 150 may include a conductive stack comprising a variety of conductive materials. For example, the second gate 150 may include a stack of a second ring gate layer 151, a second inner gate liner layer 152, and a second low-resistivity gate layer 153. The second ring gate layer 151 may cover the upper surface F1, the lower surface F2, and the first side surface F3 of the second nanosheet 130. The second ring gate layer 151, the second inner gate liner layer 152, and the second low-resistivity gate layer 153 may include semiconductor materials, metallic materials, metal nitrides, metal silicides, or combinations thereof. The second ring gate layer 151 may include TiN, TiSiN, TiAlN, TiCN, TaN, TaSiN, TaAlN, or TaCN. In one embodiment, the second ring gate layer 151 may include titanium nitride, the second inner gate liner layer 152 may include polycrystalline silicon, and the second low-resistivity gate layer 153 may include tungsten. In another embodiment, the second ring gate layer 151 may include a high work function material or a P-type work function material having a work function of about 4.5 eV or greater.

[0033] The second gate dielectric layer 154 can be formed between the second gate 150 and the second nanosheet 130. The second gate dielectric layer 154 can cover the surface of the substrate 101. The second gate dielectric layer 154 can include a multilayer structure disposed between the second nanosheet 130 and the second annular gate layer 151. For example, the second gate dielectric layer 154 can include a stack of a second interface layer 154A and a second high-k layer 154B. The second gate dielectric layer 154 may not include a dipole sensing layer, therefore the second gate dielectric layer 154 can be dipole-free. The second interface layer 154A can include silicon oxide or silicon oxynitride, while the second high-k layer 154B can include a hafnium-based material. The second high-k layer 154B can include: HfO2, HfON, HfSiO, HfSiON, HfZrO, or HfZrON.

[0034] The second transistor array TR2 may further include a second buried source / drain layer 161 formed in the substrate 101. The second buried source / drain layer 161 may be formed on both sides of the second nanosheet stack 130P in the substrate 101 in a third direction D3. The second transistor array TR2 may further include a second common source / drain layer 161S that is commonly connected to both ends of the second nanosheet 130. The second common source / drain layer 161S may extend perpendicularly along a first direction D1 to connect to the second buried source / drain layer 161. In another embodiment, the second common source / drain layer 161S may extend perpendicularly through the ends of the second nanosheet 130. The second common source / drain layer 161S may include an epitaxial silicon layer epitaxially grown from the ends of the second nanosheet 130. The second common source / drain layer 161S may be connected to the two ends of the second nanosheet 130 respectively. The second buried source / drain layer 161 and the second common source / drain layer 161S may include: a semiconductor material, a metal, a metal nitride, a metal silicon, or a combination thereof. In one embodiment, the second buried source / drain layer 161 may include cobalt silicon, nickel silicon, titanium silicon, tungsten silicon, or molybdenum silicon. In one embodiment, the second common source / drain layer 161S may include polycrystalline silicon.

[0035] A separation layer 111 may be formed in the substrate 101, and the separation layer 111 may contact the first buried source / drain layer 160 and the second buried source / drain layer 161. The separation layer 111 may be formed using a shallow trench isolation (STI) process. The separation layer 111 may be a dielectric separation layer. For example, the separation layer 111 may include silicon oxide, silicon nitride, or a combination thereof. The separation layer 111 may have a trench-type isolation structure. The separation layer 111 and the isolation wall 110 may be interconnected.

[0036] The capping layer 170 may be formed on both the first gate 140 and the second gate 150. The capping layer 170 may include a dielectric material such as silicon oxide or silicon nitride.

[0037] The first gate 140 and the second gate 150 can be separated from each other by the isolation wall 110.

[0038] The semiconductor device 100 described above is a dual-channel nanoplate transistor. The dual channels may include a first nanoplatelet 120 and a second nanoplatelet 130. The first transistor array TR1 may be a first nanoplate transistor array, and the second transistor array TR2 may be a second nanoplate transistor array. The first nanoplatelet 120 may be a channel of an N-channel transistor, and the second nanoplatelet 130 may be a channel of a P-channel transistor. The first transistor array TR1 may be a tri-gate N-channel nanoplate transistor array, and the second transistor array TR2 may be a tri-gate P-channel nanoplate transistor array.

[0039] The first nanosheet 120 can be referred to as an N-channel layer. The first nanosheet 120 may include a silicon layer or a silicon epitaxial layer. The first nanosheet 120 can be referred to as a silicon nanosheet. The second nanosheet 130 can be referred to as a P-channel layer. The second nanosheet 130 may include a silicon-germanium layer or a silicon-germanium epitaxial layer. The second nanosheet 130 can be referred to as a silicon-germanium nanosheet. The first nanosheet 120 and the second nanosheet 130 can be horizontally oriented along a third direction D3 to be parallel to the surface of the substrate 101. The first nanosheet 120 and the second nanosheet 130 can be formed by epitaxial growth.

[0040] Referring back to Figure 2D, the first nanosheet 120 and the second nanosheet 130 can be spaced apart from each other by a partition wall 110. The partition wall 110 is inserted between the first nanosheet 120 and the second nanosheet 130, allowing them to be located at different horizontal levels. The first nanosheet 120 and the second nanosheet 130 can also be located at different horizontal heights. For example, the first nanosheet 120 at its lowest horizontal level can be located at a first horizontal height L1, and the second nanosheet 130 at its lowest horizontal level can be located at a second horizontal height L2. The first horizontal height L1 can refer to a horizontal position higher than the second horizontal height L2. Therefore, the first nanosheet 120 and the second nanosheet 130 do not need to be located at the same horizontal height. The second nanosheet 130 at its lowest horizontal level can directly contact the substrate 101. The first nanosheet 120 at its lowest horizontal level can be spaced apart from the substrate 101.

[0041] The first nanosheet 120 and the second nanosheet 130 can have the same height (or thickness). For example, the first nanosheet 120 can have a first height H1, and the second nanosheet 130 can have a second height H2. The first height H1 and the second height H2 can refer to the height (or thickness) in a first direction D1. The first height H1 and the second height H2 can be the same. The first height H1 of the first nanosheet 120 and the second height H2 of the second nanosheet 130 can be from 50 Å to 300 Å.

[0042] The first spacing S1 between the first nanosheets 120 and the second spacing S2 between the second nanosheets 130 can be the same. The first spacing S1 between the first nanosheets 120 and the second spacing S2 between the second nanosheets 130 can be from 50 Å to 300 Å.

[0043] The second spacing S2 between the second nanosheets 130 and the first height H1 of the first nanosheet 120 can be the same. The first spacing S1 between the first nanosheets 120 and the second height H2 of the second nanosheet 130 can be the same.

[0044] Figures 3A to 3D are diagrams illustrating dual-channel nanosheets according to other embodiments of the present invention.

[0045] Referring to Figure 3A, a partition wall 110 is inserted between the first nanosheet 120 and the second nanosheet 130, allowing the first nanosheet 120 and the second nanosheet 130 to be located at different horizontal levels. The first nanosheet 120 and the second nanosheet 130 can also be located at different horizontal heights. For example, the first nanosheet 120 at its lowest horizontal level can be located at a second horizontal height L2, and the second nanosheet 130 at its lowest horizontal level can be located at a first horizontal height L1. The first horizontal height L1 can refer to a horizontal level higher than the second horizontal height L2. Therefore, the first nanosheet 120 and the second nanosheet 130 do not necessarily have to be located at the same horizontal height. The first nanosheet 120 at its lowest horizontal level can directly contact the substrate 101, while the second nanosheet 130 at its lowest horizontal level can be spaced apart from the substrate 101. The first nanosheet 120 and the second nanosheet 130 can have the same thickness.

[0046] Referring to Figure 3B, a partition wall 110 is inserted between the first nanosheet 120 and the second nanosheet 130', allowing the first nanosheet 120 and the second nanosheet 130' to be located at different horizontal levels. The first nanosheet 120 and the second nanosheet 130' can also be located at different horizontal heights. For example, the first nanosheet 120 at its lowest horizontal position can be located at a first horizontal height L1, and the second nanosheet 130' can be located at a second horizontal height L2. The first horizontal height L1 can refer to a horizontal position higher than the second horizontal height L2. Therefore, the first nanosheet 120 and the second nanosheet 130' may not be located at the same horizontal height. The second nanosheet 130' at its lowest horizontal position can directly contact the substrate 101. The first nanosheet 120 at its lowest horizontal position can be spaced apart from the substrate 101.

[0047] The first nanosheet 120 and the second nanosheet 130' can have different heights (or thicknesses). For example, the first nanosheet 120 can have a first height H1, and the second nanosheet 130' can have a second height H2', where the first height H1 can be greater than the second height H2'. The first height H1 of the first nanosheet 120 can be from 50 Å to 300 Å.

[0048] The first spacing S1' between the first nanosheets 120 and the second spacing S2 between the second nanosheets 130' can be different from each other. For example, the first spacing S1' between the first nanosheets 120 can be smaller than the second spacing S2 between the second nanosheets 130'. The second spacing S2 of the second nanosheets 130' can be from 50 Å to 300 Å.

[0049] The second spacing S2 between the second nanosheets 130' and the first height H1 of the first nanosheet 120 can be the same. The first spacing S1' between the first nanosheets 120 and the second height H2' of the second nanosheet 130' can be the same.

[0050] In another embodiment, the thickness of the second nanosheets 130 and 130' can be adjusted according to the desired threshold voltage. For example, if the P-channel transistor requires a high threshold voltage, the height of the second nanosheet 130 can be 50 Å to 80 Å. If the P-channel transistor requires a low threshold voltage, the height of the second nanosheets 130 and 130' can be 80 Å to 300 Å. As the height of the second nanosheets 130 and 130' increases, the flat-band voltage shifts more in the positive direction, thereby further reducing the threshold voltage of the P-channel transistor.

[0051] Referring to Figure 3C, the first nanosheet 120 and the second nanosheets 130A, 130B, 130C, and 130D are positioned with a spacer wall 110 inserted between them. The first nanosheet 120 and the second nanosheets 130A, 130B, 130C, and 130D can be located at different horizontal levels. The first nanosheet 120 and the second nanosheets 130A, 130B, 130C, and 130D can be located at different horizontal heights. For example, the first nanosheet 120 at the lowest horizontal level can be located at a first horizontal height L1, and the second nanosheet 130A at the lowest horizontal level can be located at a second horizontal height L2. The first horizontal height L1 can refer to a horizontal position higher than the second horizontal height L2. Therefore, the first nanosheet 120 and the second nanosheets 130A, 130B, 130C, and 130D can not be located at the same horizontal height. The second nanosheet 130A at the lowest horizontal level can directly contact the substrate 101. The first nanosheet 120, which is at the lowest level among the first nanosheets 120, can be spaced apart from the substrate 101.

[0052] The first nanosheet 120 can have the same height. The second nanosheets 130A, 130B, 130C, and 130D can have different heights. The height of the second nanosheet 130A at the lowest horizontal position can gradually decrease from the second nanosheet 130D at the highest horizontal position (i.e., along the first direction D1). The height of the second nanosheet 130A at the lowest horizontal position can be the largest, and the height of the second nanosheet 130D at the highest horizontal position can be the smallest. The height of the second nanosheet 130D at the highest horizontal position can be 50 Å to 80 Å, and the height of the second nanosheet 130A at the lowest horizontal position can be 80 Å to 300 Å. For example, the second nanosheets 130C and 130D can be channels of P-channel transistors requiring high threshold voltages, while the second nanosheets 130A and 130B can be channels of P-channel transistors requiring low threshold voltages.

[0053] In another embodiment, the height of the second nanosheet 130A at the lowest horizontal position can gradually increase from the second nanosheet 130D at the highest horizontal position (i.e., along the first direction D1). The height of the second nanosheet 130A at the lowest horizontal position can be the smallest, while the height of the second nanosheet 130D at the highest horizontal position can be the largest.

[0054] Referring to Figure 3D, a partition wall 110 is inserted between the first nanosheet 120 and the second nanosheet 130, allowing the first nanosheet 120 and the second nanosheet 130 to be located at different horizontal levels. The first nanosheet 120 and the second nanosheet 130 can also be located at different horizontal heights. For example, the first nanosheet 120 at its lowest horizontal level can be located at a first horizontal height L1, and the second nanosheet 130 at its lowest horizontal level can be located at a second horizontal height L2. The first horizontal height L1 can refer to a horizontal position higher than the second horizontal height L2. Therefore, the first nanosheet 120 and the second nanosheet 130 do not need to be located at the same horizontal height. The second nanosheet 130 at its lowest horizontal level can directly contact the substrate 101, while the first nanosheet 120 at its lowest horizontal level can be spaced apart from the substrate 101.

[0055] Interface layers 144A' and 154A' can be formed by selectively oxidizing the surfaces of the first nanosheet 120 and the second nanosheet 130. The first nanosheet 120 and the second nanosheet 130 can have rounded corners. Subsequently, as shown in FIG2A, high-k layers 144B and 154B can be formed on interface layers 144A' and 154A', respectively.

[0056] Figures 4 to 18 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 4 to 18 are cross-sectional views taken along lines A-A', B-B', and C-C' of Figure 1B to illustrate the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0057] As shown in Figure 4, alternating stacks 12 can be formed on substrate 11. Substrate 11 can be a material suitable for semiconductor processing. Substrate 11 can include at least one of conductive materials, dielectric materials, and semiconductor materials. Substrate 11 can include a semiconductor substrate. Substrate 11 can be made of a silicon-containing material. Substrate 11 can include: silicon, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayer structures thereof. Substrate 11 can include a compound semiconductor substrate such as GaAs. Substrate 11 can include a silicon-on-insulator (SOI) substrate. As referenced in Figures 1A and 1B, substrate 11 can include a first transistor array TR1 and a second transistor array TR2.

[0058] Before forming the alternating stack 12, the surface of the substrate 11 can be exposed to a cleaning process. Native oxides and impurities on the surface of the substrate 11 can be removed by the cleaning process. The cleaning process can include a dry cleaning process or a wet cleaning process. Hydrogen can be supplied to dangling bonds on the surface of the substrate 11 through the cleaning process, thereby inhibiting the growth of native oxides.

[0059] The alternating stack 12 may include at least one first semiconductor layer 13 and at least one second semiconductor layer 14. In the alternating stack 12, multiple first semiconductor layers 13 and multiple second semiconductor layers 14 may be stacked alternately. The first semiconductor layer 13 and the second semiconductor layer 14 may be epitaxially grown as single crystals. The bottommost layer of the alternating stack 12 may be the first semiconductor layer 13, and the topmost layer of the alternating stack 12 may also be the first semiconductor layer 13. The first semiconductor layer 13 and the second semiconductor layer 14 may be made of different materials. For example, the first semiconductor layer 13 may include a silicon-germanium layer, and the second semiconductor layer 14 may include a silicon layer. In another embodiment, the first semiconductor layer 13 may include a silicon layer, and the second semiconductor layer 14 may include a silicon-germanium layer. The first semiconductor layer 13 and the second semiconductor layer 14 may have the same thickness. In another embodiment, the first semiconductor layer 13 may be thinner than the second semiconductor layer 14, or the first semiconductor layer 13 may be thicker than the second semiconductor layer 14. The first semiconductor layer 13 and the second semiconductor layer 14 may be referred to as a first channel layer and a second channel layer, respectively.

[0060] In one embodiment, an alternating stack 12 can be formed by alternately stacking silicon-germanium layers and silicon layers. The silicon-germanium layers and silicon layers can be epitaxially grown as single crystals. The thickness of the silicon-germanium layers can be from 50 Å to 300 Å, and the thickness of the silicon layers can also be from 50 Å to 300 Å. The number of times the silicon-germanium layers and silicon layers are alternately stacked can be adjusted according to the target driving current value of the transistor.

[0061] A hard mask layer 15 can be formed on the alternating stack 12. The hard mask layer 15 can have etch selectivity relative to the alternating stack 12. The hard mask layer 15 can be used as an etch barrier layer or as a mask for etching the alternating stack 12. The hard mask layer 15 can include, for example, silicon nitride. The hard mask layer 15 can be deposited in a single-chamber or batch-chamber configuration. Alternatively, the hard mask layer 15 can be deposited using thermal chemical vapor deposition (thermal CVD) or plasma chemical vapor deposition (plasma CVD). The thickness of the hard mask layer 15 can be from 500 Å to 1000 Å.

[0062] Subsequently, the hard mask layer 15 can be patterned using a photoresist pattern (not shown).

[0063] As shown in Figure 5, a trench 16 can be formed by etching the alternating stacks 12. To form the trench 16, a hard mask layer 15 can be used as an etch barrier layer to etch the alternating stacks 12. A wafer stack 12S can be formed through the trench 16. The wafer stack 12S can include multiple wafer stacks 12N and 12P. The wafer stacks 12N and 12P can include a first wafer stack 12N and a second wafer stack 12P. In the first wafer stack 12N and the second wafer stack 12P, a first semiconductor layer 13 and a second semiconductor layer 14 can be alternately stacked in a direction perpendicular to the upper surface of the substrate 11. A trench 16 can be defined between the first wafer stack 12N and the second wafer stack 12P. The bottom surface of the trench 16 can extend into the substrate 11. The trench 16 can be used to separate the first wafer stack 12N and the second wafer stack 12P from each other.

[0064] Each of the first stack 12N and the second stack 12P can extend in a direction perpendicular to the substrate 11. The hard mask layer 15 can be located on the first stack 12N and the second stack 12P.

[0065] As described above, the wafer stack 12S may include: a first wafer stack 12N, a second wafer stack 12P, and a trench 16 between the first wafer stack 12N and the second wafer stack 12P.

[0066] As shown in Figure 6, an isolation wall 17 can be formed for the trench 16 of the filler stack 12S. The isolation wall 17 can be deposited in a single-chamber or batch-chamber configuration. Alternatively, the isolation wall 17 can be deposited using thermal chemical vapor deposition (thermal CVD) or plasma chemical vapor deposition (plasma CVD). The thickness of the isolation wall 17 can be from 300 Å to 600 Å. The isolation wall 17 can include a dielectric material. For example, the isolation wall 17 can include, for example, silicon nitride, silicon oxide, or a combination thereof. In one embodiment, the isolation wall 17 can be formed of silicon nitride. The isolation wall 17 can also be referred to as a support. After masking (not shown) the first stack 12N and the second stack 12P to form the isolation wall 17, a dielectric material can be deposited to fill the trench 16. Subsequently, the dielectric material can be planarized until the upper surface of the hard mask layer 15 is exposed.

[0067] As described above, the wafer stack 12S may include a first wafer stack 12N, a second wafer stack 12P, and an isolation wall 17 between the first wafer stack 12N and the second wafer stack 12P.

[0068] As shown in Figure 7, a separation layer 18 can be formed on both sides of the wafer stack 12S in the substrate 11. The separation layer 18 can be formed by a shallow trench isolation (STI) process. The separation layer 18 may include silicon oxide, silicon nitride, or a combination thereof. The isolation wall 17 may be referred to as a pillar-type isolation layer, while the separation layer 18 may be referred to as a trench-type separation layer.

[0069] The isolation wall 17 and the separation layer 18 can be formed of the same material or different materials. For example, the isolation wall 17 can be silicon nitride, while the separation layer 18 can be silicon oxide.

[0070] In the line A-A' direction, the separation layer 18 can be formed by aligning it on both sides of the sheet stack 12S. In the lines B-B' and C-C' directions, the separation layer 18 can be formed at a predetermined distance from the bottom edge of each of the first sheet stack 12N and the second sheet stack 12P. The line A-A' direction can refer to the width of the first sheet stack 12N and the second sheet stack 12P, while the lines B-B' and C-C' directions can refer to the length of the first sheet stack 12N and the second sheet stack 12P.

[0071] As shown in Figure 8, the substrate 11 can be etched to a predetermined depth to align with the two sidewalls of the first stack 12N and the second stack 12P. Therefore, a plurality of recesses 19 can be formed on the surface of the substrate 11. Recesses 19 can be formed on both sides of the stack 12S along lines B-B' and C-C' on the substrate 11. For example, the surface of the substrate 11 between the first stack 12N and the separator layer 18 in the line B-B' direction can be etched to form a recess 19. Furthermore, a recess 19 can be formed when etching the surface of the substrate 11 between the second stack 12P and the separator layer 18 along the line C-C' direction. The recesses 19 can have the same depth, and the recesses 19 can be shallower than the separator layer 18. Recesses 19 can not be formed between the first stack 12N and the separator layer 18 or between the second stack 12P and the separator layer 18 in the line A-A' direction.

[0072] As shown in Figure 9, a first buried source / drain layer 20 and a second buried source / drain layer 20 can be formed to fill the recess 19. The first buried source / drain layer 20 can be formed between the first stack 12N and the separator layer 18. The second buried source / drain layer 20 can be formed between the second stack 12P and the separator layer 18. The first buried source / drain layer 20 and the second buried source / drain layer 20 can be referred to as source / drain regions or buried bit lines. The first buried source / drain layer 20 and the second buried source / drain layer 20 can include semiconductor materials, metals, metal nitrides, metal silicides, or combinations thereof. The first buried source / drain layer 20 and the second buried source / drain layer 20 can include cobalt silicon, nickel silicon, titanium silicon, tungsten silicon, or molybdenum silicon.

[0073] For example, to form the first buried source / drain layer 20 and the second buried source / drain layer 20, a metal layer can be deposited to fill the recess 19, followed by heat treatment to form metal silicide, and unreacted metal layers can be removed. The metal layer filling the recess 19 can be deposited using only physical vapor deposition (PVD). If chemical vapor deposition (CVD) or atomic layer deposition (ALD) is used to deposit the metal layer, the metal layer can be deposited on the sidewalls of the first stack 12N and the second stack 12P, allowing a silicide reaction of the semiconductor materials of the first stack 12N and the second stack 12P to occur during the subsequent heat treatment. Due to the linearity of PVD, using the PVD method may not result in metal layer deposition on the sidewalls of the stack 12S. The subsequent heat treatment can be performed using rapid thermal annealing (RTA) in the range of 500 to 700°C. Unreacted metal layers can be removed by a cleaning process.

[0074] In addition, the first buried source / drain layer 20 and the second buried source / drain layer 20 may not be formed in the A-A' direction.

[0075] As shown in Figure 10, a first masking layer 21 can be formed. The first masking layer 21 may include a photoresist pattern. The first masking layer 21 can selectively expose a portion of the first stack 12N or the second stack 12P. For example, the first semiconductor layer 13 and the second semiconductor layer 14 of the first stack 12N can be selectively exposed in the line A-A' direction by the first masking layer 21. The second stack 12P can be covered in the line B-B' and line C-C' directions by the first masking layer 21. The first stack 12N can be covered in the line B-B' and line C-C' directions by the first masking layer 21.

[0076] Next, the first semiconductor layer 13 of the first stack 12N can be selectively removed using the first masking layer 21. Therefore, a first horizontal recess 22 can be formed between the second semiconductor layers 14. The first semiconductor layer 13 can be selectively removed using wet etching.

[0077] The vertically stacked second semiconductor layer 14 with the first horizontal recess 22 interposed between it can be abbreviated as "first nanosheet N1". A first nanosheet stack 14N comprising a plurality of first nanosheets N1 vertically stacked on the substrate 11 can be formed. The first nanosheets N1 may include silicon nanosheets.

[0078] As shown in Figure 11, a second masking layer 23 can be formed after removing the first masking layer 21. The second masking layer 23 may include a photoresist pattern. The second masking layer 23 can selectively expose portions of the second stack 12P. For example, the sidewalls of the first semiconductor layer 13 and the second semiconductor layer 14 of the second stack 12P can be selectively exposed in the line A-A' direction through the second masking layer 23. The second stack 12P can be covered in both the line B-B' and line C-C' directions through the second masking layer 23. All of the first nanosheet N1 and the first horizontal recess 22 can be covered in the line A-A', line B-B', and line C-C' directions through the second masking layer 23.

[0079] Next, the second semiconductor layer 14 can be selectively removed from the first semiconductor layer 13 and the second semiconductor layer 14 of the second stacked 12P by using the second masking layer 23. Therefore, a second horizontal recess 24 can be formed between the first semiconductor layers 13. The second semiconductor layer 14 can be removed by wet etching.

[0080] The vertically stacked first semiconductor layer 13 with the second horizontal recess 24 interposed between it can be abbreviated as "second nanosheet N2". A second nanosheet stack 13P comprising a plurality of second nanosheets N2 vertically stacked on the substrate 11 can be formed. The second nanosheets N2 may include silicon-germanium nanosheets.

[0081] As shown in Figure 12, the second mask layer 23 can be removed.

[0082] Through the above series of processes, multiple first nanosheets N1 can be formed on one side of the isolation wall 17, and multiple second nanosheets N2 can be formed on the other side of the isolation wall 17. The isolation wall 17 can be disposed between the first nanosheets N1 and the second nanosheets N2. The isolation wall 17 can be used as a support for the first nanosheets N1 and the second nanosheets N2.

[0083] Each of the first nanosheet N1 and the second nanosheet N2 can be referred to as a nanosheet channel. The first nanosheet N1 and the second nanosheet N2 can be horizontally oriented parallel to the surface of the substrate 11. The first nanosheet N1 and the second nanosheet N2 can be located at different horizontal heights. That is, the first nanosheet N1 and the second nanosheet N2 may not be located at the same horizontal height. A first horizontal recess 22 can be formed between the first nanosheets N1, and a second horizontal recess 24 can be formed between the second nanosheets N2.

[0084] Next, the hard mask layer 15 can be selectively removed. The hard mask layer 15 can be removed by wet etching. Removing the hard mask layer 15 by dry etching may damage the underlying structure.

[0085] As shown in Figure 13, a gate dielectric layer 25 can be formed. The gate dielectric layer 25 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. For example, the gate dielectric layer 25 may include a stack of an interface layer 25A and a high-k layer 25B. The interface layer 25A may include silicon oxide or silicon oxynitride, while the high-k layer 25B may include a hafnium-based material. The high-k layer 25B may include HfO₂, HfON, HfSiO, HfSiON, HfZrO, or HfZrON.

[0086] Gate dielectric layers 25 can be formed on the respective surfaces of the first nanosheet N1 and the second nanosheet N2. A portion of the gate dielectric layer 25 can cover the exposed upper surface of the isolation wall 17.

[0087] The gate dielectric layer 25 formed on the first nanosheet N1 may include a stack of an interface layer 25A, a high-k layer 25B, and a dipole sensing layer 25C. The dipole sensing layer 25C may include lanthanum oxide or magnesium oxide. The gate dielectric layer 25 formed on the second nanosheet N2 may include a stack of an interface layer 25A and a high-k layer 25B. The gate dielectric layer 25 formed on the second nanosheet N2 may be dipole-free.

[0088] In the line A-A' direction, the gate dielectric layer 25 can cover three surfaces of the first nanosheet N1 and the second nanosheet N2 respectively. In the line B-B' direction and the line C-C' direction, the gate dielectric layer 25 can cover all surfaces of the first nanosheet N1 and the second nanosheet N2 respectively.

[0089] As shown in Figure 14, a first gate layer 26 can be formed on the gate dielectric layer 25. The first gate layer 26 may include a metal base material. The first gate layer 26 may include a metal nitride. The first gate layer 26 may include TiN, TiSiN, TiAlN, TiCN, TaN, TaSiN, TaAlN, or TaCN. The first gate layer 26 can be deposited using an ALD method to have a thickness of 20 Å to 100 Å. In one embodiment, the first gate layer 26 may include titanium nitride. The first gate layer 26 can cover the three surfaces of the first nanosheet N1 and the second nanosheet N2 respectively in the line A-A' direction, while the first gate layer 26 can completely cover the first nanosheet N1 and the second nanosheet N2 in the line B-B' direction and the line C-C' direction. The first gate layer 26 can fill the first horizontal recess 22 between the first nanosheet N1 and the second horizontal recess 24 between the second nanosheet N2.

[0090] As shown in Figure 15, a second gate layer 27 and a third gate layer 28 can be sequentially formed on the first gate layer 26. The second gate layer 27 may include a semiconductor material, while the third gate layer 28 may include a metal-based material. For example, the second gate layer 27 may include polysilicon, while the third gate layer 28 may include tungsten. In another embodiment, the third gate layer 28 can be formed by sequentially stacking titanium nitride and tungsten. The second gate layer 27 can be deposited using CVD or ALD methods to have a thickness of 200 Å to 500 Å. The third gate layer 28 can be deposited using CVD or ALD methods to have a thickness of 200 Å to 400 Å. The second gate layer 27 and the third gate layer 28 may not completely cover the first nanosheet N1 and the second nanosheet N2. That is, only the first gate layer 26 may surround the first nanosheet N1 and the second nanosheet N2.

[0091] As shown in Figure 16, a first gate G1 and a second gate G2 can be formed. To form the first gate G1 and the second gate G2, a third gate layer 28, a second gate layer 27, and a first gate layer 26 can be etched sequentially along the line A-A'. The first gate G1 can be disposed around the first nanosheet N1, and the gate dielectric layer 25 is inserted between the first gate G1 and the first nanosheet N1. The second gate G2 can be disposed around the second nanosheet N2, and the gate dielectric layer 25 is inserted between the second gate G2 and the second nanosheet N2. The first gate layer 26 of the first gate G1 can be disposed around the first nanosheet N1, and the gate dielectric layer 25 is inserted between the first gate layer 26 of the first gate G1 and the first nanosheet N1. The first gate layer 26 of the second gate G2 can be disposed around the second nanosheet N2, and the gate dielectric layer 25 is inserted between the first gate layer 26 of the second gate G2 and the second nanosheet N2. The first gate G1 and the second gate G2 may extend in a direction perpendicular to the substrate 11. The first gate G1 and the second gate G2 may be referred to as the "first vertical gate" and the "second vertical gate," respectively. The first gate layer 26 of the first gate G1 and the second gate G2 may be referred to as the ring gate layer. The second gate layer 27 of the first gate G1 and the second gate G2 may be referred to as the inner gate layer. The third gate layer 28 of the first gate G1 and the second gate G2 may be referred to as the low resistivity gate layer.

[0092] The first gate G1 and the second gate G2 can have a combined structure that is interconnected.

[0093] As shown in Figure 17, a capping layer 29 can be formed on the first gate G1 and the second gate G2. The capping layer 29 may include, for example, silicon nitride. The capping layer 29 may cover the sidewalls of the third gate layer 28. The capping layer 29 can be deposited using ALD or CVD methods to have a thickness of 500 Å to 1000 Å. For example, to form the capping layer 29, a planarization process and an etch-back process can be sequentially performed after the deposition of silicon nitride. The first gate G1 and the second gate G2 can be spaced apart from each other by the planarization and etch-back processes used to form the capping layer 29.

[0094] As shown in Figure 18, multiple first common source / drain layers 30 and second common source / drain layers 31 can be formed through the capping layer 29. Referring to line B-B', the first common source / drain layers 30 can be connected to both ends of the first nanosheet N1. Referring to line C-C', the second common source / drain layers 31 can be connected to both ends of the second nanosheet N2. The first common source / drain layers 30 and the second common source / drain layers 31 can be connected to the first buried source / drain layer 20 and the second buried source / drain layer 20, respectively. To form the first common source / drain layers 30 and the second common source / drain layers 31, a portion of the gate dielectric layer 25 can be etched to expose the ends of the first nanosheet N1 and the second nanosheet N2.

[0095] The first nanosheet N1, the gate dielectric layer 25, and the first gate G1 can constitute an N-channel transistor. The threshold voltage of the N-channel transistor can be controlled by the dipole sensing layer 25C of the gate dielectric layer 25. The second nanosheet N2, the gate dielectric layer 25, and the second gate G2 can constitute a P-channel transistor. The threshold voltage of the P-channel transistor can be controlled by the second nanosheet N2.

[0096] In one embodiment, a first nanosheet N1 and a second nanosheet N2 are stacked vertically, and a first gate G1 and a second gate G2 are formed around the first nanosheet N1 and the second nanosheet N2. Therefore, gate control is improved, and short-channel effects can be suppressed.

[0097] In this embodiment, because the first nanosheet N1 and the second nanosheet N2, which have a three-dimensional structure, are stacked vertically, the driving current may be increased compared to the driving current of a two-dimensional transistor.

[0098] Figure 19 is a diagram illustrating a semiconductor device according to another embodiment of the present invention. The semiconductor device 200 of Figure 19 may be similar to the semiconductor device 100 of Figures 1A and 1B. Detailed descriptions of repeating components may be omitted below.

[0099] Referring to Figures 1A, 1B, and 19, the semiconductor device 200 may include a cell region CR containing memory cells and a peripheral circuit region PR containing a plurality of peripheral circuit transistors for controlling the memory cells. The cell region CR may include buried word lines (BWL), bit lines (BL), and capacitors (CP). The peripheral circuit region PR may include a plurality of nanochip transistor arrays (NMOS and PMOS), and the NMOS and PMOS arrays may include an N-channel NMOS array containing a first nanochip stack of 120N and a P-channel PMOS array containing a second nanochip stack of 130P.

[0100] N-channel nanoplatelet transistor array (NMOS) may include a first nanoplatelet stack 120N, a first gate dielectric layer 144, and a first gate 140. The first nanoplatelet stack 120N may include a plurality of first nanoplatelets 120 stacked in a direction perpendicular to the substrate 101. The first gate 140 may include a first ring gate layer 141, a first inner gate liner layer 142, and a first low resistivity gate layer 143. The first gate dielectric layer 144 may include a dipole sensing layer. As shown in Figures 1A and 1B, a first common source / drain layer 160S may be connected to both ends of the first nanoplatelet 120, and the first common source / drain layer 160S may be connected to a first buried source / drain layer 160 buried in the substrate 101.

[0101] P-channel nanoplatelet transistor arrays (PMOS) may include a second nanoplatelet stack 130P, a second gate dielectric layer 154, and a second gate 150. The second nanoplatelet stack 130P may include a plurality of second nanoplatelets 130 stacked in a direction perpendicular to the substrate 101. The second gate 150 may include a second ring gate layer 151, a second inner gate liner layer 152, and a second low-resistivity gate layer 153. The second gate dielectric layer 154 does not contain a dipole and does not include a dipole sensing layer. As shown in Figures 1A and 1B, a second common source / drain layer 161S may be connected to the two ends of the second nanoplatelet 130, and the second common source / drain layer 161S may be connected to a second buried source / drain layer 161 buried in the substrate 101.

[0102] An isolation wall 110 can be formed between an N-channel nanometer transistor array (NMOS) and a P-channel nanometer transistor array (PMOS). The isolation wall 110 can also be formed between a first nanometer stack 120N and a second nanometer stack 130P. The first nanometer 120 and the second nanometer 130 can be spaced apart from each other, with the isolation wall 110 inserted between them. The first nanometer 120 and the second nanometer 130 can be positioned at different horizontal heights.

[0103] The separation layer 111 can be formed in the substrate 101, and the cell region CR and the peripheral circuit region PR can be separated from each other by the separation layer 111.

[0104] The buried word line BWL can be spaced apart from the first gate 140 and the second gate 150 and buried in the substrate 101.

[0105] The first nanosheet 120 may include a silicon nanosheet, while the second nanosheet 130 may include a silicon-germanium nanosheet.

[0106] In another embodiment, as described above, a dielectric layer may be further formed between the lowest second nanosheet 130 of the second nanosheet stack 130P and the substrate 101. Therefore, the lowest second nanosheet 130 may be spaced apart from the substrate 101.

[0107] In another embodiment, as described above, at least one of the first nanosheet 120 and the second nanosheet 130 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO). For example, both the first nanosheet 120 and the second nanosheet 130 can be formed of an oxide semiconductor material. The first nanosheet 120 may be a silicon nanosheet, while the second nanosheet 130 may be an oxide semiconductor nanosheet. The first nanosheet 120 may be an oxide semiconductor nanosheet, while the second nanosheet 130 may be a silicon-germanium nanosheet.

[0108] The present invention is not limited to the above embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications and changes can be made without departing from the spirit and scope of the present invention.

[0109] 11:Substrate 12: Alternating stacking 12N: Stacked wafers / First wafer stack 12P: Stacked wafers / Second wafer stack 12S: Sheet stacking 13: First semiconductor layer 13P: Second nanosheet stacking 14: Second semiconductor layer 14N: First nanosheet stacking 15: Hard mask layer 16: Trench 17: Isolation Wall 18: Separation layer 19: concave part 20: First buried source / drain layer / Second buried source / drain layer 21: First masking layer 22: First horizontal recess 23: Second masking layer 24: Second horizontal recess 25: Gate dielectric layer 25A: Interface Layer 25B: High floor 25C: Dipole Sensing Layer 26: First gate layer 27: Second gate layer 28: Third gate layer 29: Covering layer 30: First shared source / drain layer 31: Second shared source / drain layer 100: Semiconductor devices 101:Substrate 110: Isolation Barrier 111: Separation layer 120: The First Nanoparticle 120N: First nanosheet stacking 130: Second Nanoparticle 130': Second Nanoparticle 130A: Second Nanosheet 130B: Second Nanoparticle 130C: Second Nanoparticle 130D: Second Nanofilm 130P: Second nanosheet stacking 140: First gate 141: First Ring Gate Layer 142: First inner liner gate layer 143: First low resistivity gate layer 144: First gate dielectric layer 144A: First Interface Layer 144A': Interface layer 144B: First Highest Floor 144C: ​​Dipole Induction Layer 150: Second gate 151: Second ring gate layer 152: Second inner liner gate layer 153: Second low resistivity gate layer 154: Second gate dielectric layer 154A: Second Interface Layer 154A': Interface layer 154B: The second highest floor (k level) 160: First buried source / drain layer 160S: First Common Source / Drain Layer 161: Second buried source / drain layer 161S: Second Common Source / Drain Layer 170: Covering layer 200: Semiconductor devices A-A':line B-B': line BL: Bitline BWL: Buried Letter Line C-C': line CP: Capacitor CR: Cell area D1: First Direction D2: Second Direction D3: Third direction F1: Upper surface F2: Lower surface F3: First side view F4: Second side G1: First gate G2: Second gate H1: First Height H2: Second Altitude H2': Second Height L1: First horizontal height L2: Second horizontal height N1: The First Nanosheet N2: Second Nanosheet PR: Peripheral Circuit Area S1: First Interval S1': First interval S2: Second Interval TR1: First Transistor Array TR2: Second Transistor Array

Claims

1. A semiconductor device, comprising: The substrate includes a first buried source / drain layer and a second buried source / drain layer; A first nanosheet stack comprising a plurality of first nanosheets stacked in a direction perpendicular to the substrate; a second nanosheet stack comprising a plurality of second nanosheets stacked in a direction perpendicular to the substrate; an isolation wall disposed between the first nanosheet stack and the second nanosheet stack; a first gate covering a portion of the first nanosheet stack and extending in a direction perpendicular to the substrate; a second gate covering a portion of the second nanosheet stack and extending in a direction perpendicular to the substrate; a first common source / drain layer connected to an end of the first nanosheet and the first buried source / drain layer; and a second common source / drain layer connected to an end of the second nanosheet and the second buried source / drain layer.

2. The semiconductor device according to claim 1, wherein, The first nanosheet and the second nanosheet are horizontally oriented parallel to the surface of the substrate and are positioned at different horizontal heights.

3. The semiconductor device according to claim 1, wherein, The first nanosheet and the second nanosheet are formed from different semiconductor materials.

4. The semiconductor device according to claim 1, wherein, The first nanosheet includes a silicon layer, and the second nanosheet includes a silicon-germanium layer.

5. The semiconductor device according to claim 1, wherein, The first nanosheet includes channels of an N-channel transistor, and the second nanosheet includes channels of a P-channel transistor.

6. The semiconductor device according to claim 1, wherein, The first gate and the second gate each include a first gate layer, wherein the first gate layer fills the space between the first nanosheets and the space between the second nanosheets.

7. The semiconductor device according to claim 6, wherein, The first gate and the second gate each further include a second gate layer above the first gate layer and a third gate layer above the second gate layer.

8. The semiconductor device according to claim 7, wherein, The first gate layer and the third gate layer comprise a metal-based material, and the second gate layer comprises polycrystalline silicon.

9. The semiconductor device according to claim 1, wherein, The first buried source / drain layer and the second buried source / drain layer each comprise a metal silicate.

10. The semiconductor device according to claim 1, wherein, The first common source / drain layer and the second common source / drain layer extend in a direction perpendicular to the substrate.

11. The semiconductor device according to claim 1, wherein, The first shared source / drain layer and the second shared source / drain layer each comprise polycrystalline silicon.

12. The semiconductor device according to claim 1, wherein, The bottom surface of the isolation wall extends into the substrate.

13. The semiconductor device according to claim 1, further comprising: A first gate dielectric layer includes a dipole sensing layer disposed between the first nanosheet and the first gate; And a second gate dielectric layer, which is dipole-free and disposed between the second nanosheet and the second gate.

14. The semiconductor device according to claim 13, wherein, The dipole sensing layer comprises lanthanum oxide or magnesium oxide.

15. The semiconductor device according to claim 1, wherein, Each of the first nanosheet and the second nanosheet includes: an upper surface, a lower surface opposite to the upper surface, a first side surface and a second side surface, the second side surface being opposite to the first side surface and in contact with the isolation wall, wherein the first gate includes a three-gate structure covering the upper surface and the lower surface of the first nanosheet and the first side surface, and wherein the second gate includes a three-gate structure covering the upper surface and the lower surface of the second nanosheet and the first side surface.

16. The semiconductor device according to claim 1, wherein, The first nanosheet and the second nanosheet have different thicknesses.

17. A semiconductor device, comprising: substrate; The first nanosheet transistor array includes a plurality of silicon nanosheets stacked in a direction perpendicular to the substrate; The second nanoplate transistor array includes a plurality of silicon-germanium nanoplates stacked in a direction perpendicular to the substrate; and an isolation wall disposed between the first nanoplate transistor array and the second nanoplate transistor array, wherein the silicon nanoplates and the silicon-germanium nanoplates are disposed at different horizontal heights.

18. The semiconductor device according to claim 17, wherein, The first nanosheet transistor array includes: a first gate disposed around a portion of the silicon nanosheet and extending in a direction perpendicular to the substrate; a first gate dielectric layer disposed between the first gate and the silicon nanosheet and including a dipole sensing layer; a first common source / drain layer connected to an end of the silicon nanosheet and extending in a direction perpendicular to the substrate; and a first buried source / drain layer buried in the substrate to connect to the first common source / drain layer.

19. The semiconductor device according to claim 18, wherein, The second nanoplate transistor array includes: a second gate disposed around a portion of the silicon-germanium nanoplate and extending in a direction perpendicular to the substrate; a second gate dielectric layer, which is dipole-free and disposed between the second gate and the silicon-germanium nanoplate; a second common source / drain layer connected to an end of the silicon-germanium nanoplate and extending in a direction perpendicular to the substrate; and a second buried source / drain layer buried in the substrate to connect to the second common source / drain layer.

20. The semiconductor device according to claim 19, wherein, Each of the silicon nanosheet and the silicon-germanium nanosheet includes: an upper surface, a lower surface opposite to the upper surface, a first side surface and a second side surface, the second side surface being opposite to the first side surface and in contact with the isolation wall, wherein the first gate includes a three-gate structure covering the upper surface, the lower surface and the first side surface of the silicon nanosheet, and wherein the second gate includes a three-gate structure covering the upper surface, the lower surface and the first side surface of the silicon-germanium nanosheet.

21. A method of manufacturing a semiconductor device, the method comprising: An alternating stack of a first semiconductor material and a second semiconductor material is formed on a substrate; the first stack and the second stack are formed by etching the alternating stack; An isolation wall is formed between the first and second wafer stacks; a buried source / drain layer is formed in the substrate to align with the first and second wafer stacks; the second semiconductor material is removed from the first wafer stack to form a first nanosheet stack of the first semiconductor material; the first semiconductor material is removed from the second wafer stack to form a second nanosheet stack of the second semiconductor material; a first gate and a second gate are formed on the first and second nanosheet stacks, respectively; and a first common source / drain layer and a second common source / drain layer are formed, respectively connected to the first and second nanosheet stacks; wherein the first common source / drain layer extends vertically to connect to the first buried source / drain layer, and the second common source / drain layer extends vertically to connect to the second buried source / drain layer.

22. The method according to request item 21, wherein, The first semiconductor material of the first nanosheet stack and the second semiconductor material of the second nanosheet stack are horizontally oriented and parallel to the surface of the substrate, and are set at different horizontal heights.

23. The method according to request item 21, wherein, The first semiconductor material includes a silicon layer, and the second semiconductor material includes a silicon-germanium layer.

24. The method according to request item 21, wherein, The buried source / drain layer comprises metal silicates.

25. The method according to request item 21, wherein, The first shared source / drain layer and the second shared source / drain layer comprise polycrystalline silicon.

26. The method according to claim 21 further includes: A first gate dielectric layer is formed, the first gate dielectric layer being disposed between the first semiconductor material and the first gate and including a dipole sensing layer.

27. The method according to claim 26, wherein, The dipole sensing layer comprises lanthanum oxide or magnesium oxide.

28. The method according to claim 21 further includes: A second gate dielectric layer is formed, which is disposed between the second semiconductor material and the second gate, wherein the second gate dielectric layer is dipole-free.

29. The method according to request item 21, wherein, The first gate covers a portion of the first semiconductor material of the first nanosheet stack and extends in a direction perpendicular to the substrate, and wherein the second gate covers a portion of the second semiconductor material of the second nanosheet stack and extends in a direction perpendicular to the substrate.

30. The method according to request item 21, wherein, The first common source / drain layer is connected to the end of the first semiconductor material of the first nanosheet stack and extends in a direction perpendicular to the substrate, and wherein the second common source / drain layer is connected to the end of the second semiconductor material of the second nanosheet stack and extends in a direction perpendicular to the substrate.

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