Semiconductor device

Abstract

A semiconductor device is provided, comprising: an active pattern on a substrate; a source / drain pattern on the active pattern; a gate electrode on a channel pattern connected to the source / drain pattern; an active contact on the source / drain pattern; a first lower interconnect on the active contact; a second lower interconnect on the gate electrode; a first spacer between the gate electrode and the active contact; and a second spacer between the first spacer and either the gate electrode or the active contact. The gate electrode includes an electrode body portion and an electrode protrusion portion protruding from the top surface of the electrode body portion and contacting the second lower interconnect. The active contact includes a contact body portion and a contact protrusion portion protruding from the top surface of the contact body portion and contacting the first lower interconnect.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This U.S. non - provisional patent application claims priority under 35 U.S.C.§119 to Korean Patent Application No. 10 - 2021 - 0123811, filed on September 16, 2021, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field - effect transistor and a method of manufacturing the same.

Background Art

[0004] Semiconductor devices include integrated circuits that contain metal - oxide - semiconductor field - effect transistors (MOSFETs). To meet the increasing demand for semiconductor devices with smaller pattern sizes and higher performance manufactured using simplified design rules, MOSFETs are being aggressively scaled down. The scaling down of MOSFETs can lead to the degradation of the operating characteristics of semiconductor devices. For example, when two conductive components of a MOSFET are placed closely due to scaling down, the shorter margin can be reduced. Various studies are being conducted to overcome the technical limitations associated with the scaling down of semiconductor devices and to achieve high - performance semiconductor devices.

Summary of the Invention

[0005] Example embodiments of the present inventive concept provide a semiconductor device having enhanced electrical characteristics.

[0006] Example embodiments of the present inventive concept provide a method of reducing process failures that may occur during the process of manufacturing a semiconductor device.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor device may include: an active pattern located on a substrate; a source / drain pattern located on the active pattern; a channel pattern connected to the source / drain pattern; a gate electrode located on the channel pattern; an active contact located on the source / drain pattern; a first lower interconnect located on the active contact; a second lower interconnect disposed on the gate electrode and positioned at the same horizontal height as the first lower interconnect; a first spacer located between the gate electrode and the active contact; and a second spacer spaced apart from the first spacer with the gate electrode or the active contact inserted between the second spacer and the first spacer. The gate electrode may include an electrode body portion and an electrode protruding portion that protrudes from a top surface of the electrode body portion and contacts a bottom surface of the second lower interconnect. The active contact may include a contact body portion and a contact protruding portion that protrudes from a top surface of the contact body portion and contacts a bottom surface of the first lower interconnect. A top surface of the first spacer may be higher than a top surface of the second spacer.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor device may include: an active pattern located on a substrate; a source / drain pattern located on the active pattern; a channel pattern connected to the source / drain pattern; a gate electrode located on the channel pattern; an active contact located on the source / drain pattern; a first lower interconnect located on the active contact; a second lower interconnect disposed on the gate electrode and positioned at the same horizontal height as the first lower interconnect; and a first spacer located between the gate electrode and the active contact. The gate electrode may include an electrode body portion and an electrode protruding portion that protrudes from a top surface of the electrode body portion and contacts a bottom surface of the second lower interconnect, and the active contact may include a contact body portion and a contact protruding portion that protrudes from a top surface of the contact body portion and contacts a bottom surface of the first lower interconnect. The first spacer may include a first portion adjacent to the electrode protruding portion, a second portion adjacent to the contact protruding portion, and a third portion between the first portion and the second portion. A top surface of the first portion and a top surface of the second portion may be higher than a top surface of the third portion.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor device may include: a substrate including a PMOSFET region and an NMOSFET region adjacent to each other in a first direction; a first active pattern and a second active pattern disposed on the PMOSFET region and the NMOSFET region, respectively; a first source / drain pattern located on the first active pattern, and a second source / drain pattern located on the second active pattern; active contacts located on the first source / drain pattern and the second source / drain pattern; a first channel pattern and a second channel pattern connected to the first source / drain pattern and the second source / drain pattern, respectively, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked in sequence and spaced apart from each other; a first gate electrode and a second gate electrode extending in the first direction to pass through the first active pattern and the second active pattern, respectively, and each of the first gate electrode and the second gate electrode including a first portion inserted between the substrate and the first semiconductor pattern, a second portion inserted between the first semiconductor pattern and the second semiconductor pattern, a third portion inserted between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion located on the third semiconductor pattern; a first gate insulating layer and a second gate insulating layer inserted between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode, respectively; a first metal layer located on the first gate electrode and the second gate electrode; a first spacer located between one of the first gate electrode and the active contacts; a second spacer spaced apart from the first spacer when one of the first gate electrode or the active contacts is inserted between the second spacer and the first spacer; and a second metal layer disposed on the first metal layer. The first metal layer may include a first interconnect line, and the second metal layer may include second interconnect lines electrically connected to the first interconnect line, respectively. Each of the active contacts may include a contact body portion and a contact protruding portion protruding from a top surface of the contact body portion and contacting a bottom surface of one of the first interconnect lines, and each of the first gate electrode and the second gate electrode may include an electrode body portion and an electrode protruding portion protruding from a top surface of the electrode body portion and contacting a bottom surface of the other of the first interconnect lines. A top surface of the first spacer may be higher than a top surface of the second spacer.

[0010] According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device may include: forming a device isolation layer on a substrate to define active patterns; forming source / drain patterns and a channel pattern on the active patterns; forming a gate electrode on the channel pattern; forming active contacts on the source / drain patterns; forming a mask pattern to cover the gate electrode and the active contacts; and patterning the gate electrode and the active contacts using the mask pattern as an etching mask. As a result of the patterning, the active contacts may be formed to include a contact body portion and a contact protruding portion that protrudes from a top surface of the contact body portion and contacts a bottom surface of a first lower interconnect line. As a result of the patterning, the gate electrode may be formed to include an electrode body portion and an electrode protruding portion that protrudes from a top surface of the electrode body portion and contacts a bottom surface of a second lower interconnect line. The mask pattern may include: a first portion formed on the active contact to define the contact protruding portion; a second portion formed on the gate electrode to define the electrode protruding portion; and a third portion connecting the first portion to the second portion.

Embodiments

[0012] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0013] FIG. 1 is a plan view of a semiconductor device showing an exemplary embodiment according to the inventive concept. FIGS. 2A to 2E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 1, respectively. FIG. 3A is a perspective view showing region Q of FIG. 1. FIG. 3B is an enlarged view showing region P of FIG. 2C. FIG. 3C is an enlarged view showing region R of FIG. 2D. FIG. 3D is an enlarged view showing region S of FIG. 2A. FIG. 3E is an enlarged view showing region X of FIG. 2E. FIG. 3F is a conceptual diagram showing a first spacer and its adjacent region.

[0014] Referring to FIGS. 1 and 2A to 2E, the logic cell LC can be disposed on the substrate 100. The logic transistors constituting the logic circuit can be placed on the logic cell LC. The substrate 100 can be a semiconductor substrate formed of or including the following: silicon (Si), germanium (Ge), compound semiconductor materials such as silicon carbide (SiC), silicon-germanium (SiGe), silicon-germanium carbide (SiGeC), gallium arsenide (GaAs), gallium antimonide (GaSb), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), lead telluride (PbTe) compounds or indium gallium arsenide (InGaAs), or similar materials. In addition, the substrate 100 can include one or more semiconductor layers or structures and can include the active or operative portions of semiconductor devices. In an exemplary embodiment of the inventive concept, the substrate 100 can be a silicon (Si) substrate.

[0015] The logic cell LC can include a P-type metal-oxide-semiconductor field effect transistor (PMOSFET) region PR and an N-type metal-oxide-semiconductor field effect transistor (NMOSFET) region NR. The PMOSFET region PR and the NMOSFET region NR can be defined by a second trench TR2 formed in the upper portion of the substrate 100. In other words, the second trench TR2 can be placed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR can be spaced apart from each other in a first direction D1 with the second trench TR2 inserted between the PMOSFET region PR and the NMOSFET region NR.

[0016] The first active pattern AP1 and the second active pattern AP2 can be defined by a first trench TR1 formed in the upper portion of the substrate 100. In other words, the first active pattern AP1 and the second active pattern AP2 can each correspond to a portion of the substrate 100 defined by the first trench TR1. The first active pattern AP1 and the second active pattern AP2 can be respectively disposed on the PMOSFET region PR and the NMOSFET region NR. The first trench TR1 can be shallower than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 can be arranged in the first direction D1 and can extend parallel to each other in a second direction D2. The first active pattern AP1 and the second active pattern AP2 can be vertically protruding portions of the substrate 100.

[0017] The device isolation layer ST can be configured to fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of or include: silicon oxide (SiO2). The upper portions of the first active pattern AP1 and the second active pattern AP2 can protrude vertically above the device isolation layer ST (e.g., see FIG. 2D). The device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2, and may cover the lower side surfaces of the first active pattern AP1 and the second active pattern AP2. A lining insulating layer can be disposed between the device isolation layer ST and the first active pattern AP1 and the second active pattern AP2. The lining insulating layer can be conformally disposed along the first trench TR1 and the second trench TR2. The lining insulating layer can be formed of or include: for example, silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0018] The first active pattern AP1 can include a first channel pattern CH1. The second active pattern AP2 can include a second channel pattern CH2. Each of the first channel pattern CH1 and the second channel pattern CH2 can include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be spaced apart from each other in the vertical direction (i.e., the third direction D3). Although the number of semiconductor patterns in each of the first channel pattern CH1 and the second channel pattern CH2 is illustrated as three, this is for illustrative purposes only, and the number is not limited thereto. For example, the number of semiconductor patterns included in each of the first channel pattern CH1 and the second channel pattern CH2 can be two or more than three.

[0019] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be formed of or include at least one of the following: for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In an exemplary embodiment of the inventive concept, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be formed of or include: crystalline silicon (c-Si).

[0020] A plurality of first grooves RS1 may be formed in an upper portion of the first active pattern AP1. The first source / drain patterns SD1 may be respectively disposed in the first grooves RS1. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., p-type). The first channel pattern CH1 may be inserted between each pair of the first source / drain patterns SD1 and connected to each pair of the first source / drain patterns SD1. In other words, each pair of the first source / drain patterns SD1 may be connected to each other by the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 of the first channel pattern CH1.

[0021] A plurality of second grooves RS2 may be formed in an upper portion of the second active pattern AP2. The second source / drain patterns SD2 may be respectively disposed in the second grooves RS2. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be inserted between each pair of the second source / drain patterns SD2 and connected to each pair of the second source / drain patterns SD2. In other words, a pair of the second source / drain patterns SD2 may be connected to each other by the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0022] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the first source / drain pattern SD1 may be formed by performing the SEG process in the first groove RS1. The second source / drain pattern SD2 may be formed by performing the SEG process in the second groove RS2. As an example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface located at a substantially same horizontal height as a top surface of the third semiconductor pattern SP3. However, in an exemplary embodiment of the inventive concept, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the third semiconductor pattern SP3.

[0023] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of a semiconductor element (e.g., Si) of the substrate 100. In this case, a pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 interposed therebetween. For example, silicon-germanium (SiGe) in the source and drain of a PMOSFET (e.g., the first source / drain pattern SD1) induces uniaxial compressive strain in the channel (e.g., the first channel pattern CH1), thereby increasing hole mobility. The second source / drain pattern SD2 may be formed of or include a semiconductor material that is the same as the semiconductor material of the substrate 100 (e.g., Si). In an exemplary embodiment of the inventive concept, the second source / drain pattern SD2 may be formed of or include single-crystalline silicon (sc-Si). Alternatively, the second source / drain pattern SD2 may include silicon carbide (SiC).

[0024] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 stacked in sequence. The cross-sectional shape of the first source / drain pattern SD1 taken parallel to the second direction D2 will be described with reference to FIG. 2A.

[0025] The first semiconductor layer SEL1 may cover the inner surface of the first recess RS1. Due to the cross-sectional profile of the first recess RS1, the first semiconductor layer SEL1 may have a 'U'-shaped cross-section. In an exemplary embodiment of the inventive concept, the width of the first recess RS1 may increase in the second direction D2 and decrease in the third direction D3 away from the substrate 100. However, the inventive concept is not limited thereto. The second semiconductor layer SEL2 may fill the remaining space of the first recess RS1 covered by the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 may be greater than the volume of the first semiconductor layer SEL1. In other words, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 may be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0026] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be formed of or include: silicon-germanium (SiGe). Specifically, the first semiconductor layer SEL1 may be configured to have a relatively low germanium (Ge) concentration. In an exemplary embodiment of the inventive concept, the first semiconductor layer SEL1 may be configured to contain only silicon (Si) and no germanium (Ge). Alternatively, the first semiconductor layer SEL1 may be configured to contain silicon-germanium (SiGe) with a small amount of germanium (Ge). The germanium (Ge) concentration of the first semiconductor layer SEL1 may range from 0 atomic % to about 10 atomic %. As used herein, "about" includes the stated value and means within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art considering the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations or within ±30%, 20%, 10%, 5% of the stated value.

[0027] The second semiconductor layer SEL2 may be configured to have a relatively high germanium (Ge) concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 may range from about 30 atomic % to about 70 atomic %. The germanium (Ge) concentration of the second semiconductor layer SEL2 may increase as the distance from the substrate 100 increases in the third direction D3. For example, the germanium concentration of the second semiconductor layer SEL2 may be about 40 atomic % near the first semiconductor layer SEL1, but may be about 60 atomic % at its top horizontal height. By utilizing the gradient germanium (Ge) concentration, each of the first source / drain patterns SD1 may provide a gradient compressive stress, and by combining this stress, a higher mobility may be achieved, and thus a higher device performance may be achieved.

[0028] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may contain impurities (e.g., boron (B)) such that the first source / drain patterns SD1 have p-type conductivity. In an exemplary embodiment of the inventive concept, the impurity concentration (in atomic %) in the second semiconductor layer SEL2 may be higher than the impurity concentration in the first semiconductor layer SEL1.

[0029] The gate electrode GE may be configured to pass through the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1, and may be arranged in the second direction D2 with a first pitch P1. Each of the gate electrodes GE may be vertically overlapped with the first channel pattern CH1 and the second channel pattern CH2.

[0030] The gate electrode GE may include a first portion P01 inserted between the substrate 100 and the first semiconductor pattern SP1, a second portion P02 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion P03 inserted between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion P04 located on the third semiconductor pattern SP3.

[0031] Referring back to FIG. 2A, the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE on the PMOSFET region PR may have different widths from each other. For example, the maximum width of the third portion P03 in the second direction D2 may be greater than the maximum width of the second portion P02 in the second direction D2. The maximum width of the first portion P01 in the second direction D2 may be greater than the maximum width of the third portion P03 in the second direction D2. For example, since the width of the first groove RS1 may increase in the second direction D2 and decrease in the third direction D3 away from the substrate 100, and the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE are inserted between two adjacent first grooves RS1, the maximum width of the second portion P02 may be the smallest among the maximum widths of the first portion P01, the second portion P02, and the third portion P03. However, the inventive concept is not limited thereto.

[0032] Referring back to FIG. 2D, the gate electrode GE may be arranged to face the top surface, the bottom surface, and the opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. In other words, the logic transistor according to the present exemplary embodiment may be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET)), in which the gate electrode GE is arranged to surround the channel pattern in a three-dimensional manner.

[0033] Referring back to FIGS. 1 and 2A through 2D, a pair of spacers GS may be respectively disposed on opposite side surfaces of the fourth portion P04 of the gate electrode GE. The spacers GS can be used to electrically isolate the gate electrode GE from the active contact, and the spacers will be described below. The spacers GS may extend along the gate electrode GE and in the first direction D1. The spacers GS may be formed of or include at least one of the following: for example, silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), or silicon nitride (Si3N4). In an exemplary embodiment of the present inventive concept, the spacers GS may have a multi-layer structure that includes at least two different materials selected from the following: for example, silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), and silicon nitride (Si3N4).

[0034] The gate insulating layer GI may be inserted between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface, bottom surface, and opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST under the gate electrode GE (see, for example, FIG. 2D).

[0035] In an exemplary embodiment of the present inventive concept, the gate insulating layer GI may include, for example, a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of or include at least one of the following: high-k dielectric materials having a dielectric constant higher than that of silicon oxide (SiO2). For example, the high-k dielectric material may include at least one of the following: for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium zirconium oxide (HfZrO4), hafnium tantalum oxide (Hf2Ta2O9), hafnium aluminum oxide (HfAlO3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTi2O6), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), or lead zinc niobate [Pb(Zn1 / 3Nb2 / 3)O3]. In an exemplary embodiment of the present inventive concept, the semiconductor device may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric characteristics and a paraelectric layer exhibiting paraelectric characteristics.

[0036] The ferroelectric layer may have a negative capacitance, and the paraelectric layer may have a positive capacitance. In the case where two or more than two capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance may be reduced to a value less than the capacitance of each of the capacitors. In contrast, in the case where at least one of the capacitors connected in series has a negative capacitance, the total capacitance of the capacitors connected in series may have a positive value and may be greater than the absolute value of each capacitance.

[0037] In the case where a ferroelectric layer having a negative capacitance and a paraelectric layer having a positive capacitance are connected in series, the total capacitance of the connected ferroelectric layer and paraelectric layer may increase. Due to this increase in the total capacitance, a transistor including the ferroelectric layer may have a subthreshold swing (SS) of less than 60 millivolts per decade (mV / decade) at room temperature. For example, in a negative capacitance FET (NC-FET), an insulating ferroelectric material layer acts as a negative capacitor, such that the channel surface potential can be amplified to be greater than the gate voltage, and thus the device can operate with an SS of less than 60 millivolts per decade at room temperature.

[0038] The ferroelectric layer may have ferroelectric properties. The ferroelectric layer may be formed of or include at least one of the following: for example, hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO4), barium strontium titanium oxide (BaSrTi2O6), barium titanate (BaTiO3), and / or lead zirconium titanate (Pb(Ti,Zr)O3). For each of the above ferroelectric materials, the ratio between metals may vary and the composition may be non-stoichiometric. For example, hafnium zirconium oxide (HfZrO4) may be hafnium oxide (HfO2) doped with zirconium (Zr). Alternatively, hafnium zirconium oxide may be a compound composed of hafnium (HF), zirconium (Zr), and / or oxygen (O). In other words, hafnium zirconium oxide may be represented by HfxZryOz with various combinations of the numerical values of x, y, and z instead of by HfZrO4.

[0039] The ferroelectric layer may further include a dopant. For example, the dopant may include at least one of the following: for example, aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the type of ferroelectric material included in the ferroelectric layer.

[0040] When the ferroelectric layer contains hafnium oxide (HfO2), the dopant in the ferroelectric layer may include at least one of the following: for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y). However, the inventive concept is not limited thereto. For example, other dopants such as strontium (Sr), lanthanum (La), titanium (Ti), and tantalum (Ta) may also be used to dope the ferroelectric material layer containing hafnium oxide (HfO2).

[0041] When the dopant is aluminum (Al), the content of aluminum (Al) in the ferroelectric layer may be in the range of about 3 atomic % (atomic percentage) to about 8 atomic %. Here, the content of aluminum (Al) as a dopant may be the ratio of the number of aluminum (Al) atoms to the number of hafnium (Hf) atoms and the number of aluminum (Al) atoms.

[0042] When the dopant is silicon (Si), the content of silicon in the ferroelectric layer may be in the range of about 2 atomic % to about 10 atomic %. When the dopant is yttrium (Y), the content of yttrium (Y) in the ferroelectric layer may be in the range of about 2 atomic % to about 10 atomic %. When the dopant is gadolinium (Gd), the content of gadolinium (Gd) in the ferroelectric layer may be in the range of about 1 atomic % to about 7 atomic %. When the dopant is zirconium (Zr), the content of zirconium (Zr) in the ferroelectric layer may be in the range of about 50 atomic % to about 80 atomic %.

[0043] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of or include at least one of the following: for example, silicon oxide (SiO2) and / or high-k metal oxide. The metal oxide that can be used as the paraelectric layer may include at least one of the following: for example, hafnium oxide (HfO2), barium strontium titanate (BaSrTi2O6), zirconium oxide (ZrO2), and / or aluminum oxide (Al2O3), but the inventive concept is not limited thereto.

[0044] The ferroelectric layer and the paraelectric layer may be formed of the same material or include the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not have ferroelectric properties. For example, when the ferroelectric layer and the paraelectric layer contain hafnium oxide (HfO2), the crystal structure of hafnium oxide (HfO2) in the ferroelectric layer may be different from the crystal structure of hafnium oxide (HfO2) in the paraelectric layer.

[0045] Only when the thickness of the ferroelectric layer is within a specific range, the ferroelectric layer may exhibit ferroelectric properties. In an exemplary embodiment of the inventive concept, the thickness of the ferroelectric layer may be in the range of about 0.5 nanometers to about 10 nanometers, but the inventive concept is not limited thereto. Since the critical thickness associated with the emergence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer may change depending on the type of ferroelectric material.

[0046] In an exemplary embodiment of the inventive concept, the gate insulating layer GI may include a single ferroelectric layer. In an exemplary embodiment of the inventive concept, the gate insulating layer GI may include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0047] The gate electrode GE may include a first metal pattern and a second metal pattern formed on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal, and the work function metal may be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor having a desired threshold voltage can be obtained. For example, the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE may be formed of the first metal pattern or the work function metal.

[0048] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of, for example, titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In an exemplary embodiment of the inventive concept, the first metal pattern may further include carbon (C). In an exemplary embodiment of the inventive concept, the first metal pattern may control the work function and may include one or more compounds selected from the following: for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), niobium nitride (NbN), niobium carbide (NbC), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), and combinations thereof. The first metal pattern may include a plurality of stacked work function metal layers.

[0049] The second metal pattern may include a metal material having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of, for example, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium aluminum (TiAl), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), molybdenum (Mo), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. In an exemplary embodiment of the inventive concept, the fourth portion P04 of the gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern.

[0050] Referring back to FIG. 2B, the inner spacer IP may be disposed on the NMOSFET region NR. The inner spacer IP may be inserted between the second source / drain pattern SD2 and the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE, respectively. The inner spacer IP may be in direct contact with the second source / drain pattern SD2. Each of the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the inner spacer IP. The inner spacer IP may be formed of or include at least one of the following: for example, silicon nitride (Si3N4), silicon carbonitride (SiCN), or silicon carbon oxynitride (SiCON). Referring back to FIG. 2B, the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE on the NMOSFET region NR may have the same width. However, the inventive concept is not limited thereto.

[0051] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The second interlayer insulating layer 113 may be disposed on the first interlayer insulating layer 110. In an exemplary embodiment of the inventive concept, the first interlayer insulating layer 110 and the second interlayer insulating layer 113 may be formed of or include the following: silicon dioxide (SiO2).

[0052] A pair of split structures DB opposite to each other in the second direction D2 may be disposed on both sides of the logic unit LC. The split structure DB may extend in the first direction D1 and may be parallel to the gate electrode GE. The pitch between the split structure DB and its adjacent gate electrode GE may be equal to the first pitch P1.

[0053] The split structure DB can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 113, and can extend into the first active pattern AP1 and the second active pattern AP2. The split structure DB can penetrate the upper portions of each of the first active pattern AP1 and the second active pattern AP2. The split structure DB can separate the PMOSFET region PR and the NMOSFET region NR of the logic cell LC from the active regions of another logic cell adjacent to the logic cell LC.

[0054] The sacrificial layer SAL adjacent to the split structure DB can be disposed on each of the first active pattern AP1 and the second active pattern AP2, and can be stacked to be spaced apart from each other. Each of the sacrificial layers SAL can be at the same horizontal height as a corresponding one of the first portion P01, the second portion P02, and the third portion P03 of the gate electrode GE. The split structure DB can be configured to penetrate the sacrificial layer SAL.

[0055] The sacrificial layer SAL can be formed of or include: silicon-germanium (SiGe). The germanium (Ge) concentration in each of the sacrificial layers SAL can be in the range of about 10 atomic % to about 30 atomic %. The germanium (Ge) concentration of the sacrificial layer SAL can be higher than the germanium (Ge) concentration of the first semiconductor layer SEL1 described above.

[0056] The active contact AC can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 113, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively disposed on both sides of the gate electrode GE. For example, a pair of active contacts AC can be arranged in the second direction D2, and can be spaced apart from each other with the gate electrode GE inserted between the pair of active contacts AC. When viewed in a plan view, the active contact AC can be a strip pattern extending in the first direction D1. As shown in FIG. 2C, the active contacts AC arranged in the first direction D1 can be spaced apart from each other with the gate pattern 111 inserted between the active contacts AC. The gate pattern 111 can be formed of or include at least one of the following: for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxycarbide (SiOC), or aluminum oxide (Al2O3).

[0057] The active contact AC can be a self-aligned contact. In other words, the active contact AC can be formed by a self-alignment process using the gate electrode GE and the spacer GS. For example, the active contact AC can cover at least a part of the side surface of the spacer GS.

[0058] The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM may be formed of or include at least one of the following: a metal material (e.g., aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), etc.). The barrier pattern BM may cover the side surface and the bottom surface of the conductive pattern FM. In an exemplary embodiment of the inventive concept, the barrier pattern BM may include two layers, such as a metal layer and a metal nitride layer. The metal layer may be formed of or include a metal or a metal alloy, the metal or the metal alloy including at least one of the following: e.g., titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), or platinum (Pt). The metal nitride layer may be formed of or include at least one of the following, e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0059] Hereinafter, the active contact AC will be described in more detail with reference to FIGS. 3A and 3B. The active contact AC may include a contact body portion LB and a contact protruding portion LA. The contact body portion LB may be a strip-shaped pattern extending in a first direction D1, and may have a first top surface TS1 located at a first height. The contact protruding portion LA may have a shape protruding from the first top surface TS1 of the contact body portion LB in a third direction D3. The contact protruding portion LA may have a second top surface TS2 located at a second height. The second top surface TS2 of the contact protruding portion LA may be in direct contact with the first metal layer M1 (e.g., the bottom surface of the first lower interconnect M1_I1). In other words, the top surface (e.g., the second top surface TS2) of the active contact AC may be directly connected to the first lower interconnect M1_I1 without an additional structure being inserted therebetween.

[0060] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include a first lower interconnect M1_I1 to a fifth lower interconnect M1_I5, and a sixth lower interconnect M1_R1 and a seventh lower interconnect M1_R2. Each of the lower interconnects M1_I1 to M1_I5, the lower interconnect M1_R1, and the lower interconnect M1_R2 may extend in a second direction D2 to pass through the logic unit LC. The lower interconnects M1_I1 to M1_I5, the lower interconnect M1_R1, and the lower interconnect M1_R2 may also be referred to as first interconnects. In an exemplary embodiment of the inventive concept, a drain voltage VDD and a source voltage VSS may be applied to the sixth lower interconnect M1_R1 and the seventh lower interconnect M1_R2, respectively.

[0061] The contact protruding portion LA may include a first stepped structure SK1 having a side surface with a discontinuously varying slope. As an example, the contact protruding portion LA may include a recessed side surface. Specifically, the lower side surface of the contact protruding portion LA connected to the contact main body portion LB may be defined by a first groove region RR1, and the upper side surface of the contact protruding portion LA connected to the first lower interconnect line M1_I1 may be defined by a second groove region RR2. The first groove region RR1 and the second groove region RR2 may be empty spaces formed by partially removing the upper portion of the active contact AC and not connected to the first metal layer M1. The first groove region RR1 may be formed during a patterning process for forming the contact protruding portion LA in the upper portion of the active contact AC, and the lower portion of the active contact AC below the contact protruding portion LA and / or below the first groove region RR1 may then be defined as the contact main body portion LB. The first stepped structure SK1 may be defined near the boundary between the first groove region RR1 and the second groove region RR2. The second interlayer insulating layer 113 may be provided to fill the first groove region RR1. The liner insulating layer 114 may be provided between the second interlayer insulating layer 113 and the contact main body portion LB, but the inventive concept is not limited thereto. The liner insulating layer 114 may also be provided between the second interlayer insulating layer 113 and the contact protruding portion LA in the first groove region RR1. The third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 113 to fill the second groove region RR2. The second groove region RR2 may be formed during a patterning process for forming the first lower interconnect line M1_I1 and may be aligned with the side surface of the first lower interconnect line M1_I1. Thus, the contact protruding portion LA may include a side surface aligned with the side surface of the first lower interconnect line M1_I1. As an example, the width of the second top surface TS2 of the contact protruding portion LA in the first direction D1 may be substantially equal to the width of the bottom surface of the first lower interconnect line M1_I1.

[0062] The third interlayer insulating layer 130 may extend into the region between the lower interconnect line M1_I1 to the lower interconnect lines M1_I5, the lower interconnect line M1_R1, and the lower interconnect line M1_R2. For example, the bottom surface of the third interlayer insulating layer 130 may be lower than the bottom surface of the first metal layer M1. Each of the second interlayer insulating layer 113, the third interlayer insulating layer 130, and the liner insulating layer 114 may be formed of or include at least one of the following, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxycarbide (SiOC), or aluminum oxide (Al2O3).

[0063] The contact body portion LB and the contact protruding portion LA can be arranged to have no interface therebetween and to form a single object. In other words, the contact body portion LB and the contact protruding portion LA can be two parts of a structure formed of the same material at the same time. As will be described later with reference to FIGS. 11A to 13D, the contact body portion LB and the contact protruding portion LA can be formed by etching the upper portion of the active contact AC exposed through the mask pattern HM, and by partially etching the contact protruding portion LA during the process of etching the metal layer to form the first lower interconnect M1_I1. The barrier pattern BM can extend from a region on the side surface of the contact body portion LB to a region on the side surface of the contact protruding portion LA.

[0064] Hereinafter, the gate electrode GE will be described in more detail with reference to FIGS. 3A and 3C. The gate electrode GE can include an electrode body portion GB and an electrode protruding portion GC. The electrode body portion GB can be a linear pattern or a strip pattern extending in the first direction D1, and can have a third top surface TS3 located at a third height. The electrode protruding portion GC can have a shape protruding from the third top surface TS3 of the electrode body portion GB in the third direction D3. The electrode protruding portion GC can have a fourth top surface TS4 located at a fourth height. The fourth top surface TS4 of the electrode protruding portion GC can be in direct contact with the first metal layer M1 (for example, the bottom surface of the fourth lower interconnect M1_I4). In other words, the top surface (for example, the fourth top surface TS4) of the gate electrode GE can be directly connected to the fourth lower interconnect M1_I4 without inserting an additional structure therebetween.

[0065] The electrode protruding portion GC may include a second stepped structure SK2 having a side surface with a discontinuously varying slope. As an example, the electrode protruding portion GC may include a recessed side surface. Specifically, the lower side surface of the electrode protruding portion GC connected to the electrode main body portion GB may be defined by a third groove region RR3, and the upper side surface of the electrode protruding portion GC connected to the fourth lower interconnect line M1_I4 may be defined by a fourth groove region RR4. The third groove region RR3 and the fourth groove region RR4 may be empty spaces formed by partially removing an upper portion of the gate electrode GE and not connected to the first metal layer M1. The third groove region RR3 may be formed during a patterning process for forming the electrode protruding portion GC in the upper portion of the gate electrode GE, and the lower portion of the gate electrode GE below the electrode protruding portion GC and / or below the third groove region RR3 may then be defined as the electrode main body portion GB. The second stepped structure SK2 may be defined near the boundary between the third groove region RR3 and the fourth groove region RR4. The second interlayer insulating layer 113 may be provided to fill the third groove region RR3. A liner insulating layer 114 may be provided between the second interlayer insulating layer 113 and the electrode main body portion GB, however, the inventive concept is not limited thereto. The liner insulating layer 114 may also be provided between the second interlayer insulating layer 113 and the electrode protruding portion GC in the third groove region RR3. The third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 113 to fill the fourth groove region RR4. The fourth groove region RR4 may be formed during a patterning process for forming the fourth lower interconnect line M1_I4 and may be aligned with the side surface of the fourth lower interconnect line M1_I4. Accordingly, the electrode protruding portion GC may include a side surface aligned with the side surface of the fourth lower interconnect line M1_I4. As an example, the width of the fourth top surface TS4 of the electrode protruding portion GC in the first direction D1 may be substantially equal to the width of the bottom surface of the fourth lower interconnect line M1_I4.

[0066] The electrode main body portion GB and the electrode protruding portion GC may be provided without an interface therebetween and may be provided to form a single object. In other words, the electrode main body portion GB and the electrode protruding portion GC may be two parts of a structure formed of the same material simultaneously. As will be described later with reference to FIGS. 11A to 13D, the electrode main body portion GB and the electrode protruding portion GC may be formed by etching an upper portion of the gate electrode GE exposed through a mask pattern HM and by partially etching the electrode protruding portion GC during a process of etching a metal layer to form the fourth lower interconnect line M1_I4. The gate insulating layer GI may extend from a region on the side surface of the electrode main body portion GB to a region on the side surface of the electrode protruding portion GC.

[0067] As shown in FIG. 3B, the contact protrusion portion LA of the active contact AC may be adjacent to the electrode protrusion portion GC of the gate electrode GE connected to the second lower interconnect M1_I2. More specifically, the second top surface TS2 of the contact protrusion portion LA connected to the first lower interconnect M1_I1 may be spaced apart from the fourth top surface TS4 of the electrode protrusion portion GC connected to the second lower interconnect M1_I2 by a first distance d1. The first lower interconnect M1_I1 and the second lower interconnect M1_I2 may be interconnects extending in a direction (e.g., the second direction D2) in the extending direction of the gate electrode GE, adjacent to each other and parallel. The second lower interconnect M1_I2 may be disposed on the gate electrode GE and disposed at the same horizontal height as the first lower interconnect M1_I1.

[0068] Similarly, as shown in FIG. 3C, the electrode protrusion portion GC of the gate electrode GE may be adjacent to the contact protrusion portion LA connected to the fifth lower interconnect M1_I5. More specifically, the fourth top surface TS4 of the electrode protrusion portion GC connected to the fourth lower interconnect M1_I4 may be spaced apart from the second top surface TS2 of the contact protrusion portion LA connected to the fifth lower interconnect M1_I5 by a second distance d2. The second distance d2 and the first distance d1 may be equal to each other or may be different from each other. The first top surface TS1 may be located at the same horizontal height as the third top surface TS3, but the inventive concept is not limited thereto. The second top surface TS2 may be located at the same horizontal height as the fourth top surface TS4, but the inventive concept is not limited thereto.

[0069] As the integration density of the semiconductor device increases, the distance between the active contact AC and the gate electrode GE may be reduced, and thus the risk of process failures increases, such as an unexpected connection between vias or contacts. According to an exemplary embodiment of the inventive concept, by forming the contact protrusion portion LA from the upper portion of the active contact AC and forming the electrode protrusion portion GC from the upper portion of the gate electrode GE, the active contact AC and the gate electrode GE can be connected to the lower interconnects without additional vias or contacts for connection to the lower interconnects. Therefore, misalignment problems or connection failures that may occur when forming additional vias or contacts can be avoided. In addition, due to the recessed area, the contact protrusion portion LA and the electrode protrusion portion GC can be separated by a sufficient distance and thus process failures (e.g., contact problems or short circuit problems between the contact protrusion portion LA and the electrode protrusion portion GC) can be avoided.

[0070] The silicide pattern SC can be inserted between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2 respectively to provide reliable metal-semiconductor contact and reduce the resistance between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or the source / drain pattern SD2 through the silicide pattern SC. The bottom surface of the active contact AC can be lower than the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2. However, the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, the bottom surface of the active contact AC can be formed on the same plane as the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2. The silicide pattern SC can be formed of or include at least one of the following: metal silicide materials (e.g., titanium silicide (TiSi2), tantalum silicide (TaSi2), tungsten silicide (WSi2), nickel silicide (NiSi2), or cobalt silicide (CoSi2)).

[0071] Hereinafter, the gate electrode GE, the active contact AC, and the spacer GS in the cross-section taken along the second direction D2 will be described in more detail with reference to FIGS. 3D and 3E.

[0072] Referring to FIG. 3D, the top surface t1 of the active contact AC (e.g., the contact protrusion LA of the active contact AC) can be higher than the top surface t2 of the gate electrode GE (e.g., the electrode main body part GB of the gate electrode GE). The top surface t1 can correspond to the second top surface TS2 of FIG. 3B, and the top surface t2 can correspond to the third top surface TS3 of FIG. 3C. However, the inventive concept is not limited thereto.

[0073] Referring to FIG. 3E, the top surface t6 of the gate electrode GE (e.g., the electrode protrusion GC of the gate electrode GE) can be higher than the top surface t7 of the active contact AC (e.g., the contact main body part LB of the active contact AC). The top surface t6 can correspond to the fourth top surface TS4 of FIG. 3C, and the top surface t7 can correspond to the first top surface TS1 of FIG. 3B. However, the inventive concept is not limited thereto.

[0074] Referring to FIGS. 3D and 3E, the spacer GS may include a first spacer GS1 to a fourth spacer GS4. The third spacer GS3, the second spacer GS2, the first spacer GS1, and the fourth spacer GS4 may be sequentially arranged in the second direction D2. The first spacer GS1 may extend into the region between the contact protrusion portion LA and the electrode protrusion portion GC. Different from the first spacer GS1, the second spacer GS2 to the fourth spacer GS4 may not extend into the region between the contact protrusion portion LA and the electrode protrusion portion GC. In an exemplary embodiment of the inventive concept, the second spacer GS2 may be spaced apart from the first spacer GS1 when the active contact AC is inserted between the second spacer GS2 and the first spacer GS1. The third spacer GS3 may be spaced apart from the second spacer GS2 in the opposite direction of the second direction D2 when the gate electrode GE is inserted between the third spacer GS3 and the second spacer GS2, the second spacer GS2 being relative to the first spacer GS1 located on the opposite side. In other words, the second spacer GS2 and the third spacer GS3 may be disposed on the opposite side surfaces of the gate electrode GE. The fourth spacer GS4 may be spaced apart from the first spacer GS1 in the second direction D2 when the gate electrode GE is inserted between the fourth spacer GS4 and the first spacer GS1.

[0075] Referring to FIG. 3D, the height of the top surface t3 of the first spacer GS1 may be equal to or lower than the height of the top surface t1 of the contact protrusion portion LA. As will be described later, the first spacer GS1 may be protected from etching during the etching process by a bridging mask pattern disposed above and covering the first spacer GS1. However, a part (e.g., the top part) of the first spacer GS1 may be removed during the etching process. The amount of the first spacer GS1 removed may vary depending on the etching degree, so the first spacer GS1 may have its top surface t3 at a height equal to or lower than the height of the top surface t1 of the contact protrusion portion LA. The top surface t3 of the first spacer GS1 may be higher than the top surface t4 of the second spacer GS2 and the top surface t5 of the third spacer GS3. The top surface t2 of the electrode main body portion GB may be lower than the top surface t4 of the second spacer GS2 and the top surface t5 of the third spacer GS3.

[0076] Referring to FIG. 3E, the height of the top surface t8 of the first spacer GS1 may be equal to or lower than the height of the top surface t6 of the electrode protruding portion GC. Since a part of the first spacer GS1 (for example, the top part) may be removed during the etching process, the amount of the first spacer GS1 removed may vary depending on the etching degree. Therefore, the first spacer GS1 may have its top surface t8 at a height equal to or lower than the height of the top surface t6 of the electrode protruding portion GC. The top surface t8 of the first spacer GS1 may be higher than the top surface t10 of the second spacer GS2 and the top surface t9 of the fourth spacer GS4. The top surface t7 of the contact main body portion LB may be lower than the top surface t10 of the second spacer GS2 and the top surface t9 of the fourth spacer GS4. The height of the top surface t8 of the first spacer GS1 may be equal to the height of the top surface t3 of the first spacer GS1, but the concept of the present invention is not limited thereto.

[0077] FIG. 3F shows the profile of the first spacer GS1 in the first direction D1. The first spacer GS1 may have a profile similar to the profiles of the gate electrode GE and the active contact AC. For example, the first spacer GS1 may include a part disposed between the top surface t3 and the top surface t8 respectively disposed near the contact protruding portion LA and the electrode protruding portion GC and having a top surface t11 with a height lower than the heights of the top surface t3 and the top surface t8. The first spacer GS1 may further have a top surface t12 and a top surface t13, which are respectively placed near the contact main body portion LB and the electrode main body portion GB and are lower than the top surface t3 near the contact protruding portion LA, the top surface t8 near the electrode protruding portion GC, and the top surface t11 between the top surface t3 and the top surface t8. In other words, the first spacer GS1 may include a first component (or part) adjacent to the electrode protruding portion GC, a second component adjacent to the contact protruding portion LA, and a third component located between the first component and the second component, wherein the top surface t8 of the first component and the top surface t3 of the second component are higher than the top surface t11 of the third component. The first spacer may further include a fourth component, which is spaced apart from the third component when the first component or the second component is inserted between the fourth component and the third component, and the top surface t11 of the third component may be higher than the top surface t12 or the top surface t13 of the fourth component.

[0078] In other aspects, the first spacer GS1 may include a first portion PP1 having a height and profile similar to the height profiles of the contact body portion LB and the electrode body portion GB, and a second portion PP2 and a third portion PP3 having a height and profile similar to the height and profile of the contact protruding portion LA and the electrode protruding portion GC. A stepped structure similar to the first stepped structure SK1 and the second stepped structure SK2 may be provided between the second portion PP2 and the third portion PP3.

[0079] Returning to FIG. 1, a first unit boundary CB1 extending in the second direction D2 may be defined in a portion of the logic unit LC. A second unit boundary CB2 extending in the second direction D2 may be defined in another portion of the logic unit LC, and the second unit boundary CB2 is opposite to the first unit boundary CB1. A sixth lower interconnect line M1_R1 to which a drain voltage VDD (i.e., a power supply voltage) is applied may be disposed on the first unit boundary CB1. The sixth lower interconnect line M1_R1 to which the drain voltage VDD is applied may extend along the first unit boundary CB1 and in the second direction D2. A seventh lower interconnect line M1_R2 to which a source voltage VSS (i.e., a ground voltage) is applied may be disposed on the second unit boundary CB2. The seventh lower interconnect line M1_R2 to which the source voltage VSS is applied may extend along the second unit boundary CB2 and in the second direction D2. The first lower interconnect lines M1_I1 to the fifth lower interconnect lines M1_I5 may be arranged between the sixth lower interconnect line M1_R1 and the seventh lower interconnect line M1_R2 and spaced apart in the first direction D1 by a second pitch P2. The second pitch P2 may be smaller than the first pitch P1.

[0080] The second metal layer M2 may be provided in the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnect lines M2_I. The upper interconnect lines M2_I may also be referred to as second interconnect lines. Each of the upper interconnect lines M2_I may be a linear pattern or a strip pattern extending in the first direction D1. In other words, the upper interconnect lines M2_I may extend in the first direction D1 and may be parallel to each other. When viewed in a plan view, the upper interconnect lines M2_I may be parallel to the gate electrode GE. The upper interconnect lines M2_I may be arranged in the second direction D2 with a third pitch P3. The third pitch P3 may be smaller than the first pitch P1 and may be larger than the second pitch P2.

[0081] The second metal layer M2 may further include an upper via VI. The upper via VI may be disposed below the upper interconnect M2_I. The upper via VI may connect the lower interconnect to the upper interconnect M2_I. The upper interconnect M2_I of the second metal layer M2 and the upper via VI under the upper interconnect M2_I may be formed by the same process and may form a single object. For example, the upper interconnect M2_I and the upper via VI thereunder may be formed of the same material.

[0082] The lower interconnects M1_R1, M1_R2 of the first metal layer M1 and the lower interconnects M1_I1 to M1_I5 may include the same conductive material or may include different conductive materials from each other. For example, the lower interconnects M1_R1, M1_R2 and the lower interconnects M1_I1 to M1_I5 and the upper interconnect M2_I may be formed of or include at least one of the following: metal materials (e.g., aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co)).

[0083] In an exemplary embodiment of the inventive concept, additional metal layers may be further stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include wirings constituting an interconnect structure.

[0084] FIGS. 4A to 13D are diagrams showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Specifically, FIGS. 4A to 9A, 10B, and FIGS. 11A to 13A are cross-sectional views corresponding to line A-A' of FIG. 1. FIGS. 5B, 6B, and 7B are cross-sectional views corresponding to line B-B' of FIG. 1. FIGS. 5C, 6C, 7C, 8B, 9B, 10D, 11C, 12C, and 13C are cross-sectional views corresponding to line C-C' of FIG. 1. FIGS. 4B, 5D, 6D, 7D, 8C, 9C, 10E, 11D, 12D, and 13D are cross-sectional views corresponding to line D-D' of FIG. 1. FIGS. 10C, 11B, 12B, and 13B are cross-sectional views corresponding to line E-E' of FIG. 1. FIG. 10A is a plan view corresponding to FIG. 1 and shows a mask pattern.

[0085] Referring to FIGS. 1, 4A, and 4B, a substrate 100 including a PMOSFET region PR and an NMOSFET region NR can be provided. The sacrificial layer SAL and the active layer ACL can be alternately stacked on the substrate 100. For example, the sacrificial layers SAL can extend parallel to each other in the second direction D2 and can be disposed in the first direction D1 and spaced apart from each other in the first direction D1. The sacrificial layer SAL can be formed of or include one of the following, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe); and the active layer ACL can be formed of or include the other of the following, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In an exemplary embodiment of the inventive concept, the sacrificial layer SAL can be formed of or include silicon-germanium (SiGe), and the active layer ACL can be formed of or include silicon (Si). The germanium (Ge) concentration in each of the sacrificial layers SAL can be in the range of about 10 atomic % to about 30 atomic %.

[0086] Mask patterns can be respectively formed on the PMOSFET region PR and the NMOSFET region NR of the substrate 100. The mask patterns can be linear patterns or strip patterns extending in the second direction D2. A first patterning process using the mask patterns as an etching mask can be performed to form a first trench TR1 defining a first active pattern AP1 and a second active pattern AP2. The first patterning process can include a lithography process and an etching process. The first active pattern AP1 and the second active pattern AP2 can be respectively formed on the PMOSFET region PR and the NMOSFET region NR. Each of the first active pattern AP1 and the second active pattern AP2 can include a sacrificial layer SAL and an active layer ACL, which are disposed in an upper portion of the active pattern and alternately stacked.

[0087] A second patterning process can be performed on the substrate 100 to form a second trench TR2 that defines the PMOSFET region PR and the NMOSFET region NR. The second patterning process can include a lithography process and an etching process. The second trench TR2 can be formed between the PMOSFET region PR and the NMOSFET region NR and can separate the PMOSFET region PR from the NMOSFET region NR. The second trench TR2 can be formed deeper than the first trench TR1. Subsequently, a device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. For example, an insulating layer can be formed on the substrate 100 to cover the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed by recessing the insulating layer until the sacrificial layer SAL is exposed. For example, the device isolation layer ST can be formed on the substrate 100 to define the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed of or include at least one of the following, a thermal insulation material (e.g., silicon oxide (SiO2)). Each of the first active pattern AP1 and the second active pattern AP2 can include an upper portion that protrudes above the device isolation layer ST.

[0088] Referring to FIGS. 5A to 5D, a sacrificial pattern PP can be formed on the substrate 100 to pass through the first active pattern AP1 and the second active pattern AP2. Each of the sacrificial patterns PP can be a linear pattern or a strip pattern extending in the first direction D1. The sacrificial patterns PP can be arranged at a specific pitch in the second direction D2.

[0089] The formation of the sacrificial pattern PP can include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial patterns can extend parallel to each other in the first direction D1 and can be arranged in the second direction D2 and spaced apart from each other. The sacrificial layer can be formed of or include the following: polysilicon (p-Si).

[0090] A pair of spacers GS can be formed on both side surfaces of each of the sacrificial pattern PP and the hard mask pattern MP. The formation of the spacers GS can include conformally forming a spacer layer on the substrate 100 and anisotropically etching the spacer layer. To form the spacers GS, a process such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a combination thereof can be used. The spacer layer can be formed of or include at least one of the following: for example, silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), or silicon nitride (Si3N4). Alternatively, the spacer layer can be a multilayer structure including at least two of the following, for example, silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), or silicon nitride (Si3N4).

[0091] A first groove RS1 can be formed in the upper portion of the first active pattern AP1. The portions of the device isolation layer ST located on both sides of each of the first active patterns AP1 can be recessed during the formation of the first groove RS1. The first groove RS1 can be formed by etching the upper portion of the first active pattern AP1 using the hard mask pattern MP and the spacers GS as etching masks. First source / drain patterns SD1 can be respectively formed in the first grooves RS1. For example, a first SEG process using the inner surface of the first groove RS1 as a seed layer can be performed to form a first semiconductor layer SEL1. The first semiconductor layer SEL1 can be grown using the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 exposed through the first groove RS1 and the substrate 100 as seeds. As an example, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0092] The first semiconductor layer SEL1 can be formed of or include the following: a semiconductor material (such as SiGe) having a lattice constant greater than that of a semiconductor element (such as Si) of the substrate 100. The first semiconductor layer SEL1 can be formed to have a relatively low germanium (Ge) concentration. In an exemplary embodiment of the inventive concept, the first semiconductor layer SEL1 can contain only silicon (Si) and no germanium (Ge). Alternatively, the first semiconductor layer SEL1 can be provided to contain a small amount of germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 can be in the range of about 0 atomic % to about 10 atomic %.

[0093] The second semiconductor layer SEL2 can be formed by performing a second SEG process on the first semiconductor layer SEL1. The second semiconductor layer SEL2 can be formed to completely fill the first recess RS1. The second semiconductor layer SEL2 can be formed to have a relatively high germanium (Ge) concentration. As an example, the germanium (Ge) concentration of the second semiconductor layer SEL2 can be in the range of about 30 atomic % to about 70 atomic %.

[0094] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can constitute a first source / drain pattern SD1. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can be doped with impurities in-situ during the first SEG process and the second SEG process. Alternatively, after the first source / drain pattern SD1 is formed, the first source / drain pattern SD1 can be doped with impurities via an ion implantation process. For example, an ion implantation process can be used after the SEG process to inject dopants into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type). In an exemplary embodiment of the present inventive concept, each of the first source / drain patterns SD1 can include a silicon germanium (SiGe) layer doped with a p-type dopant such as boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0095] The second recess RS2 can be formed in an upper portion of the second active pattern AP2. Second source / drain patterns SD2 can be respectively formed in the second recesses RS2. For example, the second source / drain patterns SD2 can be formed by a SEG process using the inner surface of the second recesses RS2 as a seed layer. In an exemplary embodiment of the present inventive concept, the second source / drain patterns SD2 can be formed of or include a semiconductor material (e.g., Si) that is the same as the semiconductor material of the substrate 100. The second source / drain patterns SD2 can be doped to have a second conductivity type (e.g., n-type). In an exemplary embodiment of the present inventive concept, each of the second source / drain patterns SD2 can include a silicon (Si) layer doped with an N-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi).

[0096] Referring to FIGS. 6A to 6D, a first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the spacer GS, and then a planarization process may be performed on the first interlayer insulating layer 110 to expose at least a portion of the sacrificial pattern PP. The planarization process of the first interlayer insulating layer 110 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. The hard mask pattern MP may be completely removed during the planarization process. Subsequently, an upper trench ET1 may be formed to expose the side surface of the sacrificial layer SAL. The sacrificial layer SAL disposed on the PMOSFET region PR and the NMOSFET region NR of the logic cell LC and exposed through the upper trench ET1 may be selectively removed, while the sacrificial layer SAL on the side regions of the logic cell LC may not be removed. Specifically, an etching process that selectively etches only the sacrificial layer SAL may be performed to remove only the sacrificial layer SAL and leave the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Since the sacrificial layer SAL is selectively removed, only the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may remain on each of the first active pattern AP1 and the second active pattern AP2. Hereinafter, the empty region formed by removing the sacrificial layer SAL will be referred to as a third recess ET2. For example, the sacrificial layer SAL may be selectively etched by using the etch selectivity difference between the sacrificial layer SAL and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 to form the third recess ET2. In an exemplary embodiment of the inventive concept, the third recess ET2 may be formed by a wet etching process. The third recess ET2 may be defined between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0097] Referring to FIGS. 7A to 7D, an inner spacer IP may be formed in the third recess ET2. In an exemplary embodiment of the inventive concept, the inner spacer IP may be formed by forming an insulating layer to cover the second source / drain pattern SD2 and performing an etching process on the insulating layer. The inner spacer IP may be formed of or include at least one of the following: for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxycarbide (SiOC), or aluminum oxide (Al2O3).

[0098] The gate insulating layer GI can be conformally formed in the upper trench ET1 and the third groove ET2. The gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE can be formed to fill the upper trench ET1 and the third groove ET2. Specifically, the gate electrode GE can include a first portion P01, a second portion P02, and a third portion P03 that fill the third groove ET2. The gate electrode GE can further include a fourth portion P04 that fills the upper trench ET1. The gate capping pattern GP can be formed on the gate electrode GE.

[0099] Referring to FIGS. 8A to 8C, an upper portion of the first interlayer insulating layer 110 between the gate electrodes GE can be removed, and the gate pattern 111 for defining the region of the active contact AC can be formed between the gate electrodes GE. The gate pattern 111 can be formed of or include at least one of the following: for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxycarbide (SiOC), or aluminum oxide (Al2O3).

[0100] Referring to FIGS. 9A to 9C, the first interlayer insulating layer 110 between the gate patterns 111 can be removed to expose the first source / drain pattern SD1 and the second source / drain pattern SD2, and then, the active contact AC can be formed on the first source / drain pattern SD1 and the second source / drain pattern SD2. The formation of the active contact AC can include sequentially forming a barrier pattern BM and a conductive pattern FM, and performing a planarization process. The planarization process can be performed to expose the top surface of the gate electrode GE. The barrier pattern BM can be formed to include a metal layer and a metal nitride layer. The conductive pattern FM can be formed of or include at least one of the following: metal materials (such as aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co)). During the formation of the active contact AC, the silicide pattern SC can be respectively formed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2 to provide a reliable metal-semiconductor contact and reduce the resistance between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. In an exemplary embodiment of the present inventive concept, the silicide pattern SC can be formed of or include at least one of the following: for example, titanium silicide (TiSi2), tantalum silicide (TaSi2), tungsten silicide (WSi2), nickel silicide (NiSi2), or cobalt silicide (CoSi2).

[0101] Referring to FIGS. 10A to 10E, a blocking insulating layer 120 can be formed, and a mask pattern HM can be formed to define an electrode protrusion GC in the upper part of the gate electrode GE and a contact protrusion LA in the upper part of the active contact AC. In an exemplary embodiment of the inventive concept, the blocking insulating layer 120 can be formed of or include at least one of the following: for example, silicon nitride (Si3N4) or silicon oxynitride (SiON). The mask pattern HM can be formed of or include at least one of the following: for example, a photoresist material, silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0102] Each of the mask patterns HM can include a first portion P1 for defining the contact protrusion LA (see, for example, FIG. 11A), a second portion P2 for defining the electrode protrusion GC (see, for example, FIG. 11B), and a third portion P3 connecting the first portion P1 to the second portion P2. The third portion P3 can cover a first spacer GS1, which is a part of a spacer GS placed between the contact protrusion LA and the region of the electrode protrusion GC. The first portion P1 and the second portion P2 can be offset from each other in a first direction D1 with the third portion P3 inserted between the first portion P1 and the second portion P2. Since the sizes of the first portion P1 and the second portion P2 can be small (e.g., about 20 nm), there is a problem of lifting, such as during an etching process, the first portion P1 and / or the second portion P2 detaching from the blocking insulating layer 120. When a bridging mask pattern such as the third portion P3 is used to connect the first portion P1 and the second portion P2, mask lifting during the etching process can be avoided. FIG. 10A shows an example in which one first portion P1 and one second portion P2 are connected to each other via one third portion P3 inserted between the first portion P1 and the second portion P2, but at least one of the first portion P1 to the third portion P3 can be provided as a plurality.

[0103] Referring to FIGS. 11A to 11D, the first groove region RR1 can be formed by etching the upper portions of the gate electrode GE and the active contact AC exposed through the mask pattern HM. For example, the mask pattern HM can be used as an etching mask to perform a patterning process on the gate electrode GE and the active contact AC. Accordingly, the electrode protrusion GC can be formed in the upper portion of the gate electrode GE, and the contact protrusion LA can be formed in the upper portion of the active contact AC. The lower portion of the gate electrode GE below the electrode protrusion GC can be defined as the electrode main body portion GB, and the lower portion of the active contact AC below the contact protrusion LA can be defined as the contact main body portion LB. The formation of the first groove region RR1 can include at least one of a dry etching process and / or a wet etching process. The electrode protrusion GC and the contact protrusion LA can be formed through the same etching process, but the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, the electrode protrusion GC and the contact protrusion LA can be separately formed through different etching processes. The first groove region RR1 may not be formed in a part of the first spacer GS1 covered by the third part P3. During the formation of the first groove region RR1, in addition to the first spacer GS1, the upper portions of other parts of the spacer GS may be etched. For example, since the first spacer may not be etched, during the formation of the first groove RR1, the top surface of the first spacer GS1 and the top surfaces of the electrode protrusion GC and the contact protrusion LA may be at the same height. During the formation of the first groove region RR1, the blocking insulating layer 120 may also be etched to form a blocking insulating pattern 121.

[0104] Referring to FIGS. 12A to 12D, the mask pattern HM can be removed, an insulating layer can be formed to fill the first groove region RR1, and then the second interlayer insulating layer 113 can be formed by performing a planarization process on the insulating layer. The top surface of the second interlayer insulating layer 113 can be formed at the same horizontal height as the top surfaces of the contact protrusion LA and the electrode protrusion GC. The second interlayer insulating layer 113 can be formed of or include at least one of the following: for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxycarbide (SiOC), or aluminum oxide (Al2O3).

[0105] Referring to FIGS. 13A to 13D, a metal layer may be formed on the second interlayer insulating layer 113 and may be patterned to form lower interconnects M1_R1, lower interconnects M1_R2, and lower interconnects M1_I1 to lower interconnects M1_I5. During the patterning of the metal layer, the second interlayer insulating layer 113, the contact protrusion LA, and the electrode protrusion GC may also be partially etched to form a second groove region RR2. In an exemplary embodiment of the inventive concept, a portion of the first spacer GS1 disposed between the gate electrode GE and the active contact AC may be removed during the formation of the lower interconnects M1_R1, lower interconnects M1_R2, and lower interconnects M1_I1 to lower interconnects M1_I5. Since a portion (e.g., the top portion) of the first spacer GS1 may be removed, the height of the top surface t3 of the first spacer GS1 may be equal to or lower than the height of the top surface t1 of the contact protrusion LA (e.g., see FIGS. 3D and 3E). According to an exemplary embodiment of the inventive concept, since a bridging mask pattern such as the third portion P3 of the mask pattern HM is used in the etching process, mask bulge can be avoided, and the first spacer GS1 disposed between the gate electrode GE and the active contact AC may be less recessed compared to an etching process of a mask pattern without a bridging mask pattern (e.g., without the third portion P3), thereby facilitating a shorter margin.

[0106] Referring back to FIGS. 2A to 2E, a second metal layer M2 including upper vias VI and upper interconnects M2_I may be formed. The second metal layer M2 may be formed in the fourth interlayer insulating layer 140. The upper interconnects M2_I and the upper vias VI of the second metal layer M2 may be formed in one step by a dual damascene process. The lower interconnects M1_R1, lower interconnects M1_R2, and lower interconnects M1_I1 to lower interconnects M1_I5 and the upper interconnects M2_I may be formed of or include at least one of the following: a metal material (e.g., aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and cobalt (Co)).

[0107] As the integration density of semiconductor devices increases, the size of the mask pattern used to form a precise structure decreases. In this case, since the contact area between the mask pattern and the underlying layer decreases, the mask pattern may be detached from the underlying layer or misaligned with the underlying layer for various reasons. This may lead to process failures or a reduction in the reliability of semiconductor devices. According to an exemplary embodiment of the inventive concept, the mask patterns used to form the contact protrusion and the electrode protrusion may be formed to be connected to each other. In this case, detachment of the mask pattern from the underlying layer can be avoided, and thus process failures of semiconductor devices can be avoided.

[0108] In a semiconductor device according to an exemplary embodiment of the inventive concept, since the upper portions of the active contacts and the upper portions of the gate electrodes serve as the contact protrusion portions and the electrode protrusion portions, the active contacts and the gate electrodes can be connected to the lower interconnects without additional vias or contacts for connecting to the lower interconnects. Accordingly, misalignment problems or connection failures that may occur when forming additional vias or contacts can be avoided. In addition, due to the groove region, the contact protrusion portions and the electrode protrusion portions can be separated by a sufficiently large distance and thus process failures (e.g., contact problems or short circuit problems between the contact protrusion portions and the electrode protrusion portions) can be avoided.

[0109] According to an exemplary embodiment of the inventive concept, mask patterns respectively for forming the contact protrusion portions and the electrode protrusion portions may be formed to be connected to each other. In this case, detachment of the mask patterns from the underlying layer can be avoided and thus process failures of the semiconductor device can be avoided.

[0110] Although embodiments of the inventive concept have been specifically illustrated and described, those of ordinary skill in the art will understand that changes in form and detail may be made to the embodiments without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Brief Description of the Drawings

[0011] Exemplary embodiments of the inventive concept will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view showing a semiconductor device according to an exemplary embodiment of the inventive concept. FIGS. 2A to 2E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 1, respectively. FIG. 3A is a perspective view showing region Q of FIG. 1. FIG. 3B is an enlarged view showing region P of FIG. 2C. FIG. 3C is an enlarged view showing region R of FIG. 2D. FIG. 3D is an enlarged view showing region S of FIG. 2A. FIG. 3E is an enlarged view showing region X of FIG. 2E. FIG. 3F is a conceptual view showing a first spacer and its adjacent region. FIGS. 4A, 4B, 5A to 5D, 6A to 6D, 7A to 7D, 8A to 8C, 9A to 9C, 10B to 10E, 11A to 11D, 12A to 12D, and 13A to 13D are cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. FIG. 10A is a plan view corresponding to FIG. 1. Since the drawings in FIGS. 1 to 13D are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity.

Claims

1. A semiconductor device, comprising: Active pattern, located on the substrate; The source / drain pattern is located on the active pattern; Channel pattern, connected to the source / drain pattern; A gate electrode is located on the channel pattern; an active contact is located on the source / drain pattern; a first lower interconnect is located on the active contact; a second lower interconnect is disposed on the gate electrode and positioned at the same horizontal height as the first lower interconnect; a first spacer is located between the gate electrode and the active contact; and a second spacer is spaced apart from the first spacer when the gate electrode or the active contact is inserted between the second spacer and the first spacer, wherein the gate electrode includes an electrode body portion and an electrode protrusion portion, the electrode protrusion portion protrudes from the top surface of the electrode body portion and contacts the bottom surface of the second lower interconnect; the active contact includes a contact body portion and a contact protrusion portion, the contact protrusion portion protrudes from the top surface of the contact body portion and contacts the bottom surface of the first lower interconnect; the contact protrusion portion and the electrode protrusion portion are spaced apart from each other, and the top surface of the first spacer is higher than the top surface of the second spacer.

2. The semiconductor device as claimed in claim 1, wherein the first spacer comprises: The first part is adjacent to the electrode protrusion; The second part is adjacent to the protruding contact portion; And a third part, located between the first part and the second part, wherein the top surface of the first part and the top surface of the second part are higher than the top surface of the third part.

3. The semiconductor device of claim 2, wherein the first spacer further includes a fourth portion, the fourth portion being spaced apart from the third portion when the first portion or the second portion is inserted between the fourth portion and the third portion, and the top surface of the third portion being higher than the top surface of the fourth portion.

4. The semiconductor device of claim 1, wherein the height of the top surface of the contact protrusion is equal to or higher than the height of the top surface of the first spacer.

5. The semiconductor device of claim 1, wherein the height of the top surface of the electrode protrusion is equal to or higher than the height of the top surface of the first spacer.

6. The semiconductor device of claim 1, wherein the top surface of the electrode protrusion is located at the same horizontal height as the top surface of the contact protrusion.

7. The semiconductor device of claim 1, wherein the electrode body portion and the electrode protrusion portion are configured to have no interface therebetween and are configured to form a single object.

8. The semiconductor device of claim 1, wherein the electrode protrusion includes a stepped structure having side surfaces with discontinuously varying slopes.

9. The semiconductor device of claim 1, wherein the contact protrusion includes a side surface aligned with the side surface of the first lower interconnect.

10. The semiconductor device of claim 1, wherein the contact body portion and the contact protrusion portion are configured to have no interface therebetween and to form a single object.

11. The semiconductor device of claim 1, wherein the active contact includes a barrier pattern that extends from a side surface of the contact body portion to a side surface of the contact protrusion portion.

12. The semiconductor device of claim 1, wherein the contact protrusion includes a stepped structure having side surfaces with discontinuously varying slopes.

13. A semiconductor device, comprising: Active pattern, located on the substrate; The source / drain pattern is located on the active pattern; Channel pattern, connected to the source / drain pattern; A gate electrode is located on the channel pattern; an active contact is located on the source / drain pattern; a first lower interconnect is located on the active contact; a second lower interconnect is disposed on the gate electrode and positioned at the same horizontal height as the first lower interconnect; and a first spacer is located between the gate electrode and the active contact, wherein the gate electrode includes an electrode body portion and an electrode protrusion portion, the electrode protrusion portion protrudes from the top surface of the electrode body portion and contacts the bottom surface of the second lower interconnect; the active contact includes a contact body portion and a contact protrusion portion, the contact protrusion portion protrudes from the top surface of the contact body portion and contacts the bottom surface of the first lower interconnect; the contact protrusion portion and the electrode protrusion portion are spaced apart from each other; the first spacer includes: a first portion adjacent to the electrode protrusion portion; a second portion adjacent to the contact protrusion portion; and a third portion located between the first portion and the second portion, wherein the top surfaces of the first portion and the second portion are higher than the top surface of the third portion.

14. The semiconductor device of claim 13, wherein the first spacer further includes a fourth portion, the fourth portion being spaced apart from the third portion when the first portion or the second portion is inserted between the fourth portion and the third portion, and the top surface of the third portion being higher than the top surface of the fourth portion.

15. The semiconductor device of claim 13, wherein the height of the top surface of the contact protrusion is equal to or higher than the height of the top surface of the first spacer.

16. The semiconductor device of claim 13, wherein the height of the top surface of the electrode protrusion is equal to or higher than the height of the top surface of the first spacer.

17. The semiconductor device of claim 13, wherein the top surface of the electrode protrusion is located at the same horizontal height as the top surface of the contact protrusion.

18. A semiconductor device, comprising: A substrate comprising a P-type metal-oxide-semiconductor (MOSFET) region and an N-type metal-oxide-semiconductor (MOSFET) region adjacent to each other in a first direction; a first active pattern and a second active pattern respectively disposed on the P-type MOSFET region and the N-type MOSFET region; a first source / drain pattern and a second source / drain pattern, wherein the first source / drain pattern is located on the first active pattern and the second source / drain pattern is located on the second active pattern; an active contact located on the first source / drain pattern and the second source / drain pattern; a first channel pattern and a second channel pattern respectively connected to the first source / drain pattern and the second source / drain pattern, each of the first channel pattern and the second channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other. A first gate electrode and a second gate electrode extend in the first direction to pass through the first active pattern and the second active pattern, respectively, and each of the first gate electrode and the second gate electrode includes a first portion inserted between the substrate and the first semiconductor pattern, a second portion inserted between the first semiconductor pattern and the second semiconductor pattern, a third portion inserted between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion located on the third semiconductor pattern; a first gate insulating layer and a second gate insulating layer are respectively inserted between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode; a first metal layer is located on the first gate electrode and the second gate electrode, the first metal layer including a first interconnect; a first spacer is located between the first gate electrode and one of the active contacts. A second spacer, spaced apart from the first spacer when one of the first gate electrode or the active contact is inserted between the second spacer and the first spacer; and a second metal layer disposed on the first metal layer, the second metal layer including second interconnects electrically connected to the first interconnects respectively, wherein each of the active contacts includes a contact body portion and a contact protrusion portion, the contact protrusion portion protruding from the top surface of the contact body portion and contacting the bottom surface of one of the first interconnects, each of the first gate electrode and the second gate electrode includes an electrode body portion and an electrode protrusion portion, the electrode protrusion portion protruding from the top surface of the electrode body portion and contacting the bottom surface of the other of the first interconnects, the contact protrusion portion and the electrode protrusion portion being spaced apart from each other, and the top surface of the first spacer being higher than the top surface of the second spacer.

19. The semiconductor device of claim 18, wherein the first spacer comprises: The first component is located adjacent to the electrode protrusion. The second component is located adjacent to the protruding contact portion; And a third component, located between the first component and the second component, wherein the top surface of the first component and the top surface of the second component are higher than the top surface of the third component.

20. The semiconductor device of claim 19, wherein the first spacer further includes a fourth component, the fourth component being spaced apart from the third component when the first component or the second component is inserted between the fourth component and the third component, and the top surface of the third component is higher than the top surface of the fourth component.

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