Methods of forming semiconductor structures

Abstract

A method for forming a semiconductor structure and multiple semiconductor structures is described. The method includes patterning a substrate to form a first opening and a second opening, the substrate including an n-transistor and a p-transistor, the first opening being on the n-transistor and the second opening being on the p-transistor; pre-cleaning the substrate; depositing titanium silicon dioxide (TiSi) layers on the n-transistor and p-transistor by plasma-enhanced chemical vapor deposition (PECVD); depositing a first barrier layer on the TiSi layers as appropriate, and selectively removing the first barrier layer from the p-transistor; selectively forming a molybdenum silicon dioxide (MoSi) layer on the TiSi layers on the n-transistor and p-transistor; forming a second barrier layer on the MoSi layers; and annealing the semiconductor structure. This method can be performed in a processing chamber without disrupting the vacuum.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of semiconductor devices and the manufacture of semiconductor devices. More specifically, the embodiments of this disclosure relate to a method for selectively forming silicon layers having ohmic and pseudo-ohmic contacts. Prior Technology

[0002] Integrated circuits have evolved into complex components that can include millions of transistors, capacitors, and resistors on a single chip. In the evolution of integrated circuits, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest components (or lines) produced by the manufacturing process) has decreased.

[0003] Transistors are critical components in most integrated circuits. Since the drive current and resulting speed of a transistor are proportional to its gate width, faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and fin field-effect transistors (FFETs) have been developed to address this conflict between maximizing drive current and minimizing size. FinFETs feature a fin-shaped channel region, significantly increasing the transistor's size without substantially increasing its footprint, and are now used in many integrated circuits. However, finFETs also have their own drawbacks.

[0004] As transistor feature sizes continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor structure to enhance electrostatic coupling and reduce negative impacts such as parasitic capacitance and off-state leakage. Examples of transistor structures include planar structures, FinFET structures, and gate-all-around (GAA) structures. The performance of a logic gate is related to the properties of the materials used, as well as the thickness and area of ​​the structural layers. However, challenges arise as some gate characteristics are adjusted to accommodate device scaling.

[0005] Ohmic or pseudo-ohmic contacts are key components for achieving low contact resistance at the source / drain contacts in transistors. There is a need in the art for methods to selectively form ohmic and pseudo-ohmic contacts on both nFET and pFET contacts. Summary of the Invention

[0006] One or more embodiments of this disclosure relate to a method for forming a semiconductor structure. The method includes patterning a substrate to form a first opening and a second opening, the substrate including an n-transistor and a p-transistor, the first opening being on the n-transistor and the second opening being on the p-transistor; pre-cleaning the substrate; depositing a titanium silicon carbide (TiSi) layer on the n-transistor and the p-transistor by plasma-enhanced chemical vapor deposition (PECVD); depositing a first barrier layer on the TiSi layer as appropriate, and selectively removing the first barrier layer from the p-transistor; selectively forming a molybdenum silicon carbide (MoSi) layer on the TiSi layer on the n-transistor and the p-transistor; forming a second barrier layer on the MoSi layer; and annealing the semiconductor structure.

[0007] Another embodiment of this disclosure relates to a method for forming a semiconductor structure. The method includes patterning a substrate to form a first opening, the substrate including an n-transistor and a p-transistor, the first opening being above the n-transistor; pre-cleaning the substrate; depositing a titanium silicon dioxide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD); filling the first opening with a first interstitial material; forming a mask layer on the top surface of the n-transistor; patterning the substrate to form a second opening above the p-transistor; selectively forming a molybdenum silicon dioxide (MoSi) layer on the p-transistor; annealing the semiconductor structure; and filling the second opening with a second interstitial material.

[0008] Other embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes an n-transistor and a p-transistor; one or more of the n-transistor and p-transistor having titanium silicon dioxide (TiSi) layers; one or more of the n-transistor and p-transistor having molybdenum silicon dioxide (MoSi) layers; optionally, one or more of the titanium silicon dioxide (TiSi) layers and molybdenum silicon dioxide (MoSi) layers having barrier layers; and an interstitial material. Simple Explanation of the Diagram

[0009] To gain a more detailed understanding of the features described above, a more specific description of the present disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and should therefore not be considered as limiting its scope, as the present disclosure may acknowledge other equivalent embodiments.

[0010] Figure 1A illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0011] Figure 1B illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0012] Figure 1C illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0013] Figure 1D illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0014] Figure 1E illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0015] Figure 1F illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0016] Figure 2A illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0017] Figure 2B illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0018] Figure 2C illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0019] Figure 2D illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0020] Figure 2E illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0021] Figure 2F illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0022] Figure 2G illustrates a semiconductor structure according to one or more embodiments of this disclosure;

[0023] Figure 3 illustrates a process flow diagram of a method according to one or more embodiments of this disclosure; and

[0024] Figure 4 illustrates a process flow diagram of a method according to one or more embodiments of this disclosure.

[0025] In the accompanying drawings, similar parts and / or features may have the same element symbol. Furthermore, various parts of the same type may be distinguished by adding a hyphen after the element symbol and a second reference numeral to differentiate similar parts. If only the first reference numeral is used in the specification, the description applies to any similar parts having the same first reference numeral, regardless of the second reference numeral. Implementation

[0026] Before describing several exemplary embodiments of the invention, it should be understood that the invention is not limited to the details of the construction or process steps set forth in the following description. The invention can have other embodiments and can be practiced or performed in various ways.

[0027] As used herein, the term "substrate" refers to the surface or portion of the surface on which the process is applied. Those skilled in the art will also understand that, unless the context clearly states otherwise, reference to substrate may also refer to only a portion of the substrate. Furthermore, reference to deposition on a substrate may refer to a bare substrate or a substrate on which one or more films or features are deposited or formed.

[0028] Furthermore, as used herein, the term "substrate" refers to any substrate on which a film treatment is performed during the manufacturing process, or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatment can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, dielectric materials, other conductive materials, or combinations thereof. In some embodiments, the substrate comprises silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminum (TiAl), silicon germanium (SiGe), silicon germanium boron (SiGeB), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃), or combinations thereof. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the disclosed film treatment steps may also be performed on the underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as referred to in the context.

[0029] According to one or more embodiments, the term "on" regarding a film or film layer includes a film or layer directly on a surface, such as a substrate surface, and a film or layer having one or more underlying layers between it and a surface (e.g., a substrate surface). Therefore, in one or more embodiments, the phrase "on a substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film in contact with a surface, such as a substrate surface, without an intermediate layer. Therefore, the phrase "layer directly on a substrate surface" refers to a layer in direct contact with a substrate surface without any intermediate layers therebetween.

[0030] As used herein, the term "substrate surface" means any substrate surface on which layers may be formed. A substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of a feature may be any suitable shape, including but not limited to peaks, trenches, and cylindrical vias. As used herein, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom; peaks having a top and two sidewalls extending upward from the surface; and vias having sidewalls extending downward from the surface having an open bottom.

[0031] As used herein, the term "processing chamber" includes portions of the processing chamber adjacent to the substrate surface, but does not encompass the entire internal volume of the processing chamber. For example, in a sector of a spatially separated processing chamber, a portion of the processing chamber adjacent to the substrate surface is cleared of one or more reactive compounds by any suitable technique, including but not limited to moving the substrate through an air curtain to a portion or sector of the processing chamber that does not contain or substantially does not contain reactive compounds.

[0032] As used herein, the terms "atomic layer deposition" or "cyclic deposition" refer to the sequential exposure of two or more reactive compounds to deposit a material layer on a substrate surface. The substrate or portions of its surface are sequentially exposed to two or more reactive compounds introduced into a reaction zone within a processing chamber. This sequential exposure of the reactive gases prevents or minimizes gas-phase reactions between them. In time-domain ALD processes, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface. In spatial ALD processes, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds such that no given point on the substrate is substantially exposed to more than one reactive compound simultaneously. As used in this specification and the appended claims, the term "substantially" as understood by one skilled in the art means that a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and that such simultaneous exposure is unintentional.

[0033] In one state of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between reactive compound pulses. The reactive compounds are alternately pulsed until the desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsed compound A, purge gas, compound B, and purge gas constitutes one cycle. The cycle may begin with compound A or compound B and continue in the respective order until a film with the desired thickness is obtained. In one or more embodiments, the time-domain ALD process may be performed in a predetermined sequence using more than two reactive compounds.

[0034] In one embodiment of a spatial ALD process, a first reactant gas and a second reactant gas are simultaneously delivered to the reaction zone, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery device such that any given point on the substrate is exposed to the first reactant gas and the second reactant gas. In one or more embodiments, the spatial ALD process can be performed using more than two reactive compounds in a predetermined sequence.

[0035] In some embodiments, the substrate surface is substantially sequentially exposed to the first reactive compound and the second reactive compound. As used throughout the specification, "substantially sequentially" means that the majority of the exposure time of the first reactive compound does not overlap with the exposure time of the second reactive compound, although some overlap may exist.

[0036] As used herein, the term "chemical vapor deposition" refers to exposing at least one reactive compound to deposit a layer of material on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive compounds in a processing chamber to allow for vapor-phase reaction and deposition of the reactive compounds. In some embodiments, a CVD process includes simultaneously exposing a substrate surface to two or more reactive compounds. In some embodiments, a CVD process includes continuously exposing a substrate surface to a first reactive compound and intermittently exposing it to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film of a predetermined thickness. In a CVD process, the film may be deposited by a single exposure to a mixed reactive compound, or by multiple exposures to a mixed reactive compound, with decontamination in between. In some embodiments, the substrate surface is substantially simultaneously exposed to both a first and a second reactive compound.

[0037] As used throughout this specification, "substantially simultaneously" means that the majority of the duration of exposure to the first reacting compound overlaps with the duration of exposure to the second reacting compound.

[0038] As used herein, the term "decontamination" includes any suitable decontamination process that removes unreacted precursors, reaction products, and byproducts from a processing area. Suitable decontamination processes include moving a substrate through a gas curtain to a portion or sector of the processing area that does not contain or substantially does not contain reactants. In one or more embodiments, the decontamination chamber includes the application of a vacuum. In some embodiments, the decontamination area includes the flow of a decontamination gas over the substrate. In some embodiments, the decontamination process includes the flow of an inert gas. In one or more embodiments, the decontamination gas system is selected from one or more of nitrogen (N₂), helium (He), and argon (Ar). In some embodiments, the first reaction compound is purged from the reaction chamber for a duration ranging from 0.2 to 30 seconds, 0.2 to 10 seconds, 0.2 to 5 seconds, 0.5 to 30 seconds, 0.5 to 10 seconds, 0.5 to 5 seconds, 1 to 30 seconds, 1 to 10 seconds, 1 to 5 seconds, 5 to 30 seconds, 5 to 10 seconds, or 10 to 30 seconds before the substrate is exposed to the second reaction compound.

[0039] Plasma-enhanced chemical vapor deposition (PECVD) is widely used for depositing thin films due to its cost-effectiveness and versatility in film properties. For example, in a PECVD process, a hydrocarbon source, such as gaseous hydrocarbons or liquid hydrocarbon vapors already entrained in a carrier gas, is introduced into the PECVD chamber. A plasma-initiating gas, typically helium, is also introduced into the chamber. The plasma is then activated in the chamber to generate excited CH radicals. These excited CH radicals chemically bind to the substrate surface located within the chamber, forming the desired film thereon. The embodiments described herein with reference to the PECVD process can be performed using any suitable thin film deposition system. Any apparatus description herein is and should not be construed as limiting the scope of the embodiments described herein.

[0040] As used herein, the terms "shim" or "barrier layer" refer to a layer compliantly formed along at least a portion of the sidewall and / or lower surface of an opening, such that a majority of the opening prior to layer deposition remains unfilled after layer deposition. The shim may be formed along the entire sidewall and the lower surface of the opening. The shim may be formed by any process known to those skilled in the art. In some embodiments, the shim comprises a metal nitride, a PVD metal, or a combination thereof.

[0041] Transistors are circuit components or elements that are often formed on semiconductor devices. Depending on the circuit design, in addition to capacitors, inductors, resistors, diodes, wires, or other components, many other transistors can be formed on semiconductor devices. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET). They have an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the applied voltage is used to amplify or switch electronic signals.

[0042] Generally, a transistor includes a gate formed between a source region and a drain region. The source and drain regions may include doped regions of the substrate and may exhibit a doping profile suitable for a specific application. The gate is located above the channel region and may include a gate electrode inserted into the substrate between the gate and the channel region.

[0043] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a device. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device, generated by the voltage difference between the body and the gate. The three terminals of a FET are the source (S), through which charge carriers enter the channel; the drain (D), through which charge carriers leave the channel; and the gate (G), which is the terminal for modulating the channel conductivity. Conventionally, the current entering the channel at the source (S) is designated as IS, and the current entering the channel at the drain (D) is designated as ID. The drain-to-source voltage is designated as VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0044] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitor between the body electrode and the gate electrode located above the body, and is insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated from the body region. These regions can be p-type or n-type, but they belong to the same type and are the opposite of the body region. The source and drain (different from the body) are highly doped, as indicated by the "+" sign after the doping type.

[0045] If the MOSFET is an n-channel or nMOS FET, then the source and drain are in the n+ region, while the bulk is in the p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are in the p+ region, while the bulk is in the n region. The source is named as such because it is the origin of charge carriers flowing through the channel (electrons in the n-channel and holes in the p-channel); similarly, the drain is where charge carriers leave the channel.

[0046] Embodiments of this disclosure provide semiconductor structures and methods for forming semiconductor structures. Ohmic and / or pseudo-ohmic contacts are key components for achieving low contact resistance of source / drain contacts. One or more embodiments advantageously provide an integration scheme to produce double silicide to create ohmic / pseudo-ohmic contacts on both nFET and pFET contacts.

[0047] Embodiments of this disclosure are described with the aid of accompanying drawings, which illustrate the process for forming double silicide on ohmic / pseudo-ohmic contacts on both nFET and pFET contacts. Referring to Figures 1A-1E, a semiconductor structure 100 is shown. The semiconductor structure 100 includes an n-transistor 102 and a p-transistor 104. In one or more embodiments, each of the n-transistor 102 and the p-transistor 104 includes a dielectric material 110, a source / drain material 120, and a substrate 130.

[0048] In one or more embodiments, dielectric material 110 may comprise any suitable dielectric material known to those skilled in the art. In some embodiments, dielectric material 110 comprises one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and low-k dielectrics. As used herein, terms such as “silicon oxide” and “silicon nitride” refer to materials comprising silicon and oxygen or silicon and nitrogen. “Silicon oxide” and “silicon nitride” should not be construed as implying any stoichiometric ratio. In other words, dielectric materials comprising silicon oxide or silicon nitride may be stoichiometric or non-stoichiometric, silicon-rich or silicon-poor. In some embodiments, dielectric material 110 comprises silicon oxide (SiO2).

[0049] In some embodiments, the n-transistor 102 and p-transistor 104 include source and drain contacts. In one or more embodiments, the source / drain material 120 may have more than one layer. In some embodiments, the source / drain material 120 includes a silicon layer (e.g., SiGe, SiP, etc.) having a doped epitaxial layer, a second silicide layer that may contain nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0050] In one or more specific embodiments, the source / drain material 120 of the n-transistor 102 comprises phosphorus (P)-doped silicon (Si). In one or more embodiments, the source / drain material 120 of the n-transistor 102 has a band gap in the range of about 1.0 eV to about 1.2 eV.

[0051] In one or more embodiments, the source / drain material 120 of the p-cell 104 comprises boron (B)-doped silicon germanium (SiGe). In one or more embodiments, the source / drain material 120 of the p-cell 104 has a band gap in the range of about 0.5 eV to about 1.0 eV.

[0052] Referring to Figures 1A to 1D, a first opening 106 is present on the n-cell 102, and a second opening 108 is present on the p-cell 104. The first and second openings may have any suitable aspect ratio (the ratio of the opening's depth to its width). In one or more embodiments, the first and second openings may independently have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0053] In one or more embodiments, a cleaning structure (or surface of the structure) 100 is performed. In some embodiments, the cleaning structure 100 removes oxides from the surface. In some embodiments, the oxides are native oxides. In some embodiments, the cleaning surface forms a substantially oxide-free surface. As used in this way, the term "substantially oxide-free" means that the surface contains less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, anisotropic etching removes more oxides from the surface of the source / drain material 120 than from the dielectric material 110. In one or more embodiments, the cleaning structure forms a substantially oxide-free source / drain material 120.

[0054] Referring to Figure 1B, a titanium silicon (TiSi) layer 140 is deposited on each of the n-transistor 102 and the p-transistor 104. The titanium silicon layer 140 may have any suitable thickness. In some embodiments, the thickness of the titanium silicon layer 140 is in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the titanium silicon (TiSi) layer 140 has a thickness of about 40 Å. The titanium silicon (TiSi) layer 140 on the n-transistor 102 has a Schottky barrier height in the range of about 0.4 eV to about 0.55 eV.

[0055] Referring to Figure 1C, an optional first barrier layer 150 is deposited on each of the n-cell 102 and the p-cell 104. In one or more embodiments, the optional first barrier layer 150 comprises a metal. In one or more embodiments, the optional first barrier layer 150 comprises a metal nitride. In one or more embodiments, the optional first barrier layer 150 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN). In one or more embodiments, the n-cell 102 having the optional first barrier layer 150 has a lower Schottky barrier height than the n-cell without the optional first barrier layer.

[0056] Referring to Figure 1D, when present, the first barrier layer 150 on the p-cell 104 is selectively removed from the p-cell 104 rather than from the n-cell. The first barrier layer 150 can be removed by any suitable technique known to those skilled in the art. In one or more embodiments, the first barrier layer 150 is removed by one or more of etching, chemical mechanical polishing (CMP), planarization, etc.

[0057] Referring to Figure 1E, a molybdenum silicon dioxide (MoSi) layer 160 is formed on a titanium silicon dioxide (TiSi) layer 140 on each of the n-transistor 102 and the p-transistor 104. In one or more embodiments, the MoSi layer 160 is formed on an optional first barrier layer 150 on the n-transistor 102. The MoSi layer 160 may have any suitable thickness. In some embodiments, the thickness of the MoSi layer 160 is in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the MoSi layer 160 has a thickness of about 40 Å.

[0058] The molybdenum silicon (MoSi) layer 160 can be formed using any suitable process known to those skilled in the art. In one or more embodiments, structure 100 is first cleaned to remove oxides from the surface. In some embodiments, the oxides are native oxides. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this way, the term "substantially oxide-free" means that the surface contains less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms. In one or more embodiments, anisotropic etching is used to remove oxides from the surface.

[0059] In one or more embodiments, a metal film is selectively formed on a titanium silicon (TiSi) layer 140 to form a molybdenum silicon (MoSi) layer 160. In some embodiments, structure 100 is exposed to a metal precursor and reactants. The metal film may be deposited by an ALD deposition process, a CVD deposition process, or a combination thereof. In some embodiments, the metal film comprises a molybdenum silicon (MoSi) film.

[0060] In one or more embodiments, the metal precursor comprises a molybdenum precursor. In some embodiments, the molybdenum precursor comprises molybdenum halide. In some embodiments, the molybdenum halide comprises molybdenum fluoride, molybdenum chloride, or a combination thereof. In a particular embodiment, the molybdenum precursor comprises molybdenum fluoride. In other particular embodiments, the molybdenum precursor comprises molybdenum chloride. In one or more embodiments, a carrier gas is used to flow the precursor through a surface. In some embodiments, the carrier gas flows through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N₂, Ar, and He.

[0061] In one or more embodiments, the reactants comprise an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactants comprise hydrogen (H₂), ammonia (NH₃), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher silanes, and substituted silanes. In a particular embodiment, the reactants comprise silane to form a molybdenum silicide (MoSi) layer 160. In one or more embodiments, a carrier gas is used to flow the reactants through the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N₂, Ar, and He. In other embodiments, the reactant gas can flow continuously and the flow of the molybdenum precursor into the chamber can be opened and closed.

[0062] Referring to Figure 1E, a second barrier layer 170 is formed on each of the n-cell 102 and the p-cell 104. The second barrier layer 170 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second barrier layer 170 comprises a PVD metal film. In one or more embodiments, the second barrier layer 170 comprises molybdenum silicon nitride (MoSiN). In one or more embodiments, the second barrier layer 170 comprises molybdenum nitride (MoN). In one or more embodiments, the second barrier layer 170 prevents the formation of oxides on the molybdenum silicon nitride (MoSi) layer 160. In one or more embodiments, the n-cell 102 on which the second barrier layer 170 is formed has a lower Schottky barrier height than the n-cell on which the second barrier layer is not formed. In one or more embodiments, the p-cell 104 on which the second barrier layer 170 is formed has a lower Schottky barrier height than the p-cell on which the second barrier layer is not formed.

[0063] The second barrier layer 170 can be formed by any process known to those skilled in the art. In some embodiments, the second barrier layer 170 is formed on a molybdenum silicate (MoSi) layer 160. In some embodiments, the molybdenum silicate (MoSi) layer 160 is treated to form the second barrier layer 170. In some embodiments, the second barrier layer 170 is formed by nitriding the molybdenum silicate (MoSi) layer 160 or a portion thereof. In some embodiments, the second barrier layer 170 is formed by nitriding the molybdenum silicate (MoSi) layer 160 with ammonia (NH3). In some embodiments, the second barrier layer 170 is formed by plasma treatment of the molybdenum silicate (MoSi) layer 160 to nitrid the molybdenum silicate (MoSi) layer 160. In some embodiments, the plasma treatment includes nitrogen (N2) plasma treatment. In some embodiments, the second barrier layer 170 comprises a metal nitride, a PVD metal, or a combination thereof.

[0064] Referring to Figure 1F, the first opening 106 on the n-transistor 102 and the second opening 108 on the p-transistor 104 are each independently filled with interstitial material 180 and interstitial material 182, respectively. In one or more embodiments, the interstitial material 180 is substantially free of voids or seams. The interstitial materials 180 and 182 may independently comprise any suitable interstitial material known to those skilled in the art. In one or more embodiments, the interstitial materials 180 and 182 independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the interstitial material 180 in the first opening 106 on the n-transistor 102 is the same as the interstitial material 182 in the second opening 108 on the p-transistor 104. In one or more embodiments, the interstitial material 180 in the first opening 106 on the n-transistor 102 is different from the interstitial material 182 in the second opening 108 on the p-transistor 104.

[0065] The gap-filling process may include any suitable gap-filling process known to those skilled in the art. In one or more embodiments, the gap-filling process includes exposing the semiconductor structure 100 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0066] In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process includes a conformal gap filling process.

[0067] Figures 2A to 2G illustrate a semiconductor structure 200. The semiconductor structure 200 includes an n-transistor 202 and a p-transistor 204. Each of the n-transistor 202 and the p-transistor 204 includes a dielectric material 210, a source / drain material 220, and a substrate 230.

[0068] In one or more embodiments, the dielectric material 210 may comprise any suitable material known to those skilled in the art. In some embodiments, the dielectric material 210 comprises one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and low-k dielectrics. In some embodiments, the dielectric material 210 comprises silicon oxide (SiO2).

[0069] In some embodiments, the n-transistor 202 and p-transistor 204 include source and drain contacts. In one or more embodiments, the source / drain material 220 may have more than one layer. In some embodiments, the source / drain material 220 includes a silicon layer (e.g., SiGe, SiP, etc.) having a doped epitaxial layer, a second silicide layer that may contain nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0070] In one or more embodiments, the source / drain material 220 of the n-transistor 202 comprises phosphorus (P)-doped silicon (Si). In one or more embodiments, the source / drain material 220 of the n-transistor 202 has a band gap in the range of about 1.0 eV to about 1.2 eV.

[0071] In one or more embodiments, the source / drain material 220 of the p-cell 204 comprises boron (B)-doped silicon germanium (SiGe). In one or more embodiments, the source / drain material 220 of the p-cell 204 has a band gap in the range of about 0.5 eV to about 1.0 eV.

[0072] Referring to Figures 2A and 2B, a first opening 206 is present on the n-cell 202, and a second opening 208 is present on the p-cell 204. The first opening 206 and the second opening 208 may have any suitable aspect ratio (the ratio of the opening's depth to its width). In one or more embodiments, the first opening 206 and the second opening 208 may independently have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0073] Referring to Figure 2B, a titanium silicon (TiSi) layer 240 is deposited on the n-cell transistor 202. The titanium silicon (TiSi) layer 240 may have any suitable thickness. In some embodiments, the thickness of the titanium silicon (TiSi) layer 240 is in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the titanium silicon (TiSi) layer 240 has a thickness of about 40 Å.

[0074] Referring to Figure 2C, an optional barrier layer 250 is formed on the titanium silicon (TiSi) layer 240 on the n-cell 202. In one or more embodiments, the optional first barrier layer 250 comprises a metal. In one or more embodiments, the optional first barrier layer 250 comprises a metal nitride. In one or more embodiments, the optional first barrier layer 250 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

[0075] In one or more embodiments, the first opening 206 above the n-transistor 202 is filled with a first interstitial material 280. In one or more embodiments, the first interstitial material 280 is substantially free of voids or seams. In one or more embodiments, the first interstitial material 280 comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0076] The gap-filling process may include any suitable gap-filling process known to those skilled in the art. In one or more embodiments, the gap-filling process includes exposing the semiconductor structure 200 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0077] Referring to Figure 2D, a masking layer 270 is formed on the top surfaces of the n-cell 202 and the p-cell 204. In one or more embodiments, the masking layer 270 comprises one or more of a hard masking layer 272 and a photoresist layer 274. The hard masking layer 272 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the hard masking layer 272 comprises silicon dioxide (SiO2). The photoresist layer 274 may comprise any suitable material known to those skilled in the art. As those skilled in the art will appreciate, although the photoresist layer 274 is shown as not present in the p-cell, this is merely for ease of drawing. Those skilled in the art will understand that the hard masking layer 272 and the photoresist layer 274 are formed on the top surfaces of both the n-cell 202 and the p-cell 204. The process of forming the second opening 208 removes the photoresist layer 274. In one or more embodiments, a second opening 208 is formed on the p-cell 204. The second opening 208 can be formed by any suitable process known to those skilled in the art. In one or more embodiments, the second opening 208 is formed by etching.

[0078] The second opening 208 may have any suitable aspect ratio. In one or more embodiments, the second opening may have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0079] Referring to Figure 2E, the photoresist layer 280 is removed from the masking layer 270 of the n-transistor 202. The photoresist layer 280 can be removed by any suitable method known to those skilled in the art. In one or more embodiments, the photoresist layer 280 is removed by peeling.

[0080] Referring to Figure 2F, a molybdenum silicate (MoSi) layer 245 is selectively formed on the source / drain material 220 of the p-cell 204. The MoSi layer 245 can be formed by any suitable process known to those skilled in the art. The MoSi layer 245 can have any suitable thickness. In some embodiments, the thickness of the MoSi layer 245 is in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the MoSi layer 245 has a thickness of about 40 Å.

[0081] The molybdenum silicon (MoSi) layer 245 can be formed using any suitable process known to those skilled in the art. In one or more embodiments, structure 200 is first cleaned to remove oxides from the surface. In some embodiments, the oxides are natural oxides. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this way, the term "substantially oxide-free" means that the surface contains less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms. In one or more embodiments, anisotropic etching is used to remove oxides from the surface.

[0082] In one or more embodiments, a metal film is selectively formed on the source / drain material 220 to form the molybdenum silicon dioxide (MoSi) layer 245. In some embodiments, the semiconductor structure 200 is exposed to the metal precursor and reactants. The metal film may be deposited by an ALD deposition process, a CVD deposition process, or a combination thereof. In some embodiments, the metal film comprises a molybdenum silicon dioxide film.

[0083] In one or more embodiments, the metal precursor comprises a molybdenum precursor. In some embodiments, the molybdenum precursor comprises molybdenum halide. In some embodiments, the molybdenum halide comprises molybdenum fluoride, molybdenum chloride, or a combination thereof. In a particular embodiment, the molybdenum precursor comprises molybdenum fluoride. In other particular embodiments, the molybdenum precursor comprises molybdenum chloride. In one or more embodiments, a carrier gas is used to flow the precursor through a surface. In some embodiments, the carrier gas flows through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N₂, Ar, and He.

[0084] In one or more embodiments, the reactants comprise an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactants comprise hydrogen (H₂), ammonia (NH₃), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher silanes, and substituted silanes. In a particular embodiment, the reactants comprise silane to form a molybdenum silicide (MoSi) layer 245. In one or more embodiments, a carrier gas is used to flow the reactants through the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N₂, Ar, and He. In other embodiments, the reactant gas can flow continuously and the flow of the molybdenum precursor into the chamber can be opened and closed.

[0085] Referring to Figure 2G, the masking layer 270 formed on the top surfaces of each of the n-cell 202 and p-cell 204 is removed. The masking layer 270 can be removed by any suitable method known to those skilled in the art. In some embodiments, the masking layer 270 is removed by etching or planarization.

[0086] In one or more embodiments, the second opening 208 on the p-cell 204 is filled with a second interstitial material 282. In one or more embodiments, the second interstitial material 282 is substantially free of voids or seams. The first interstitial material 280 and the second interstitial material 282 may independently comprise any suitable interstitial material known to those skilled in the art. In one or more embodiments, the second interstitial material 282 comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the interstitial material 280 on the n-cell 202 is the same as the interstitial material 282 on the p-cell 204. In one or more embodiments, the interstitial material 280 is different from the interstitial material 282.

[0087] The gap-filling process may include any suitable gap-filling process known to those skilled in the art. In one or more embodiments, the gap-filling process includes exposing the semiconductor structure 200 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0088] In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process includes a conformal gap filling process.

[0089] Figure 3 illustrates a process flow diagram of a method 300 for forming a semiconductor structure. Figure 3 also illustrates a method for forming any semiconductor structure of one or more embodiments shown in Figures 1A-1F and 2A-2G.

[0090] In one or more embodiments, method 300 for forming a semiconductor structure includes, in operation 310, patterning a substrate to form a first opening and a second opening, the substrate including an n-transistor and a p-transistor, the first opening being over the n-transistor and the second opening being over the p-transistor. In operation 320, method 300 includes pre-cleaning the substrate. In operation 330, method 300 includes depositing titanium silicon (TiSi) layers on the n-transistor and p-transistor by plasma-enhanced chemical vapor deposition (PECVD). In operation 340, method 300 includes, as appropriate, depositing a first barrier layer on the titanium silicon (TiSi) layer and selectively removing the first barrier layer from the p-transistor. In operation 350, method 300 includes selectively forming a molybdenum silicon (MoSi) layer on the titanium silicon (TiSi) layer on the n-transistor and p-transistor. In operation 360, method 300 includes forming a second barrier layer on the molybdenum silicon (MoSi) layer. In operation 370, method 300 includes annealing the semiconductor structure.

[0091] In operation 310, method 300 includes patterning a substrate to form at least one of a first opening and a second opening. In one or more embodiments, the patterned substrate includes one or more patterning techniques known to those skilled in the art of microelectronic component manufacturing.

[0092] In operation 320, method 300 includes pre-cleaning the substrate. In one or more embodiments, the pre-cleaning process is maintained under vacuum to ensure that no oxides are introduced / formed on the substrate surface during method 300. In some embodiments, the pre-cleaned substrate (or substrate surface) removes oxides from the surface. In some embodiments, the oxides are native oxides. In some embodiments, the cleaned surface forms a substantially oxide-free surface. As used in this way, the term "substantially oxide-free" means that the surface contains less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, the pre-cleaned surface forms a substantially oxide-free source / drain material.

[0093] In operation 330, method 300 includes depositing titanium silicon (TiSi) layers on an n-cell and a p-cell by plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, after depositing the TiSi layers on the n-cell and p-cell, a rapid thermal process (RTP) is performed. In one or more embodiments, the rapid thermal process (RTP) includes heating the TiSi layers to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the rapid thermal process (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal process (RTP) removes unreacted metal from the TiSi layers.

[0094] In operation 340, method 300 may include, as appropriate, depositing a first barrier layer on a titanium silicon (TiSi) layer on an n-transistor and selectively removing the first barrier layer from the p-transistor. In one or more embodiments, selective removal of the first barrier layer from the p-transistor allows a molybdenum silicon (MoSi) layer on the p-transistor to form an ohmic contact with the titanium silicon (TiSi) layer on the p-transistor.

[0095] In some embodiments, the titanium silicon (TiSi) layers on the n-transistor and p-transistor are protected from oxide formation by a first barrier layer. The first barrier layer can be formed by any process known to those skilled in the art. In one or more embodiments, at operation 340, the first barrier layer is formed by an atomic layer deposition (ALD) process. In one or more embodiments, at operation 340, the first barrier layer is formed by a physical vapor deposition (PVD) process.

[0096] In some embodiments, a first barrier layer is formed on a titanium silicon (TiSi) layer. In some embodiments, the titanium silicon (TiSi) layer is treated to form the first barrier layer. In some embodiments, the first barrier layer is formed by a titanium nitride silicon (TiSi) layer. In some embodiments, the first barrier layer is formed by nitriding the titanium silicon (TiSi) layer with ammonia (NH3). In some embodiments, the first barrier layer is formed by plasma treatment of the titanium silicon (TiSi) layer to nitrid the titanium silicon (TiSi) layer. In some embodiments, the plasma treatment includes nitrogen (N2) plasma treatment.

[0097] In one or more embodiments, the titanium silicon nitride (TiSiN) layer is formed by forming a first barrier layer using a titanium silicon nitride (TiSi) layer. In one or more embodiments, the semiconductor structure having the titanium silicon nitride (TiSiN) layer has a lower Schottky barrier height than the semiconductor structure without the titanium silicon nitride (TiSiN) layer. In one or more embodiments, the semiconductor structure having the titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.50 eV to about 0.55 eV. In one or more embodiments, the semiconductor structure without the titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.6 eV to about 0.7 eV.

[0098] In some embodiments, operation 350, method 300 includes selectively forming a molybdenum silicon dioxide (MoSi) layer on a titanium silicon dioxide (TiSi) layer on an n-transistor and a p-transistor. In one or more embodiments, the MoSi layer is formed on a boron (B)-doped silicon germanium (SiGe) substrate of the p-transistor. In one or more embodiments, after selectively forming the MoSi layer on the p-transistor, a rapid thermal processing (RTP) is performed. In one or more embodiments, the RTP includes heating the MoSi layer to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the RTP is performed for about 1 minute. In one or more embodiments, the RTP removes unreacted metal from the MoSi layer.

[0099] In another embodiment of this disclosure, the method 300 for forming a semiconductor structure includes reducing the contact resistance of the semiconductor structure. In some embodiments, during operation 370, the semiconductor structure is annealed to reduce the contact resistance. In one or more embodiments, annealing the semiconductor structure produces a smooth surface. In one or more embodiments, during operation 370, annealing the semiconductor structure forms one or more ohmic and pseudo-ohmic contacts on n-transistors and p-transistors.

[0100] The semiconductor structure can be annealed using any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, rapid thermal processing (RTP) includes annealing the semiconductor structure to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, rapid thermal processing (RTP) includes annealing the semiconductor structure to a temperature of about 600°C.

[0101] In some embodiments, the annealed semiconductor structure has a root mean square (RMS) roughness in the range of 4% to less than 30%, 4% to less than 20%, 4% to less than 10%, 10% to less than 30%, 10% to less than 20%, or 20% to less than 30%.

[0102] In some embodiments, method 300 includes performing a gap-filling process. In one or more embodiments, the gap-filling process includes independently filling a first opening on an n-transistor and a second opening on a p-transistor. In some embodiments, the gap-filling process is a bottom-up gap-filling process. In other embodiments, the gap-filling process includes a conformal gap-filling process. In one or more embodiments, method 300 includes filling the first opening on the n-transistor with a first gap-filling material and filling the second opening on the p-transistor with a second gap-filling material. In one or more embodiments, each of the first and second gap-filling materials is substantially free of voids or seams. In one or more embodiments, each of the first and second gap-filling materials comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0103] In one or more embodiments, method 300 includes optional post-processing operations.

[0104] Figure 4 illustrates a process flow diagram of a method 400 for forming a semiconductor structure. Figure 4 also illustrates a method for forming any semiconductor structure of one or more embodiments shown in Figures 1A-1F and 2A-2G.

[0105] In some embodiments, method 400 of forming a semiconductor structure includes, in operation 410, patterning a substrate to form a first opening, the substrate including an n-transistor and a p-transistor, the first opening being over the n-transistor. In operation 420, method 400 includes pre-cleaning the substrate. In operation 430, method 400 includes depositing a titanium silicon carbide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD). In operation 435, method 400 includes, as appropriate, forming a barrier layer on the titanium silicon carbide (TiSi) layer on the n-transistor. In operation 440, method 400 includes filling the first opening with a first interstitial material. In operation 450, method 400 includes forming a mask layer on the top surface of the n-transistor. In operation 460, method 400 includes patterning the substrate to form a second opening over the p-transistor. In one or more embodiments, method 400 includes, as appropriate, depositing a first barrier layer on the titanium silicon carbide (TiSi) layer and selectively removing the first barrier layer from the p-transistor. In operation 470, method 400 includes selectively forming a molybdenum silicon oxide (MoSi) layer on a p-transistor. In operation 480, method 400 includes annealing the semiconductor structure. In operation 490, method 400 includes filling the second opening with a second interstitial material.

[0106] In operation 410, method 400 includes patterning a substrate to form a first opening over an n-transistor. In one or more embodiments, the patterned substrate includes one or more patterning techniques known to those skilled in the art of microelectronic component manufacturing.

[0107] In operation 420, method 400 includes pre-cleaning the substrate. In one or more embodiments, the pre-cleaning process is maintained under vacuum to ensure that no oxides are introduced / formed on the substrate surface during method 400. In some embodiments, the pre-cleaned substrate (or substrate surface) removes oxides from the surface. In some embodiments, the oxides are native oxides. In some embodiments, the cleaned surface forms a substantially oxide-free surface. As used in this way, the term "substantially oxide-free" means that the surface contains less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, the pre-cleaned surface forms a substantially oxide-free source / drain material.

[0108] In operation 430, method 400 includes depositing a titanium silicon (TiSi) layer on an n-cell transistor by plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, after depositing the TiSi layer on the n-cell transistor, a rapid thermal processing (RTP) is performed. In one or more embodiments, the rapid thermal processing (RTP) involves heating the TiSi layer to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the rapid thermal processing (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal processing (RTP) removes unreacted metal from the TiSi layer.

[0109] In operation 435, method 400 may include depositing a first barrier layer on a titanium silicon (TiSi) layer on an n-transistor. In some embodiments, the titanium silicon (TiSi) layer on the n-transistor is protected from oxide formation by the first barrier layer. The first barrier layer may be formed by any process known to those skilled in the art. In one or more embodiments, in operation 435, the first barrier layer is formed by an atomic layer deposition (ALD) process. In one or more embodiments, in operation 435, the first barrier layer is formed by a physical vapor deposition (PVD) process.

[0110] In some embodiments, a first barrier layer is formed on a titanium silicon (TiSi) layer. In some embodiments, the titanium silicon (TiSi) layer is treated to form the first barrier layer. In some embodiments, the first barrier layer is formed by a titanium silicon (TiSi) nitride layer. In some embodiments, the first barrier layer is formed by using ammonia (NH3) to nitride the titanium silicon (TiSi) layer. In some embodiments, the first barrier layer is formed by plasma treatment of the titanium silicon (TiSi) layer to nitride the titanium silicon (TiSi) layer. In some embodiments, the plasma treatment includes nitrogen (N2) plasma treatment.

[0111] In one or more embodiments, the titanium silicon nitride (TiSiN) layer is formed by forming a first barrier layer using a titanium silicon nitride (TiSi) layer. In one or more embodiments, the semiconductor structure having the titanium silicon nitride (TiSiN) layer has a lower Schottky barrier height than the semiconductor structure without the titanium silicon nitride (TiSiN) layer. In one or more embodiments, the semiconductor structure having the titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.50 eV to about 0.55 eV. In one or more embodiments, the semiconductor structure without the titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.6 eV to about 0.7 eV.

[0112] In operation 440, method 400 includes filling a first opening with a first gap-filling material. In some embodiments, filling the first opening includes a bottom-up gap-filling process. In other embodiments, filling the first opening includes a conformal gap-filling process. In one or more embodiments, the first gap-filling material is substantially free of voids or seams. In one or more embodiments, the first gap-filling material includes one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0113] In some embodiments, operation 450, method 400 includes forming a masking layer on the top surface of an n-type transistor. In one or more embodiments, the masking layer comprises one or more of a hard masking layer and a photoresist layer. The hard masking layer may comprise any suitable material known to those skilled in the art. In one or more embodiments, the hard masking layer comprises silicon dioxide (SiO2). The photoresist layer may comprise any suitable material known to those skilled in the art.

[0114] In operation 460, method 400 includes patterning a substrate to form a second opening over a p-transistor. In one or more embodiments, the patterned substrate includes one or more patterning techniques known to those skilled in the art of microelectronic component manufacturing.

[0115] In operation 470, method 400 includes selectively forming a molybdenum silicon dioxide (MoSi) layer on a titanium silicon dioxide (TiSi) layer on a p-transistor. In one or more embodiments, after selectively forming the MoSi layer on the p-transistor, a rapid thermal processing (RTP) is performed. In one or more embodiments, the RTP involves heating the MoSi layer to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the RTP is performed for about 1 minute. In one or more embodiments, the RTP removes unreacted metal from the MoSi layer.

[0116] In another embodiment of this disclosure, the method 400 for forming a semiconductor structure includes reducing the contact resistance of the semiconductor structure. In some embodiments, during operation 480, the semiconductor structure is annealed to reduce the contact resistance. In one or more embodiments, annealing the semiconductor structure produces a smooth surface. In one or more embodiments, during operation 480, annealing the semiconductor structure forms one or more ohmic and pseudo-ohmic contacts on n-transistors and p-transistors.

[0117] The semiconductor structure can be annealed using any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, rapid thermal processing (RTP) includes annealing the semiconductor structure to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, rapid thermal processing (RTP) includes annealing the semiconductor structure to a temperature of about 600°C.

[0118] In some embodiments, the annealed semiconductor structure has a root mean square (RMS) roughness in the range of 4% to less than 30%, 4% to less than 20%, 4% to less than 10%, 10% to less than 30%, 10% to less than 20%, or 20% to less than 30%.

[0119] In operation 490, method 400 includes filling the second opening with a second gap-filling material. In some embodiments, filling the second opening includes a bottom-up gap-filling process. In other embodiments, filling the second opening includes a conformal gap-filling process. In one or more embodiments, the second gap-filling material is substantially free of voids or seams. In one or more embodiments, the second gap-filling material includes one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0120] In one or more embodiments, method 400 includes optional post-processing operations.

[0121] Spatial terms such as “below,” “under,” “below,” “above,” and “above” are used herein to facilitate description of the relationship between one element or feature and another, as illustrated in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “below” other elements or features would subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0122] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims of invention), the terms "a / an" and "the," and similar designations, shall be construed as encompassing both the singular and plural, unless otherwise stated herein or clearly contradicted by the context. Unless otherwise stated herein, the enumeration of numerical ranges herein is intended only as a shorthand method for individually referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were individually enumerated herein. Unless otherwise stated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. The use of any and all instances or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods and does not constitute a limitation on the scope, unless otherwise stated. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0123] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" refer to a particular feature, structure, material, or characteristic described in connection with an embodiment that is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" appearing in various places throughout the specification do not necessarily represent the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0124] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. Various modifications and variations to the methods and elements of the invention will be readily apparent to those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

[0125] 100: Semiconductor Structure 102:n transistor 104:p transistor 106: First Opening 108: Second opening 110: Dielectric materials 120: Source / Drain Materials 130:Substrate 140: Titanium silicon layer 150: First Barrier Layer 160: Molybdenum silicate layer 170: Second Barrier Layer 180: Gap Filling Material 182: Gap Filling Material 200: Semiconductor Structure 202:n transistor 204:p transistor 206: First Opening 208: Second opening 210: Dielectric materials 220: Source / Drain Materials 230:Substrate 240: Titanium silicon layer 245: Molybdenum silicate layer 250: Barrier Layer 270: Mask layer 272: Hard mask layer 274: Photoresist layer 280: First gap-filling material 282: Second gap-filling material 300: Method 310: Operation 320: Operation 330: Operation 340: Operation 350: Operation 360: Operation 370: Operation 400: Method 410: Operation 420: Operation 430: Operation 435: Operation 440: Operation 450: Operation 460: Operation 470: Operation 480: Operation 490: Operation

[0126] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor structure, the method comprising the steps of: patterning a substrate to form a first opening and a second opening, the substrate including an n-transistor and a p-transistor, the first opening being on the n-transistor and the second opening being on the p-transistor; pre-cleaning the substrate; depositing a titanium silicon dioxide (TiSi) layer on the n-transistor and the p-transistor by plasma-enhanced chemical vapor deposition (PECVD); depositing a first barrier layer on the TiSi layer as appropriate, and selectively removing the first barrier layer from the p-transistor; forming a molybdenum silicon dioxide (MoSi) layer on the TiSi layer on the n-transistor and the p-transistor; forming a second barrier layer on the MoSi layer; and annealing the semiconductor structure.

2. The method as claimed in claim 1, wherein the n-transistor comprises silicon (Si) doped with phosphorus (P) and the p-transistor comprises silicon germanium (SiGe) doped with boron (B).

3. The method as described in claim 1, wherein the first barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

4. The method as described in claim 3, wherein the first barrier layer is formed by one or more of an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process.

5. The method as described in claim 1, wherein the second barrier layer comprises molybdenum nitride (MoN), molybdenum silicon nitride (MoSi), and a PVD metal film.

6. The method as described in claim 1 further includes the step of: independently filling the first opening and the second opening with a gap-filling material.

7. The method as described in claim 6, wherein the filler material is substantially free of voids or seams.

8. The method as described in claim 6, wherein the interstitial material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).

9. The method as claimed in claim 1, wherein the step of annealing the semiconductor structure forms one or more ohmic and pseudo-ohmic contacts on the n-transistor and the p-transistor.

10. The method as claimed in claim 1, wherein the titanium silicon (TiSi) layer on the n-transistor has a Schottky barrier height in the range of about 0.4 eV to about 0.55 eV.

11. A method of forming a semiconductor structure, the method comprising the steps of: patterning a substrate to form a first opening, the substrate including an n-transistor and a p-transistor, the first opening being on the n-transistor; pre-cleaning the substrate; depositing a titanium silicon dioxide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD); filling the first opening with a first interstitial material; forming a mask layer on a top surface of the n-transistor; patterning the substrate to form a second opening on the p-transistor; forming a molybdenum silicon dioxide (MoSi) layer on the p-transistor; annealing the semiconductor structure; and filling the second opening with a second interstitial material.

12. The method as described in claim 11, wherein the masking layer comprises one or more of a hard masking layer and a photoresist layer.

13. The method as described in claim 11 further comprises the step of forming a barrier layer on the titanium silicon (TiSi) layer on the n-transistor.

14. The method of claim 13 further comprises the steps of: depositing the barrier layer on the molybdenum silicon (MoSi) layer on the p-cell and selectively removing the barrier layer from the p-cell.

15. The method as described in claim 13, wherein the barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

16. The method as described in claim 11, wherein the first interstitial material and the second interstitial material independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).

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