Semiconductor device using pipe circuit

Abstract

This application discloses a semiconductor device including an output control circuit configured to generate a pre-output control signal and an output control signal based on the number of times an output strobe pulse is input. The semiconductor device also includes a pipeline circuit configured to generate latched data by latching input data based on the input control signal, selecting some bits of the latched data based on the pre-output control signal and setting the selected bits as pre-output data, and outputting the pre-output data as output data based on the output control signal.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device using a pipe circuit. [Previous Technology]

[0002] A semiconductor device includes a pipeline circuit to efficiently process continuously transmitted data. The pipeline circuit may include multiple latch circuits configured to latch data input synchronously with the input timing and to output the latched data synchronously with the output timing. [Summary of the Invention]

[0003] Cross-reference to related applications: This application claims priority to Korean Application No. 10-2021-0158953, filed with the Korean Intellectual Property Office on November 17, 2021, the entire contents of which are incorporated herein by reference.

[0004] Some embodiments of this disclosure relate to a semiconductor device using a pipe circuit.

[0005] In one embodiment, a semiconductor device may include an output control circuit configured to generate a pre-output control signal and an output control signal based on the number of times an output strobe pulse is input. The semiconductor device may also include a pipeline circuit configured to generate latched data by latching input data based on the input control signal, select some bits of the latched data based on the pre-output control signal and set the selected bits as pre-output data, and output the pre-output data as output data based on the output control signal.

[0006] In another embodiment, a semiconductor device may include a first pipeline latch circuit configured to: select one of input data latched in a first node and input data latched in a second node according to the logic level of a pre-output control signal, and set the selected data as the first bit of the pre-output data; and output the first bit of the pre-output data as output data when the first bit of the output control signal is activated. The semiconductor device may also include a second pipeline latch circuit configured to: select one of input data latched in a third node and input data latched in a fourth node according to the logic level of the pre-output control signal, and set the selected data as a second bit of the pre-output data; and output the second bit of the pre-output data as output data when the second bit of the output control signal is activated. The semiconductor device may also include an output control circuit configured to change the logic level of the pre-output control signal synchronously with the first bit of the output control signal.

[0007] In another embodiment, a semiconductor device may include a first pipeline latch circuit configured to: select one of input data latched in a first node and input data latched in a second node according to the logic level of a first pre-output control signal, and set the selected data as the first bit of the pre-output data; and output the first bit of the pre-output data as output data when the first bit of the output control signal is activated. The semiconductor device may further include a second pipeline latch circuit configured to: select one of input data latched in a third node and input data latched in a fourth node according to the logic level of the second pre-output control signal, and set the selected data as the second bit of the pre-output data; and output the second bit of the pre-output data as output data when the second bit of the output control signal is activated. The semiconductor device may further include an output control circuit configured to change the logic level of the second pre-output control signal synchronously with the first bit of the output control signal.

[0008] According to some embodiments, the semiconductor device according to the present disclosure can set only some bits of the data latched in the pipeline circuit as pre-output data, selected according to the number of times the output data is output, and output the pre-output data as output data in sync with the output timing when the output latched data is output, thereby reducing the load on the node from the pipeline circuit to which the output data is output.

Implementation Method

[0010] In the following description of the embodiments, the term "preset" indicates that the value of the parameter is predetermined when it is used in the processing or algorithm. Depending on the implementation, the value of the parameter may be set when the processing or algorithm is started or when the processing or algorithm is executed.

[0011] Terms such as “first” and “second” used to distinguish various components are not limited to components. For example, a first component can be referred to as a second component, and vice versa.

[0012] When a component is referred to as “coupled” or “connected” to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component placed between them. On the other hand, when a component is referred to as “directly coupled” or “directly connected” to another component, it should be understood that these components may be directly coupled or connected to each other without another component placed between them.

[0013] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal having a "logic high level" is different from a signal having a "logic low level". For example, when a signal having a first voltage corresponds to a "logic high level", a signal having a second voltage can correspond to a "logic low level". According to an embodiment, the "logic high level" can be set to a voltage higher than the "logic low level". According to an embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, according to an embodiment, a signal having a logic high level can be set to have a logic low level, and according to an embodiment, a signal having a logic low level can be set to have a logic high level.

[0014] The teachings of this disclosure will be described in more detail below through embodiments. The embodiments are for illustrative purposes only, and the scope of this disclosure is not limited to the embodiments.

[0015] FIG1 is a block diagram showing the configuration of a semiconductor device 100a according to one embodiment. As shown in FIG1, the semiconductor device 100a may include an input strobe pulse generation circuit (STBP_1 GEN) 201, an output strobe pulse generation circuit (STBP_0 GEN) 203, a data storage circuit 205, an input control circuit 207, an output control circuit 215a, and a pipeline circuit 223a. The semiconductor device 100a can receive commands (not shown) and clock CLK from an external device (not shown), and can perform various internal operations including read operations.

[0016] The input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I from the command pulse CMDP in sync with the clock CLK. The command pulse CMDP can be generated from a command (not shown) used to perform a read operation. Whenever a read operation is performed, the input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I according to the command pulse CMDP.

[0017] Synchronously with the clock CLK, the output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read operation of the command pulse CMDP based on the delay signal LTC. The delay signal LTC may include a bit combination corresponding to the read delay. The delay signal LTC can be stored and output by a mode register (not shown). Whenever a read operation is performed, the output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read operation of the command pulse CMDP.

[0018] The data storage circuit 205 may include a plurality of cell arrays (not shown) configured to store input data DIN. The data storage circuit 205 may output the input data DIN stored in the cell array in synchronization with the input strobe pulse STBP_I.

[0019] The input control circuit 207 may include an input counting signal generation circuit (CNT_I GEN) 209, a selection signal generation circuit (SEL GEN) 211, and an input control signal generation circuit (PIN GEN) 213. The input control circuit 207 may generate an input control signal PIN based on the input strobe pulse STBP_I. The input control signal PIN may include the first to the 2Nth bits. Here, "N" may be set to a natural number equal to or greater than 2. The input control circuit 207 may sequentially activate the bits of the input control signal PIN according to the number of times the input strobe pulse STBP_I is input. For example, the input control circuit 207 may activate the first bit PIN<1> of the input control signal when the input strobe pulse STBP_I is input for the first time, and activate the second bit PIN<2> of the input control signal when the input strobe pulse STBP_I is input for the second time. Then, when the input strobe pulse STBP_I is input for the 2N+1th time, the input control circuit 207 may restart the first bit PIN<1> of the input control signal.

[0020] The input counting signal generation circuit 209 can sequentially activate bits of the input counting signal CNT_I by counting the number of times the input strobe pulse STBP_I is input. The input counting signal CNT_I can include the first to the Nth bits. For example, the input counting signal generation circuit 209 can activate the first bit CNT_I<1> of the input counting signal when the input strobe pulse STBP_I is input for the first time, and activate the second bit CNT_I<2> of the input counting signal when the input strobe pulse STBP_I is input for the second time. Then, when the input strobe pulse STBP_I is input for the (N+1)th time, the input counting signal generation circuit 209 can restart the first bit CNT_I<1> of the input counting signal. The structure and operation of the input counting signal generation circuit 209 will be described in detail below with reference to FIG2.

[0021] The selection signal generation circuit 211 can generate a selection signal SEL based on the input counting signal CNT_I. The selection signal generation circuit 211 can synchronously change the logic level of the selection signal SEL with a preset bit in the bits of the input counting signal CNT_I. For example, the selection signal generation circuit 211 can synchronously change the logic level of the selection signal SEL with the Nth bit CNT_I<N> of the input counting signal. In different embodiments, the number of bits included in the selection signal SEL can be set to various values. The structure and operation of the selection signal generation circuit 211 will be described in detail below with reference to FIG3.

[0022] The input control signal generation circuit 213 can generate an input control signal PIN from an input strobe pulse STBP_I based on the input counting signal CNT_I and the selection signal SEL. The input control signal generation circuit 213 can output the input strobe pulse STBP_I as one of the bits of the input control signal PIN based on the logical level combination of the input counting signal CNT_I and the logical level of the selection signal SEL. For example, when the selection signal SEL has a first logical level, the input control signal generation circuit 213 can output the input strobe pulse STBP_I as one of the first to Nth bits PIN<1:N> of the input control signal based on the logical level combination of the input counting signal CNT_I. When the selection signal SEL has a second logical level, the input control signal generation circuit 213 can output the input strobe pulse STBP_I as one of the (N+1)th to 2Nth bits PIN<N+1:2N> of the input control signal based on the logical level combination of the input counting signal CNT_I. The structure and operation of the input control signal generation circuit 213 will be described in detail below with reference to FIG4.

[0023] The output control circuit 215a may include an output counting signal generation circuit (CNT_O GEN) 217a, a pre-output control signal generation circuit (PRE_POUT GEN) 219a, and an output control signal generation circuit (POUT GEN) 221a. The output control circuit 215a can generate an output control signal POUT and a pre-output control signal PRE_POUT based on the output strobe pulse STBP_O. The output control signal POUT may include the first to the Nth bits. The output control circuit 215a can sequentially activate the bits of the output control signal POUT according to the number of times the output strobe pulse STBP_O is input. For example, the output control circuit 215a can activate the first bit POUT<1> of the output control signal when the output strobe pulse STBP_O is input for the first time, and activate the second bit POUT<2> of the output control signal when the output strobe pulse STBP_O is input for the second time. Then, when the output strobe pulse STBP_O is input for the (N+1)th time, the output control circuit 215a can restart the first bit POUT<1> of the output control signal. The output control circuit 215a can generate a pre-output control signal PRE_POUT based on the number of times the output strobe pulse STBP_O is input. More specifically, the output control circuit 215a can change the logic level of the pre-output control signal PRE_POUT synchronously with a preset bit in the bits of the output control signal POUT. For example, the output control circuit 215a can change the logic level of the pre-output control signal PRE_POUT synchronously with the Nth bit POUT<N> of the output control signal.

[0024] The output counting signal generation circuit 217a can sequentially activate the bits of the output counting signal CNT_O by counting the number of times the output strobe pulse STBP_O is input. The output counting signal CNT_O can include the first to the Nth bits. For example, the output counting signal generation circuit 217a can activate the first bit CNT_O<1> of the output counting signal when the output strobe pulse STBP_O is input for the first time, and activate the second bit CNT_O<2> of the output counting signal when the output strobe pulse STBP_O is input for the second time. Then, the output counting signal generation circuit 217a can restart the first bit CNT_O<1> of the output counting signal when the output strobe pulse STBP_O is input for the (N+1)th time. The structure and operation of the output counting signal generation circuit 217a will be described in detail below with reference to FIG6.

[0025] The pre-output control signal generation circuit 219a can generate a pre-output control signal PRE_POUT based on the output counting signal CNT_O. The pre-output control signal generation circuit 219a can synchronously change the logic level of the pre-output control signal PRE_POUT with a preset bit in the bits of the output counting signal CNT_O. For example, the pre-output control signal generation circuit 219a can synchronously change the logic level of the pre-output control signal PRE_POUT with the Nth bit CNT_O<N> of the output counting signal. The structure and operation of the pre-output control signal generation circuit 219a will be described in detail below with reference to FIG7.

[0026] The output control signal generation circuit 221a can generate an output control signal POUT from the output gating pulse STBP_O based on the output counting signal CNT_O. The output control signal generation circuit 221a can output the output gating pulse STBP_O as one of the bits of the output control signal POUT according to the logic level combination of the output counting signal CNT_O. For example, the output control signal generation circuit 221a can output the output gating pulse STBP_O as one of the first to Nth bits POUT<1:N> of the output control signal according to the logic level combination of the output counting signal CNT_O. The structure and operation of the output control signal generation circuit 221a will be described in detail below with reference to FIG8.

[0027] The pipe circuit 223a may include multiple pipe latch circuits 223_1a to 223_Na. The pipe circuit 223a can generate latched data (not shown) by latching input data DIN based on the input control signal PIN, can select some bits of the latched data based on the pre-output control signal PRE_POUT and set the selected bits as pre-output data (not shown), and can output the pre-output data as output data DOUT based on the output control signal POUT.

[0028] The pipe circuit 223a can generate the first to Nth bits of latched data by latching the input data DIN based on the first to Nth bits PIN<1:N> of the input control signal. More specifically, when the Kth bit PIN<K> of the input control signal is activated, the pipe circuit 223a can generate the Kth bit of latched data by latching the input data DIN. Here, "K" is a natural number equal to or less than "N". For example, the pipe circuit 223a can generate the first bit of latched data by latching the input data DIN when the first bit PIN<1> of the input control signal is activated, and generate the second bit of latched data by latching the input data DIN when the second bit PIN<2> of the input control signal is activated.

[0029] The pipe circuit 223a can generate the (N+1)th to (2N)th bits of the latched data by latching the input data DIN based on the (N+1)th to (2N)th bits of the input control signal PIN<N+1:2N>. More specifically, when the (N+K)th bit of the input control signal PIN<N+K> is activated, the pipe circuit 223a can generate the (N+K)th bit of the latched data by latching the input data DIN. For example, when the (N+1)th bit of the input control signal PIN<N+1> is activated, the pipe circuit 223a can generate the (N+1)th bit of the latched data by latching the input data DIN, and when the (N+2)th bit of the input control signal PIN<N+2> is activated, the (N+2)th bit of the latched data can be generated by latching the input data DIN.

[0030] Pipeline circuit 223a can select some bits from the latched data based on the logic level of the pre-output control signal PRE_POUT, and set the selected bits as bits of the pre-output data. For example, when the pre-output control signal PRE_POUT has a first logic level, pipeline circuit 223a can select the first to the Nth bits from the first to the 2Nth bits of the latched data, and set the selected bits as the first to the Nth bits of the pre-output data respectively. When the pre-output control signal PRE_POUT has a second logic level, pipeline circuit 223a can select the (N+1)th to the 2Nth bits from the first to the 2Nth bits of the latched data, and set the selected bits as the first to the 2Nth bits of the pre-output data respectively. Therefore, pipeline circuit 223a can set only some bits from the latched data selected according to the number of times the output data DOUT is output as pre-output data based on the pre-output control signal PRE_POUT, thereby reducing the load on the node that outputs the output data DOUT.

[0031] The pipe circuit 223a can output the first to Nth bits of the pre-output data as output data DOUT based on the first to Nth bits of the output control signal POUT<1:N>. More specifically, when the Kth bit of the output control signal POUT<K> is activated, the pipe circuit 223a can output the Kth bit of the pre-output data as output data DOUT. For example, the pipe circuit 223a can output the first bit of the pre-output data as output data DOUT when the first bit of the output control signal POUT<1> is activated, and can output the second bit of the pre-output data as output data DOUT when the second bit of the output control signal POUT<2> is activated.

[0032] Multiple pipeline latch circuits 223_1a to 223_Na can latch input data DIN based on the Kth bit PIN<K> of the input control signal, the N+Kth bit PIN<N+K> of the input control signal, the pre-output control signal PRE_POUT, and the Kth bit POUT<K> of the output control signal, and output the latched data as output data DOUT. For example, when the first bit PIN<1> of the input control signal is activated, the first pipeline latch circuit 223_1a can generate the first bit of the latched data by latching the input data DIN. When the N+1th bit PIN<N+1> of the input control signal is activated, the first pipeline latch circuit 223_1a can generate the N+1th bit of the latched data by latching the input data DIN. The first pipeline latch circuit 223_1a can select one of the first bit and the N+1th bit of the latched data according to the logic level of the pre-output control signal PRE_POUT, and set the selected bit as the first bit of the pre-output data. When the first element of the output control signal POUT<1> is activated, the first pipe latch circuit 223_1a can output the first element of the pre-output data as the output data DOUT.

[0033] When the Kth bit of the input control signal PIN<K> is activated, the pre-output control signal PRE_POUT can have a logic level for setting the Kth bit of the latched data to the Kth bit of the pre-output data. For example, when the first bit of the input control signal PIN<1> is activated, the first pipeline latch circuit 223_1a can generate the first bit of the latched data by latching the input data DIN, and can set the first bit of the latched data to the first bit of the pre-output data according to the logic level of the pre-output control signal PRE_POUT. When the (N+K)th bit of the input control signal PIN<N+K> is activated, the pre-output control signal PRE_POUT can have a logic level for setting the (N+K)th bit of the latched data to the Kth bit of the pre-output data. For example, when the N+1th bit PIN<N+1> of the input control signal is activated, the first pipe latch circuit 223_1a can generate the N+1th bit of the latched data by latching the input data DIN, and can set the N+1th bit of the latched data as the first bit of the pre-output data according to the logic level of the pre-output control signal PRE_POUT.

[0034] The Kth bit of the output control signal, POUT<K>, can be activated after a delay time elapsed from the time point when one of the Kth bit of the input control signal, PIN<K>, or the (N+Kth bit) of the input control signal, PIN<N+K>. The delay time varies depending on the read delay. For example, after the delay time elapsed following the activation of the first bit of the input control signal, PIN<1>, the first pipe latch circuit 223_1a can output the first bit of the pre-output data as output data DOUT based on the first bit of the output control signal, POUT<1>. After the delay time elapsed following the activation of the (N+1th bit) of the input control signal, PIN<N+1>, the first pipe latch circuit 223_1a can output the first bit of the pre-output data as output data DOUT based on the first bit of the output control signal, POUT<1>. The structure and operation of the pipe circuit 223a will be described in detail below with reference to FIG10.

[0035] FIG2 is a circuit diagram showing an example of the input counting signal generation circuit 209 included in the input control circuit 207 shown in FIG1. ​​As shown in FIG2, the input counting signal generation circuit 209 may include flip-flops (F / F) 209_1 to 209_5.

[0036] Flip-flops 209_1 to 209_5 can set the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal to "H, L, L, L, L" when the initialization operation is performed, based on the reset signal RST and the inverted reset signal RSTB. When the initialization operation is performed, the reset signal RST and the inverted reset signal RSTB can have logic high and logic low levels, respectively. Flip-flops 209_1 to 209_5 can sequentially change the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal according to the number of times the input strobe pulse STBP_I is input. For example, when the input strobe pulse STBP_I is input for the first time after the initialization operation is performed, flip-flops 209_1 to 209_5 can set the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal to "L, H, L, L, L". When the input strobe pulse STBP_I is input for the second time after the initialization operation is performed, flip-flops 209_1 to 209_5 can set the logic level combination of the first to fifth bits CNT_I<1:5> of the input count signal to "L, L, H, L, L".

[0037] FIG3 is a circuit diagram showing an example of the selection signal generation circuit 211 included in the input control circuit 207 shown in FIG1. ​​As shown in FIG3, the selection signal generation circuit 211 may include a first selection signal generation circuit 231 and a second selection signal generation circuit 233.

[0038] The first selection signal generation circuit 231 may include inverters 231_1, 231_3, 231_5, 231_6 and 231_7, an inverter gate 231_2, and a transmission transistor 231_4. The first selection signal generation circuit 231 may synchronously change the logic level of the first bit SEL<1> of the selection signal with the falling edge of the second bit CNT_I<2> of the input counting signal.

[0039] When the second bit of the input counting signal CNT_I<2> and the second bit of the inverted input counting signal CNT_IB<2> have logic high and logic low levels respectively, the first selection signal generation circuit 231 can buffer the first bit SELB<1> of the inverted selection signal through the inverter 231_1 and the inverting gate 231_2 and output the buffered bit through node nd11. The second bit of the inverted input counting signal CNT_IB<2> can be generated by inverting the logic level of the second bit of the input counting signal CNT_I<2>. During the initialization operation, the first selection signal generation circuit 231 can set node nd11 to the logic high level based on the inverted reset signal RSTB with the logic low level through the inverting gate 231_2.

[0040] When the second bit of the input counting signal CNT_I<2> and the second bit of the inverted input counting signal CNT_IB<2> have logic low level and logic high level respectively, the first selection signal generation circuit 231 can latch the signal of node nd11 through the inverting gate 231_2 and the inverter 231_3, and invert and buffer the signal of node nd11 through the transmission transistor 231_4 and the inverter 231_5 and output the inverted and buffered signal as the first bit of the inverted selection signal SELB<1>.

[0041] When the second bit of the input counting signal CNT_I<2> and the second bit of the inverted input counting signal CNT_IB<2> have logic high level and logic low level respectively, the first selection signal generation circuit 231 can latch the first bit of the inverted selection signal SELB<1> through inverters 231_5 and 231_6.

[0042] The first selection signal generation circuit 231 can invert and buffer the first bit of the inverted selection signal SELB<1> through the inverter 231_7, and output the inverted and buffered bit as the first bit of the selection signal SEL<1>.

[0043] The second selection signal generation circuit 233 may include inverters 233_1, 233_3, 233_5, 233_6, and 233_7, an inverter gate 233_2, and a transmission transistor 233_4. The second selection signal generation circuit 233 may synchronously change the logic level of the second bit SEL<2> of the selection signal with the falling edge of the fifth bit CNT_I<5> of the input counting signal. The operation of the second selection signal generation circuit 233 is implemented in the same manner as the operation of the first selection signal generation circuit 231.

[0044] FIG4 is a circuit diagram showing an example of the input control signal generation circuit 213 included in the input control circuit 207 shown in FIG1. ​​As shown in FIG4, the input control signal generation circuit 213 may include inverters 213_1 to 213_10.

[0045] When the first bit of the input counting signal, CNT_I<1>, is activated, the anti-ghosting gates 213_1 and 213_6 can output the input strobe pulse STBP_I as the first bit PIN<1> or the sixth bit PIN<6> of the input control signal, depending on whether either the first bit SEL<1> of the selection signal or the first bit SELB<1> of the inverting selection signal is activated to a logic high level. The anti-ghosting gates 213_2 and 213_7 operate in the same way as the anti-ghosting gates 213_1 and 213_6.

[0046] When the third bit of the input counting signal CNT_I<3> is activated, the anti-gating gates 213_3 and 213_8 can output the input strobe pulse STBP_I as the third bit PIN<3> or the eighth bit PIN<8> of the input control signal, depending on whether either the second bit SEL<2> of the selection signal or the second bit SELB<2> of the inverted selection signal is activated to a logic high level. The operation of anti-gating gates 213_4 and 213_9 and the operation of anti-gating gates 213_5 and 213_10 are implemented in the same way as anti-gating gates 213_3 and 213_8.

[0047] Figure 5 is a timing diagram for describing the operation of the input control circuit 207 shown in Figure 1.

[0048] During the initialization operation, the input control circuit 207 can set the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal to "H, L, L, L, L". After the initialization operation, the input control circuit 207 can synchronously rotate the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal in the order of "L, H, L, L, L", "L, L, H, L, L", "L, L, L, H, L", "L, L, L, L, H", and "H, L, L, L, L".

[0049] The input control circuit 207 can synchronously change the logic level of the first bit SEL<1> of the selection signal with the falling edge of the second bit CNT_I<2> of the input counting signal. The input control circuit 207 can synchronously change the logic level of the second bit SEL<2> of the selection signal with the falling edge of the fifth bit CNT_I<5> of the input counting signal.

[0050] When the input strobe pulse STBP_I is continuously input, the input control circuit 207 can sequentially start the first to tenth bits PIN<1:10> of the input control signal according to the logic level combination of the first to fifth bits CNT_I<1:5> of the input counting signal and the logic levels of the first and second bits SEL<1:2> of the selection signal.

[0051] Figure 6 is a circuit diagram showing an example of the output counting signal generation circuit 217a included in the output control circuit 215a shown in Figure 1. As shown in Figure 6, the output counting signal generation circuit 217a may include flip-flops 217_1a to 217_5a. When the initialization operation is performed based on the reset signal RST and the inverted reset signal RSTB, flip-flops 217_1a to 217_5a can set the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal to "H, L, L, L, L". Flip-flops 217_1a to 217_5a can sequentially change the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal according to the number of times the output strobe pulse STBP_O is input. For example, when the output strobe pulse STBP_O is input for the first time after the initialization operation is performed, flip-flops 217_1a to 217_5a can set the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal to "L, H, L, L, L". Then, when the output strobe pulse STBP_O is input for the second time after the initialization operation is performed, flip-flops 217_1a to 217_5a can set the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal to "L, L, H, L, L".

[0052] Figure 7 is a circuit diagram showing an example of the pre-output control signal generation circuit 219a included in the output control circuit 215a shown in Figure 1. As shown in Figure 7, the pre-output control signal generation circuit 219a may include inverters 219_1a, 219_3a, 219_5a, 219_6a, and 219_7a, an inverter gate 219_2a, and a transmission transistor 219_4a. The pre-output control signal generation circuit 219a can change the logic level of the pre-output control signal PRE_POUT synchronously with the falling edge of the fifth bit CNT_O<5> of the output counting signal. Since the operation of the pre-output control signal generation circuit 219a in changing the logic level of the pre-output control signal PRE_POUT is implemented in the same way as the operation of the first selection signal generation circuit (231 in Figure 3) in changing the logic level of the first bit SEL<1> of the selection signal, its detailed description will be omitted herein.

[0053] Figure 8 is a circuit diagram showing an example of the output control signal generation circuit 221a included in the output control circuit 215a shown in Figure 1. As shown in Figure 8, the output control signal generation circuit 221a may include inverting gates 221_1a to 221_5a. When the first element CNT_O<1> of the output counting signal is activated, the inverting gate 221_1a can invert and buffer the output gating pulse STBP_O, and output the inverted and buffered pulse as the first element POUT<1> of the output control signal. The operation of inverting gates 221_2a to 221_5a is implemented in the same manner as that of inverting gate 221_1a.

[0054] Figure 9 is a timing diagram for describing the operation of the output control circuit 215a shown in Figure 1.

[0055] During the initialization operation, the output control circuit 215a can set the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal to "H, L, L, L, L". After the initialization operation, the output control circuit 215a can synchronously rotate the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal in the order of "L, H, L, L, L", "L, L, H, L, L", "L, L, L, H, L", "L, L, L, L, H", and "H, L, L, L, L".

[0056] The output control circuit 215a can change the logic level of the pre-output control signal PRE_POUT synchronously with the falling edge of the fifth bit CNT_O<5> of the output counting signal.

[0057] When the output strobe pulse STBP_O is continuously input, the output control circuit 215a can sequentially start the first to fifth bits POUT<1:5> of the output control signal according to the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal.

[0058] FIG10 is a diagram showing an example of the pipe circuit 223a shown in FIG1. ​​As shown in FIG10, the pipe circuit 223a may include a first pipe latch circuit 223_1a, a second pipe latch circuit 223_2a, a third pipe latch circuit 223_3a, a fourth pipe latch circuit 223_4a and a fifth pipe latch circuit 223_5a.

[0059] The first pipeline latch circuit 223_1a can latch the input data DIN and output the latched data as output data DOUT based on the first bit PIN<1> of the input control signal, the sixth bit PIN<6> of the input control signal, the pre-output control signal PRE_POUT, and the first bit POUT<1> of the output control signal. When the first bit PIN<1> of the input control signal is activated, the first pipeline latch circuit 223_1a can generate the first bit LD<1> of the latched data by latching the input data DIN in node nd31. When the sixth bit PIN<6> of the input control signal is activated, the first pipeline latch circuit 223_1a can generate the sixth bit LD<6> of the latched data by latching the input data DIN in node nd32. The first pipeline latch circuit 223_1a can set one of the first bit LD<1> and the sixth bit LD<6> of the latched data as the first bit PRE_DOUT<1> of the pre-output data according to the logic level of the pre-output control signal PRE_POUT. For example, the first pipeline latch circuit 223_1a can set the first bit LD<1> of the latched data as the first bit PRE_DOUT<1> of the pre-output data when the pre-output control signal PRE_POUT has a logic high level, and set the sixth bit LD<6> of the latched data as the first bit PRE_DOUT<1> of the pre-output data when the pre-output control signal PRE_POUT has a logic low level. When the first bit POUT<1> of the output control signal is activated, the first pipeline latch circuit 223_1a can output the first bit PRE_DOUT<1> of the pre-output data as the output data DOUT. The first pipeline latch circuit 223_1a may include transmission transistors 223_1_1a, 223_1_4a, 223_1_5a and 223_1_8a, and inverters 223_1_2a, 223_1_3a, 223_1_6a, 223_1_7a and 223_1_9a.

[0060] The second pipeline latch circuit 223_2a can latch the input data DIN and output the latched data as output data DOUT based on the second bit PIN<2> of the input control signal, the seventh bit PIN<7> of the input control signal, the pre-output control signal PRE_POUT, and the second bit POUT<2> of the output control signal. When the second bit PIN<2> of the input control signal is activated, the second pipeline latch circuit 223_2a can generate the second bit LD<2> of the latched data by latching the input data DIN in node nd33. When the seventh bit PIN<7> of the input control signal is activated, the second pipeline latch circuit 223_2a can generate the seventh bit LD<7> of the latched data by latching the input data DIN in node nd34. The second pipeline latch circuit 223_2a can set one of the second bit LD<2> and the seventh bit LD<7> of the latched data as the second bit PRE_DOUT<2> of the pre-output data according to the logic level of the pre-output control signal PRE_POUT. When the second bit POUT<2> of the output control signal is activated, the second pipeline latch circuit 223_2a can output the second bit PRE_DOUT<2> of the pre-output data as the output data DOUT. The second pipeline latch circuit 223_2a may include transmission transistors 223_2_1a, 223_2_4a, 223_2_5a and 223_2_8a and inverters 223_2_2a, 223_2_3a, 223_2_6a, 223_2_7a and 223_2_9a. The structure and operation of the third pipeline latch circuit 223_3a, the fourth pipeline latch circuit 223_4a, and the fifth pipeline latch circuit 223_5a are implemented in the same manner as the first pipeline latch circuit 223_1a and the second pipeline latch circuit 223_2a.

[0061] FIG11 is a timing diagram for describing the operation of the semiconductor device 100a shown in FIG1. ​​As shown in FIG11, whenever a command (not shown) is applied, the semiconductor device 100a can generate a command pulse CMDP.

[0062] The input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I from the command pulse CMDP. The data storage circuit 205 can output the input data DIN stored in the cell array synchronously with the input strobe pulse STBP_I. The input control circuit 207 can sequentially activate the first to tenth bits PIN<1:10> of the input control signal according to the number of times the input strobe pulse STBP_I is input.

[0063] The output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read command pulse CMDP. The output control circuit 215a can sequentially activate the first to fifth bits POUT<1:5> of the output control signal according to the number of times the output strobe pulse STBP_O is input. The output control circuit 215a can synchronously change the logic level of the pre-output control signal PRE_POUT at times T11 and T12 with the fifth bit POUT<5> of the output control signal.

[0064] When the first to tenth bits of the input control signal PIN<1:10> are activated sequentially, the pipe circuit 223a can generate the first to tenth bits of the latched data LD<1:10> sequentially by latching the input data DIN.

[0065] When the pre-output control signal PRE_POUT has a logic high level, the pipe circuit 223a can set the first to fifth bits LD<1:5> of the latched data to the first to fifth bits PRE_DOUT<1:5> of the pre-output data respectively.

[0066] When the pre-output control signal PRE_POUT has a logic low level, the pipeline circuit 223a can set the sixth to tenth bits LD<6:10> of the latched data to the first to fifth bits PRE_DOUT<1:5> of the pre-output data at time T11.

[0067] When the pre-output control signal PRE_POUT has a logic high level, the pipeline circuit 223a can reset the first to fifth bits LD<1:5> of the latched data to the first to fifth bits PRE_DOUT<1:5> of the pre-output data at time T12.

[0068] When the first to fifth bits of the output control signal POUT<1:5> are activated sequentially, the pipe circuit 223a can output the output data DOUT sequentially from the first to fifth bits PRE_DOUT<1:5> of the pre-output data.

[0069] FIG12 is a block diagram illustrating the configuration of a semiconductor device 100b according to another embodiment. As shown in FIG12, the semiconductor device 100b may include an input gating pulse generation circuit (STBP_I GEN) 201, an output gating pulse generation circuit (STBP_O GEN) 203, a data storage circuit 205, an input control circuit 207, an output control circuit 215b, and a pipeline circuit 223b.

[0070] The input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I from the command pulse CMDP in sync with the clock CLK. Whenever a read operation is performed, the input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I according to the command pulse CMDP.

[0071] Synchronously with the clock CLK, the output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read of the command pulse CMDP based on the delay signal LTC. Whenever a read operation is performed, the output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read of the command pulse CMDP.

[0072] The data storage circuit 205 may include a plurality of cell arrays (not shown) configured to store input data DIN. The data storage circuit 205 may output the input data DIN stored in the cell array in synchronization with the input strobe pulse STBP_I.

[0073] The input control circuit 207 may include an input counting signal generation circuit (CNT_I GEN) 209, a selection signal generation circuit (SEL GEN) 211, and an input control signal generation circuit (PIN GEN) 213. The input control circuit 207 can sequentially activate the bits of the input control signal PIN according to the number of times the input strobe pulse STBP_I is input. The input control signal PIN may include the first to the 2Nth bits.

[0074] The output control circuit 215b may include an output counting signal generation circuit (CNT_O GEN) 217b, a pre-output control signal generation circuit (PRE_POUT GEN) 219b, and an output control signal generation circuit (POUT GEN) 221b. The output control circuit 215b can sequentially activate bits of the output control signal POUT according to the number of times the output strobe pulse STBP_O is input. The output control signal POUT may include the first to the Nth bits. The output control circuit 215b can synchronously change the logic levels of the first and second pre-output control signals PRE_POUT1 and PRE_POUT2 with preset bits in the bits of the output control signal POUT. In this embodiment, the preset bits of the output control signal POUT may be set to multiple bits. For example, the output control circuit 215b can change the logic level of the first pre-output control signal PRE_POUT1 synchronously with the third bit POUT<3> of the output control signal, and change the logic level of the second pre-output control signal PRE_POUT2 synchronously with the first bit POUT<1> of the output control signal.

[0075] The output counting signal generation circuit 217b can sequentially activate the bits of the output counting signal CNT_O by counting the number of times the output strobe pulse STBP_O is input. The output counting signal CNT_O may include the first to the Nth bits. The structure and operation of the output counting signal generation circuit 217b are implemented in the same manner as the output counting signal generation circuit 217a shown in FIG1.

[0076] The pre-output control signal generation circuit 219b can synchronously change the logic levels of the first and second pre-output control signals PRE_POUT1 and PRE_POUT2 with preset bits in the bits of the output counting signal CNT_O. For example, the pre-output control signal generation circuit 219b can synchronously change the logic level of the first pre-output control signal PRE_POUT1 with the third bit CNT_O<3> of the output counting signal, and synchronously change the logic level of the second pre-output control signal PRE_POUT2 with the first bit CNT_O<1> of the output counting signal. The structure and operation of the pre-output control signal generation circuit 219a will be described in detail below with reference to FIG13.

[0077] The output control signal generation circuit 221b can output an output strobe pulse STBP_O as one of the bits of the output control signal POUT based on the logic level combination of the output counting signal CNT_O. The structure and operation of the output control signal generation circuit 221b are implemented in the same way as the output control signal generation circuit 221a shown in FIG1.

[0078] The pipe circuit 223b may include multiple pipe latch circuits 223_1b to 223_Nb. The pipe circuit 223b can generate latched data (not shown) by latching input data DIN based on the input control signal PIN, can select some bits of the latched data based on the first pre-output control signal PRE_POUT1 and the second pre-output control signal PRE_POUT2 and set the selected bits as pre-output data (not shown), and can output the pre-output data as output data DOUT based on the output control signal POUT.

[0079] The pipe circuit 223b can generate the first to second N bits of latched data by latching the input data DIN based on the first to second N bits PIN<1:2N> of the input control signal.

[0080] The pipeline circuit 223b can select some bits of the latched data according to the logic levels of the first and second pre-output control signals PRE_POUT1 and PRE_POUT2, and can set the selected bits as bits of the pre-output data. For example, the pipeline circuit 223b can set the first and second bits of the latched data as the first and second bits of the pre-output data according to the logic level of the first pre-output control signal PRE_POUT1, or set the sixth and seventh bits of the latched data as the first and second bits of the pre-output data. The pipeline circuit 223b can set the third to fifth bits of the latched data as the third to fifth bits of the pre-output data according to the logic level of the second pre-output control signal PRE_POUT2, or set the eighth to tenth bits of the latched data as the third to fifth bits of the pre-output data. Therefore, the pipeline circuit 223b can set only a few bits of the latched data, selected according to the number of times the output data DOUT is output, as pre-output data based on the first and second pre-output control signals PRE_POUT1 and PRE_POUT2, thereby reducing the load on the node that outputs the output data DOUT.

[0081] The pipe circuit 223b can output the first to Nth bits of the pre-output data as the output data DOUT based on the first to Nth bits of the output control signal POUT<1:N>. The configuration and operation of the pipe circuit 223b will be described in detail below with reference to FIG15.

[0082] FIG13 is a circuit diagram showing an example of the pre-output control signal generation circuit 219b included in the output control circuit 215b shown in FIG12. As shown in FIG13, the pre-output control signal generation circuit 219b may include a first pre-output control signal generation circuit 241 and a second pre-output control signal generation circuit 243.

[0083] The first pre-output control signal generation circuit 241 may include inverters 241_1, 241_3, 241_5, 241_6, and 241_7, an inverting gate 241_2, and a transmission transistor 241_4. The first pre-output control signal generation circuit 241 may change the logic level of the first pre-output control signal PRE_POUT1 synchronously with the falling edge of the third bit CNT_O<3> of the output counting signal. The first pre-output control signal generation circuit 241 may set the first pre-output control signal PRE_POUT1 to a logic high level based on the inverted reset signal RSTB with a logic low level during the initialization operation. Since the operation of the first pre-output control signal generation circuit 241 in changing the logic level of the first pre-output control signal PRE_POUT1 is implemented in the same way as the operation of the first selection signal generation circuit (231 in FIG. 3) in changing the logic level of the first bit SEL<1> of the selection signal, its detailed description will be omitted herein.

[0084] The second pre-output control signal generation circuit 243 may include inverters 243_1, 243_2, 243_3, 243_6, and 243_7, a transmission transistor 243_4, and an inverting gate 243_5. The second pre-output control signal generation circuit 243 may change the logic level of the second pre-output control signal PRE_POUT2 synchronously with the falling edge of the first bit CNT_O<1> of the output counting signal. The second pre-output control signal generation circuit 243 may set the second pre-output control signal PRE_POUT2 to a logic low level based on the inverted reset signal RSTB with a logic low level during the initialization operation. Since the operation of the second pre-output control signal generation circuit 243 in changing the logic level of the second pre-output control signal PRE_POUT2 is implemented in the same way as the operation of the first selection signal generation circuit (231 in FIG. 3) in changing the logic level of the first bit SEL<1> of the selection signal, its detailed description will be omitted here.

[0085] Figure 14 is a timing diagram for describing the operation of the output control circuit 215b shown in Figure 12.

[0086] During the initialization operation, the output control circuit 215b can set the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal to "H, L, L, L, L". After the initialization operation, the output control circuit 215b can synchronously rotate the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal in the order of "L, H, L, L, L", "L, L, H, L, L", "L, L, L, H, L", "L, L, L, L, H", and "H, L, L, L, L".

[0087] The output control circuit 215b can change the logic level of the first pre-output control signal PRE_POUT1 synchronously with the falling edge of the third bit CNT_O<3> of the output counting signal.

[0088] The output control circuit 215b can change the logic level of the second pre-output control signal PRE_POUT2 synchronously with the falling edge of the first bit CNT_O<1> of the output counting signal.

[0089] When the output strobe pulse STBP_O is continuously input, the output control circuit 215a can sequentially start the first to fifth bits POUT<1:5> of the output control signal according to the logic level combination of the first to fifth bits CNT_O<1:5> of the output counting signal.

[0090] FIG15 is a diagram showing an example of the pipe circuit 223b shown in FIG12. As shown in FIG15, the pipe circuit 223b may include a first pipe latch circuit 223_1b, a second pipe latch circuit 223_2b, a third pipe latch circuit 223_3b, a fourth pipe latch circuit 223_4b, and a fifth pipe latch circuit 223_5b.

[0091] The first channel latch circuit 223_1b may include transmission transistors 223_1_1b, 223_1_4b, 223_1_5b, and 223_1_8b, and inverters 223_1_2b, 223_1_3b, 223_1_6b, 223_1_7b, and 223_1_9b. When the first bit of the input control signal PIN<1> is activated, the first channel latch circuit 223_1b can generate the first bit of the latched data LD<1> by latching the input data DIN into node nd51. When the sixth bit of the input control signal PIN<6> is activated, the first channel latch circuit 223_1b can generate the sixth bit of the latched data LD<6> by latching the input data DIN into node nd52. The first pipeline latch circuit 223_1b can set one of the first bit LD<1> and the sixth bit LD<6> of the latched data as the first bit PRE_DOUT<1> of the pre-output data according to the logic level of the first pre-output control signal PRE_POUT1. When the first bit POUT<1> of the output control signal is activated, the first pipeline latch circuit 223_1b can output the first bit PRE_DOUT<1> of the pre-output data as the output data DOUT. The structure and operation of the second pipeline latch circuit 223_2b are implemented in the same way as the first pipeline latch circuit 223_1b.

[0092] The third-channel latch circuit 223_3b may include transmission transistors 223_3_1b, 223_3_4b, 223_3_5b, and 223_3_8b, and inverters 223_3_2b, 223_3_3b, 223_3_6b, 223_3_7b, and 223_3_9b. When the third bit PIN<3> of the input control signal is activated, the third-channel latch circuit 223_3b can generate the third bit LD<3> of the latched data by latching the input data DIN into node nd53. When the eighth bit PIN<8> of the input control signal is activated, the third-channel latch circuit 223_3b can generate the eighth bit LD<8> of the latched data by latching the input data DIN into node nd54. The third-pipe latch circuit 223_3b can set one of the third bit LD<3> and the eighth bit LD<8> of the latched data to the third bit PRE_DOUT<3> of the pre-output data according to the logic level of the second pre-output control signal PRE_POUT2. When the third bit POUT<3> of the output control signal is activated, the third-pipe latch circuit 223_3b can output the third bit PRE_DOUT<3> of the pre-output data as the output data DOUT. The fourth and fifth-pipe latch circuits 223_4b and 223_5b are implemented in the same way as the third-pipe latch circuit 223_3b.

[0093] FIG16 is a timing diagram for describing the operation of the semiconductor device 100b shown in FIG12. Whenever a command (not shown) is applied, the semiconductor device 100b can generate a command pulse CMDP.

[0094] The input strobe pulse generation circuit 201 can generate the input strobe pulse STBP_I from the command pulse CMDP. The data storage circuit 205 can output the input data DIN stored in the cell array synchronously with the input strobe pulse STBP_I. The input control circuit 207 can sequentially activate the first to tenth bits PIN<1:10> of the input control signal according to the number of times the input strobe pulse STBP_I is input.

[0095] The output strobe pulse generation circuit 203 can generate the output strobe pulse STBP_O by delaying the read command pulse CMDP. The output control circuit 215b can sequentially activate the first to fifth bits POUT<1:5> of the output control signal according to the number of times the output strobe pulse STBP_O is input. The output control circuit 215b can synchronously change the logic level of the first pre-output control signal PRE_POUT1 at times T22 and T24 with the third bit POUT<3> of the output control signal. The output control circuit 215b can synchronously change the logic level of the second pre-output control signal PRE_POUT2 at times T21 and T23 with the first bit POUT<1> of the output control signal.

[0096] When the first to tenth bits of the input control signal PIN<1:10> are activated sequentially, the pipe circuit 223b can generate the first to tenth bits of latched data LD<1:10> sequentially by latching the input data DIN.

[0097] When the first pre-output control signal PRE_POUT1 has a logic high level, the pipe circuit 223b can set the first and second bits LD<1:2> of the latched data to the first and second bits PRE_DOUT<1:2> of the pre-output data, respectively. When the second pre-output control signal PRE_POUT2 has a logic low level, the pipe circuit 223b can set the eighth to tenth bits LD<8:10> of the latched data to the third to fifth bits PRE_DOUT<3:5> of the pre-output data, respectively.

[0098] When the second pre-output control signal PRE_POUT2 has a logic high level, the pipeline circuit 223b can set the third to fifth bits LD<3:5> of the latched data to the third to fifth bits PRE_DOUT<3:5> of the pre-output data respectively at time T21.

[0099] When the first pre-output control signal PRE_POUT1 has a logic low level, the pipeline circuit 223b can set the sixth and seventh bits LD<6:7> of the latched data to the first and second bits PRE_DOUT<1:2> of the pre-output data at time T22.

[0100] When the second pre-output control signal PRE_POUT2 has a logic low level, the pipeline circuit 223b can reset the eighth to tenth bits LD<8:10> of the latched data to the third to fifth bits PRE_DOUT<3:5> of the pre-output data at time T23.

[0101] When the first pre-output control signal PRE_POUT1 has a logic high level, the pipeline circuit 223b can reset the first and second bits LD<1:2> of the latched data to the first and second bits PRE_DOUT<1:2> of the pre-output data at time T24.

[0102] When the first to fifth bits of the output control signal POUT<1:5> are activated sequentially, the pipe circuit 223b can output the output data DOUT sequentially from the first to fifth bits PRE_DOUT<1:5> of the pre-output data.

[0103] As described above, the semiconductor device according to the present disclosure can set only some bits of the data latched in the pipeline circuit as pre-output data according to the number of times the output data is output, and output the pre-output data as output data in sync with the output timing when the output latched data is output, thereby reducing the load on the node from the pipeline circuit to which it outputs output data.

[0104] Although some embodiments of this teaching have been disclosed for illustrative purposes, those skilled in the art to which this invention pertains will recognize that various modifications, additions and substitutions may be made without departing from the scope and spirit of this teaching as defined by the appended claims. [Simplified Explanation of the Diagram]

[0009] FIG1 is a block diagram showing the configuration of a semiconductor device according to one embodiment. FIG2 is a circuit diagram showing an example of an input counting signal generation circuit included in the input control circuit shown in FIG1. ​​FIG3 is a circuit diagram showing an example of a selection signal generation circuit included in the input control circuit shown in FIG1. ​​FIG4 is a circuit diagram showing an example of an input control signal generation circuit included in the input control circuit shown in FIG1. ​​FIG5 is a timing diagram for describing the operation of the input control circuit shown in FIG1. ​​FIG6 is a circuit diagram showing an example of an output counting signal generation circuit included in the output control circuit shown in FIG1. ​​FIG7 is a circuit diagram showing an example of a pre-output control signal generation circuit included in the output control circuit shown in FIG1. ​​FIG8 is a circuit diagram showing an example of an output control signal generation circuit included in the output control circuit shown in FIG1. ​​FIG9 is a timing diagram for describing the operation of the output control circuit shown in FIG1. ​​FIG10 is a diagram showing an example of a pipeline circuit shown in FIG1. ​​FIG11 is a timing diagram for describing the operation of the semiconductor device shown in FIG1. ​​FIG12 is a block diagram showing the structure of a semiconductor device according to another embodiment. Figure 13 is a circuit diagram illustrating an example of the pre-output control signal generation circuit included in the output control circuit shown in Figure 12. Figure 14 is a timing diagram illustrating the operation of the output control circuit shown in Figure 12. Figure 15 is a diagram illustrating an example of the pipeline circuit shown in Figure 12. Figure 16 is a timing diagram illustrating the operation of the semiconductor device shown in Figure 12.

Claims

1. A semiconductor device, comprising: The output control circuit generates a pre-output control signal and an output control signal based on the number of times the output strobe pulse is input. And the pipeline circuit, which: generates latched data by latching input data based on the input control signal, selects one bit of the latched data according to the logic level of the pre-output control signal, sets the selected bit as pre-output data, and outputs the pre-output data as output data based on the output control signal.

2. The semiconductor device as claimed in claim 1, wherein, The pipeline circuit: When the Kth bit of the input control signal is activated, the Kth bit of the latched data is generated by latching the input data; and when the (N+K)th bit of the input control signal is activated, the (N+K)th bit of the latched data is generated by latching the input data, wherein K is a natural number equal to or less than N, and N is set to a natural number equal to or greater than 2.

3. The semiconductor device as claimed in claim 2, further comprising an input control circuit, wherein the input control circuit sequentially activates bits of the input control signal according to the number of times an input strobe pulse is input, wherein, The input control signal includes the first bit to the 2Nth bit.

4. The semiconductor device as claimed in claim 3, further comprising: An input strobe pulse generation circuit generates the input strobe pulse from the command pulse whenever a read operation is performed; And an output strobe pulse generation circuit, which generates the output strobe pulse by delaying the read operation whenever the read operation is performed.

5. The semiconductor device as claimed in claim 2, wherein, The pipeline circuit: selects one of the Kth bit and the N+Kth bit of the latched data according to the logic level of the pre-output control signal, sets the selected bit as the Kth bit of the pre-output data, and outputs the Kth bit of the pre-output data as the output data when the Kth bit of the output control signal is activated.

6. The semiconductor device as claimed in claim 5, wherein, The output control circuit sequentially activates the bits of the output control signal according to the number of times the output strobe pulse is input, wherein the output control signal includes the first bit to the Nth bit.

7. The semiconductor device as claimed in claim 5, wherein, The output control circuit synchronously changes the logic level of the pre-output control signal in sync with the preset bits in the bits of the output control signal.

8. The semiconductor device as claimed in claim 5, wherein, The output control circuit includes: an output counting signal generation circuit that sequentially activates bits of an output counting signal by counting the number of times the output strobe pulse is input; a pre-output control signal generation circuit that synchronously changes the logic level of the pre-output control signal with a preset bit in the bits of the output counting signal; and an output control signal generation circuit that outputs the output strobe pulse as one of the bits of the output control signal according to the logic level combination of the output counting signal.

9. The semiconductor device as claimed in claim 1, wherein, The pipeline circuit includes a first pipeline latch circuit, which: generates the first bit and the (N+1)th bit of the latched data by latching the input data based on the first bit and the (N+1)th bit of the input control signal; selects one of the first bit and the (N+1)th bit of the latched data according to the logic level of the pre-output control signal; sets the selected bit as the first bit of the pre-output data; and outputs the first bit of the pre-output data as the output data based on the first bit of the output control signal, wherein N is set to a natural number equal to or greater than 2.

10. The semiconductor device as claimed in claim 9, wherein, The first pipeline latch circuit: When the first bit of the input control signal is activated, it generates the first bit of the latched data by latching the input data, and sets the first bit of the latched data as the first bit of the pre-output data based on the pre-output control signal.

11. The semiconductor device as claimed in claim 10, wherein, The first pipeline latch circuit: When the (N+1)th bit of the input control signal is activated, it generates the (N+1)th bit of the latched data by latching the input data, and sets the (N+1)th bit of the latched data as the first bit of the pre-output data based on the pre-output control signal.

12. The semiconductor device as claimed in claim 9, wherein, When the first bit of the output control signal is activated, the first pipeline latch circuit outputs the first bit of the pre-output data as the output data. The first bit of the output control signal is activated after a delay time, which is determined from the time point when one of the first bit of the input control signal and the (N+1)th bit is activated. The delay time is changed according to the read delay.

13. The semiconductor device as claimed in claim 9, wherein, The pipeline circuit includes a second pipeline latch circuit, which: generates the Kth and N+Kth bits of the latched data by latching the input data based on the Kth and N+Kth bits of the input control signal; sets one of the Kth and N+Kth bits of the latched data as the Kth bit of the pre-output data according to the logic level of the pre-output control signal; and outputs the Kth bit of the pre-output data as the output data based on the Kth bit of the output control signal, wherein K is a natural number equal to or less than N.

14. A semiconductor device, comprising: A first pipeline latch circuit: selects one of the input data latched in a first node and the input data latched in a second node according to the logic level of the pre-output control signal; sets the selected data as the first bit of the pre-output data; and outputs the first bit of the pre-output data as output data when the first bit of the output control signal is activated. A second pipeline latch circuit: selects one of the input data latched in a third node and the input data latched in a fourth node according to the logic level of the pre-output control signal; sets the selected data as the second bit of the pre-output data; and outputs the second bit of the pre-output data as output data when the second bit of the output control signal is activated. An output control circuit synchronously changes the logic level of the pre-output control signal with respect to the first bit of the output control signal.

15. The semiconductor device as claimed in claim 14, wherein, The first pipeline latch circuit: When the first bit of the input control signal is activated, the input data is latched in the first node, and when the second bit of the input control signal is activated, the input data is latched in the second node, wherein the first bit of the output control signal is activated after a delay time from the time point when one of the first bit and the second bit of the input control signal is activated.

16. The semiconductor device as claimed in claim 15, wherein, The second pipeline latch circuit: When the third bit of the input control signal is activated, the input data is latched in the third node, and when the fourth bit of the input control signal is activated, the input data is latched in the fourth node, wherein the second bit of the output control signal is activated after the delay time has elapsed from the time point when one of the third bit and the fourth bit of the input control signal is activated.

17. A semiconductor device, comprising: A first pipeline latch circuit: selects one of the input data latched in a first node and the input data latched in a second node according to the logic level of a first pre-output control signal; sets the selected data as the first bit of the pre-output data; and outputs the first bit of the pre-output data as output data when the first bit of the output control signal is activated. A second pipeline latch circuit: selects one of the input data latched in a third node and the input data latched in a fourth node according to the logic level of a second pre-output control signal; sets the selected data as the second bit of the pre-output data; and outputs the second bit of the pre-output data as output data when the second bit of the output control signal is activated. An output control circuit synchronously changes the logic level of the second pre-output control signal with respect to the first bit of the output control signal.

18. The semiconductor device as claimed in claim 17, wherein, The output control circuit synchronously changes the logic level of the first pre-output control signal with the second bit of the output control signal.

19. The semiconductor device as claimed in claim 17, wherein, The first pipeline latch circuit: When the first bit of the input control signal is activated, the input data is latched in the first node, and when the second bit of the input control signal is activated, the input data is latched in the second node, wherein the first bit of the output control signal is activated after a delay time from the time point when one of the first bit and the second bit of the input control signal is activated.

20. The semiconductor device as claimed in claim 19, wherein, The second pipeline latch circuit: When the third bit of the input control signal is activated, the input data is latched in the third node, and when the fourth bit of the input control signal is activated, the input data is latched in the fourth node, wherein the second bit of the output control signal is activated after a delay time from the time point when one of the third bit and the fourth bit of the input control signal is activated.

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