Surface mount device chip fuse

Abstract

The present invention provides a surface mount device wafer fuse, comprising: a dielectric substrate; conductive first upper terminal and second upper terminal disposed on the top surface of the dielectric substrate and defining a gap therebetween; a fusible element formed of solder disposed on the top surface of the dielectric substrate and bridging the first upper terminal and the second upper terminal within the gap; and conductive first lower terminal and second lower terminal disposed on the bottom surface of the dielectric substrate and electrically connected to the first upper terminal and the second upper terminal, respectively, wherein the material of the dielectric substrate exhibits anti-wetting properties relative to the solder forming the fusible element.

Description

[Technical Field]

[0001] This disclosure generally relates to the field of circuit protection devices. More specifically, this disclosure relates to a surface mount device chip fuse comprising a fusible element formed of solder disposed on a moisture-resistant substrate. [Previous Technology]

[0002] Fuses are commonly used as circuit protection devices and are typically installed between a power supply and a component in a circuit to be protected. Conventional surface mount device (SMD) chip fuses comprise a fusible element disposed on an electrically insulating substrate. The fusible element may extend between conductive terminals located at opposite ends of the substrate. Upon the occurrence of a fault condition such as an overcurrent condition, the fusible element melts or otherwise separates to interrupt the flow of current through the fuse.

[0003] When the fusible element of a fuse separates due to an overcurrent condition, an electric arc may sometimes propagate through the air between the separated portions of the fusible element (e.g., through vaporized particles that have molten the fusible element). If not extinguished, this arc can allow a large amount of subsequent current to flow from the power source to the protected component in the circuit, thereby damaging the protected component despite the physical disconnection of the fusible element.

[0004] The improvements of the present invention may be useful in light of these and other considerations. [Summary of the Invention]

[0005] This summary is provided to introduce, in a simplified form, a series of concepts further described in the following embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to serve as an aid in determining the scope of the claimed subject matter.

[0006] A surface mount device wafer fuse according to an exemplary embodiment of the present disclosure may include: a dielectric substrate; conductive first upper terminal and second upper terminal disposed on a top surface of the dielectric substrate and defining a gap therebetween; a fusible element formed of solder disposed on the top surface of the dielectric substrate and bridging the first upper terminal and the second upper terminal within the gap; and conductive first lower terminal and second lower terminal disposed on a bottom surface of the dielectric substrate and electrically connected to the first upper terminal and the second upper terminal, respectively, wherein the material of the dielectric substrate exhibits anti-wetting properties relative to the solder forming the fusible element.

Implementation Method

[0008] Exemplary embodiments of surface mount device (SMD) chip fuses according to the present disclosure will now be described more fully below with reference to the accompanying drawings. However, SMD chip fuses may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will convey certain exemplary forms of SMD chip fuses to those skilled in the art.

[0009] Referring to FIG1, a perspective view illustrating an SMD wafer fuse 10 according to an exemplary embodiment of the present disclosure is shown. The SMD wafer fuse 10 may generally include a dielectric substrate 12, conductive first upper terminals 14a and second upper terminals 14b, conductive first lower terminals 16a and second lower terminals 16b, and a fusible element 18. The dielectric substrate 12 may be a substantially flat rectangular wafer formed of a low surface energy, electrically insulating, heat-resistant material. Examples of such materials include, but are not limited to, glass, ceramics, FR-4, perfluoroalkoxy (PFA), ethylene tetrafluoroethylene (ETFE), or polyvinylidene fluoride (PVdF). The longitudinal edges of the dielectric substrate 12 may have semi-circular serrated structures 20a and 20b formed therein (wherein the serration is also called a castellation). The present disclosure is not limited thereto.

[0010] Upper terminals 14a and 14b, and lower terminals 16a and 16b, may be disposed on the top and bottom surfaces of the dielectric substrate 12, respectively, and may be formed of any suitable conductive material, including but not limited to copper, gold, silver, nickel, tin, etc. Upper terminals 14a and 14b may extend from their respective longitudinal edges toward each other from the dielectric substrate 12 and may terminate near the longitudinal center of the top surface to define a gap 22 therebetween. Toothed structures 20a and 20b may be electroplated or otherwise coated with a conductive material (e.g., the same conductive material as that forming terminals 14a and 14b, and lower terminals 16a and 16b) to provide electrical connections between upper terminals 14a and lower terminals 16a and between upper terminals 14b and lower terminals 16b, respectively. In an alternative embodiment of the SMD chip fuse 10 illustrated in FIG. 2, the toothed structures 20a and 20b may be omitted, and the substantially flat longitudinal edges 21a and 21b of the dielectric substrate 12 may be electroplated or otherwise coated with a conductive material to provide electrical connections between the upper terminal 14a and the lower terminal 16a, and between the upper terminal 14b and the lower terminal 16b, respectively. In another alternative embodiment of the SMD chip fuse 10 illustrated in FIG. 3, conductive vias 25a and 25b may extend through the dielectric substrate 12 between the upper terminal 14a and the lower terminal 16a, and between the upper terminal 14b and the lower terminal 16b, respectively, to provide separate electrical connections therebetween. This disclosure is not limited thereto.

[0011] Referring back to FIG. 1, the fusible element 18 may be formed from a certain amount of solder disposed on the top surface of the dielectric substrate 12 within the gap 22, bridging the upper terminals 14a and 14b therebetween to provide an electrical connection. The solder forming the fusible element 18 may be selected such that, when the solder is in a molten or semi-molten state, the solder may averse to or tend to be drawn away from the surface of the dielectric substrate 12. That is, the material of the dielectric substrate 12 may exhibit significant "wetting resistance" relative to the solder forming the fusible element 18. In one example, the dielectric substrate 12 may be formed of PFA and the solder may be SAC305 solder. In another example, the dielectric substrate 12 may be formed of ETFE and the solder may be a eutectic solder. In yet another example, the dielectric substrate 12 may be formed of FR-4, PI (polyimide), and the solder may be a high-melting-point solder (i.e., a solder with a melting temperature above 260 degrees Celsius). This disclosure is not limited thereto.

[0012] During normal operation, the SMD chip fuse 10 can be connected in a circuit (e.g., lower terminals 16a and 16b can be soldered to individual contacts on a printed circuit board) and current can flow through lower terminals 16a and 16b, upper terminals 14a and 14b, and the fusible element 18. In the event of an overcurrent condition, where the current flowing through the SMD chip fuse 10 exceeds its rated current, the fusible element 18 may melt or otherwise separate. This stops the current flowing through the SMD chip fuse 10 to prevent or mitigate damage to connected and surrounding circuit components.

[0013] Furthermore, due to the low surface energy and aversion-resistant "wetting-resistant" properties of the dielectric substrate 12 relative to the molten or semi-molten solder of the fusible element 18 (described above), the separated portions of the fusible element 18 can be pulled apart from each other and from the surface of the dielectric substrate 12, and can accumulate on the opposite edges / parts of the upper terminals 14a and 14b, thereby ensuring that the SMD chip fuse 10 disconnects the current in response to an overcurrent condition. This prevents or mitigates arcing between the separated portions of the fusible element 18.

[0014] Referring to FIG4, an alternative embodiment of the SMD chip fuse 10 is shown, wherein the adjacent portions of the fusible element 18 and the upper terminals 14a and 14b may be covered with a dielectric passivation layer 26 to protect the fusible element 18 from external contaminants and prevent short circuits with external circuit components. The passivation layer 26 may be formed of epoxy resin, polyimide, glass, ceramic, or other materials that exhibit "wetting resistance" properties relative to the solder forming the fusible element 18. Therefore, when the fusible element 18 melts during the overcurrent condition of the SMD chip fuse 10, the aversion to wetting resistance of the passivation layer 26 to the molten or semi-molten solder of the fusible element 18 may repel the separated portions of the fusible element 18, further aiding in current separation therebetween.

[0015] Referring to FIG. 5, another alternative embodiment of the SMD chip fuse 10 is provided, wherein the top surfaces of the opposite portions of the upper terminals 14a and 14b are coated or plated with collecting pads 31a and 31b formed of a flux or wetting agent that exhibits significant affinity or "wetting" properties relative to the solder forming the fusible element 18. Examples of such materials include, but are not limited to, flux compounds made of rosin and / or polyethylene glycol ethers. Therefore, when the fusible element 18 melts during an overcurrent condition in the SMD chip fuse 10, the molten portion and the separated portion of the fusible element 18 can be drawn to and accumulated on the collecting pads 31a and 31b to further aid in current separation between the upper terminals 14a and 14b.

[0016] Referring to FIG6, another alternative embodiment of the SMD chip fuse 10 is provided, the SMD chip fuse 10 including a "non-contact" cover plate 30 disposed on the adjacent portions of the fusible element 18 and the upper terminals 14a and 14b for protecting the fusible element 18 from external contaminants and preventing short circuits with external circuit components. The cover plate 30 may be substantially the same as the dielectric substrate 12 (e.g., formed from the same material and having the same size and shape as the dielectric substrate 12), but may include a cavity 32 formed in its bottom surface. When the cover plate 30 is stacked on top of the dielectric substrate 12 as illustrated, the adjacent portions of the fusible element 18 and the upper terminals 14a and 14b may be disposed within the cavity 32.

[0017] Referring to FIG7, another alternative embodiment of the SMD chip fuse 10 is provided, wherein the SMD chip fuse 10 includes electrically insulating metal pads 34a and 34b disposed on top of the dielectric substrate 12 and extending below the fusible element 18 within a gap 22. When the fusible element 18 melts during an overcurrent condition in the SMD chip fuse 10, the metal pads 34a and 34b provide additional surface areas for collecting the molten solder of the fusible element 18, clearing the gap 22, and providing current separation between the upper terminals 14a and 14b. Thus, the metal pads 34a and 34b facilitate high fuse ratings and low resistance in a small fuse package, while also providing high insulation resistance after current disconnection.

[0018] Referring to FIG8, another alternative embodiment of the SMD wafer fuse 10 is provided, the SMD wafer fuse 10 including a recess or trench 36 formed in a dielectric substrate 12 beneath the fusible element 18. When the fusible element 18 melts during an overcurrent condition in the SMD wafer fuse 10, the trench 36 provides space for collecting the molten solder of the fusible element 18 to clear the gap 22 and provides current separation between the upper terminals 14a and 14b. Therefore, the trench 36 can facilitate high fuse ratings and low resistance in a small fuse package.

[0019] As used herein, an element or step described in the singular and referred to as "a / an" should be understood to not exclude a plurality of elements or steps unless such exclusion is expressly stated. Furthermore, reference to "one embodiment" of this disclosure is not intended to exclude the existence of additional embodiments that also contain the described features.

[0020] While this disclosure refers to certain embodiments, numerous modifications, alterations, and variations of the described embodiments are possible without departing from the field and scope of this disclosure as defined in the appended claims. Therefore, this disclosure is intended to be limited to the described embodiments, but has the full scope defined by the language of the following claims and their equivalents. [Simplified Explanation of the Diagram]

[0007] FIG1 is a perspective view showing a wafer fuse of a surface mount device according to an exemplary embodiment of the present disclosure. FIG2 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG3 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG4 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG5 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG6 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG7 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure. FIG8 is a perspective view showing a wafer fuse of a surface mount device according to another exemplary embodiment of the present disclosure.

Claims

1. A surface mount device wafer fuse, comprising: Dielectric substrate; A conductive first upper terminal and a second upper terminal are disposed on the top surface of the dielectric substrate, and a gap is defined between the first upper terminal and the second upper terminal. A fusible element, formed of solder disposed on the top surface of the dielectric substrate, bridging a first upper terminal and a second upper terminal within the gap; and conductive first lower terminals and second lower terminals, respectively disposed on the bottom surface of the dielectric substrate and electrically connected to the first upper terminal and the second upper terminal; a first metal pad and a second metal pad, disposed on the top surface of the dielectric substrate and extending from opposite sides of the gap into the gap below the fusible element, wherein the first metal pad and the second metal pad are electrically isolated, wherein when the fusible element melts under an overcurrent condition, the first metal pad and the second metal pad collect the solder to clear the gap and provide current separation between the first upper terminal and the second upper terminal, wherein the material of the dielectric substrate exhibits anti-wetting properties relative to the solder forming the fusible element.

2. The surface mount device wafer fuse as claimed in claim 1, wherein the edge of the dielectric substrate includes a conductive material disposed thereon for providing an electrical connection between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal.

3. The surface mount device wafer fuse as claimed in claim 2, wherein the edge of the dielectric substrate is serrated.

4. The surface mount device wafer fuse as claimed in claim 1, further comprising a conductive via extending through the dielectric substrate and providing electrical connections between the first upper terminal and the first lower terminal and between the second upper terminal and the second lower terminal.

5. The surface mount device wafer fuse as claimed in claim 1, further comprising a passivation layer disposed on the fusible element and adjacent portions of the first upper terminal and the second upper terminal.

6. The surface mount device wafer fuse as claimed in claim 1, further comprising a collection pad disposed on opposite portions of the first upper terminal and the second upper terminal, the collection pad being formed of a wetting agent exhibiting wetting properties relative to the solder forming the fusible element.

7. The surface mount device wafer fuse as claimed in claim 1, further comprising a non-contact cover plate disposed on the top surface of the dielectric substrate, the non-contact cover plate being formed of a dielectric material and having a cavity formed in its bottom surface, the fusible element being disposed within the cavity.

8. The surface mount device wafer fuse as claimed in claim 1, further comprising a trench formed in the top surface of the dielectric substrate below the fusible element.

9. The surface mount device wafer fuse as claimed in claim 1, wherein the electrically insulating metal pad extends beyond the gap.

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