Selectively thinned gate-all-around (GAA) structures

Abstract

This document provides techniques for forming semiconductor devices that have thinner semiconductor regions (e.g., thinner nanobands) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within the same or adjacent layers). In an example, adjacent semiconductor devices for a given memory cell include p-channel devices and n-channel devices. The p-channel device may be a GAA transistor with a semiconductor nanoband of a first width, while the n-channel device may be a GAA transistor with a semiconductor nanoband of a second width greater than the first width (e.g., the first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally reduce the operating current through the p-channel device by reducing the width of the active semiconductor channel.

Description

[Technical Field]

[0001] This invention relates to integrated circuits, and more specifically, to gate-all-around (GAA) semiconductor devices. [Previous Technology]

[0002] As the size of integrated circuits continues to shrink, many challenges arise. For example, reducing the size of memory and logic cells is becoming increasingly difficult. The power consumption of such a large number of semiconductor devices is becoming a growing concern. Some processor cores employ voltage scaling techniques to reduce the power consumption of integrated circuits, but this makes various semiconductor devices more susceptible to variations in manufacturing processes and / or dopants, potentially causing devices to malfunction. Therefore, many significant challenges remain in designing semiconductor devices that can operate at lower voltage levels. [Summary of the Invention]

[0003] and

Implementation Method

[0011] This document provides techniques for forming semiconductor devices with thinner semiconductor regions (e.g., thinner nanobands) compared to other semiconductor devices on the same substrate. These techniques can be used in any number of integrated circuit applications and are particularly useful for logic and memory cells, such as cells using gate-all-around (GAA) transistors. In an example, adjacent semiconductor devices of a given memory cell, such as synchronous random access memory (SRAM) cells, include p-channel devices and n-channel devices. More specifically, the p-channel device can be a GAA transistor having a semiconductor nanoband with a first width, while the n-channel device can be a GAA transistor having a semiconductor nanoband with a second width greater than the first width. Note that this width difference can be seen in a cross-section passing through the channel region and perpendicular to the fin structure forming the nanoband. Further note that in such a cross-section, an imaginary horizontal plane can pass through at least a portion of the two nanobands, such that they are at comparable heights; in other embodiments, the two nanobands are at slightly different heights, such that no imaginary horizontal plane passes through the two nanobands (e.g., the example of nanobands being released from two adjacent layers of a stack of alternating layers). In some cases, the width of the nanoband in the p-channel device is approximately half the width of the nanoband in the n-channel device. According to one embodiment, the p-channel device is fabricated with a thinner width than the corresponding n-channel device in order to structurally reduce the operating current through the p-channel device by reducing the width of the active semiconductor channel. Many variations and embodiments will be apparent according to the invention. General Overview

[0012] As mentioned above, many complex challenges remain in designing semiconductor devices that consume less energy. With decreasing operating voltages, the successful operation of integrated circuit semiconductor devices becomes more susceptible to system process variations and / or random dopant fluctuations. In the example of memory cells, such random dopant and / or process variations can result in p-channel devices (strong p-type and weak n-type devices) with, for example, higher drive currents than their corresponding n-channel devices, potentially leading to memory write errors. In particular, such memory cells cannot be written below a certain minimum voltage (write failure below Vmin). Several techniques have been implemented to mitigate write failures, but they generate additional power consumption, occupy valuable wafer footprint, and are relatively difficult to design (layout).

[0013] Therefore, and according to embodiments of the invention, techniques for forming selectively thinned transistor structures are provided herein. By selectively thinning the semiconductor region of a p-channel device compared to an n-channel device, the drive current through the p-channel device is reduced and more easily controlled. Thus, thinning techniques provide a structural solution to reduce potential write errors in memory cells. While many transistor designs may benefit from these techniques, they are particularly useful for GAA structures in which the nanobands of the p-channel devices have a smaller width than the corresponding nanobands of the corresponding n-channel devices on the same substrate. In some embodiments, the width difference can be as high as 50%, 60%, or 75%. Note that these techniques can also be applied to other channel configurations, such as nanowires (or other GAA configurations) and fins (e.g., dual-gate and triple-gate configurations), where the p-type nanowires or fins have a thinner width than the corresponding width of the n-type nanowires or fins.

[0014] In one embodiment, according to one embodiment, during the fabrication of a given p-channel device, a dielectric helmet or protective structure is formed on a fin of semiconductor material. The helmet structure protects the top of the fin during an isotropic etching process that laterally etches the exposed portion of the fin to reduce the overall width of the fin. Once the helmet structure has been removed, the remainder of the process can be performed on the p-channel device and any other n-channel device in the same manner. Subsequent processing may include, for example, selective etching of a sacrificial layer (e.g., a silicon-germanium layer) included in the fin to release the nanoribbon (e.g., silicon).

[0015] According to one embodiment, the integrated circuit includes a first semiconductor device having a first semiconductor nanoribbon extending between a first source region and a first drain region, and a second semiconductor device having a second semiconductor nanoribbon extending between a second source region and a second drain region. The first semiconductor nanoribbon has a length and a first width. The length corresponds to a first distance between the source and drain regions, and the width corresponds to a second distance between the sidewalls of the first nanoribbon, the second distance extending in a direction orthogonal to the direction in which the first distance extends. The second semiconductor nanoribbon may have the same length as the first semiconductor nanoribbon and a second width less than the first width. If the nanoribbon lengths are at least within 1 nm of each other, they can be considered to be the same. In other embodiments, the nanoribbon lengths may be different.

[0016] According to another embodiment, an electronic device includes a wafer package having one or more chips. At least one of the one or more chips includes a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor material body extending between a first source region and a first drain region and has a first sub-fin below the first semiconductor material body. The second semiconductor device has a second semiconductor material body extending between a second source region and a second drain region and has a second sub-fin below the second semiconductor material body. A first gate dielectric layer surrounds the first semiconductor material body, and a second gate dielectric layer surrounds the second semiconductor material body. The first semiconductor material body has a first width that may be substantially the same as the width of the first sub-fin, and the second semiconductor material body has a second width that is smaller than the width of the second sub-fin and smaller than the width of the first semiconductor material body.

[0017] According to another embodiment, a method of forming an integrated circuit includes forming a first multilayer fin and a second multilayer fin, each of the first multilayer fin and the second multilayer fin including a first material layer and a second material layer, wherein the second material layer contains a semiconductor material suitable for use as a nanoband channel; forming a helmet structure on the top surface of the first multilayer fin and the second multilayer fin; masking the second multilayer fin while exposing the first multilayer fin; and performing a lateral etching process on the sidewalls of the first multilayer fin to reduce the width of the first multilayer fin.

[0018] As described above, these techniques are particularly well-suited for use with nanowires and nanocharged crystals (e.g., gate-all-around transistors), but may also be applicable to finFET devices in certain cases. For example, the source and drain regions may be doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement of the source / drain formation process. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-first or gate-last process (sometimes referred to as metal gate removal or RMG process). Any number of semiconductor materials can be used to form the transistor, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0019] The use of the techniques and structures provided herein can be detected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); combined mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography; local electrode atomic probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable example analytical tools. For example, in some example embodiments, such tools can indicate some p-type semiconductor devices having nanobands with smaller widths compared to corresponding nanobands of other n-type semiconductor devices. In some embodiments, such a tool can indicate a semiconductor device having a nanoband with a narrower width compared to the width of the sub-fin region of the same semiconductor device (except for a relatively slight taper of the fin structure due to process limitations rather than intentional thinning). In some embodiments, such a tool can indicate one or more semiconductor devices having an undercut region at the upper edge of the sub-fin beneath the narrower nanoband. In this way, the upper edge of the sub-fin beneath the narrower nanoband can be tapered or otherwise have a concave or angled profile, while the upper edge of the sub-fin beneath the unthinned nanoband is not.

[0020] It should be readily understood that the meanings of "above" and "on top" in this invention should be interpreted in the broadest sense, such that "above" and "on top" not only mean "directly on" something, but also include the meaning of a layer having an intermediate feature or being in between. Furthermore, for ease of description, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0021] As used herein, the term "layer" refers to a portion of material comprising a region having a thickness. A monolayer is a layer composed of a single layer of atoms of a given material. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the thickness of the layer is less than the thickness of the continuous structure. For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A layer may conformally to a given surface (whether flat or curved) and have a relatively uniform thickness throughout the layer.

[0022] As used herein, “different composition” or “different composition” materials refer to two materials with different chemical compositions. For example, such compositional differences may be due to elements in one material but not in the other (e.g., SiGe is compositionally different from silicon), or due to one material having all the same elements as the second material, but at least one of these elements being intentionally provided in one material at a different concentration relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this diversity of chemical composition, these materials may also have different dopants (e.g., gallium and magnesium) or the same dopants but at different concentrations. In yet another embodiment, different compositional materials may also refer to two materials with different crystallographic orientations. For example, (110) silicon is compositionally different from (100) silicon. For example, blank wafer layer transfer can be used to create stacks with different orientations. Architecture

[0023] FIG1A is a cross-sectional view taken across two example semiconductor devices 102 and 104 according to an embodiment of the present invention. Each of semiconductor devices 102 and 104 may be a non-planar metal-oxide-semiconductor (MOS) transistor, such as a tri-gate or gate-all-around (GAA) transistor, although other transistor topologies and types may also benefit from the techniques provided herein. The embodiments shown herein use a GAA structure. Semiconductor devices 102 and 104 represent a portion of an integrated circuit that may contain any number of similar semiconductor devices.

[0024] As can be seen, semiconductor devices 102 and 104 are formed on substrate 106. Any number of semiconductor devices can be formed on substrate 106, but two are used here as examples. Substrate 106 may be, for example, a bulk substrate comprising group IV semiconductor materials (e.g., silicon, germanium, or silicon-germanium), group III-V semiconductor materials (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate may be a semiconductor-on-insulator substrate having the desired semiconductor layer (e.g., silicon on silicon dioxide) on a buried insulating layer. Alternatively, the substrate may be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used.

[0025] The semiconductor material in each of semiconductor devices 102 and 104 can be formed from substrate 106. Semiconductor devices 102 and 104 can each include semiconductor material as nanowires or nanoribbons, which can be, for example, native to substrate 106 (formed by the substrate itself). Alternatively, the semiconductor material can be formed from material deposited on an underlying substrate. In one such example, a silicon germanium (SiGe) blanket layer can be deposited onto a silicon substrate, followed by patterning and etching to form multiple SiGe fins or nanoribbons. In another such example, non-native fins can be formed in a process known as aspect ratio trapping, where native fins are etched away to leave fin trenches, which can then be replaced with alternative semiconductor materials (e.g., group IV or group III-V materials). In yet another embodiment, the fin includes alternating material layers (e.g., alternating silicon and SiGe layers) that facilitate the formation of nanowires and nanobelts during the gate formation process, wherein one type of alternating layer is selectively etched away to release other types of alternating layers within the channel region so that a gate-all-around (GAA) process can be performed.

[0026] As can be further seen, adjacent semiconductor devices are separated by a dielectric filler 108, which may include silicon oxide. The dielectric filler 108 provides shallow trench isolation (STI) between any adjacent semiconductor devices. The dielectric filler 108 may be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxide.

[0027] Semiconductor device 102 includes a sub-fin region 110 and a plurality of nanobands 112a above the sub-fin region 110 (semiconductor device 104 similarly includes nanobands 112b above the sub-fin region 110). According to some embodiments, the sub-fin region 110 includes the same semiconductor material as the substrate 106 and is adjacent to the dielectric filler 108. According to some embodiments, nanobands 112a and 112b extend between corresponding source and drain regions to provide an active region of the transistor (e.g., a semiconductor region below the gate). The source and drain regions are not shown in the cross-sectional view of FIG1A. The formation of this transistor structure is described in more detail with reference to FIG3A-3H.

[0028] According to some embodiments, the source and drain regions are epitaxial regions provided using etching and alternative processes. In other embodiments, one or both of the source and drain regions may be native portions of implanted doping, such as semiconductor fins or substrates. Any semiconductor material suitable for the source and drain regions (e.g., group IV and III-V semiconductor materials) may be used. The source and drain regions may include multiple layers, such as pads and capping layers, to improve contact resistance. In any such case, the composition and doping of the source and drain regions may be the same or different, depending on the transistor polarity. For example, in one example, one transistor is a p-type MOS (PMOS) transistor, while the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials may be used.

[0029] Nanobands 112a and 112b include a gate dielectric 114, which may comprise a single material layer or multiple stacked material layers. In some embodiments, the gate dielectric 114 includes a first dielectric layer such as silicon oxide and a second dielectric layer comprising a high-k material such as hafnium oxide. Hafnium oxide may be doped to influence the threshold voltage of a given semiconductor device. In some embodiments, the gate dielectric 114 surrounding semiconductor device 102 has a different elemental doping concentration than the gate dielectric 114 surrounding semiconductor device 104. According to some embodiments, the doping element used in the gate dielectric 114 is lanthanum. The gate dielectric 114 is present around each nanoband 112a and 112b and may also be present above the sub-fin portion 110. In some embodiments, the gate dielectric 114 is also present above the top surface of the dielectric filler 108.

[0030] According to some embodiments, gate structures 116 extend over nanobands 112a and 112b of semiconductor devices 102 and 104, respectively. Gate structures 116 may comprise any sufficiently conductive material, such as metals, metal alloys, or doped polycrystalline silicon. According to some embodiments, gate structures 116 may be interrupted by gate cleaving structures between any adjacent semiconductor devices. In some embodiments, one or more work function metals may be included around nanobands 112a and 112b. In some embodiments, semiconductor device 102 is a p-channel device comprising a work function metal having titanium, and semiconductor device 104 is an n-channel device comprising a work function metal having tungsten.

[0031] As described above, semiconductor device 102 may be a p-channel device having a semiconductor nanoband 112a doped with an n-type dopant (e.g., phosphorus or arsenic), and semiconductor device 104 may be an n-channel device having a semiconductor nanoband 112b doped with a p-type dopant (e.g., boron). According to some embodiments, nanoband 112a has a smaller width (w2) than the width (w1) of nanoband 112b. Furthermore, the width of nanoband 112b may be substantially the same as the width of sub-fin 110. If they are within 1 nm of each other, they can be considered to have substantially the same width. Therefore, the width w2 of nanoband 112a may be smaller than the width w1 of sub-fin 110. In some embodiments, the width w1 is between about 5 nm and about 8 nm, and the width w2 is between about 2 nm and about 4 nm. In some embodiments, the width w2 is at least 50% smaller than the width w1. Note that, according to some embodiments, the widths of the nanobands being compared can be two laterally adjacent or adjacent nanobands (as shown by dashed lines) through which an imaginary horizontal plane passes. In some other embodiments, the widths of the nanobands being compared can be two nanobands offset from each other by one or two layers of a given multilayer fin structure. In this case, the heights of the two nanobands being compared are slightly different, so no imaginary horizontal plane passes through the two nanobands. In a more general sense, the two nanobands being compared are at comparable heights (e.g., within the same horizontal plane or offset by one or two layers).

[0032] FIG1B illustrates an integrated circuit similar to that depicted in FIG1A according to an embodiment, except that various features are drawn to reflect actual process conditions. For example, although FIG1A generally uses straight lines, right angles, and smooth surfaces to indicate various features, the actual integrated circuit structure configured according to an embodiment of the invention may have imperfect straight lines and right angles, and some features may have rough surface topography or be otherwise unsmooth, taking into account practical limitations such as etching and deposition processes. As can be seen in FIG1B, the sub-fin 110 may be tapered rather than rectangular, and the nanobands 112a / 112b are more rounded and speckled. Note that the nanobands may also taper gradually, such that the width of the uppermost nanoband is smaller than the width of the lowermost nanoband, and the middle nanobands have a width between the width of the lowermost nanoband and the width of the uppermost nanoband. Further note that the sidewall of the right sub-fin may be collinear with the sidewall of nanoband 112b (because there is no intentional thinning along this fin structure), and the sidewall of the left sub-fin is not collinear with the sidewall of nanoband 112a (because nanoband 112a is intentionally thinned). Additionally, the corner of the left sub-fin region 110 of the semiconductor device 102 may show signs of etching (e.g., undercut etching), as will be discussed in more detail herein. Manufacturing Method

[0033] Figures 2A to 2G include cross-sectional views according to embodiments of the invention, which collectively illustrate an example process for forming an integrated circuit with a semiconductor device having a narrower nanoband compared to other semiconductor devices on the same substrate. Each figure shows an example structure generated from the process up to that point in time, and thus the depicted structure evolves as the process continues, eventually forming the structure shown in Figure 2G, which is similar to the structure shown in Figure 1A. The illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuits not shown. Example materials and process parameters are given, but as will be understood, the invention is not intended to be limited to any particular such materials or parameters.

[0034] FIG. 2A illustrates a cross-sectional view across a substrate according to an embodiment of the present invention, the substrate having a series of material layers deposited thereon. The previous discussion regarding the example configuration and materials of the substrate 106 also applies here. Alternating material layers may be deposited on the substrate 106, including a sacrificial layer 202 alternating with a semiconductor layer 204. The semiconductor layer 204 may include silicon, germanium, or a combination thereof. The sacrificial layer 202 has a different material composition than the semiconductor layer 204. In some embodiments, the sacrificial layer 202 includes some combination of silicon and germanium. In other embodiments, the sacrificial layer 202 includes a higher germanium content than the semiconductor layer 204. Although the dimensions may vary depending on the example embodiment, the thickness of each semiconductor layer 204 and sacrificial layer 202 may be between approximately 5 nm and approximately 25 nm. Each of the sacrificial layer 202 and the semiconductor layer 204 can be deposited using any known material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0035] FIG2B illustrates a cross-sectional view of the structure shown in FIG2A after the formation of semiconductor fins according to an embodiment of the present invention. Any number of fins can be patterned on the integrated circuit, but only two are shown here for clarity. Each of semiconductor devices 102 and 104 includes a semiconductor fin. As shown, the fin may include at least a portion that is native to the substrate, or it may be non-native to the substrate. Each fin shown includes a multilayer structure with alternating sacrificial layers 202 and semiconductor layers 204. In some embodiments, the fins are alternating for transistor polarity. For example, the fin of semiconductor device 102 may include a PMOS material fin (e.g., semiconductor layer 204 is doped with an n-type dopant) and the fin of semiconductor device 104 may include an NMOS material fin (e.g., semiconductor layer 204 is doped with a p-type dopant) for a first logic or memory cell. Many other configurations can be used, including fins included in integrated circuit portions other than memory or logic portions, such as analog mixed-signal portions, input / output portions, radio frequency or transducer portions.

[0036] The fins can be formed using a patterned hard mask layer or photoresist, such as capping layer 206. According to some embodiments, capping layer 206 protects the underlying material during directional etching processes such as reactive ion etching (RIE). The capping layer can be, for example, a nitride, oxide oxynitride, carbide, or oxycarbonitride. Although the dimensions can vary depending on the example embodiments, the total height of the fins extending above the surface of substrate 106 can range from about 100 nm to about 250 nm.

[0037] It should be noted that the fin process described with reference to Figures 2A and 2B is only an example process for forming multi-layer fins. Other processes can also be used, such as the aforementioned aspect ratio-based process.

[0038] FIG2C illustrates a cross-sectional view of the structure shown in FIG2B after the formation of dielectric fill 108 according to an embodiment of the present invention. Dielectric fill 108 can act as shallow trench isolation (STI) between adjacent semiconductor devices. In some embodiments, dielectric fill 108 comprises silicon oxide, although other oxides or dielectrics may also be used. Dielectric fill 108 may first be deposited to at least the same height as the fin, and then recessed backward to the final height shown using any known controlled etching process. According to some embodiments, each fin includes a sub-fin portion 110 between the exposed fin 207 and the dielectric fill 108. Sub-fin portion 110 may comprise the same material as semiconductor substrate 106 and may be an integral part of semiconductor substrate 106, which will extend below dielectric fill 108. After the formation of dielectric fill 108, the exposed fin 207 extending over the top surface of dielectric layer 108 may have a height between approximately 50 nm and approximately 200 nm. The width of the fin can be, for example, in the range of about 5 to about 15 nm, such as 6 nm wide.

[0039] FIG2D illustrates a cross-sectional view of the structure shown in FIG2C after the helmet structure 208 has been formed above the fin according to an embodiment of the present invention. According to some embodiments, the helmet structure 208 comprises a dielectric material and is deposited using a PVD process such as sputtering, although other suitable deposition techniques, such as CVD, can be used for selective deposition on the top of the fin, where reactant species are available on the top surface of the fin where growth is desired. In some embodiments, the helmet structure 208 comprises a metal oxide to provide high etch selectivity with the underlying fin material. PVD or other selective deposition techniques are used to maximize deposition of the helmet structure 208 on the top surface of the fin while minimizing deposition between fins and along the sidewalls of the fin. In some embodiments, the helmet structure 208 has rounded edges, creating a curved top surface instead of the flat top surface illustrated, which may also manifest as curved sidewalls. The helmet structure 208 can be deposited to any desired thickness, as long as the deposition does not result in the helmet structure 208 being deposited substantially along any portion of the sidewalls of the fin. In some example embodiments, the helmet structure 208 has a thickness between approximately 5 nm and approximately 50 nm.

[0040] FIG. 2E illustrates a cross-sectional view of the structure shown in FIG. 2D according to an embodiment of the present invention after an etching process to trim the width of the fins of one of the semiconductor devices. Masking material 210 is deposited and patterned to cover one or more fins, such as the fins of semiconductor device 104. In some embodiments, masking material 210 is patterned to cover one or more n-channel semiconductor devices while simultaneously exposing one or more p-channel semiconductor devices. Masking material 210 may be a photoresist or a hard masking material, such as a carbon hard mask.

[0041] According to some embodiments, a lateral etching process is performed on exposed fins (e.g., exposed fin 207 of semiconductor device 102) to reduce the width of alternating material layers in the fin. In one example, an isotropic wet or dry etching process provides similar etching rates for semiconductor layer 204 and sacrificial layer 202. Since the top surface of the fin is protected by the helmet structure 208, the sides of the fin are etched laterally inward while maintaining the thickness of the top material layer. In some embodiments, the final width w2 of the laterally etched fin is at least 25%, at least 50%, at least 60%, or at least 75% smaller than the width w1 of the unetched fin. Similarly, the final width w2 of the laterally etched fin may be at least 25%, at least 50%, at least 60%, or at least 75% smaller than the width w1 of the sub-fin 110 below the laterally etched fin. As described above, the width w1 may be between approximately 5 nm and approximately 8 nm, and the width w2 may be between approximately 2 nm and approximately 4 nm.

[0042] In some embodiments, the isotropic etching process used for laterally etching both the semiconductor layer 204 and the sacrificial layer 202 may also etch one or more portions of the sub-fin 110 below the laterally etched fin. This occurs when the lowest material layer in the exposed fin 207 of the semiconductor device 102 is etched back to expose the sub-fin 110 to the same etchant. If the sub-fin 110 comprises a material composition similar to that of the semiconductor layer 204 or the sacrificial layer 202, a portion of it may also be etched. This is shown in the burst portion focused on the corner of the sub-fin 110, where the material around the corner has been removed to form an inwardly curved surface.

[0043] FIG2F illustrates a cross-sectional view of the structure shown in FIG2E after the removal of the masking material 210 and the helmet structure 208 according to an embodiment of the present invention. The masking material 210 can be removed using any standard ashing process. The helmet structure 208 can be removed using any wet or dry etching technique that selectively etches the material of the helmet structure 208 while providing minimal etching to the fins or dielectric filler 108.

[0044] At this stage, subsequent processes are performed to form the remaining GAA transistor structure, ultimately producing the structure shown in FIG2G. In short, these remaining processes include forming source and drain regions for each semiconductor device 102 and 104, removing the sacrificial layer 202 to form suspended nanobands 112a / 112b, forming a gate dielectric 114 around the nanobands 112a / 112b, and forming a gate structure 116. The results of many of these processes are not visible in the cross-sections shown, as illustrated in FIG3A-3H, which include planar views that collectively illustrate an example process for forming the GAA transistor structure of semiconductor devices 102 and 104 according to an embodiment of the invention.

[0045] FIG3A illustrates a plan view of semiconductor devices 102 and 104 from FIG2F according to an embodiment of the present invention. Each fin extends parallel to each other, and a top semiconductor layer 204 is visible on each fin. Note that the top layer of the material stack in any fin may also be a sacrificial layer 202. Dielectric filler 108 is visible on either side of each fin. According to some embodiments, due to the lateral etching process described with reference to FIG2E, the fins of semiconductor device 102 are narrower than the fins of semiconductor device 104. Therefore, portions of sub-fins 110 may be visible on either side of the fins of semiconductor device 102.

[0046] FIG3B illustrates a plan view of the structure shown in FIG3A after the deposition of the sacrificial gate 302 according to an embodiment of the present invention. The sacrificial gate 302 may extend in a direction orthogonal to each fin and may include any material that can be safely removed later in the process without etching or otherwise damaging any portion of the fins or sidewall spacers formed in the next step. In some embodiments, the sacrificial gate 302 includes a capping layer (not shown) for defining the pattern of the sacrificial gate 302 during a reactive ion etching (RIE) process. In some examples, the capping layer comprises silicon nitride, while the sacrificial gate 302 comprises polycrystalline silicon. The capping layer may be removed after the location of the sacrificial gate 302 has been patterned.

[0047] FIG. 3C illustrates a plan view of the structure shown in FIG. 3B after the spacer structure 304 is formed on either side of the sacrificial gate 302 according to an embodiment of the present invention. The spacer structure 304 can be formed using an etch-back process, wherein spacer material is deposited at various locations, followed by anisotropic etching to leave material only on the sidewalls of the structure. The spacer structure 304 may include dielectric materials, such as silicon nitride, silicon oxynitride, or any formulation of those layers doped with carbon or boron dopants.

[0048] FIG. 3D illustrates a plan view of the structure shown in FIG. 3C after removing the exposed fin portions not covered by the sacrificial gate 302 and spacer structure 304, according to an embodiment of the present invention. The exposed fin portions can be removed using a RIE process to selectively etch the semiconductor material through both the semiconductor layer 204 and the sacrificial layer 202. According to some embodiments, the removal of the fins exposes part (or all) of the top surface of the sub-fins 110 of the semiconductor devices 102 and 104. It should be noted that the narrower fins of the semiconductor device 102 remain and are protected under the sacrificial gate 302 and spacer structure 304.

[0049] FIG. 3E illustrates a plan view of the structure shown in FIG. 3D after forming a source or drain region 306 for each of semiconductor devices 102 and 104 according to an embodiment of the present invention. In some examples, the source or drain region 306 is epitaxially grown over an exposed sub-fin 110. Any semiconductor material suitable for the source or drain region 306 (e.g., group IV and group III-V semiconductor materials) can be used. The source or drain region 306 may include multiple layers, such as pads and capping layers, to improve contact resistance. In any such case, the composition and doping of the source or drain region 306 may be the same or different, depending on the polarity of the transistor. In one example, semiconductor device 102 is a p-type MOS (PMOS) transistor having a source or drain region 306 including a high concentration of p-type dopant, and semiconductor device 104 is an n-type MOS (NMOS) transistor having a source or drain region 306 including a high concentration of n-type dopant. Any number of source and drain configurations and materials can be used.

[0050] FIG3F illustrates a plan view of the structure shown in FIG3E after removal of the sacrificial gate 302 according to an embodiment of the present invention. The sacrificial gate 302 can be removed using any wet or dry isotropic process, thereby exposing portions of the fins beneath the sacrificial gate 302. Alternating layer stacks of each fin are exposed within the trenches left after removal of the sacrificial gate 302. At this stage, although not seen in the figures, the sacrificial layer 202 within each fin is removed using a selective isotropic etching process that removes material from the sacrificial layer 202 but does not remove (or removes very little) the layer of semiconductor layer 204. At this time, the suspended semiconductor layer 204 forms nanoribbons or nanowires extending between the source or drain regions 306 in each of the semiconductor devices 102 and 104.

[0051] FIG. 3G illustrates a plan view of the structure shown in FIG. 3F after the formation of the gate dielectric 114 according to an embodiment of the present invention. The gate dielectric 114 may include any suitable dielectric (e.g., silicon dioxide and / or high-k dielectric materials). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 114 is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 114 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric 114 may be a multilayer structure. For example, gate dielectric 114 may include a first layer on semiconductor layer 204 and a second layer on the first layer. The first layer may be, for example, an oxide (e.g., silicon dioxide) of semiconductor layer 204 and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, an annealing process may be performed on gate dielectric 114 to improve its quality when using high-k dielectric materials. In some embodiments, the high-k material may be nitrided to improve its aging resistance.

[0052] In the example shown, the gate dielectric 114 is shown on the semiconductor layer 204, but it may also be present along the inner sidewall of the spacer structure 304 and the top surface of the filling dielectric 108. In addition, the gate dielectric 114 may be formed over any exposed portion of the sub-fins 110 of the semiconductor device 102 and / or the semiconductor device 104.

[0053] FIG3H illustrates a plan view of the structure shown in FIG3G after forming a gate structure 116 in the trenches between spacer structures 304 according to an embodiment of the present invention. The gate structure 116 can be any standard or proprietary gate structure and can include any number of gate cutouts. In some embodiments, the gate structure 116 includes doped polysilicon, metal, or metal alloy. Examples of suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate structure 116 may include, for example, one or more work function layers, resistance-reducing layers, and / or barrier layers. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., aluminum titanium carbide) for an NMOS gate.

[0054] FIG4 illustrates an example embodiment of a wafer package 400 according to an embodiment of the present invention. As can be seen, the wafer package 400 includes one or more dies 402. The one or more dies 402 may include at least one integrated circuit having a semiconductor device, such as any semiconductor device disclosed herein. In some example configurations, the one or more dies 402 may include any other circuitry for interfacing with other devices formed on the die or connected to other devices of the wafer package 400.

[0055] As can be further seen, the wafer package 400 includes a housing 404 bonded to a package substrate 406. The housing 404 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the wafer package 400. One or more dies 402 can be conductively coupled to the package substrate 406 using connections 408, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball gate arrays (BGAs), pins, or wire bonding, to name just a few. The package substrate 406 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between or at different locations on each face of the package substrate 406. In some embodiments, the package substrate 406 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 412 may be disposed on opposite surfaces of the package substrate 406 for conductive contact, such as a printed circuit board (PCB). One or more vias 410 extend through the thickness of the package substrate 406 to provide conductive pathways between one or more connections 408 to the one or more contacts 412. For ease of illustration, the vias 410 are shown as a single straight line through the package substrate 406, although other configurations may be used (e.g., damascene, dual damascene, through-silicon vias, or meandering through the thickness of the substrate 406 to contact one or more intermediate interconnect structures therein). In yet another embodiment, the vias 410 are made of a plurality of smaller stacked vias, or staggered at different locations on the package substrate 406. In the illustrated embodiment, the contacts 412 are solder balls (e.g., for bump-based connections or ball gate array configurations), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array configuration or ground in a ground grid array configuration). In some embodiments, solder resist is disposed between the contacts 412 to suppress short circuits.

[0056] In some embodiments, mold material 414 may be disposed around one or more dies 402 included within housing 404 (e.g., as underfill material between die 402 and packaging substrate 406, and as overfill material between die 402 and housing 404). Although the size and quality of mold material 414 may vary from embodiment to embodiment, in some embodiments, the thickness of mold material 414 is less than 1 mm. Example materials that can be used for mold material 414 include suitable epoxy mold materials. In some cases, mold material 414 has thermal conductivity in addition to electrical insulation. Method

[0057] Figure 5 is a flowchart of a method 500 for forming at least a portion of an integrated circuit according to an embodiment. Various operations of method 500 can be shown in Figures 2A-2G. However, the relevance of the various operations of method 500 to the specific components shown in the above figures is not intended to imply any structural and / or usage limitations. Rather, the above figures provide an example embodiment of method 500. Other operations may be performed before, during, or after any operation of method 500. For example, method 500 is not explicitly described as a series of steps performed to form a common transistor structure. Some operations of method 500 may be performed in a different order than those shown.

[0058] Method 500 begins at operation 502, wherein at least first and second multilayer fins are formed. The multilayer fins may include alternating sacrificial layers and semiconductor layers on a substrate. The thickness of each semiconductor layer and sacrificial layer may be between about 5 nm and about 25 nm. Each of the sacrificial and semiconductor layers may be deposited using any known material deposition technique, such as CVD, PECVD, PVD, or ALD. Once the material layers are deposited, a patterned masking material may be used to define the fins to protect them from etching via an anisotropic etching process (e.g., RIE). The fin height may include alternating material layers and sub-fin portions formed from the substrate material. While the dimensions may vary depending on the example embodiment, the total height of the fins extending above the substrate surface may range from about 100 nm to about 250 nm. The fin width may, for example, range from about 5 to about 15 nm, such as 6 nm wide.

[0059] Method 500 continues to operation 504, wherein a helmet structure is formed on the first and second fins. The helmet structure may include a dielectric material (e.g., silicon nitride) and can be deposited using a PVD process such as sputtering, although other suitable deposition techniques, such as CVD, which allow selective deposition of material on the top of the fin, may be used, where reactant species are available on the top surface of the fin to be grown. In some embodiments, the helmet structure includes a metal oxide to provide high etch selectivity with the underlying fin material. In some embodiments, the helmet structure has rounded edges, creating a curved top surface instead of the flat top surface illustrated, which may also manifest as curved sidewalls. In some example embodiments, the helmet structure has a thickness between approximately 5 nm and approximately 50 nm.

[0060] Method 500 continues to operation 506, wherein a masking layer is used to mask the second fin while exposing the first fin. The masking layer may be patterned to cover one or more n-channel semiconductor devices while simultaneously exposing one or more p-channel semiconductor devices. Thus, in this example, the first fin may include a semiconductor material having n-type dopant and the second fin may include a semiconductor material having p-type dopant. The masking layer may be a photoresist or a hard masking material, such as a carbon hard mask.

[0061] Method 500 continues to operation 508, wherein the exposed first fin is laterally etched to reduce the width of the first fin. In one example, an isotropic wet or dry etching process provides a similar etching rate for each alternating material layer in the first fin. Since the top surface of the fin is protected by a helmet structure, the sides of the fin are etched laterally inward while maintaining the thickness of the top material layer. In some embodiments, the final width of the laterally etched first fin is at least 25%, at least 50%, at least 60%, or at least 75% smaller than the width of the second fin protected by the masking layer. In some embodiments, the width of the second fin may be between approximately 5 nm and approximately 8 nm, and the width of the first fin may be between approximately 2 nm and approximately 4 nm. In some embodiments, the isotropic etching process for laterally etching the first fin may also etch one or more portions of a sub-fin below the laterally etched first fin.

[0062] Method 500 continues with operation 510, wherein remaining transistor structures are formed to complete the formation of the first and second semiconductor devices from the first and second fins, respectively. These remaining processes involve forming source and drain regions for each semiconductor device, removing the sacrificial material layer within each fin to form a suspended semiconductor nanoribbon, forming a gate dielectric around the nanoribbon, and forming a gate structure or gate structure around the nanoribbon. The results of many of these processes are shown in Figures 3A-3H, including plan views that collectively illustrate exemplary processes for forming the GAA transistor structures of the two semiconductor devices 102 and 104. Example System

[0063] FIG6 is an example computing system implemented using one or more integrated circuit structures as disclosed herein, according to some embodiments of the present invention. It can be seen that the computing system 600 houses a motherboard 602. The motherboard 602 may include multiple components, including but not limited to a processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to the motherboard 602 or otherwise integrated therein. As will be understood, the motherboard 602 may be, for example, any printed circuit board (PCB), whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 600, etc.

[0064] Depending on its application, the computing system 600 may include one or more other components that may be physically and electrically coupled to the motherboard 602 or not physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processor, digital signal processor, encryption processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital versatile discs (DVDs), etc.). Any components included in the computing system 600 may include one or more integrated circuit structures or devices configured according to example embodiments (e.g., a module including integrated circuit devices on a substrate having one or more first semiconductor devices having nanobands of a first width and one or more second semiconductor devices having nanobands of a second width less than the first width, as provided herein differently). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 606 may be part of or otherwise integrated into the processor 604).

[0065] Communication chip 606 implements wireless communication for transmitting data to and from computing system 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated device does not contain any wires, although they may not in some embodiments. Communication chip 606 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and above. Computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, while the second communication chip 606 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0066] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the processor's integrated circuit die includes onboard circuitry implemented using one or more semiconductor devices as described herein. The term "processor" may mean any device or part of a device that processes, for example, electronic data from a register and / or memory to convert that electronic data into other electronic data that can be stored in the register and / or memory.

[0067] The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described differently herein. As will be understood according to the invention, note that multi-standard wireless capabilities can be directly integrated into the processor 604 (e.g., the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). Further note that the processor 604 may be a chipset having such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 can be used. Similarly, any chip or chipset can have multiple functions integrated therein.

[0068] In various embodiments, the computing system 600 may be a laptop, a lightweight laptop, a notebook computer, a smartphone, a tablet computer, a personal digital assistant (PDA), a supercomputer, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as described herein.

[0069] It should be understood that in some embodiments, various components of the computing system 600 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further example embodiments

[0070] The following examples relate to further embodiments, from which many permutations and configurations will be apparent.

[0071] Example 1 is an integrated circuit including a first semiconductor device having a first semiconductor nanoribbon extending between a first source region and a first drain region, and a second semiconductor device having a second semiconductor nanoribbon extending between a second source region and a second drain region. The first semiconductor nanoribbon has a first length and a first width, and the second semiconductor nanoribbon has a second length and a second width smaller than the first width. The length of the semiconductor nanoribbon corresponds to a first distance between corresponding source and drain regions. The width of the semiconductor nanoribbon corresponds to a second distance between the sidewalls of the corresponding nanoribbon. The second distance extends in a horizontal direction orthogonal to the horizontal direction extending the first distance.

[0072] Example 2 includes the object of Example 1, wherein the first semiconductor device includes a first sub-fin below the first semiconductor nanoband, and the second semiconductor device includes a second sub-fin below the second semiconductor nanoband, wherein both the first sub-fin and the second sub-fin have a first width.

[0073] Example 3 includes the object of Example 1 or 2, wherein the first semiconductor device includes a first sub-fin below the first semiconductor nanoband, and the second semiconductor device includes a second sub-fin below the second semiconductor nanoband, wherein the first and second sub-fins each include a tapered profile, and wherein the sidewall of the first sub-fin is collinear with the sidewalls of the first semiconductor nanoband, and the sidewall of the second sub-fin is not collinear with the sidewalls of the second semiconductor nanoband.

[0074] Example 4 includes the subject of any one of Examples 1 to 3, wherein the first semiconductor device includes a first sub-fin below the first semiconductor nanoband, and the second semiconductor device includes a second sub-fin below the second semiconductor nanoband, and wherein the upper edge of the second sub-fin is more tapered or angled than the upper edge of the first sub-fin.

[0075] Example 5 includes the object of any one of Examples 1 to 4, wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.

[0076] Example 6 includes the object of any one of Examples 1 to 5, wherein the second width is at least 50% smaller than the first width.

[0077] Example 7 includes the subject matter of any one of Examples 1 to 6, wherein the first semiconductor nanoband and the second semiconductor nanoband comprise germanium, silicon, or a combination thereof.

[0078] Example 8 includes the subject of any one of Examples 1 to 7, wherein the imaginary horizontal plane passes at least partially through each of the first and second semiconductor nanobands.

[0079] Example 9 is a printed circuit board that includes any one of Examples 1 to 8.

[0080] Example 10 is an electronic device including a wafer package comprising one or more dies. At least one of the one or more dies includes a first semiconductor device and a second semiconductor device. The first semiconductor device has a first semiconductor material body extending between a first source region and a first drain region, and has a first sub-fin below the first semiconductor material body. The second semiconductor device has a second semiconductor material body extending between a second source region and a second drain region, and has a second sub-fin below the second semiconductor material body. The first semiconductor material body has a first width substantially the same as the width of the first sub-fin, and the second semiconductor material body has a second width smaller than the width of the second sub-fin and smaller than the first width.

[0081] Example 11 includes the object of Example 10, wherein the first fin and the second fin both have substantially the same width.

[0082] Example 12 includes the object of Example 10 or 11, wherein the first and second sub-fins each include a tapered profile, and wherein the sidewall of the first sub-fin is collinear with the sidewalls of the first semiconductor material body, and the sidewall of the second sub-fin is not collinear with the sidewalls of the second semiconductor material body.

[0083] Example 13 includes the object of any one of Examples 10 to 12, wherein the upper edge of the second fin is more tapered or angled than the upper edge of the first fin.

[0084] Example 14 includes the object of any one of Examples 10 to 13, wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.

[0085] Example 15 includes the object of any one of Examples 10 to 14, wherein the second width is at least 50% smaller than the first width.

[0086] Example 16 includes the subject matter of any one of Examples 10 to 15, wherein the first semiconductor material body and the second semiconductor material body comprise germanium, silicon, or a combination thereof.

[0087] Example 17 includes the subject of any one of Examples 10 to 16, wherein the imaginary horizontal plane passes at least partially through each of the first and second semiconductor material bodies.

[0088] Example 18 includes the subject matter of any one of Examples 10 to 17, and further includes a printed circuit board, wherein the chip package is attached to the printed circuit board.

[0089] Example 19 is a method of forming an integrated circuit. The method includes forming a first multilayer fin and a second multilayer fin, each of the first and second multilayer fins comprising first and second material layers, wherein the second material layer comprises a semiconductor material suitable for use as a nanoband channel; forming a helmet structure on the top surface of the first multilayer fin and the second multilayer fin; shielding the second multilayer fin while exposing the first multilayer fin; and performing a lateral etching process on the sidewalls of the first multilayer fin to reduce the width of the first multilayer fin.

[0090] Example 20 includes the object of Example 19, wherein forming the first multilayer fin and the second multilayer fin includes recessing the dielectric layer between the first multilayer fin and the second multilayer fin, such that the first and second multilayer fins extend over the top surface of the dielectric layer.

[0091] Example 21 includes the object of Example 20, wherein a first semiconductor sub-fin is located below the first multilayer fin and in the dielectric layer, and a second semiconductor sub-fin is located below the second multilayer fin and in the dielectric layer, and wherein the lateral etching process further etches a portion of the first semiconductor sub-fin.

[0092] Example 22 includes the object of any one of Examples 19 to 21, wherein forming the helmet structure includes forming the helmet structure through a sputtering process.

[0093] Example 23 includes the object of any one of Examples 19 to 22, wherein the first material layer comprises silicon and germanium and the second material layer comprises silicon.

[0094] Example 24 includes the object of any one of Examples 19 to 23, and further includes removing the first material layer from the first multilayer fin and removing the first material layer from the second multilayer fin.

[0095] Example 25 includes the object of any one of Examples 19 to 24, wherein the mask comprises a carbon hard mask formed above the second multilayer fin.

[0096] Example 26 includes the subject of any one of Examples 19 to 25, wherein performing the lateral etching process comprises using an etching process having substantially the same etching rate through each of the first material layer and the second material layer.

[0097] Example 27 includes the object of any one of Examples 19 to 26, and further includes the second material layer of the first multilayer fin doped with a p-type dopant and the second material layer of the second multilayer fin doped with an n-type dopant.

[0098] The foregoing description of embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible according to the invention. The purpose is that the scope of the invention is not limited by this detailed description, but rather by the scope of the appended claims. [Simplified Explanation of the Diagram]

[0004] [Figures 1A and 1B] are cross-sectional views illustrating an example integrated circuit with a semiconductor device according to an embodiment of the present invention, the semiconductor device having a thinned semiconductor region.

[0005] [Figures 2A to 2G] are cross-sectional views illustrating an example process for forming a semiconductor device having thinned semiconductor regions according to embodiments of the present invention.

[0006] [Figures 3A to 3H] are plan views illustrating various stages in an example process for forming a transistor structure for a semiconductor device according to an embodiment of the present invention.

[0007] [Figure 4] illustrates a cross-sectional view of a wafer package comprising one or more semiconductor dies according to some embodiments of the present invention.

[0008] [Figure 5] is a flowchart of a process for manufacturing a semiconductor device having a thinned semiconductor region according to an embodiment of the present invention.

[0009] [Figure 6] illustrates a computing system comprising one or more integrated circuits according to an embodiment of the present invention, as described in different ways herein.

[0010] Although the following detailed description will be given with reference to illustrative embodiments, many alternatives, modifications, and variations will be apparent from the invention. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the invention to the specific configurations shown. For example, while some drawings typically represent perfect straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have imperfect straight lines and right angles, and some features may have surface topologies or be otherwise non-smooth, taking into account the limitations of the actual fabrication apparatus and techniques used.

Claims

1. An integrated circuit comprising: a first semiconductor device having a first semiconductor nanoribbon or nanowire extending between a first source region and a first drain region, and a first sub-fin below the first semiconductor nanoribbon or nanowire and having a first width, the first semiconductor nanoribbon or nanowire having a first length and a first width; and a second semiconductor device having a second semiconductor nanoribbon or nanowire extending between a second source region and a second drain region, and a second sub-fin below the second semiconductor nanoribbon or nanowire and having the first width, the second semiconductor nanoribbon or nanowire having a second length and a second width less than the first width, wherein... The length of the semiconductor nanoband or nanoline corresponds to a first distance between the corresponding source and drain regions, and the width of the semiconductor nanoband or nanoline corresponds to a second distance between the sidewalls of the corresponding nanoband or nanoline, the second distance extending in a horizontal direction orthogonal to the horizontal direction extending the first distance.

2. As in request item 1, the integrated circuit, wherein, The second fin has an inwardly curved top surface between the first portion of the second fin having the second width and the second portion of the second fin having the first width.

3. As in request item 1, the integrated circuit, wherein, The first and second sub-fins each include a tapered profile, wherein the sidewall of the first sub-fin is collinear with the sidewalls of the first semiconductor nanoband or nanowire, and the sidewall of the second sub-fin is not collinear with the sidewalls of the second semiconductor nanoband or nanowire.

4. As in request item 1, the integrated circuit, wherein, The upper edge of the second fin is more tapered or angled than the upper edge of the first fin.

5. As in request item 1, the integrated circuit, wherein, The first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.

6. An integrated circuit as described in any of requests 1 to 5, wherein, The second width is at least 50% smaller than the first width.

7. An integrated circuit as described in any of requests 1 to 5, wherein, The first semiconductor nanoribbon or nanowire and the second semiconductor nanoribbon or nanowire include germanium, silicon, or combinations thereof.

8. An integrated circuit as described in any of requests 1 to 5, wherein, An imaginary horizontal plane passes at least partially through each of the first and second semiconductor nanoribbons or nanowires.

9. A die comprising an integrated circuit according to any one of claims 1 to 5.

10. An electronic device comprising: a wafer package including one or more dies, at least one of the one or more dies comprising: a first semiconductor device having a first semiconductor material body extending between a first source region and a first drain region, and having a first sub-fin below the first semiconductor material body, the first semiconductor material body having a first width substantially the same as the width of the first sub-fin; and a second semiconductor device having a second semiconductor material body extending between a second source region and a second drain region, and having a second sub-fin below the second semiconductor material body, the second semiconductor material body having a second width smaller than the width of the second sub-fin and smaller than the first width, wherein... The first semiconductor material body is a first semiconductor nanoribbon or nanowire, and the second semiconductor material body is a second semiconductor nanoribbon or nanowire.

11. The electronic device as claimed in claim 10, wherein, Both the first and second fins have substantially the same width.

12. The electronic device as claimed in claim 10, wherein, The first and second sub-fins each include a tapered profile, wherein the sidewall of the first sub-fin is collinear with the sidewalls of the first semiconductor material body, and the sidewall of the second sub-fin is not collinear with the sidewalls of the second semiconductor material body.

13. The electronic device as claimed in claim 10, wherein, The upper edge of the second fin is more tapered or angled than the upper edge of the first fin.

14. The electronic device as claimed in claim 10, wherein, The first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.

15. The electronic device as claimed in claim 10, wherein, The second width is at least 50% smaller than the first width.

16. The electronic device of claim 10, wherein the first semiconductor material body and the second semiconductor material body comprise germanium, silicon, or a combination thereof.

17. An electronic device as described in any of claims 10 to 16, wherein, An imaginary horizontal plane passes at least partially through each of the first and second semiconductor material bodies.

18. The electronic device according to any one of claims 10 to 16 further comprises a printed circuit board, wherein, The chip package is attached to the printed circuit board.

19. A method of forming an integrated circuit, comprising: forming a first multilayer fin and a second multilayer fin, each of the first and second multilayer fins comprising first and second material layers, wherein, The second material layer contains a semiconductor material suitable for use as a nanoband channel; a helmet structure is formed on the top surface of the first multilayer fin and the second multilayer fin; the second multilayer fin is shielded while the first multilayer fin is exposed; and a lateral etching process is performed on the sidewalls of the first multilayer fin to reduce the width of the first multilayer fin.

20. As in request item 19, wherein, Forming the first multilayer fin and the second multilayer fin involves recessing the dielectric layer between the first multilayer fin and the second multilayer fin, such that the first and second multilayer fins extend above the top surface of the dielectric layer.

21. As in request item 20, wherein, A first semiconductor sub-fin is located below the first multilayer fin and within the dielectric layer, and a second semiconductor sub-fin is located below the second multilayer fin and within the dielectric layer, wherein the lateral etching process further etches a portion of the first semiconductor sub-fin.

22. As in request item 19, wherein, The formation of the helmet structure includes forming the helmet structure through a sputtering process.

23. The method of any one of claims 19 to 22, further comprising removing the first material layer from the first multilayer fin and removing the first material layer from the second multilayer fin, wherein, The mask is contained within a carbon hard mask formed above the second multi-layer fin.

24. The method of any one of claims 19 to 22, wherein, Performing this lateral etching process involves using an etching process with substantially the same etching rate through each of the first and second material layers.

25. The method of any one of claims 19 to 22 further comprises doping the second material layer of the first multilayer fin with a p-type dopant and doping the second material layer of the second multilayer fin with an n-type dopant.

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