Transistor device and method of forming the same

Abstract

A transistor device is provided. The transistor device includes a substrate. The transistor device includes a lower transistor located on the substrate, the lower transistor having a lower gate and a lower channel region. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is located between the upper transistor and the substrate. The transistor device includes an isolation region separating the lower channel region of the lower transistor from the upper channel region of the upper transistor. Furthermore, the lower gate of the lower transistor contacts the upper gate of the upper transistor. A method for forming the transistor device is also provided.

Description

Multiple stacked transistors having isolation regions and common gate electrodes and related manufacturing methods This disclosure generally relates to the field of semiconductor devices, and more particularly, to three-dimensional transistor structures. The density of transistors in electronic devices continues to increase. Although three-dimensional transistor structures can help increase transistor density, they may experience electrical vulnerabilities such as parasitic capacitance. For example, the parasitic capacitance between the contact metal and the gate metal of a three-dimensional transistor structure may reduce device performance. In addition, it may be difficult to form inner spacers for three-dimensional transistor structures. Also, the deposition and removal of gate metal for three-dimensional transistor structures may be complex and difficult to control. According to some embodiments herein, a transistor device may include a substrate. The transistor device may include a lower transistor located on the substrate, the lower transistor having a lower gate and a lower channel region. The transistor device may include an upper transistor having an upper gate and an upper channel region. The lower transistor may be located between the upper transistor and the substrate. The transistor device includes an isolation region that may separate the lower channel region of the lower transistor from the upper channel region of the upper transistor. In addition, the lower gate of the lower transistor may contact the upper gate of the upper transistor. According to some embodiments, a transistor device may include a lower nanosheet transistor having a lower nanosheet stack and a lower gate located on the lower nanosheet stack. The transistor device may include an upper nanosheet transistor located on top of the lower nanosheet transistor. The upper nanosheet transistor may include an upper nanosheet stack and an upper gate located on the upper nanosheet stack. The transistor device may include an isolation region that separates the lower nanosheet stack from the upper nanosheet stack. In addition, the lower gate of the lower nanosheet transistor may contact the upper gate of the upper nanosheet transistor. According to some embodiments, a method of forming a transistor device may include forming a preliminary transistor stack including a lower channel layer, an upper channel layer, and a sacrificial layer that separates the lower channel layer from the upper channel layer. The method may include forming an insulating spacer between the lower channel layer and the upper channel layer. The method may include removing the sacrificial layer. The method may include forming an isolation layer in the opening formed by removing the sacrificial layer. The method may include forming a lower gate on the lower channel layer below the isolation layer and an upper gate on the upper channel layer above the isolation layer. In addition, the upper gate may contact the lower gate. According to an embodiment of the present invention, a transistor device is provided. The transistor device includes a common gate and an isolation region that separates a lower channel region of a lower transistor from an upper channel region of an upper transistor. Since the boundary between the upper transistor and the lower transistor is not defined, forming an inner spacer for a three-dimensional transistor structure may have process restrictions. For example, the inner spacer may have an incomplete pinchoff (e.g., removal / separation) between the upper transistor and the lower transistor. Also, the deposition and removal of gate metal located between the upper device and the lower device may be restricted by the vertical space and gate length between the upper device and the lower device, and these processes may be complex and difficult to control. However, the transistor device and the method of forming the transistor device according to an embodiment of the present invention can solve these problems by forming a sacrificial layer that defines the boundary between the upper transistor and the lower transistor. The defined boundary provided by the sacrificial layer can improve the control of the subsequent formation of the inner spacer. In addition, the sacrificial layer is subsequently replaced with an isolation layer that is part of the isolation region inside the common gate of the upper transistor and the lower transistor. Forming the isolation layer inside the region where the common gate will be formed helps to control the amount and position of the gate metal formed in the region. Exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Figures 1A through 1D provide views of a transistor device observed along different axes according to various embodiments. Figure 1A is a plan view of a nanosheet transistor device 100 according to some embodiments of the present invention. Device 100 includes a first transistor stack 110-1 and a second transistor stack 110-2. For the sake of illustration simplicity, only two transistor stacks 110 are shown in Figure 1A. However, in some embodiments, device 100 may include three transistor stacks 110, four transistor stacks 110, or more transistor stacks 110. For example, the two transistor stacks 110-1, 110-2 may be a pair of transistor stacks 110 that are closer to each other than any other transistor stack 110 in device 100. The first transistor stack 110-1 includes a first nanosheet stack 120-1, which is located between a pair of source / drain regions 150-1 in a first horizontal direction X. The first nanosheet stack 120-1 includes an upper nanosheet NS-U and a lower nanosheet NS-L (FIG. 1B), and an upper gate G-U and a lower gate G-L (FIG. 1B) located on the nanosheets NS. Although the nanosheets NS can contact the source / drain regions 150-1, the gates G-U and G-L can be spaced apart from the source / drain regions 150-1 in the direction X by an upper insulating spacer IS-U and a lower insulating spacer IS-L (FIG. 1C), which can be referred to herein as "inner spacers". Each source / drain region 150-1 can have a corresponding source / drain contact 140-1 adjacent to it in a second horizontal direction Y, which can be perpendicular to the direction X. Thus, a pair of source / drain contacts 140-1 can be on opposite sides of the first nanosheet stack 120-1. Each source / drain contact 140-1 can comprise, for example, metal. To reduce the parasitic capacitance with the source / drain contacts 140-1, an insulating region 160 of the transistor stack 110-1 is provided adjacent to the source / drain contacts 140-1 (e.g., aligned / overlapped with the source / drain contacts 140-1 in the direction X). The region 160 can also reduce the parasitic capacitance with the two source / drain regions 150-1. Similarly, a second nanosheet stack 120-2 of the second transistor stack 110-2 is located between a pair of source / drain regions 150-2, and the transistor stack 110-2 has an insulating region 160 adjacent to the source / drain contacts 140-2. FIG. 1B is a cross-sectional view of the first transistor stack 110-1 of the nanosheet transistor device 100 shown in FIG. 1A taken along the direction Y. As shown in FIG. 1B, the nanosheet stack 120-1 of the first transistor stack 110-1 includes a plurality of lower nanosheets NS-L of a lower transistor T-L and a plurality of upper nanosheets NS-U of an upper transistor T-U. The upper nanosheets NS-U overlap the lower nanosheets NS-L in a vertical direction Z perpendicular to the horizontal direction X and the horizontal direction Y. The lower transistor T-L further includes a lower gate G-L located on the lower nanosheet NS-L. In the cross-sectional view shown in FIG. 1B, the lower gate G-L is shown to be located on four sides of each of the lower nanosheets NS-L. On the other hand, the upper transistor T-U further includes an upper gate G-U, which is located on three sides of each of the upper nanosheets NS-U in the cross-sectional view shown in FIG. 1B, and an insulating region 160 is provided on the fourth side of each of the upper nanosheets NS-U. Therefore, the transistors T-L and T-U shown in FIG. 1B are a gate-all-around (GAA) transistor GA and a tri-gate nanosheet transistor TG, respectively. The insulating region 160 may contact the corresponding sidewalls of the upper nanosheet NS-U and may overlap with the lower nanosheet NS-L in the vertical direction. The insulating region 160 may include, for example, silicon nitride or silicon oxide. In some embodiments, the insulating region 160 may include a low-k spacer, which may better reduce capacitance than a higher-k insulator. As used herein, the term "low-k" refers to a material having a dielectric constant less than that of silicon dioxide. The isolation region IL separates the lower nanosheet NS-L from the upper nanosheet NS-U. The isolation region IL may include, for example, an oxide material. The insulating region 160 may be located on the upper surface of the isolation region IL. As an example, the length of the isolation region IL in the direction Y may be equal to the combined length of the upper nanosheet NS-U and the insulating region 160 in the direction Y and / or equal to the length of the lower nanosheet NS-L in the direction Y. In some embodiments, the upper gate G-U may be located on the opposite sidewalls of the isolation region IL. The isolation region IL may thus be located inside the upper gate G-U. In other embodiments, the isolation region IL may be located inside the lower gate G-L. In some embodiments, the isolation region IL may be located between the upper gate G-U and the lower gate G-L. The gates G-L and G-U may contact each other and may thus jointly provide a common gate electrode shared by the transistors T-L and T-U. For example, FIG. 1B shows that the lower surface of the upper gate G-U may contact the upper surface of the lower gate G-L. Additionally, in some embodiments, each transistor stack 110 (FIG. 1A) may be a complementary field-effect transistor (CFET) stack, where the lower transistor T-L and the upper transistor T-U are an N-type transistor and a P-type transistor, respectively, or vice versa. Therefore, the gates G-L and G-U may include different corresponding metals. As an example, the different metals may have different corresponding work functions. Although transistors T-L and T-U are shown as nanosheet transistors in FIG. 1B, in some embodiments, at least one of transistors T-L and T-U can be a vertical field-effect transistor (“VFET”) or a fin field-effect transistor (“FinFET”). For example, the lower transistor T-L can be a nanosheet transistor as shown in FIG. 1B, while the upper transistor T-U can be a VFET or a FinFET that can have a single channel region instead of the multiple upper nanosheets NS-U shown in FIG. 1B. Thus, the present invention is not limited to transistors having multiple nanosheets NS. Transistors T-L and T-U can be stacked on substrate 101, such that the lower transistor T-L is located between the upper transistor T-U and the substrate 101. The substrate 101 can be, for example, a semiconductor substrate. In some embodiments, portions of the substrate 101 located on opposite sides of the transistors T-L and T-U can be recessed and filled with an insulating material to provide the trench isolation region 102. According to some embodiments, an upper metal layer M-U can be located on the upper gate G-U, and a lower metal layer M-L can be located on the lower gate G-L. For example, each of the metal layers M-U and M-L can include tungsten. Portions of the metal layers M-U and M-L can overlap the trench isolation region 102 in the vertical direction. FIG. 1B also shows that the widths of the upper nanosheets NS-U in the direction Y can be different from the widths of each of the lower nanosheets NS-L in the direction Y. Specifically, due to the insulating region 160, the widths of the upper nanosheets NS-U can be narrower than the widths of the lower nanosheets NS-L. The nanosheet stack 120-1 can thus represent a stepped nanosheet (“sNS”) structure. Exemplary sNS structures are discussed in U.S. Provisional Patent Application No. 63 / 086,781, filed Oct. 2, 2020, the disclosure of which is hereby incorporated by reference in its entirety. Since the nanosheet NS of the lower transistor T-L has a wider width, the lower transistor T-L can have fewer nanosheets NS (e.g., two versus three) than the upper transistor T-U, while still having the same total nanosheet NS cross-sectional area (and / or the same total nanosheet NS surface area) as the upper transistor T-U. Additionally, for the sake of simplicity of illustration, the gate insulating layer is omitted in FIG. 1B. However, it should be understood that the gate insulating layer can extend between each nanosheet NS and the gate G. For example, the gate insulating layer can be located between each upper nanosheet NS-U and the upper gate G-U, and can be located between each lower nanosheet NS-L and the lower gate G-L. The gate insulating layer can surround each nanosheet NS and can be thinner than the isolation region IL. FIG. 1C is a cross-sectional view taken along the direction X of the first transistor stack 110-1 shown in FIG. 1A according to some embodiments of the present invention. As shown in FIG. 1C, the stack 110-1 can include an upper source / drain region 150-U located on the sidewalls of the upper nanosheet NS-U and a lower source / drain region 150-L located on the sidewalls of the lower nanosheet NS-L. Each upper nanosheet NS-U can provide an upper channel region CH-U between the upper source / drain regions 150-U. Similarly, each lower nanosheet NS-L can provide a lower channel region CH-L between the lower source / drain regions 150-L. The sidewalls of the upper gate G-U located between the upper nanosheets NS-U can have upper insulating spacers IS-U. Similarly, the sidewalls of the lower gate G-L located between the lower nanosheets NS-L can have lower insulating spacers IS-L. The isolation region IL can separate the lower nanosheets NS-L from the upper nanosheets NS-U, as well as separate the lower insulating spacers IS-L from the upper insulating spacers IS-U and separate the lower source / drain region 150-L from the upper source / drain region 150-U. In some embodiments, the isolation region IL can have a non-uniform thickness in the direction Z. For example, the isolation region IL can have a first thickness T1 that separates the lower source / drain region 150-L from the upper source / drain region 150-U. Additionally, the isolation region IL can have a second thickness T2 between the uppermost one of the lower insulating spacers IS-L (and / or the lower gate G-L) and the lowermost one of the upper insulating spacers IS-U (and / or the upper gate G-U). The second thickness T2 can be thinner than the first thickness T1. Moreover, the uppermost one of the lower insulating spacers IS-L can contact the lower portion (e.g., the lower surface and the side surfaces) of the isolation region IL, and the lowermost one of the upper insulating spacers IS-U can contact the upper portion (e.g., the upper surface and the side surfaces) of the isolation region IL. As shown in the cross-sectional view of FIG. 1C, in some embodiments, the lower gate G-L may be wider than the upper gate G-U in the direction X. Thus, the lower insulating spacers IS-L may be spaced farther apart from each other in the direction X than the upper insulating spacers IS-U. Still referring to FIG. 1C, an upper isolation region UI may be present on top of the upper source / drain region 150-U. The upper isolation region UI may comprise, for example, an oxide material. In some embodiments, the upper isolation region UI and the isolation region IL may comprise the same oxide material. FIG. 1D is a cross-sectional view taken along the direction X of a modified first transistor stack 110-1' corresponding to the stack 110-1 shown in FIG. 1A according to other embodiments of the present invention. The modified stack 110-1' shown in FIG. 1D differs from the stack 110-1 shown in FIG. 1C in that the isolation region IL of the modified stack 110-1' has a uniform thickness T2. Thus, the isolation region IL shown in FIG. 1D separates the lower source / drain region 150-L from the upper source / drain region 150-U by the same distance as it separates the lower gate G-L from the upper gate G-U. Thus, a bonding process may be used to bond the lower transistor T-L to the upper transistor T-U. On the other hand, the stack 110-1 shown in FIG. 1C may be implemented without using a bonding process. FIGS. 2A to 2AN are cross-sectional views showing the operations of forming the transistor stack 110-1 shown in FIGS. 1B and 1C. Referring to FIG. 2A, a plurality of sacrificial layers SL may alternate with a plurality of preliminary nanosheets NS-P in a vertical stack. The sacrificial layers SL may comprise, for example, silicon germanium (“SiGe”), and the preliminary nanosheets NS-P may each be, for example, a silicon (“Si”) sheet. In some embodiments, the sacrificial layers SL and / or the preliminary nanosheets NS-P may be epitaxially grown on a substrate 101, which may comprise Si. Since the preliminary nanosheets NS-P will be etched to form the nanosheets NS that serve as the corresponding channel regions, the upper preliminary nanosheets in the preliminary nanosheets NS-P may be referred to herein as “upper channel layers”, and the lower preliminary nanosheets in the preliminary nanosheets NS-P may be referred to herein as “lower channel layers”. In addition, the sacrificial layers SL and the preliminary nanosheets NS-P may be collectively referred to herein as “preliminary transistor stacks”. The preliminary transistor stack also includes a sacrificial layer RL that separates the upper preliminary nanosheets from the lower preliminary nanosheets in the preliminary nanosheets NS-P. In some embodiments, the sacrificial layer RL and the preliminary nanosheets NS-P can be epitaxially grown. The sacrificial layer above the sacrificial layer RL in the sacrificial layer SL is the upper sacrificial layer SL-U, and the sacrificial layer below the sacrificial layer RL in the sacrificial layer SL is the lower sacrificial layer SL-L. The upper preliminary nanosheets in the preliminary nanosheets NS-P alternate with the upper sacrificial layer SL-U, and the lower preliminary nanosheets in the preliminary nanosheets NS-P alternate with the lower sacrificial layer SL-L. In addition, the sacrificial layer RL can contact the lowermost one in the upper sacrificial layer SL-U and the uppermost one in the lower sacrificial layer SL-L. Since the sacrificial layer RL will be replaced by the isolation layer 228 (FIG. 2V) that is part of the isolation region IL (FIG. 1B), the sacrificial layer RL can also be referred to herein as a "replacement isolation dummy layer". The sacrificial layer RL can include a first sacrificial material that has an etching selectivity relative to the second sacrificial material of the sacrificial layer SL (and relative to the preliminary nanosheets NS-P). For example, the sacrificial layer RL can include Si, which has an etching selectivity relative to SiGe of the sacrificial layer SL and can be grown on SiGe. As another example, the sacrificial layer RL can include SiGe with a first Ge concentration, and the sacrificial layer SL can include SiGe with a second Ge concentration, where the first concentration is higher than the second concentration. Thus, if the high-Ge SiGe has an etching selectivity relative to the SiGe of the sacrificial layer SL, the high-Ge SiGe can be used for the sacrificial layer RL. In addition, the sacrificial layer RL can be thicker than each of the sacrificial layers SL. Insulating layers 203 to 205 in a stacked form can be provided on the tops of the preliminary nanosheets NS-P and the sacrificial layer SL. For example, the insulating layers 203 and 205 can each include an oxide material, and the insulating layer 204 can include silicon nitride ("SiN"). In addition, a hard mask layer 206 can be deposited on the tops of the insulating layers 203 to 205. As an example, the hard mask layer 206 can include Si. Referring to FIG. 2B, a mask layer 207 can be formed on the hard mask layer 206. The mask layer 207 can be patterned to be narrower than the hard mask layer 206. Referring to FIG. 2C, recessed regions 208 and 209 can be formed in the preliminary transistor stack by using the mask layer 207 and the hard mask layer 206 as etching masks. After the recessed regions 208 and 209 are formed, the mask layer 207 and the hard mask layer 206 can be removed. Referring to FIG. 2D, a dielectric region 210 may be formed in the recessed regions 208 and 209, and the dielectric region 210 may be planarized (e.g., using chemical mechanical planarization (“CMP”)) to have an upper surface coplanar with the upper surface of the insulating material 204. Referring to FIG. 2E, a mask layer 211 may be formed on top of the preliminary transistor stack. The mask layer 211 may be patterned to overlap a part (e.g., half) of the preliminary transistor stack in the vertical direction. Referring to FIG. 2F, a recessed region 201 may be formed in the preliminary transistor stack by using the mask layer 211 as an etching mask. As a result, the upper sacrificial layer SL-U and the upper preliminary nanosheet in the preliminary nanosheets NS-P are etched to reduce their widths, thereby exposing a part of the upper surface of the sacrificial layer RL. For example, the recessed region 201 may extend into the sacrificial layer RL (but not completely through the sacrificial layer RL). Referring to FIG. 2G, an insulating layer 212 may be formed in the recessed region 201 and the insulating layer 212 may be planarized (e.g., using CMP). The insulating layer 212 may include, for example, SiN. Referring to FIG. 2H, the dielectric region 210 may be recessed until it is lower than the level of the lowermost preliminary nanosheet NS-P. For example, the dielectric region 210 may be recessed to have an upper surface coplanar with the upper surface of the substrate 101. Referring to FIG. 2I which is a cross-sectional view taken along the direction Y, the insulating layer 212 may be patterned to form an insulating (e.g., dielectric) region 160. In addition, a spacer layer 213 may be deposited on the insulating region 160, the preliminary transistor stack, and the trench isolation region 102. In addition, a sacrificial material 214 may be formed on the spacer layer 213, and a hard mask layer 215 may be formed on the sacrificial material 214. The sacrificial material 214 may include, for example, polysilicon. Referring to FIG. 2J which is a cross-sectional view taken along the direction X, the hard mask layer 215 may have spacers 216 on its sidewalls. Referring to FIG. 2K which is a cross-sectional view taken along the direction X, the preliminary transistor stack is recessed to a depth of approximately the sacrificial layer RL by using the hard mask layer 215 and the spacers 216 as etching masks. As a result, the width of the upper preliminary nanosheet in the preliminary nanosheets NS-P becomes narrower, thereby forming an upper nanosheet NS-U. The width of the upper sacrificial layer SL-U also becomes narrower, thereby forming recessed regions 217 and 218 beside the upper sacrificial layer SL-U and the upper nanosheet NS-U. While forming the recessed regions 217 and 218, the sacrificial layer RL may be partially recessed without completely etching through the sacrificial layer RL to the uppermost one of the lower sacrificial layers SL-L located below the sacrificial layer RL. Referring to FIG. 2L which is a cross-sectional view taken along the direction X, the sidewalls of the upper sacrificial layer SL-U are recessed to form recessed regions 219 and 220 between the upper nanosheets NS-U, between the sacrificial layer RL and the lowermost one of the upper nanosheets NS-U, and between the uppermost one of the upper nanosheets NS-U and the sacrificial material 214. For example, the recessed regions 219 and 220 can be formed by performing a low Ge SiGe etch-back on the upper sacrificial layer SL-U. Referring to FIG. 2M which is a cross-sectional view taken along the direction X, upper insulating spacers IS-U are formed in the recessed regions 219 and 220. As a result, the upper insulating spacers IS-U are located on the sidewalls of the upper sacrificial layer SL-U. The upper insulating spacers IS-U (i) are located between the upper nanosheets NS-U, (ii) are located between the sacrificial layer RL and the lowermost one of the upper nanosheets NS-U, and (iii) are located between the uppermost one of the upper nanosheets NS-U and the sacrificial material 214. The upper insulating spacers IS-U can be formed by, for example, performing SiN deposition and etching. Referring to FIG. 2N which is a cross-sectional view taken along the direction X, spacers 221 are deposited on the sidewalls of the upper insulating spacers IS-U and on the sidewalls of the spacer 216. For example, the spacers 221 can continuously extend from the sidewalls of the sacrificial layer RL to the upper portion of the spacer 216. Referring to FIG. 2O which is a cross-sectional view taken along the direction X, while using the spacer 216, the spacer 221, and the hard mask layer 215 as an etch mask to protect the upper nanosheets NS-U and the upper insulating spacers IS-U, the lower side region of the preliminary transistor stack is recessed. As a result, the lower preliminary nanosheets in the preliminary nanosheets NS-P become narrower to form the lower nanosheets NS-L and recessed regions 222 and 223 adjacent to the lower nanosheets NS-L. The lower sacrificial layer SL-L also becomes narrower, as does the lower portion of the sacrificial layer RL. Referring to FIG. 2P which is a cross-sectional view taken along the direction X, the sidewalls of the lower sacrificial layer SL-L are recessed to form recessed regions 224 and 225 between the lower nanosheets NS-L, between the sacrificial layer RL and the uppermost one of the lower nanosheets NS-L located below the sacrificial layer RL, and between the lowermost one of the lower nanosheets NS-L and the substrate 101. For example, the recessed regions 224 and 225 can be formed by performing a SiGe etch-back on the lower sacrificial layer SL-L. Referring to FIG. 2Q, which is a cross-sectional view taken along the direction X, a lower insulating spacer IS-L is formed in the recessed regions 224 and 225. As a result, the lower insulating spacer IS-L is located on the sidewalls of the lower sacrificial layer SL-L. The lower insulating spacer IS-L (i) is located between the lower nanosheets NS-L, (ii) is located between the sacrificial layer RL and the uppermost one of the lower nanosheets NS-L located below the sacrificial layer RL, and (iii) is located between the lowermost one of the lower nanosheets NS-L and the substrate 101. The lower insulating spacer IS-L can be formed by, for example, performing SiN deposition and etchback. Referring to FIG. 2R, which is a cross-sectional view taken along the direction X, an oxide material 226 is deposited in the recessed regions 222 and 223 (FIG. 2O), and the oxide material 226 is planarized (e.g., using CMP). Referring to FIG. 2S, which is a cross-sectional view taken along the direction X, the oxide material 226 is recessed to a level lower than that of the sacrificial layer RL. Accordingly, the lower sidewalls of the sacrificial layer RL are exposed. Referring to FIG. 2T, which is a cross-sectional view taken along the direction Y, the sacrificial layer RL is removed, thereby forming an opening 227 between the upper nanosheets NS-U and the lower nanosheets NS-L. Referring to FIG. 2U, which is a cross-sectional view taken along the direction X, the opening 227 includes a gap located between the spacer 221 and the uppermost pair of the lower insulating spacers among the lower insulating spacers IS-L. In addition, the opening 227 is thicker than each of the two sacrificial layers SL located between the upper nanosheets NS-U and the lower nanosheets NS-L. Referring to FIG. 2V, which is a cross-sectional view taken along the direction Y, an isolation layer 228 is formed in the opening 227. Referring to FIG. 2W, which is a cross-sectional view taken along the direction X, the isolation layer 228 can also be formed on the top of the oxide material 226. The isolation layer 228 can include, for example, an oxide material that fills the opening and is then planarized (e.g., using CMP). Referring to FIG. 2X, which is a cross-sectional view taken along the direction X, the isolation layer 228 is recessed while using the spacer 216, the spacer 221, and the hard mask layer 215 as an etch mask to protect a part of the isolation layer 228 that separates the upper nanosheets NS-U and the lower nanosheets NS-L. Accordingly, this recessing operation removes the portion of the isolation layer 228 located on the top of the oxide material 226. The recessing operation can also remove the oxide material 226. Referring to FIG. 2Y, which is a cross-sectional view taken along direction X, a lower source / drain region 150-L is formed on the substrate 101 and on the sidewalls of the lower nanosheet NS-L. An insulating material 229 is deposited at the level of the isolation layer 228 (FIG. 2X) on top of the lower source / drain region 150-L. The insulating material 229 may comprise, for example, an oxide material and may provide an isolation region IL together with the isolation layer 228. As an example, the sidewalls of the insulating material 229 and the sidewalls of the isolation layer 228 may contact each other and may comprise the same insulating material. In some embodiments, the isolation region IL may be thicker in the vertical direction Z than each of the nanosheets NS (and thus thicker than each channel region CH (FIG. 1C) provided thereby). An upper source / drain region 150-U is formed on the sidewalls of the upper nanosheet NS-U. For example, the upper source / drain region 150-U and the lower source / drain region 150-L may be formed by epitaxial growth. In addition, an oxide material 230 is deposited on top of the upper source / drain region 150-U. Referring to FIG. 2Z, which is a cross-sectional view taken along direction Y, the hard mask layer 215 is removed, for example, by performing poly-open CMP (polycrystalline silicon open window chemical mechanical polishing). Referring to FIG. 2AA, which is a cross-sectional view taken along direction X, removing the hard mask layer 215 exposes the upper surface of the sacrificial material 214. The upper portion of the spacer 216 may also be removed. Referring to FIG. 2AB, which is a cross-sectional view taken along direction Y, a polysilicon removal operation may be performed to remove the sacrificial material 214. As a result, recessed regions 231 and 232 are formed and the spacer layer 213 is exposed. Referring to FIG. 2AC, which is a cross-sectional view taken along direction X, the polysilicon removal operation that forms the recessed regions 231 and 232 (FIG. 2AB) also forms an opening 233 between the spacers 216. The polysilicon removal operation also removes at least a portion of the spacer layer 213. As an example, FIG. 2AC shows that the polysilicon removal operation removes a portion of the spacer layer 213 on the uppermost one of the upper sacrificial layers SL-U, thereby exposing the upper surface of the uppermost one of the upper sacrificial layers SL-U. Referring to FIG. 2AD, which is a cross-sectional view taken along direction Y, the sacrificial layer SL is removed. For example, a SiGe removal operation may remove the sacrificial layer SL. Referring to FIG. 2AE, which is a cross-sectional view taken along direction X, removing the sacrificial layer SL provides openings between corresponding pairs of the insulating spacers in the insulating spacer IS. Referring to FIG. 2AF, which is a cross-sectional view taken along direction Y, a first metal material 234 is deposited on the nanosheets NS. Referring to FIG. 2AG, which is a cross-sectional view taken along the direction X, a first metal material 234 is formed in the openings between corresponding pairs of insulating spacers in the insulating spacer IS. For example, each insulating spacer IS can contact the first metal material 234. In addition, there is an opening 235 between the sidewalls of the upper portion of the first metal material 234 (i.e., between the spacers 216). Referring to FIG. 2AH, which is a cross-sectional view taken along the direction Y, a second metal material 236 is deposited on the first metal material 234. Then, the second metal material 236 is planarized (e.g., using CMP) and recessed (e.g., using chamfering) until the second metal material 236 remains on the lower portions adjacent to the lower nanosheets NS-L of the recessed regions 231 and 232 (FIG. 2AF). As an example, the upper surface of the remaining second metal material 236 can be at the level of the lower surface of the isolation region IL. The second metal material 236 can include, for example, tungsten ("W"), which can be different from the first metal material 234. Referring to FIG. 2AI, which is a cross-sectional view taken along the direction Y, the first metal material 234 can be removed above the level of the upper surface of the second metal material 236. For example, when removing the upper portion of the first metal material 234, the second metal material 236 can be used as an etch stop layer. As a result, the sidewalls of the isolation region IL can be exposed. In some embodiments, the removal of the upper portion of the first metal material 234 can be implemented using a selective wet etch between the first metal material 234 and the second metal material 236. As an example, the wet etch can include a chamfering process that terminates at the second metal material 236. In addition, the result of the wet etch (e.g., the minimum etch depth) can vary based on the thickness of the first metal material 234. Referring to FIG. 2AJ, which is a cross-sectional view taken along the direction X, the removal of the upper portion of the first metal material 234 includes removing the first metal material 234 from the sidewalls of the upper insulating spacer IS-U. As a result, an opening 237 is formed between corresponding pairs of upper insulating spacers in the upper insulating spacer IS-U. A recessed region 238 is also formed between the spacers 216. In addition, the remaining portion of the first metal material 234 provides a lower gate G-U on the lower nanosheet NS-L. Therefore, the first metal material 234 is the lower gate metal. Referring to FIG. 2AK, which is a cross-sectional view taken along the direction Y, a third gate material is deposited on the upper nanosheet NS-U to provide an upper gate G-U. Thus, the third metal material is an upper gate metal, which may include a material different from the first metal material 234 and the second metal material 236. In some embodiments, the upper gate G-U may also be formed on the exposed sidewalls of the isolation region IL (e.g., in contact with the exposed sidewalls). In other embodiments, the lower gate G-L may be formed on the sidewalls of the isolation region IL (e.g., in contact with the sidewalls). Thus, the isolation region IL may be located inside the upper gate G-U or the lower gate G-L. In some embodiments, the isolation region IL may be located between the upper gate G-U and the lower gate G-L. In addition, the openings 240 and 241 may be located on opposite sides of the upper gate G-U. Referring to FIG. 2AL, which is a cross-sectional view taken along the direction X, the formation of the upper gate G-U includes forming the upper gate G-U (FIG. 2AJ) in the opening 237. As a result, the upper gate G-U may contact the sidewalls of the upper insulating spacer IS-U. In addition, there may be an opening 239 between the sidewalls of the upper portion of the upper gate G-U (i.e., between the spacers 216). Referring to FIG. 2AM, which is a cross-sectional view taken along the direction Y, a fourth metal material 242 is deposited on the upper gate G-U and in the openings 240 and 241 (FIG. 2AK). Then, the fourth metal material 242 is planarized (e.g., using CMP). In some embodiments, the fourth metal material 242 may include the same material as the second metal material 236. For example, the second metal material 236 and the fourth metal material 242 may each include W. Referring to FIG. 2AN, which is a cross-sectional view taken along the direction X, the formation of the fourth metal material 242 may include forming the fourth metal material 242 in the opening 239 (FIG. 2AL) between the spacers 216. FIGS. 3A to 3E are flowcharts showing operations for forming the transistor stack 110-1 shown in FIGS. 1B and 1C. These operations correspond to the operations shown in the cross-sectional views shown in FIGS. 2A to 2AN. As shown in FIG. 3A, the operations include forming (block 310) a preliminary transistor stack. Referring back to FIG. 2A, the preliminary transistor stack may include a preliminary nanosheet NS-P and a sacrificial layer RL, and the sacrificial layer RL separates the lower preliminary nanosheet in the preliminary nanosheet NS-P from the upper preliminary nanosheet in the preliminary nanosheet NS-P. The preliminary transistor stack may also include a sacrificial layer SL that alternates with the preliminary nanosheet NS-P. The operations include forming (block 320) insulating spacers IS on the sidewalls of the preliminary transistor stack. For example, FIGS. 2M and 2Q show the formation of the upper insulating spacer IS-U and the lower insulating spacer IS-L, respectively. The operations include removing (block 330) the sacrificial layer RL after forming the insulating spacer IS. As an example, FIGS. 2S to 2U illustrate removing the sacrificial layer RL to form an opening 227. The operations include forming (block 340) an isolation layer 228 in the opening 227. As shown in FIG. 2X, the isolation layer 228 is part of the isolation region IL. In addition, the operations include forming (block 350) a shared gate G, which may include a lower gate G-L and an upper gate G-U in contact with the lower gate G-L. For example, the lower gate G-L may be formed on the lower nanosheet NS-L as shown in FIG. 2AI, and the upper gate G-U may be formed on the upper nanosheet NS-U as shown in FIG. 2AK. As another alternative, the upper gate G-U and the lower gate G-L may be formed isolated from each other, for example, by extending the isolation region IL between the upper gate G-U and the lower gate G-L. Although the cross-sectional views shown in FIGS. 1B, 1C, and 2A to 2AN illustrate transistors T each including a plurality of nanosheets NS, the operations shown in FIG. 3A are not limited to forming such transistors T.确切而言,藉由圖3A所示操作而形成的電晶體T可包括多個通道層或單一通道層。因此,在電晶體疊層110中,下部電晶體T-L可包括多個下部通道層或單一下部通道層,而上部電晶體T-U可包括多個上部通道層或者單一上部通道層。每一通道層可包括半導體層。在一些實施例中,半導體層是由奈米片NS提供。然而,在其他實施例中,半導體層並非由奈米片NS提供。 Rather, the transistor T formed by the operations shown in FIG. 3A may include multiple channel layers or a single channel layer. Thus, in the transistor stack 110, the lower transistor T-L may include multiple lower channel layers or a single lower channel layer, and the upper transistor T-U may include multiple upper channel layers or a single upper channel layer. Each channel layer may include a semiconductor layer. In some embodiments, the semiconductor layer is provided by the nanosheet NS. However, in other embodiments, the semiconductor layer is not provided by the nanosheet NS. Referring to FIG. 3B, the operation of forming the insulating spacer IS (block 320 shown in FIG. 3A) may include forming (block 320-A) an upper insulating spacer IS-U (FIG. 2M) on the sidewalls of the upper sacrificial layer SL-U, and then forming (block 320-B) a lower insulating spacer IS-L (FIG. 2Q) on the sidewalls of the lower sacrificial layer SL-L. Referring to FIG. 3C, the operation of forming the shared gate G (block 350 shown in FIG. 3A) may include replacing (block 350-A) the lower sacrificial layer SL-L with the lower gate G-L (FIG. 2AI), and then replacing (block 350-B) the upper sacrificial layer SL-U with the upper gate G-U (FIG. 2AK). Referring to FIG. 3D, the operation of replacing the sacrificial layer SL (blocks 350-A and 350-B shown in FIG. 3C) may include forming (block 350-A1) the lower gate G-L below the isolation region IL (FIG. 2AI), and then forming (block 350-B1) the upper gate G-U above the isolation region IL and on opposite sidewalls of the isolation region IL. Thus, in some embodiments, the isolation region IL may be located inside the upper gate G-U as shown in FIG. 2AK. According to other embodiments, the isolation region IL may be located inside the lower gate G-L. For example, referring to FIG. 3E, the operation of replacing the sacrificial layers SL (block 350-A and block 350-B shown in FIG. 3C) may include forming (block 350-A2) the lower gate G-L below the isolation region IL and on opposite sidewalls of the isolation region IL, and then forming (block 350-B2) the upper gate G-U above the isolation region IL. FIGS. 4A to 4P are perspective views showing the operations of a further embodiment of forming a transistor stack. The resulting transistor stack may be similar to the transistor stack formed by the operations shown in FIGS. 2A to 2AN. For example, similar to the purpose for which the operations shown in FIGS. 2A to 2AN are used, the operations shown in FIGS. 4A to 4P may be used to form any of the transistor stacks shown in FIGS. 1A to 1D. Therefore, the following description of FIGS. 4A to 4P may mainly focus on the differences with respect to the operations of FIGS. 2A to 2AN. As shown in FIG. 4A, the substrate 401 may have a preliminary transistor stack covered with a pad 402 thereon, and the pad 402 may be an oxide pad. Referring to FIG. 4B, the pad 402 is removed, thereby exposing the preliminary transistor stack, which includes a preliminary nanosheet NS-P, an upper sacrificial layer SL-U, a lower sacrificial layer SL-L, and a sacrificial layer RL located between the upper sacrificial layer SL-U and the lower sacrificial layer SL-L. In addition, there may be a bottom sacrificial layer BRL between the lower sacrificial layer SL-L and the substrate 401. The bottom sacrificial layer BRL has an etching selectivity with respect to the sacrificial layer SL. For example, the bottom sacrificial layer BRL may contain the same material as the sacrificial layer RL. The sacrificial layer RL and the bottom sacrificial layer BRL may each be thicker than each of the sacrificial layers SL. In addition, the bottom sacrificial layer BRL may be thinner than the sacrificial layer RL. Referring to FIG. 4C, the sacrificial layer RL and the bottom sacrificial layer BRL are removed, thereby forming openings 403 and 404. For example, the sacrificial layer RL and the bottom sacrificial layer BRL may each include a high Ge concentration (e.g., higher than the Ge concentration of the sacrificial layer SL), and the sacrificial layer RL and the bottom sacrificial layer BRL may be removed by a removal process selective to high Ge SiGe. FIG. 4D is a side perspective view of the openings 403 and 404. On the other hand, FIG. 4C is a front perspective view. Referring to FIG. 4E, a gate spacer material 405 is deposited. The operations shown in FIGS. 4E to 4O may be used as a repeated deposit-etch back sequence for finally constructing the isolation region IL and the insulating spacer IS. Referring to FIG. 4F, an etch-back operation is performed on the gate spacer material 405, thereby forming an opening 406 in the region where the sacrificial layer RL already exists. Referring to FIG. 4G, the gate spacer material 407 is deposited. Referring to FIG. 4H, an etch-back operation is performed on the gate spacer material 407, thereby forming an opening 408 in the region where the sacrificial layer RL already exists. Due to the repeated gate spacer material formation operations, the opening 408 is smaller than the opening 406 (FIG. 4F) because more gate spacer material in the gate spacer material 407 remains after its etch-back operation. Referring to FIG. 4I, the gate spacer material 409 is deposited. Referring to FIG. 4J, an etch-back operation is performed on the gate spacer material 409. This etch-back operation no longer forms an opening in the region where the sacrificial layer RL already exists, but rather provides a narrowed gate spacer region 410. Referring to FIG. 4K, the spacer material 411 is deposited. In some embodiments, the spacer material 411 can provide the isolation region IL (FIG. 1B). Referring to FIG. 4L, an etch-back operation is performed on the spacer material 411, thereby providing a recessed region 412, and the sacrificial layer SL and the preliminary nanosheet NS-P protrude outward beyond the recessed region 412. Referring to FIG. 4M, the recessed region 413 can be formed by removing the outward protruding portions of the sacrificial layer SL and the preliminary nanosheet NS-P. Referring to FIG. 4N, the upper inner spacer IS-U and the lower inner spacer IS-L can be simultaneously formed on the sidewalls of the upper sacrificial layer SL-U and the lower sacrificial layer SL-L (FIG. 4L), respectively. FIG. 4O is a front perspective view of the upper inner spacer IS-U and the lower inner spacer IS-L formed above and below the isolation region IL, respectively. FIG. 4P is a front perspective view showing the sacrificial layer SL on the sidewall of the gate G replacing the insulating spacer IS. Since the gate G can be thinner in the vertical direction than a conventional gate, the gate G can have a smaller surface area and thus can help reduce capacitance (e.g., having source / drain contact members 414 / 415 and / or having source / drain regions 450). In addition, an upper source / drain region 450-U is provided on the sidewall of the upper nanosheet NS-U, and a lower source / drain region 450-L is provided on the sidewall of the lower nanosheet NS-L. In some embodiments, a source / drain contact member 414 can be provided on each upper source / drain region 450-U, and a source / drain contact member 415 can be provided on each lower source / drain region 450-L. In addition, a bottom isolation region 416 can be provided in the space previously occupied by the bottom sacrificial layer BRL (FIG. 4B). The bottom isolation region 416 can include, for example, the same insulating material as the isolation region IL. Figures 5A and 5B are flowcharts corresponding to the operations shown in Figures 4A to 4P. As shown in Figures 5A and 4B, a preliminary transistor stack (block 510) including alternating sacrificial layers SL and preliminary nanosheets NS-P is formed. In addition, a sacrificial layer RL separates an upper sacrificial layer SL-U from a lower sacrificial layer SL-L, and a bottom sacrificial layer BRL separates the lower sacrificial layer SL-L from the substrate 401 (Figure 4A). Referring to Figures 5A and 4C, the sacrificial layer RL is removed (block 520) to form an opening 404 that separates the upper sacrificial layer SL-U from the lower sacrificial layer SL-L. In addition, the bottom sacrificial layer BRL can be removed simultaneously to form an opening 403. However, in other embodiments, the sacrificial layer RL can be removed without simultaneously removing the bottom sacrificial layer BRL. Still referring to Figure 5A, an isolation layer is formed in the opening 404 (block 530). The isolation layer can provide a part of the isolation region IL (Figure 4P). As an example, a spacer material 411 (Figure 4K) can provide the isolation layer. Referring to Figures 5A and 4O, an insulating spacer IS is formed on the sidewalls of the stack of sacrificial layers SL (block 540). The insulating spacer IS is formed after forming the isolation layer that can provide a part of the isolation region IL. Referring to Figures 5A and 4P, a common gate G is formed between the sidewalls of the insulating spacer IS (block 550). The common gate G includes an upper gate G-U and a lower gate G-L in contact with the upper gate G-U. Referring to Figures 5B and 4O, the operation of forming (block 540 shown in Figure 5A) the insulating spacer IS can include simultaneously forming (block 540S) an upper insulating spacer IS-U on the sidewalls of the upper sacrificial layer SL-U and a lower insulating spacer IS-L on the sidewalls of the lower sacrificial layer SL-L. The transistor device 100 (FIG. 1B) according to an embodiment of the present invention and a method of forming the same may provide a number of advantages. These advantages include defining a boundary between an upper transistor T-U (FIG. 1B) and a lower transistor T-L (FIG. 1B) of the transistor stack 110 (FIG. 1B). For example, the boundary may be defined by forming a sacrificial layer RL (FIG. 2A), which will be replaced by an isolation region IL (FIG. 1B) that is stacked between the transistors T-U and T-L. Defining the boundary with the sacrificial layer RL may improve the subsequent formation of the insulating spacer IS (FIG. 1C), which will separate the gate G (FIG. 1C) from the source / drain region 150 (FIG. 1C). This may help to solve the problem of incomplete pinch-off of the inner spacer in the region between the two transistors in the stack. As another example, by forming the isolation region IL inside the gate G, which may be a shared gate having an upper gate G-U and a lower gate G-L in contact with each other, the variability and control of gate metal deposition and removal may be improved. This may help to reduce the gate capacitance. Exemplary embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments may exist without departing from the teachings of this disclosure, and thus this disclosure should not be considered limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art. In the figures, the size and relative size of layers and regions may be exaggerated for clarity. The same reference numerals refer to the same elements throughout. Exemplary embodiments of the present invention are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments and intermediate structures of exemplary embodiments. Accordingly, deviations from the illustrated shapes are to be expected, for example, due to manufacturing techniques and / or tolerances. Thus, embodiments of the present invention should not be considered limited to the specific shapes shown herein, but may include shape deviations resulting from, for example, manufacturing. It should also be noted that in some alternative embodiments, the functions / actions recited in the flowchart blocks herein may not be performed in the order recited in the flowchart. For example, two blocks shown in succession may in fact be performed substantially simultaneously, or the blocks may sometimes be performed in the reverse order depending on the functions / actions involved. Additionally, the functions of a given block of a flowchart and / or block diagram may be divided into multiple blocks, and / or the functions of two or more blocks of a flowchart and / or block diagram may be at least partially integrated. Finally, other blocks may be added / inserted between the blocks shown, and / or blocks / operations may be omitted, without departing from the scope of the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and should not be interpreted as having an idealized or overly formal meaning unless clearly defined herein. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. Unless clearly stated otherwise in the context, the singular forms "a", "an", and "the" used herein are also intended to include the plural forms. It should be further understood that when the terms "comprises", "comprising", "includes", and / or "including" are used in this specification, they are used to specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as being "coupled to", "connected to", "responsive to", or "located on" another element, the element can be directly coupled to, directly connected to, directly responsive to, or directly located on the other element, or there may also be intermediate elements. In contrast, when an element is referred to as being "directly coupled to", "directly connected to", "directly responsive to", or "directly located on" another element, there are no intermediate elements. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (e.g., when used in the term "source / drain") should be understood to be equivalent to the term "and / or". It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element may be referred to as a second element without departing from the teachings of the embodiments of the present invention. In this document, for ease of explanation, spatial relative terms such as, for example, "beneath", "below", "lower", "above", "upper", and similar terms may be used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element that is described as being "below" or "beneath" another element or feature will then be oriented as being "above" the other element or feature. Thus, the term "below" can encompass both an upper and a lower orientation. The device may have other orientations (e.g., rotated 90 degrees or at other orientations), and thus the spatial relative descriptors used herein can be interpreted accordingly. Numerous different embodiments have been disclosed herein in connection with the above description and drawings. It should be understood that a literal recitation and illustration of every combination and subcombination of those embodiments would be overly repetitive and confusing. Accordingly, this specification, including the drawings, should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and processes of making and using all such combinations and subcombinations, and should support claims to any such combination or subcombination. The subject matter disclosed above will be understood to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements, and other embodiments that fall within the scope of the present invention. Accordingly, to the maximum extent permitted by law, the scope should be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited to or restricted by the foregoing detailed description. 100: Nanosheet Transistor Device / Transistor Device / Device 101, 401: Substrate 102: Trench Isolation Region 110-1: First Transistor Stack / Stack 110-1': First Transistor Stack / Transistor Stack / Stack 110-2: Second Transistor Stack / Transistor Stack 120-1: First Nanoshheet Stack / Nanoshheet Stack 120-2: Nanoshheet Stack 140-1, 140-2, 414, 415: Source / Drain Contact 150-1, 150-2: Source / Drain Region 150-L, 450-L: Lower Source / Drain Region 150-U, 450-U: Upper Source / Drain Region 160: Insulation Region / Region 201, 208, 209, 217, 218, 219, 220, 222, 223, 224, 225, 231, 232, 238, 412, 413: Recessed Region 203, 204, 205, 212: Insulating Layer 206, 215: Hard Mask Layer 207, 211: Mask Layer 210: Dielectric Region 213: Spacer Layer 214: Sacrificial Material 216, 221: Spacer 226, 230: Oxide Material 227, 233, 235, 237, 239, 240, 241, 403, 404, 406, 408: Opening 228: Isolation Layer 229: Insulating Material 234: First Metal Material 236: Second Metal Material 242: Fourth Metal Material 310, 320, 320-A, 320-B, 330, 340, 350, 350-A, 350-A1, 350-A2, 350-B, 350-B1, 350-B2, 510, 520, 530, 540, 540S, 550: Operation 402: Pad 405, 407, 409: Gate Spacer Material 410: Gate Spacer Region 411: Spacer Material 416: Bottom Isolation Region BRL: Bottom Sacrificial Layer CH-L: Lower Channel Region CH-U: Upper Channel Region GA: Gate-All-Around Transistor G-L: Lower Gate / Gate G-U: Upper Gate / Gate IL: Isolation Region IS-L: Lower Insulating Spacer / Lower Inner Spacer IS-U: Upper Insulating Spacer / Upper Inner Spacer M-L: Lower Metal Layer / Metal Layer M-U: Upper Metal Layer / Metal Layer NS-L: Lower Nanoshheet NS-P: Preliminary Nanoshheet NS-U: Upper Nanoshheet RL: Sacrificial Layer SL-L: Lower Sacrificial Layer SL-U: Upper Sacrificial Layer T1: First Thickness T2: Second Thickness / Thickness TG: Triple-Gate Nanoshheet Transistor T-L: Lower Transistor / Transistor T-U: Upper Transistor / Transistor UI: Upper Isolation Region X: Horizontal Direction / Direction / First Horizontal Direction Y: Horizontal Direction / Direction / Second Horizontal Direction Z: Vertical Direction / Direction FIG. 1A is a plan view of a nanosheet transistor device according to some embodiments of the present invention. FIG. 1B is a cross-sectional view of a first transistor stack of the nanosheet transistor device shown in FIG. 1A taken along the direction Y. FIG. 1C is a cross-sectional view of the first transistor stack shown in FIG. 1A taken along the direction X according to some embodiments of the present invention. FIG. 1D is a cross-sectional view of the first transistor stack shown in FIG. 1A taken along the direction X according to other embodiments of the present invention. FIGS. 2A to 2AN are cross-sectional views showing operations of forming the transistor stack shown in FIGS. 1B and 1C. FIGS. 3A to 3E are flowcharts showing operations of forming the transistor stack shown in FIGS. 1B and 1C. FIGS. 4A to 4P are perspective views showing operations of a further embodiment of forming a transistor stack. FIGS. 5A and 5B are flowcharts corresponding to the operations shown in FIGS. 4A to 4P. 100: Nanoscale sheet transistor device / Transistor device / Device 110-1: First transistor stack / Stack 110-2: Second transistor stack / Transistor stack 120-1: First nanosheet stack / Nanosheet stack 120-2: Nanosheet stack 140-1, 140-2: Source / drain contact 150-1, 150-2: Source / drain region 160: Insulating region / Region X: Horizontal direction / Direction / First horizontal direction Y: Horizontal direction / Direction / Second horizontal direction Z: Vertical direction / Direction

Claims

1. A transistor device, comprising: substrate; A lower transistor includes a lower gate, a lower channel region on the substrate, a lower insulating spacer on the sidewall of the lower gate, and a lower source / drain region; an upper transistor includes an upper gate, an upper channel region, an upper insulating spacer on the sidewall of the upper gate, and an upper source / drain region, wherein the lower transistor is located between the upper transistor and the substrate; and an isolation region separating the lower insulating spacer from the upper insulating spacer, the isolation region including a first portion separating the lower channel region from the upper channel region and a second portion separating the lower source / drain region from the upper source / drain region, wherein the lower gate of the lower transistor contacts the upper gate of the upper transistor, wherein the first portion of the isolation region has a first thickness less than or equal to the second thickness of the second portion of the isolation region, and wherein the width of the lower gate is greater than the width of the upper gate.

2. The transistor device of claim 1, wherein the lower surface of the upper gate of the upper transistor contacts the upper surface of the lower gate of the lower transistor.

3. The transistor device of claim 1, wherein the upper gate of the upper transistor is located on the opposite sidewall of the isolation region, and wherein the isolation region is thicker than the upper channel region of the upper transistor.

4. The transistor device of claim 1, wherein the lower transistor and the upper transistor are respectively a lower nanosheet transistor and an upper nanosheet transistor, wherein the lower nanosheet transistor includes a plurality of lower nanosheets, a first of the plurality of lower nanosheets defining a lower channel region, wherein the upper nanosheet transistor includes a plurality of upper nanosheets, a first of the plurality of upper nanosheets defining an upper channel region, and wherein the first portion of the isolation region separates the plurality of lower nanosheets of the lower nanosheet transistor from the plurality of upper nanosheets of the upper nanosheet transistor.

5. The transistor device of claim 1, wherein the first portion of the isolation region has a first thickness that is thinner than the second thickness of the second portion of the isolation region.

6. The transistor device of claim 1, wherein one of the lower insulating spacers contacts the sidewall of the lower source / drain region and the lower portion of the isolation region, and wherein one of the upper insulating spacers contacts the sidewall of the upper source / drain region and the upper portion of the isolation region.

7. The transistor device of claim 1, wherein the first of the lower transistor or the upper transistor comprises a gate-wrap nanosheet transistor or a three-gate nanosheet transistor, and wherein the second of the lower transistor or the upper transistor, different from the first, comprises a vertical field-effect transistor or a fin field-effect transistor.

8. A transistor device, comprising: A lower nanosheet transistor includes a lower nanosheet stack and a lower gate located on the lower nanosheet stack; an upper nanosheet transistor is located on top of the lower nanosheet transistor, the upper nanosheet transistor including an upper nanosheet stack and an upper gate located on the upper nanosheet stack; and an isolation region separating the lower nanosheet stack from the upper nanosheet stack, wherein the lower gate of the lower nanosheet transistor contacts the upper gate of the upper nanosheet transistor, wherein the lower nanosheet transistor further includes a lower insulating spacer in contact with a lower portion of the isolation region, and wherein the upper nanosheet transistor further includes an upper insulating spacer in contact with an upper portion of the isolation region, wherein the width of the lower gate is greater than the width of the upper gate.

9. The transistor device of claim 8, wherein the upper surface of the lower gate of the lower nanoplate transistor contacts the lower surface of the upper gate of the upper nanoplate transistor.

10. The transistor device as claimed in claim 8, wherein the upper gate of the upper nanosheet transistor contacts the opposite sidewall of the isolation region.

11. A method of forming a transistor device, the method comprising: A preliminary transistor stack is formed, the preliminary transistor stack including a lower channel layer, an upper channel layer and a sacrificial layer, the sacrificial layer separating the lower channel layer and the upper channel layer and overlapping the lower channel layer and the upper channel layer in a first direction; an insulating spacer is formed between the lower channel layer and the upper channel layer; Remove the sacrificial layer; An isolation layer is formed in an opening formed by removing the sacrificial layer and overlapping the insulating spacer in the first direction; and a lower gate is formed on the lower channel layer below the isolation layer and an upper gate is formed on the upper channel layer above the isolation layer, wherein the lower electrode contacts the upper electrode, and wherein the width of the lower gate is greater than the width of the upper gate.

12. The method of claim 11, wherein the insulating spacer is formed before the sacrificial layer is removed.

13. The method of claim 11, wherein the insulating spacer is formed after the sacrificial layer is removed and the insulating layer is formed.

14. The method of claim 11, wherein the preliminary transistor stack further comprises: A plurality of lower nanosheets, the first of which defines the lower channel layer; Multiple lower sacrificial layers, alternating with the multiple lower nanosheets; multiple upper nanosheets, the first of which defines the upper channel layer; and multiple upper sacrificial layers, alternating with the multiple upper nanosheets.

15. The method of claim 14, wherein forming the insulating spacer comprises: A lower insulating spacer is formed on the sidewall of the plurality of lower sacrificial layers; And an upper insulating spacer is formed on the sidewall of the plurality of upper sacrificial layers.

16. The method of claim 15, wherein the upper insulating spacer in the insulating spacer is formed prior to the lower insulating spacer in the insulating spacer.

17. The method of claim 15, wherein the upper insulating spacer in the insulating spacer is formed simultaneously with the lower insulating spacer in the insulating spacer.

18. The method of claim 14, wherein the initial transistor stack further includes a bottom sacrificial layer located below the plurality of lower sacrificial layers, wherein the bottom sacrificial layer is thinner than the sacrificial layers and thicker than each of the plurality of lower sacrificial layers, wherein the method further includes: Remove the bottom sacrificial layer; A bottom isolation layer is formed in the opening created by removing the bottom sacrificial layer; And after forming the isolation layer and the bottom isolation layer, the plurality of lower sacrificial layers and the plurality of upper sacrificial layers are removed, wherein forming the lower gate includes forming the lower gate in an opening formed by removing the plurality of lower sacrificial layers, and wherein forming the upper gate includes forming the upper gate in an opening formed by removing the plurality of upper sacrificial layers.

Images