Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, a III-V compound semiconductor layer, a gate structure, a drain structure, and a field plate. The III-V compound semiconductor layer is disposed on the substrate. The gate structure, drain structure, and field plate are disposed on the III-V compound semiconductor layer. The field plate is located between the gate structure and the drain structure. The field plate includes a first arcuate sidewall located at the edge of the field plate near the drain structure. The first arcuate sidewall of the field plate can be used to improve the electric field distribution in the semiconductor device, thereby improving the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device including a III-V compound semiconductor layer and a method for manufacturing the same. Prior Art

[0002] Due to their semiconducting properties, III-V semiconductor compounds can be used to form a variety of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors (HFSTs), and high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined at the junction to form a heterojunction, providing a channel for carriers. In recent years, gallium nitride (GaN) materials have become suitable for high-power and high-frequency applications due to their wide band gap and high saturation velocity. GaN HEMTs utilize the piezoelectric effect of the material itself to generate a two-dimensional electron gas (2DEG), which has high electron velocity and density, thereby increasing switching speed. Therefore, further improving the electrical performance of transistors formed using III-V compound materials through design changes in materials, structures, and / or fabrication methods has been a research focus for researchers in this field. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, which utilizes a field plate with curved sidewalls to improve the electric field distribution in the semiconductor device, thereby enhancing the electrical performance of the semiconductor device.

[0004] One embodiment of the present invention provides a semiconductor device comprising a substrate, a III-V compound semiconductor layer, a gate structure, a drain structure, and a field plate. The III-V compound semiconductor layer is disposed on the substrate, while the gate structure, the drain structure, and the field plate are disposed above the III-V compound semiconductor layer. The field plate is positioned between the gate structure and the drain structure and includes a first curved sidewall located at an edge of the field plate proximal to the drain structure.

[0005] One embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a III-V compound semiconductor layer on a substrate, and forming a gate structure, a field plate, and a drain structure on the III-V compound semiconductor layer. The field plate is positioned between the gate structure and the drain structure, and includes a first curved sidewall located at an edge of the field plate near the drain structure. Simple diagram description

[0006] FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. FIG2 to FIG5 are schematic diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 3 shows a schematic diagram of the situation after Figure 2; Figure 4 shows a schematic diagram of the situation after Figure 3; FIG. 5 is a schematic diagram showing the situation after FIG. 4 . Implementation Method

[0007] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the invention.

[0008] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0009] The terms “on,” “over,” and “over” are to be interpreted in the broadest sense, such that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0010] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0011] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0012] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0013] Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1 , semiconductor device 100 includes a substrate 10, a III-V compound semiconductor layer 12, a gate structure GE, a drain structure DE, and a field plate FP. The III-V compound semiconductor layer 12 is disposed on substrate 10, while the gate structure GE, the drain structure DE, and the field plate FP are disposed above the III-V compound semiconductor layer 12. The field plate FP is positioned between the gate structure GE and the drain structure DE. The field plate FP includes a first curved sidewall CS1 located at an edge of the field plate FP near the drain structure DE. The first curved sidewall CS1 of the field plate FP can improve the electric field distribution within the semiconductor device 100, for example, but not limited to, improving the corona effect, thereby enhancing the electrical performance of the semiconductor device 100.

[0014] To further illustrate, in some embodiments, the substrate 10 may have a top surface 10TS and a bottom surface 10BS opposite each other in a vertical direction (e.g., direction D1 shown in FIG. 1 ), and the aforementioned III-V compound semiconductor layer 12, gate structure GE, drain structure DE, and field plate FP may be disposed on one side of the top surface 10TS. In some embodiments, direction D1 may be considered the thickness direction of the substrate 10, and horizontal directions generally perpendicular to direction D1 (e.g., direction D2 and other directions perpendicular to direction D1) may be generally parallel to the top surface 10TS and / or the bottom surface 10BS of the substrate 10, but this is not limited to the above. As described herein, a relatively higher position or / and the distance between a component and the bottom surface 10BS of the substrate 10 in the direction D1 may be greater than a relatively lower position or / and the distance between a component and the bottom surface 10BS of the substrate 10 in the direction D1; the lower portion or bottom portion of each component may be closer to the bottom surface 10BS of the substrate 10 in the direction D1 than the upper portion or top portion of the component; another component above a certain component may be considered to be relatively far away from the bottom surface 10BS of the substrate 10 in the direction D1, and another component below a certain component may be considered to be relatively close to the bottom surface 10BS of the substrate 10 in the direction D1.

[0015] In some embodiments, the field plate FP in the semiconductor device 100 can be used to partially deplete the two-dimensional electron gas (2DEG) beneath the region it covers, thereby weakening the electric field in the off-state. By altering the electric field distribution, the field plate can achieve the effects of increasing the breakdown voltage and / or suppressing current collapse. In some embodiments, the field plate FP in FIG. 5 can be viewed as a partially enlarged schematic diagram of the field plate FP in FIG. As shown in FIG. 1 and FIG. 5 , a first curved sidewall CS1 of the field plate FP can be recessed toward a top surface TS1 of the field plate FP. The first curved sidewall CS1 can be directly connected to the top surface TS1 of the field plate FP at a first portion P1 of the field plate FP, and can be directly connected to a bottom surface BS1 of the field plate FP at a second portion P2 of the field plate FP. In other words, the first portion P1 of the field plate FP may include the portion where the first curved sidewall CS1 connects to the top surface TS1, while the second portion P2 of the field plate FP may include the portion where the first curved sidewall CS1 connects to the bottom surface BS1. In some embodiments, the top surface TS1 may be considered the topmost surface of the field plate FP in the direction D1, and the bottom surface BS1 may be considered the bottommost surface of the field plate FP in the direction D1. The first portion P1 may be considered the topmost portion of the edge of the field plate FP near the drain structure DE in the direction D1, while the second portion P2 may be considered the bottommost portion of the edge of the field plate FP near the drain structure DE in the direction D1, but this is not limiting. Furthermore, the portion where the first curved sidewall CS1 connects to the top surface TS1 and the portion where the first curved sidewall CS1 connects to the bottom surface BS1 may lie on a straight line L. Because the first curved sidewall CS1 of the field plate FP is recessed toward the top surface TS1 of the field plate FP, the straight line L may be located below the first curved sidewall CS1 in the direction D1.

[0016] In some embodiments, the angle between the top surface TS1 and the first curved sidewall CS1 may be smaller than the angle between the bottom surface BS1 and the first curved sidewall CS1, and the distance DS1 between the first portion P1 of the field plate FP and the drain structure DE in a horizontal direction (e.g., direction D2) may be smaller than the distance DS2 between the second portion P2 of the field plate FP and the drain structure DE in direction D2. In some embodiments, the angle between the top surface TS1 and the first curved sidewall CS1 may include an angle A1 between a tangent plane PL1 on the first curved sidewall CS1 near the junction of the first curved sidewall CS1 and the top surface TS1, and the angle between the bottom surface BS1 and the first curved sidewall CS1 may include an angle A1 between a tangent plane PL1 on the first curved sidewall CS1 near the junction of the first curved sidewall CS1 and the bottom surface BS1, but the invention is not limited thereto. The angles between the tangent plane on the first curved sidewall CS1 and the top surface TS1 and bottom surface BS1 may vary depending on the position of the tangent plane on the first curved sidewall CS1. However, the angle between the tangent plane and the top surface TS1 is less than 90 degrees, while the angle between the tangent plane and the bottom surface BS1 is greater than 90 degrees. Furthermore, the portion where the first curved sidewall CS1 and the top surface TS1 connect can be considered the tip of the field plate FP. With this design, the distance between the tip of the field plate FP and the III-V compound semiconductor layer 12 in direction D1 can be relatively increased. Therefore, when the field plate FP is used to achieve the aforementioned function, the problem of tip discharge can be alleviated, thereby improving the electrical performance of the semiconductor device 100 (for example, but not limited to, improving the breakdown voltage of the semiconductor device 100) and / or product reliability.

[0017] In some embodiments, the field plate FP may be a conductive structure, such as a metal conductive structure formed from a single layer or multiple layers of a metal conductive material, but is not limited thereto. For example, the field plate FP may include a single layer of a metal conductive material (e.g., titanium nitride) or multiple layers of metal conductive materials stacked on top of each other (e.g., a three-layer structure formed from titanium nitride, aluminum, and titanium nitride). In some embodiments, the field plate FP may be directly connected to the gate structure GE, and the material composition of the field plate FP may be the same as that of the gate structure GE. For example, the field plate FP and the gate structure GE may be formed from the same conductive material layer 40, but is not limited thereto. Furthermore, in some embodiments, the relative position of the field plate FP in direction D1 and / or direction D2 may be adjusted to produce a desired effect in the semiconductor device 100. Thus, the top surface TS1 of the field plate FP may be lower than a top surface TS2 of the gate structure GE in direction D1, but is not limited thereto.

[0018] In some embodiments, the semiconductor device 100 may further include a source structure SE disposed on the III-V compound semiconductor layer 12. At least a portion of the source structure SE and at least a portion of the drain structure DE may be located on opposite sides of the gate structure GE in the direction D2. One end of the gate structure GE in the direction D2 may be directly connected to the field plate FP, while the other end of the gate structure GE in the direction D2 may be considered an edge of the gate structure GE near the source structure SE. In some embodiments, the gate structure GE may include a second curved sidewall CS2 located at the edge of the gate structure GE near the source structure SE. The shape and related technical features of the second curved sidewall CS2 may be similar to, but not limited to, the first curved sidewall CS1 described above. For example, the second curved sidewall CS2 may be recessed toward the top surface TS2 of the gate structure GE, which may be the uppermost surface of the gate structure GE in the direction D1. The second curved sidewall CS2 may be directly connected to the top surface TS2 at the edge of the gate structure GE. Furthermore, the second curved sidewall CS2 may be directly connected to the upper surface TS2 at an upper portion of the edge of the gate structure GE near the source structure SE, and the second curved sidewall CS2 may be directly connected to a lower surface of the gate structure GE at a lower portion of the edge of the gate structure GE near the source structure SE. The distance between the upper portion of the edge of the gate structure GE and the source structure SE in the direction D2 may be smaller than the distance between the lower portion of the edge of the gate structure GE and the source structure SE in the direction D2, but the present invention is not limited thereto.

[0019] The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or other suitable materials, and the III-V compound semiconductor layer 12 may include gallium nitride, indium gallium nitride (InGaN), or other suitable III-V compound semiconductor materials. The source structure SE and the drain structure DE may include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer, but are not limited thereto. In some embodiments, the source structure SE and the drain structure DE may further include another barrier layer disposed on the metal layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive barrier materials, and the metal layer may include tungsten, copper, aluminum, a titanium-aluminum alloy, an aluminum-copper alloy, or other suitable conductive metal materials. In some embodiments, a buffer layer (not shown) may be disposed between the III-V compound semiconductor layer 12 and the substrate 10. The buffer layer may include, for example, gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable buffer materials.

[0020] In some embodiments, semiconductor device 100 may further include a III-V compound barrier layer 14, an isolation structure 16, a P-type doped III-V compound layer 20, a barrier layer 22, a dielectric layer 24, a dielectric layer 26, and a dielectric layer 30. III-V compound barrier layer 14 may be disposed on III-V compound semiconductor layer 12 and may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride, aluminum nitride (AlN), or other suitable III-V compound materials. Isolation structure 16 may be at least partially disposed within III-V compound semiconductor layer 12 and III-V compound barrier layer 14 to provide isolation. Isolation structure 16 may include a single layer or multiple layers of insulating material. A p-type doped III-V compound layer 20 may be disposed on the III-V compound barrier layer 14. The p-type doped III-V compound layer 20 may include p-type doped aluminum gallium nitride, p-type doped gallium nitride, or other suitable p-type doped III-V compound materials. The p-type dopant in the p-type doped III-V compound layer 20 may include magnesium, beryllium (Be), zinc (Zn), cyclopentadienyl magnesium (Cp2Mg), combinations of the foregoing materials, or other suitable p-type dopants. A barrier layer 22 may be disposed on the p-type doped III-V compound layer 20. The barrier layer 22 may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive barrier materials. A dielectric layer 24 may be conformally disposed on the III-V compound barrier layer 14, the p-type doped III-V compound layer 20, and the barrier layer 22. A dielectric layer 26 may be conformally disposed on the dielectric layer 24. The dielectric layer 24 may include an oxide dielectric material (eg, aluminum oxide) or other suitable dielectric materials, and the dielectric layer 26 may include an oxide dielectric material (eg, tetraethoxysilane, TEOS), a nitride dielectric material, or other suitable dielectric materials.

[0021] The gate structure GE may penetrate the dielectric layer 26 and the dielectric layer 24 in the direction D1 and contact the barrier layer 22. The gate structure GE may also be electrically connected to the P-type doped III-V compound layer 20 through the barrier layer 22, but this is not limited to the embodiment. In some embodiments, a bottom surface BS2 of the gate structure GE may be directly connected to the barrier layer 22. The bottom surface BS1 of the field plate FP may be higher than the bottom surface BS2 of the gate structure GE in the direction D1, and the bottom surface BS2 may be considered the bottommost surface of the gate structure GE in the direction D1, but this is not limited to the embodiment. A dielectric layer 30 may be disposed on the dielectric layer 26 and may include multiple layers of dielectric material, such as tetraethoxysilane, silicon oxide, silicon nitride, or other suitable dielectric materials. In some embodiments, at least a portion of the gate structure GE may be considered to be disposed in the dielectric layer 30, and a portion of the dielectric layer 30 may cover the gate structure GE in the direction D1. The source structure SE and the drain structure DE may penetrate the dielectric layer 30, the dielectric layer 26, the dielectric layer 24, and the III-V compound barrier layer 14 in the direction D1 and be partially disposed in the III-V compound semiconductor layer 12, but the present invention is not limited thereto.

[0022] Please refer to Figures 1 to 5. Figures 2 to 5 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 3 illustrates a state subsequent to Figure 2, Figure 4 illustrates a state subsequent to Figure 3, and Figure 5 illustrates a state subsequent to Figure 4. In some embodiments, Figures 2 to 5 can be considered as schematic diagrams illustrating a method for fabricating a field plate in a semiconductor device, but this is not limiting. As shown in Figure 1, the method for fabricating a semiconductor device 100 of this embodiment may include the following steps: A III-V compound semiconductor layer 12 is formed on a substrate 10, and a gate structure GE, a field plate FP, and a drain structure DE are formed on the III-V compound semiconductor layer 12. The field plate FP is located between the gate structure GE and the drain structure DE, and includes a first curved sidewall CS1 located at an edge of the field plate FP near the drain structure DE.

[0023] To further illustrate, the method for fabricating the semiconductor device 100 of this embodiment may include, but is not limited to, the following steps. A III-V compound semiconductor layer 12 may be formed on the upper surface 10TS of the substrate 10, and a III-V compound barrier layer 14 may be formed on the III-V compound semiconductor layer 12. In some embodiments, an isolation structure 16 may be at least partially formed in the III-V compound semiconductor layer 12 and the III-V compound barrier layer 14 to provide isolation and / or define an active region of the corresponding semiconductor device 100. A p-type doped III-V compound layer 20 may be formed on the III-V compound barrier layer 14, and a barrier layer 22 may be formed on the p-type doped III-V compound layer 20. A dielectric layer 24 may be conformally formed on the III-V compound barrier layer 14, the p-type doped III-V compound layer 20, and the barrier layer 22, and a dielectric layer 26 may be conformally formed on the dielectric layer 24. In addition, a portion of the dielectric layer 30 (eg, the dielectric layer 32 shown in FIG. 2 ) may be formed on the dielectric layer 26 , and after this portion of the dielectric layer 30 is formed, the aforementioned gate structure GE and field plate FP may be formed.

[0024] In some embodiments, the method for forming the field plate FP may include, but is not limited to, the following steps. As shown in FIG. 2 , a conductive material layer 40 may be formed on the dielectric layer 32, and a patterned photoresist layer 50 may be formed on the conductive material layer 40. Then, as shown in FIG. 3 , an etching process 90 may be performed on the conductive material layer 40 using the patterned photoresist layer 50 as an etching mask. A portion of the conductive material layer 40 may be patterned by the etching process 90 to form the field plate FP. In some embodiments, the etchant used in the etching process 90 may contain fluorine, but is not limited thereto. For example, the etching process 90 may include a dry etching process, and the reactant gas used in the dry etching process may include carbon tetrafluoride (CF 4 ), octafluorocyclobutane (C 4 F 8 ), or other suitable fluorine-containing reactant gases. Furthermore, during the etching process 90, by-products 92 may be formed. The by-products 92 may accumulate on the surface of the dielectric layer 32 and contact the sidewalls SW of the field plate FP. The by-products 92 may include fluorine-containing by-products, particularly when the etchant used in the etching process 90 contains fluorine, but the invention is not limited thereto.

[0025] As shown in Figures 3 and 4 , in some embodiments, a portion of the dielectric layer 32 may be removed by the etching process 90. This condition can be considered to be caused by an overetch design. The overetch design is used to ensure that a portion of the conductive material layer 40 is completely removed by the etching process 90 to form the field plate FP. In some embodiments, this overetch design may result in the formation of more byproducts 92, increasing the chance that the byproducts 92 will contact the field plate FP and react with the sidewalls SW of the field plate FP. As shown in Figures 4 and 5 , in some embodiments, the byproducts 92 may accumulate upward from the surface of the dielectric layer 32 and first contact the lower portion of the sidewalls SW of the field plate FP. The sidewalls SW of the field plate FP can then be etched by the byproducts 92 to form the first curved sidewalls CS1 described above. Furthermore, after the etching process 90, the patterned photoresist layer 50 and the byproducts 92 may be removed. As shown in Figures 4, 5, and 1, in some embodiments, the conductive material layer 40 can be patterned by an etching process 90 to simultaneously form a field plate FP and a gate structure GE. Thus, a portion of the conductive material layer 40 can be patterned by the etching process 90 to form a field plate FP having a first curved sidewall CS1, while another portion of the conductive material layer 40 can be patterned by the etching process 90 to form a gate structure GE having a second curved sidewall CS2. The second curved sidewall CS2 can be formed in the same manner as, but not limited to, the first curved sidewall CS1. It is worth noting that, in the present invention, the method for fabricating the field plate FP having the first curved sidewall CS1 is not limited to the method shown in Figures 2 to 5 above. Other suitable methods can be used to form the field plate FP having the first curved sidewall CS1 shown in Figure 1, depending on design requirements.

[0026] As shown in FIG. 5 and FIG. 1 , after forming the field plate FP having the first curved sidewall CS1, other portions of the dielectric layer 30 (e.g., portions outside the dielectric layer 32) may be formed, along with the source structure SE and the drain structure DE. In some embodiments, the source structure SE and the drain structure DE may be formed on the III-V compound semiconductor layer 12 and extend through the dielectric layer 30, the dielectric layer 26, the dielectric layer 24, and the III-V compound barrier layer 14 in a direction D1, but the present invention is not limited thereto.

[0027] In summary, in the semiconductor device and its manufacturing method of the present invention, a field plate with curved sidewalls can be formed. The curved sidewalls can improve the electric field distribution and / or alleviate problems such as tip discharge in the semiconductor device while maintaining the function of the field plate, thereby improving the electrical performance and / or product reliability of the semiconductor device. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0028] 10: Base 10BS: bottom surface 10TS: Top surface 12: III-V compound semiconductor layer 14: III-V compound barrier layer 16: Isolation Structure 20: P-type doped III-V compound layer 22: Barrier layer 24: Dielectric layer 26: Dielectric layer 30: Dielectric layer 32: Dielectric layer 40: conductive material layer 50: Patterned photoresist layer 90: Etching process 92: Byproduct 100:Semiconductor device A1: Angle A2: Angle BS1: bottom surface BS2: bottom surface CS1: first curved side wall CS2: Second curved side wall D1: Direction D2: Direction DE: Drain structure DS1: Distance DS2: Distance FP: Field Plate GE: Gate structure L: Straight line P1: Part 1 P2: Part 2 PL1: Cutting plane PL2: Cutting plane SE: Source structure SW: Sidewall TS1: Top surface TS2: Top surface

Claims

1. A semiconductor device, comprising: One base; A III-V compound semiconductor layer is disposed on the substrate; A gate structure is disposed on the III-V compound semiconductor layer; a drain structure is disposed on the III-V compound semiconductor layer; and a field plate is disposed on the III-V compound semiconductor layer and located between the gate structure and the drain structure, wherein the field plate includes a first arcuate sidewall located at an edge of the field plate near the drain structure, the first arcuate sidewall being directly connected to an upper surface of the field plate at a first portion of the field plate, and the first arcuate sidewall being directly connected to a bottom surface of the field plate at a second portion of the field plate, and the horizontal distance between the first portion of the field plate and the drain structure is less than the horizontal distance between the second portion of the field plate and the drain structure.

2. The semiconductor device as claimed in claim 1, wherein the first arcuate sidewall is recessed toward the upper surface of the field plate.

3. The semiconductor device as claimed in claim 1, wherein the angle between the upper surface and the first arcuate sidewall is smaller than the angle between the bottom surface and the first arcuate sidewall.

4. The semiconductor device as described in claim 1, further comprising: A source structure is disposed on the III-V compound semiconductor layer, wherein the gate structure includes a second arcuate sidewall located at an edge of the gate structure near the source structure.

5. The semiconductor device as claimed in claim 4, wherein the second arcuate sidewall is recessed toward an upper surface of the gate structure.

6. The semiconductor device as claimed in claim 1, wherein the material composition of the field plate is the same as the material composition of the gate structure.

7. The semiconductor device as claimed in claim 1, wherein the field plate is directly connected to the gate structure, and the upper surface of the field plate is lower than an upper surface of the gate structure in a vertical direction.

8. The semiconductor device as claimed in claim 1, wherein the field plate is a metallic conductive structure.

9. A method for manufacturing a semiconductor device, comprising: A III-V compound semiconductor layer is formed on a substrate; a gate structure is formed on the III-V compound semiconductor layer; A field plate is formed on the III-V compound semiconductor layer; and a drain structure is formed on the III-V compound semiconductor layer, wherein the field plate is located between the gate structure and the drain structure, and the field plate includes a first arcuate sidewall located at an edge of the field plate near the drain structure, wherein a method of forming the field plate includes: performing an etching process on a conductive material layer, wherein a portion of the conductive material layer is patterned by the etching process to form the field plate, the etchant used in the etching process contains fluorine, a fluorine-containing byproduct is formed in the etching process, and a sidewall of the field plate is etched by the fluorine-containing byproduct to form the first arcuate sidewall.

10. A method of fabricating a semiconductor device as claimed in claim 9, wherein another portion of the conductive material layer is patterned by the etching process to form the gate structure.

11. A method of manufacturing a semiconductor device as claimed in claim 9, wherein the first arcuate sidewall is recessed toward an upper surface of the field plate.

12. A method of manufacturing a semiconductor device as claimed in claim 9, wherein the first arcuate sidewall is directly connected to an upper surface of the field plate at a first portion thereof, and the first arcuate sidewall is directly connected to a bottom surface of the field plate at a second portion thereof.

13. A method of manufacturing a semiconductor device as claimed in claim 12, wherein the angle between the upper surface and the first arcuate sidewall is smaller than the angle between the bottom surface and the first arcuate sidewall.

14. A method of manufacturing a semiconductor device as claimed in claim 12, wherein the distance between the first portion of the field plate and the drain structure in a horizontal direction is less than the distance between the second portion of the field plate and the drain structure in the same horizontal direction.

15. The method for manufacturing a semiconductor device as described in claim 9, further comprising: A source structure is formed on the III-V compound semiconductor layer, wherein the gate structure includes a second arcuate sidewall located at an edge of the gate structure near the source structure.

16. A method of manufacturing a semiconductor device as claimed in claim 15, wherein the second arcuate sidewall is recessed toward an upper surface of the gate structure.

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