High electron mobility transistor and method for forming the same

Abstract

A high electron mobility transistor includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a gate spacer disposed on the gate structure, and a gate contact disposed on the gate spacer. The gate contact includes a first portion and a second portion located on both sides of the gate spacer and in contact with the gate structure.

Description

High electron mobility transistor and method for manufacturing the same The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a high electron mobility transistor and a manufacturing method thereof. High electron mobility transistors (HEMTs) are an emerging field-effect transistor (FET). They utilize a potential well formed at the heterojunction by joining semiconductor materials of different band gaps. This potential well gathers electrons to form a two-dimensional electron gas (2DEG), which serves as the current channel. Gallium nitride (GaN) compounds, a member of the III-V semiconductor family, exhibit wide band gaps, high breakdown voltages, strong bonding strengths, thermal stability, and unique spontaneous and piezoelectric polarization properties. These compounds can form a 2DEG with high electron concentration and high electron mobility even in the undoped state, achieving high switching speeds and response frequencies. Consequently, they have gradually replaced silicon-based transistors and are widely used in power converters, low-noise amplifiers, and radio frequency (RF) and millimeter wave (MMW) technologies. The enhancement-mode GaN high-electron-mobility transistors commonly used in the industry primarily consist of a p-type gallium nitride / aluminum gallium nitride / gallium nitride (p-GaN / AlGaN / GaN) heterostructure. The p-GaN layer is patterned into a gate structure, and a bias voltage is applied to the p-GaN layer via a metal gate contact to control the switching of the two-dimensional channel region. In the absence of a bias voltage, the built-in voltage of the p-GaN layer raises the energy band between the AlGaN and GaN layers, depleting the two-dimensional electron gas layer and achieving normally-off operation of the transistor. However, existing enhancement-mode high-electron-mobility transistors (EMHMTs) still face challenges. In particular, the strong electric field generated within the p-GaN layer during transistor operation triggers hot carrier bombardment. Over time, this leads to the accumulation of numerous defects at the interface between the p-GaN layer and the metal gate. These defects then percolate into gate leakage paths, negatively impacting device performance and reliability. The present invention aims to provide an enhanced high electron mobility transistor and a method for manufacturing the same, which can improve the problems of the conventional technology. One embodiment of the present invention provides a high electron mobility transistor, comprising a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a gate spacer disposed on the gate structure, and a gate contact disposed on the gate spacer. The gate contact comprises a first portion and a second portion, respectively located on opposite sides of the gate spacer and in contact with the gate structure. Another embodiment of the present invention provides a method for manufacturing a high electron mobility transistor, comprising the following steps. First, a substrate is provided, and then a channel layer and a barrier layer are formed on the substrate and the channel layer. Next, a gate structure is formed on the barrier layer, and a passivation layer is formed to cover the gate structure and the barrier layer. Next, a first opening and a second opening are formed through the passivation layer directly above the gate structure, and a conductive layer is formed on the passivation layer to fill the first and second openings. Subsequently, the conductive layer is patterned to form a gate contact. The high electron mobility transistor of the present invention utilizes a gate spacer disposed on the gate structure to divide the contact area between the gate structure and the gate contact into a first contact area and a second contact area, thereby reducing the electric field strength within the gate structure when operating the transistor, thereby reducing the generation of hot carriers, thereby achieving the effect of improving leakage and component reliability. To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present disclosure. To facilitate understanding and simplify the illustrations, the various figures in this disclosure depict only a portion of the display device, and certain components in the figures are not drawn to scale. Furthermore, the number and size of components in the figures are for illustrative purposes only and are not intended to limit the scope of this disclosure. In the figures, identical or similar components may be denoted by the same reference numerals. References to the upper and lower relationships between relative components in the figures described herein should be understood by those skilled in the art to refer to the relative positions of the objects, and therefore, the figures can be flipped to present the same components, all of which fall within the scope of this disclosure. In this specification, when an element or film layer is referred to as being "on" or "connected to" another element or film layer, it can be directly on or directly connected to the other element or film layer, or other elements or films may be present between the two elements or films. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there are no intervening elements or films. Throughout this specification, the terms "wafer," "substrate," or "substrate" refer to any structure with an exposed surface upon which materials may be deposited to form integrated circuit structures according to the embodiments of the present invention. It should be understood that "substrate" includes, but is not limited to, semiconductor wafers. In the context of manufacturing, "substrate" also refers to a semiconductor structure including the material layers formed thereon. Figures 1 to 6 illustrate the steps of a method for manufacturing a high electron mobility transistor 10A according to a first embodiment of the present invention. Referring to Figure 1, a substrate 10 is first provided. A heteroepitaxial stack is then formed on the substrate 10, including, from bottom to top, a buffer layer 12, a channel layer 14, a barrier layer 16, and a gate material layer 180. A patterning process (e.g., photolithography and etching) is then performed to pattern the gate material layer 180 into the gate structure 18 shown in Figure 1. For ease of illustration and to aid understanding of the structure of the high electron mobility transistor according to the present invention, spatial reference directions D1, D2, and D3 are shown. Directions D1 and D2 are perpendicular to each other and parallel to the surface of the substrate 10. Direction D3 is perpendicular to the surface of the substrate 10. According to one embodiment of the present invention, in a top view, the gate structure 18 is an elongated strip-shaped structure extending along direction D1 and having a width W4 along direction D2 (see FIG. 3 , where the dashed lines represent the sidewalls 18 a and 18 b of the gate structure 18 ). In some embodiments, an etch stop layer 20 may be optionally formed on the gate material layer 180 and then patterned. As a result, the top surface 18 s of the gate structure 18 is covered by the etch stop layer 20. The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, or a substrate formed of other suitable materials. The buffer layer 12, the channel layer 14, and the barrier layer 16 may each have a single-layer or multi-layer structure and may each include a III-V semiconductor compound material, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), graded aluminum gallium nitride (graded AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), doped gallium nitride (doped GaN), aluminum nitride (AlN), or a combination thereof, but not limited thereto. According to one embodiment of the present invention, the buffer layer 12 may be made of aluminum gallium nitride (AlGaN), the channel layer 14 may be made of gallium nitride (GaN), and the barrier layer 16 may be made of aluminum gallium nitride (AlGaN). The gate structure 18 (gate material layer 180) may include, but is not limited to, an N-type doped Group III-V semiconductor material, an N-type doped Group II-VI semiconductor material, an undoped Group III-V semiconductor material, an undoped Group II-VI semiconductor material, a P-type doped Group III-V semiconductor material, or a P-type doped Group II-VI semiconductor material. According to one embodiment of the present invention, the gate structure 18 comprises p-type gallium nitride (p-GaN) containing magnesium (Mg), iron (Fe), or other suitable doping materials. The etch stop layer 20 may include a dielectric material such as aluminum nitride (AlN), aluminum oxide (Al 2O 3) Boron nitride (BN), silicon nitride (SiN), silicon oxide (SiO 2) Zirconium oxide (ZrO 2) Hafnium oxide (HfO 2) Lanthanum oxide (La 2O 3) Lutetium oxide 2O 3) Lanthanum lutetium oxide (LaLuO 3) High-k dielectric material or other suitable dielectric material. According to one embodiment of the present invention, the etch stop layer 20 includes silicon nitride (SiN). Please refer to Figures 2 and 3. Next, a passivation layer 22 is formed to cover the barrier layer 16 and the gate structure 18, and then a patterning process (such as lithography and etching) is performed to form a first opening 24 and a second opening 26 that pass through the passivation layer 22 and the etching stop layer 20 directly above the gate structure 18 and respectively expose the first contact region R1 and the second contact region R2 of the gate structure 18. At the same time, a gate spacer SP composed of the passivation layer 22 is obtained between the first opening 24 and the second opening 26. The passivation layer 22 is composed of a dielectric material and can be a single layer or a multi-layer structure. Applicable dielectric materials may include silicon oxide (SiO 2) Silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al 2O 3) Aluminum nitride (AlN), boron nitride (BN), zirconium oxide (ZrO 2) Hafnium oxide (HfO 2) Lanthanum oxide (La 2O 3) Lutetium oxide 2O 3) Lanthanum lutetium oxide (LaLuO 3), high-k dielectric materials, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), but not limited thereto. According to one embodiment of the present invention, the passivation layer 22 may include silicon monoxide (SiO According to one embodiment of the present invention, the bottom layer of the passivation layer 22 may further include aluminum oxide (Al 2O 3) Thin layer (not shown) It should be noted that when an etch stop layer 20 is disposed on the top surface 18 s of the gate structure 18 , the gate spacer SP may further include the etch stop layer 20 between the first opening 24 and the second opening 26 . As shown in the top view of FIG. 3 , the first opening 24 and the second opening 26 are elongated strip-shaped openings disposed parallel to the gate structure 18 . They extend along the length of the gate structure 18 (i.e., along direction D1 ) and have widths W1 and W2 , respectively, along direction D2 . That is, the first contact region R1 and the second contact region R2 extend parallel to each other along direction D1 and have widths W1 and W2 , respectively. According to one embodiment of the present invention, widths W1 and W2 are equal. The distance between the first opening 24 and the second opening 26 determines the width W3 of the gate spacer SP. According to one embodiment of the present invention, widths W3, W1, and W2 are equal. The outer sidewalls 24a of the first opening 24 and the outer sidewalls 26a of the second opening 26 may be aligned with the sidewalls 18a and 18b of the gate structure 18, respectively, or, as shown in this embodiment, may be recessed inward (toward the gate spacer SP) by a certain distance. According to one embodiment of the present invention, the distance L1 by which the outer sidewall 24a of the first opening 24 is recessed from the sidewall 18a of the gate structure 18 may be between 0 nm and 1 / 10 of the width W1 of the first opening 24, but is not limited thereto. The distance L2 by which the outer sidewall 26a of the second opening 26 is recessed from the sidewall 18b of the gate structure 18 may be between 0 nm and 1 / 10 of the width W2 of the second opening 26, but is not limited thereto. When the distances L1 and L2 are greater than 0 nm, the sum of the widths W1, W2, and W3 is less than the width W4 of the gate structure 18. In some embodiments, the etching process (e.g., reactive ion etching or inductively coupled plasma etching) for forming the first opening 24 and the second opening 26 may include over-etching the exposed portion of the gate structure 18 to ensure that no residual passivation layer 22 and etch stop layer 20 remain at the bottom of the opening, thereby forming slightly recessed first and second contact regions R1 and R2. Therefore, the first and second contact regions R1 and R2 are not coplanar with the top surface 18s of the gate structure 18 and are lower than the bottom surface of the gate spacer SP. Please refer to Figures 4 and 5. Next, a conductive layer 30 is formed on the passivation layer 22, filling the first opening 24 and the second opening 26. The conductive layer 30 is then patterned (e.g., photolithography and etching) to remove excess portions of the conductive layer 30, thereby forming a gate contact 36. According to one embodiment of the present invention, the conductive layer 30 may include a liner 32 directly contacting the gate structure 18 and the passivation layer 22, and a metal layer 34 located on the liner 32 and filling the first opening 24 and the second opening 26. The material of the liner 32 may include, but is not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. The material of the metal layer 34 may include, but is not limited to, titanium (Ti), molybdenum (Mo), platinum (Pt), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), copper (Cu), or compounds, composite layers, or alloys thereof. According to one embodiment of the present invention, the liner layer 32 may include titanium nitride (TiN), and the metal layer 34 may include aluminum copper (AlCu). As shown in FIG. 4 , the gate contact 36 has an integrally formed structure, including a first portion 36a and a second portion 36b located on either side of the gate spacer SP, respectively, and a connecting portion 36c located on the passivation layer 22 and crossing the gate spacer SP to connect the first portion 36a and the second portion 36b. The first portion 36a directly contacts the first contact region R1 of the gate structure 18, and the second portion 36b directly contacts the second contact region R2 of the gate structure 18. According to one embodiment of the present invention, by selecting suitable materials for the liner 32, metal layer 34, and gate structure 18, and optionally performing an annealing process, Schottky contacts with rectifying properties can be obtained between the first portion 36a and the first contact region R1, and between the second portion 36b and the second contact region R2. As shown in the top view of FIG. 5 , the first portion 36a and the second portion 36b extend parallel to each other along the length of the gate structure 18 (i.e., along direction D1), and have widths equal to the width W1 of the first opening 24 and the width W2 of the second opening 26, respectively. According to one embodiment of the present invention, the width W5 of the connecting portion 36c may be greater than the width W4 of the gate structure 18. From the top view, the sidewalls 36d and 36e of the connecting portion 36c are located outside the sidewalls 18a and 18b of the gate structure 18, respectively. In some embodiments, the sidewalls S1 of the first portion 36a and the sidewalls S2 of the second portion 36b are respectively recessed from the sidewalls 18a and 18b of the gate structure 18 by distances L1 and L2, respectively. This reduces the electric field strength at the sidewalls of the gate structure 18 during transistor operation, thereby reducing gate leakage caused by sidewall parasitic transistors. Please refer to Figure 6. Next, another passivation layer 23 is formed on the passivation layer 22 and covers the gate contact 36. Then, one or more patterning processes (e.g., photolithography and etching) are performed to form a source opening OP1 and a drain opening OP2 located on both sides of the gate contact 36 and penetrating the passivation layer 23, the passivation layer 22, and the barrier layer 16 to expose a portion of the channel layer 14. There is also an opening OP3 located directly above the gate contact 36 and penetrating the passivation layer 23 to expose a portion of the gate contact 36. Next, a conductive layer 40 is formed on the passivation layer 23 and fills the source opening OP1, the drain opening OP2, and the opening OP3. Then, the conductive layer 40 is patterned (e.g., photolithography and etching) to remove excess portions of the conductive layer 40, thereby forming the source contact 46S, the drain contact 46D, and the conductive structure 52. According to one embodiment of the present invention, the conductive layer 40 may include a liner 42 that directly contacts the passivation layer 22, the gate contact 36, and the channel layer 14, and a metal layer 44 located on the liner 42 and filling the source opening OP1, the drain opening OP2, and the opening OP3. The materials for the liner 42 and the metal layer 44 may refer to the materials for the liner 32 and the metal layer 34 described above, respectively. The materials for the passivation layer 23 may refer to the materials for the passivation layer 22 described above, and for simplicity, these details are not repeated here. According to one embodiment of the present invention, the liner 42 may include titanium nitride (Ti), and the metal layer 44 may include aluminum copper (AlCu). The passivation layer 23 may include silicon nitride (SiN). According to one embodiment of the present invention, by selecting appropriate materials for the liner 42 and metal layer 44 and optionally performing an annealing process, low-resistance ohmic contacts can be obtained between the source contact 46S, the drain contact 46D, and the channel layer 14. At this point in the process, a high electron mobility transistor 10A according to the first embodiment of the present invention is obtained. As shown in FIG6 , the high electron mobility transistor 10A includes a substrate 10, a channel layer 14 disposed on the substrate 10, a barrier layer 16 disposed on the channel layer 14, a gate structure 18 disposed on the barrier layer 16, a gate spacer SP disposed on the gate structure 18, a gate contact 36 disposed on the gate spacer SP, and a source contact 46S and a drain contact 46D located on either side of the gate structure 18, respectively, penetrating the barrier layer 16 and contacting the channel layer 14. The junction of the channel layer 14c and the barrier layer 16 includes a two-dimensional electron gas (2DEG) layer 14a, which serves as the channel region of the high electron mobility transistor 10A. Gate contact 36 applies a bias voltage to the gate structure 18 to control the conduction and cutoff of current in the channel region between the source contact 46S and the drain contact 46D, thereby enabling the on / off operation of the high electron mobility transistor 10A. The present invention utilizes gate spacers SP to allow the gate contact 36 to contact the first and second contact regions R1 and R2 of the separated gate structure 18. This adjusts the electric field strength within the gate structure 18 during transistor operation, thereby reducing hot carrier generation and improving gate leakage and reliability issues caused by hot carrier bombardment. Furthermore, the present invention utilizes etching of the passivation layer 22 to define the position and pattern of the first and second contact regions R1 and R2, enabling convenient integration with conventional high electron mobility transistor manufacturing processes to improve device quality. The following describes various embodiments of the present invention. To simplify the description, the following focuses on the differences between the various embodiments, without reiterating the similarities. Identical components in each embodiment are labeled with the same reference numerals to facilitate cross-reference between the various embodiments. Please refer to FIG7, which is a cross-sectional view of a high electron mobility transistor 10B according to a second embodiment of the present invention. The main difference between this embodiment and the embodiment shown in FIG6 is that this embodiment forms the source contact 46S and the drain contact 46D first, and then forms the gate contact 36. For example, after forming the passivation layer 22 to cover the barrier layer 16 and the gate structure 18, a source contact 46S and a drain contact 46D are formed on both sides of the gate structure 18 through the passivation layer 22 and the barrier layer 16 to contact the channel layer 14. Then, a passivation layer 23 is formed on the passivation layer 22 to cover the source contact 46S and the drain contact 46D. Then, one or more patterning processes are performed to form a first opening 24 and a second opening 26 (marked in Figure 2) that pass through the passivation layer 23, the passivation layer 22 and the etching stop layer 20 directly above the gate structure 18 and respectively expose the first contact region R1 and the second contact region R2 of the gate structure 18, as well as an opening OP4 and an opening OP5 that pass through the passivation layer 23 to respectively expose part of the top surface of the source contact 46S and the drain contact 46D. Next, a conductive layer 30 is formed on the passivation layer 23 to fill the first opening 24, the second opening 26, the opening OP4, and the opening OP5. Excess portions of the conductive layer 30 are then removed, resulting in the gate contact 36, the conductive structure 54, and the conductive structure 56 shown in FIG7 . The gate spacer SP in the embodiment shown in FIG7 is formed by the passivation layer 22 and the passivation layer 23. When an etch stop layer 20 is provided on the gate structure 18, the gate spacer SP may further include the etch stop layer 20 between the first contact region R1 and the second contact region R2. Please refer to FIG8 , which is a schematic cross-sectional view of a high electron mobility transistor 10C according to a third embodiment of the present invention. The primary difference between this embodiment and the embodiment shown in FIG6 is that this embodiment simultaneously forms the gate contact 36 , source contact 46S, and drain contact 46D. For example, after forming the passivation layer 22 to cover the barrier layer 16 and gate structure 18 , one or more patterning processes may be performed to form a first opening 24 and a second opening 26 (shown in FIG2 ) through the passivation layer 22 and etch stop layer 20 directly above the gate structure 18, respectively exposing the first contact region R1 and the second contact region R2 of the gate structure 18. Furthermore, a source opening OP1 and a drain opening OP2 (shown in FIG6 ) are formed through the passivation layer 22 and barrier layer 16 on either side of the gate structure 18 to expose a portion of the channel layer 14. Then, a conductive layer 30 is formed on the passivation layer 22 to fill the first opening 24, the second opening 26, the source opening OP1 and the drain opening OP2. Then, excess portions of the conductive layer 30 are removed to obtain the gate contact 36, the source contact 46S and the drain contact 46D as shown in FIG. 8. Please refer to Figures 9 and 10, which are schematic diagrams of the steps of the manufacturing method of the high electron mobility transistor 10D of the fourth embodiment of the present invention. The main difference between this embodiment and the embodiment shown in Figure 6 is that the first part 36a, the second part 36b and the connecting part 36c of the gate contact 36 of this embodiment are not formed as a single piece. In detail, as shown in Figure 9, after forming the conductive layer 30 to fill the first opening 24 and the second opening 26 (marked in Figure 2), the conductive layer 30 outside the first opening 24 and the second opening 26 can be removed by etching back or chemical mechanical polishing process to obtain the first part 36a and the second part 36b located on both sides of the gate spacer SP and respectively contacting the first contact region R1 and the second contact region R2 of the gate structure 18. Next, a passivation layer 23 is formed on the passivation layer 22, covering the gate spacer SP and the first and second portions 36a and 36b. One or more patterning processes are then performed to form a source opening OP1 and a drain opening OP2 (shown in FIG. 6 ) on both sides of the gate structure 18, penetrating the passivation layer 23, the passivation layer 22, and the barrier layer 16 to expose a portion of the channel layer 14. Furthermore, an opening OP6 is formed through the passivation layer 23 directly above the gate structure 18, exposing the first and second portions 36a and 36b. Subsequently, a conductive layer 40 is formed on the passivation layer 23, filling the source opening OP1, the drain opening OP2, and the opening OP6. Excess portions of the conductive layer 40 are then removed, resulting in the connection portion 36c, the source contact 46S, and the drain contact 46D shown in FIG. 10 . In summary, the present invention addresses the gate leakage problem of enhanced high electron mobility transistors (EMHMTs) by providing a gate spacer between the metal gate contact and the semiconductor gate structure, thereby separating the contact region into a first contact region and a second contact region. This allows for adjustment of the electric field strength within the gate structure during transistor operation, thereby reducing hot carrier generation and improving gate leakage and reliability issues caused by hot carrier bombardment. The foregoing is merely a preferred embodiment of the present invention, and all equivalent variations and modifications within the scope of the present invention are intended to be covered by the present invention. 10: substrate 12: buffer layer 14: channel layer 16: barrier layer 18: gate structure 20: etch stop layer 22: passivation layer 23: passivation layer 24: first opening 26: second opening 30: conductive layer 32: liner 34: metal layer 36: gate contact 40: conductive layer 42: liner 44: metal layer 180: gate material layer 10A: high electron mobility transistor 10B: high electron mobility transistor 10C: high electron mobility transistor 10D: high electron mobility transistor 14a: two-dimensional electron gas layer 18a: sidewall 18b: sidewall 1 8s: Top surface 24a: Outer sidewall 26a: Outer sidewall 36a: First portion 36b: Second portion 36c: Connecting portion 36d: Sidewall 36e: Sidewall 46D: Drain contact 46S: Source contact D1: Direction D2: Direction D3: Direction L1: Distance L2: Distance OP1: Opening OP2: Opening OP3: Opening OP4: Opening OP5: Opening OP6: Opening R1: First contact region R2: Second contact region SP: Gate spacer S1: Sidewall S2: Sidewall W1: Width W2: Width W3: Width W4: Width W5: Width Figures 1 to 6 illustrate the steps of a method for manufacturing a high electron mobility transistor according to a first embodiment of the present invention. Figures 1, 2, 4, and 6 are schematic cross-sectional views, Figure 3 is a top view of the step shown in Figure 2, and Figure 5 is a top view of the step shown in Figure 4. Figure 7 illustrates a schematic cross-sectional view of a high electron mobility transistor according to a second embodiment of the present invention. Figure 8 illustrates a schematic cross-sectional view of a high electron mobility transistor according to a third embodiment of the present invention. Figures 9 and 10 illustrate the steps of a method for manufacturing a high electron mobility transistor according to a fourth embodiment of the present invention. 10: Base 12: Buffer layer 14: Channel layer 16: Barrier layer 18: Gate structure 18a: Side wall 18b: Sidewall 20: Etch stop layer 22: passivation layer 30: conductive layer 32: Lining 34:Metal layer 36: Gate contact 36a: Part 1 36b: Part 2 36c: Connecting part 36d: side wall 36e: Sidewall S1: Sidewall S2: Sidewall D1: Direction D2: Direction D3: Direction L1: distance L2: distance R1: first contact area R2: Second contact area SP: Gate spacer W1: width W2: width W3: Width W4: Width W5: width

Claims

1. A high electron mobility transistor, comprising: One base; A channel layer is disposed on this substrate; A barrier layer is set on this channel layer; A gate structure is disposed on the barrier layer; a gate spacer is disposed on the gate structure; and a gate contact is disposed on the gate spacer, and includes a first portion and a second portion respectively located on both sides of the gate spacer and in contact with the gate structure, wherein the gate structure includes a first Schottky contact region in contact with the first portion and a second Schottky contact region in contact with the second portion.

2. The high electron mobility transistor as described in claim 1, wherein the first portion includes a first width, the second portion includes a second width, the gate spacer includes a spacer width, and the gate structure includes a gate width, wherein the first width is equal to the second width.

3. The high electron mobility transistor as described in claim 2, wherein the width of the spacer, the first width, and the second width are equal.

4. The high electron mobility transistor as described in claim 2, wherein the sum of the first width, the second width, and the spacer width is less than the gate width.

5. The high electron mobility transistor as described in claim 1, wherein the outer walls of the first portion and the second portion are respectively recessed a distance from one side wall of the gate structure toward the gate spacer.

6. The high electron mobility transistor as described in claim 1, wherein the first Schottky contact region, the second Schottky contact region, and the gate structure are not coplanar on a top surface covered by the gate spacer.

7. The high electron mobility transistor as described in claim 1 further includes: A passivation layer is disposed on the barrier layer and the gate structure, wherein the gate contact further includes a connecting portion disposed on the gate spacer and the passivation layer and connecting the first portion and the second portion; and a source contact and a drain contact are respectively located on both sides of the gate structure and penetrate the passivation layer and the barrier layer to contact the channel layer.

8. The high electron mobility transistor as described in claim 7, wherein the connecting portion, the first portion, and the second portion are integrally formed.

9. The high electron mobility transistor as described in claim 7, wherein the gate separator and the passivation layer comprise the same material.

10. The high electron mobility transistor as described in claim 1, wherein, in a top view, the first portion and the second portion extend in the same direction as the gate structure.

11. A method for manufacturing a high electron mobility transistor, comprising: Provide a base; A channel layer is formed on the substrate and a barrier layer is formed on the channel layer; A gate structure is formed on the barrier layer; a passivation layer is formed to cover the gate structure and the barrier layer; a first opening and a second opening are formed through the passivation layer directly above the gate structure; a conductive layer is formed on the passivation layer and fills the first opening and the second opening. The conductive layer is patterned to form a gate contact, wherein the gate contact includes: a first portion located in the first opening; a second portion located in the second opening; and a connecting portion located on the passivation layer and connecting the first portion and the second portion, wherein the first portion forms a first Schottky contact region with the gate structure, and the second portion forms a second Schottky contact region with the gate structure.

12. A method for manufacturing a high electron mobility transistor as described in claim 11, wherein the gate structure includes a gate width, the first opening includes a first width, the second opening includes a second width, and the first opening and the second opening are separated by a distance, wherein the first width and the second width are equal.

13. A method for manufacturing a high electron mobility transistor as described in claim 12, wherein the distance, the first width, and the second width are equal.

14. A method for manufacturing a high electron mobility transistor as described in claim 12, wherein the sum of the first width, the second width, and the distance is less than the gate width.

15. A method for manufacturing a high electron mobility transistor as described in claim 11, wherein the outer walls of the first opening and the second opening are respectively recessed inward from one side wall of the gate structure by a distance.

16. A method for manufacturing a high electron mobility transistor as described in claim 11, wherein the first Schottky contact region, the second Schottky contact region, and the gate structure are not coplanar on a top surface covered by the passivation layer.

17. The method for manufacturing a high electron mobility transistor as described in claim 11 further includes: A source opening and a drain opening are formed on both sides of the gate structure and penetrate the passivation layer and the barrier layer to expose part of the channel layer; Another conductive layer is formed on the barrier layer and fills the source opening and the drain opening; and the other conductive layer is patterned to form a source contact and a drain contact.

18. A method for manufacturing a high electron mobility transistor as described in claim 11, wherein the connecting portion, the first portion, and the second portion are integrally formed.

19. A method of manufacturing a high electron mobility transistor as described in claim 11, wherein, in a top view, the first opening and the second opening extend in the same direction as the gate structure.

Images