Optical detection element and optical detection device

Abstract

The photodetector element and photodetector device of this invention optimize the pixel layout. An amplification unit generates a signal corresponding to the charge held in a charge holding unit and outputs it to a specific first output node. One end of a first capacitor element is connected to the first output node and holds the signal level (i.e., the reset level) when reset by a first reset unit. One end of a second capacitor element is connected to the first output node and holds the signal level (i.e., the image signal level) when the charge is transferred to the charge holding unit. A readout circuit is connected to the second output node and reads the reset level held in the first capacitor element and the image signal level held in the second capacitor element, respectively, and outputs them as a reset signal and an image signal.

Description

Technical Field

[0001] This disclosure relates to a photodetector element and a photodetector device. Prior Technology

[0002] A light detection element is used to generate an image of the subject. This light detection element is composed of a two-dimensional matrix of pixels having photoelectric conversion elements. Furthermore, the light detection element outputs the generated image by repeatedly performing: exposure to perform photoelectric conversion of light from the subject, and reading out the image signal from the pixels based on the charge generated by the photoelectric conversion.

[0003] In this pixel, the charge generated during exposure via photoelectric conversion is stored inside the photoelectric conversion element. After the exposure period, the charge stored in the photoelectric conversion element is transferred to a charge holding section. This charge holding section can be constructed using a floating diffusion layer formed from a diffusion region on the semiconductor substrate forming the photoelectric conversion element. An amplifying transistor is connected to this charge holding section to generate a signal corresponding to the charge held in the floating diffusion layer. This signal generation method is called a floating diffusion amplifier. Furthermore, the floating diffusion layer is reset by a reset section to remove any residual charge before charge transfer.

[0004] On the other hand, readout is performed sequentially for each column of pixels arranged in a two-dimensional matrix. At this time, readout is performed simultaneously for pixels arranged in one column. As a method for generating this image, rolling shutter mode and global shutter mode are used.

[0005] The rolling shutter method involves sequential exposure and readout at staggered intervals for each sequence, simplifying the configuration of the light detection element. However, because the exposure sequence differs for each sequence, the rolling shutter method can cause distortion in the image when photographing moving subjects.

[0006] Global shutter mode exposes all pixels simultaneously and retains the charge generated during the exposure period. Readout is performed sequentially for each column based on the retained charge. By exposing all pixels simultaneously with a global shutter, image distortion can be prevented. Since there is time between the end of the exposure and readout, the charge is transferred to a second charge retention section, which is different from the aforementioned floating diffuser layer. During readout, a signal is generated based on the charge in the second charge retention section. Because the floating diffuser layer is adjacent to the photoelectric conversion element, there is a problem of charge overlapping with the floating diffuser layer due to leaked incident light. To prevent image quality degradation caused by this, a second charge retention section is necessary.

[0007] In light detection elements employing this global shutter method, the industry has proposed applying capacitor elements to the light detection element in the second charge holding section. For example, the industry has proposed a light detection element (imaging element) with a sample-and-hold circuit having two capacitor elements for each pixel (for example, see Patent Document 1). [Previous Technical Documents] [Patent Literature]

[0008] Patent Document 1: U.S. Patent Application Publication No. 2020 / 279876 Summary of the Invention

[0009] [The problem the invention aims to solve]

[0010] However, in the aforementioned prior art, since the floating diffusion layer (floating diffusion region) and the reset transistor are configured separately in the pixel, there is a problem of increased noise. This is because it is difficult to remove residual charge from the floating diffusion layer by the reset transistor.

[0011] Therefore, in this disclosure, an optimal pixel layout is proposed for a light detection element employing a global shutter method. [Technical means to solve the problem]

[0012] The disclosed photodetector includes: a photoelectric conversion unit formed on a semiconductor substrate, which generates a charge corresponding to incident light; a charge transfer unit that transfers the charge to a charge holding unit that holds the charge; a first reset unit disposed adjacent to the charge holding unit and resets the charge holding unit; an amplification unit that generates a signal corresponding to the charge held in the charge holding unit and outputs it to a specific first output node; a constant current circuit connected to the first output node and constituting the load of the amplification unit; a first capacitor element, one end of which is connected to the first output node and holds the level of the signal during the reset performed by the first reset unit, i.e., the reset level; and a second capacitor element, one end of which is connected to the first output node and holds the signal at the reset level. The signal level when the charge is transferred to the charge holding section is the image signal level; a first switching element is connected between the other end of the first capacitor element and a specific second output node, and controls the current flowing in the first capacitor element; a second switching element is connected between the other end of the second capacitor element and the second output node, and controls the current flowing in the second capacitor; a second reset section resets the second output node; a readout circuit is connected to the second output node, and reads the reset level held in the first capacitor element and the image signal level held in the second capacitor element, and outputs them as a reset signal and an image signal; and a substrate contact supplies a reference potential to the semiconductor substrate. Simple Explanation of the Diagram

[0013] Figure 1 is a diagram showing an example of the configuration of the optical detection device according to an embodiment of the present disclosure. Figure 2 is a diagram showing an example of the pixel configuration of the first embodiment of this disclosure. Figure 3 is a cross-sectional view showing an example of the pixel configuration of the first embodiment of this disclosure. Figure 4 is a diagram showing an example of the configuration of a capacitor element according to an embodiment of the present disclosure. Figure 5 is a top view showing an example of the pixel composition of the first embodiment of this disclosure. Figure 6 is a diagram showing an example of the generation of image signals in the first embodiment of this disclosure. Figure 7 is a diagram showing an example of the generation of image signals in the first embodiment of this disclosure. Figure 8 is a diagram showing an example of the pixel composition of the second embodiment of this disclosure. Figure 9 is a top view showing an example of the pixel composition of the second embodiment of this disclosure. Figure 10A is a top view showing another example of the pixel configuration of the second embodiment of this disclosure. Figure 10B is a top view showing another example of the pixel configuration of the second embodiment of this disclosure. Figure 11 is a diagram showing an example of the pixel configuration of the third embodiment of this disclosure. Figure 12 is a top view showing an example of the pixel configuration of the third embodiment of this disclosure. Figure 13 is a top view showing another example of the pixel configuration of the third embodiment of this disclosure. Figure 14 is a diagram showing an example of the pixel configuration of the fourth embodiment of this disclosure. Figure 15 is a top view showing an example of the pixel configuration of the fourth embodiment of this disclosure. Figure 16 is a diagram showing an example of the pixel configuration of the fifth embodiment of this disclosure. Figure 17 is a cross-sectional view showing an example of the pixel configuration of the fifth embodiment of this disclosure. Figure 18 is a cross-sectional view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 19A is a top view showing an example of the pixel configuration of the fifth embodiment of this disclosure. Figure 19B is a top view showing an example of the pixel configuration of the fifth embodiment of this disclosure. Figure 20A is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 20B is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 21A is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 21B is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 22A is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 22B is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 23 is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figure 24 is a diagram showing an example of the pixel configuration of the sixth embodiment of this disclosure. Figure 25A is a top view showing an example of the pixel configuration of the sixth embodiment of this disclosure. Figure 25B is a top view showing an example of the pixel configuration of the sixth embodiment of this disclosure. Figure 26A is a diagram showing an example of the configuration of the imaging element in the seventh embodiment of this disclosure. Figure 26B is a diagram showing an example of the configuration of the imaging element in the seventh embodiment of this disclosure. Figure 27 is a cross-sectional view showing an example of the configuration of the camera element in the seventh embodiment of this disclosure. Figure 28 is a cross-sectional view showing another configuration example of the imaging element of the seventh embodiment of this disclosure. Figure 29 is a diagram showing another example of the configuration of the camera element in the seventh embodiment of this disclosure. Figure 30 is a cross-sectional view showing another configuration example of the camera element of the seventh embodiment of this disclosure. Figure 31 is a cross-sectional view showing another configuration example of the imaging element of the seventh embodiment of this disclosure. Figure 32 is a diagram showing another configuration example of the camera element according to the seventh embodiment of this disclosure. Figure 33 is a cross-sectional view showing another example of the configuration of the camera element in the seventh embodiment of this disclosure. Figure 34 is a cross-sectional view showing another configuration example of the imaging element of the seventh embodiment of this disclosure. Figure 35 is a diagram showing an example of the configuration of the optical detection device according to the eighth embodiment of this disclosure. Figure 36 is a top view showing an example of the pixel configuration of the eighth embodiment of this disclosure. Figure 37 is a cross-sectional view showing an example of the pixel configuration of the eighth embodiment of this disclosure. Figure 38 is a diagram showing an example of the configuration of the capacitor additional wiring in the eighth embodiment of this disclosure. Figure 39 is a cross-sectional view showing an example of the pixel configuration of the ninth embodiment of this disclosure. Figure 40A is a diagram showing an example of the configuration of the capacitor additional wiring of the ninth embodiment of this disclosure. Figure 40B is a diagram showing an example of the configuration of the capacitor additional wiring of the ninth embodiment of this disclosure. Figure 41 is a top view showing an example of the pixel configuration of the tenth embodiment of this disclosure. Figure 42 is a cross-sectional view showing an example of the pixel configuration of the tenth embodiment of this disclosure. Figure 43 is a diagram showing an example of the configuration of the light detection device according to the 11th embodiment of this disclosure. Figure 44 is a top view showing an example of the pixel configuration of the 11th embodiment of this disclosure. Figure 45 is a top view showing another example of the pixel configuration of the 11th embodiment of this disclosure. Figure 46 is a top view showing another example of the pixel configuration of the 11th embodiment of this disclosure. Figure 47 is a diagram showing an example of the configuration of the optical detection device according to the 12th embodiment of this disclosure. Figure 48A is a top view showing an example of the pixel configuration of the 12th embodiment of this disclosure. Figure 48B is a top view showing an example of the pixel configuration of the 12th embodiment of this disclosure. Figure 48C is a top view showing an example of the pixel configuration of the 12th embodiment of this disclosure. Figure 49A is a top view showing an example of the pixel configuration of the 12th embodiment of this disclosure. Figure 49B is a top view showing an example of the pixel configuration of the 12th embodiment of this disclosure. Figure 50 is a top view showing an example of the pixel configuration of the 13th embodiment of this disclosure. Figure 51A is a top view showing another example of the pixel configuration of the 13th embodiment of this disclosure. Figure 51B is a top view showing another example of the pixel configuration of the 13th embodiment of this disclosure. Figure 52A is a cross-sectional view showing an example of the configuration of the capacitor additional wiring of the 14th embodiment of this disclosure. Figure 52B is a cross-sectional view showing an example of the configuration of capacitor additional wiring in the 14th embodiment of this disclosure. Figure 52C is a cross-sectional view showing an example of the configuration of capacitor additional wiring in the 14th embodiment of this disclosure. Figure 53 is a diagram illustrating one example of the general configuration of a camera system having the above-described embodiments and variations thereof. Figure 54 shows an example of the camera sequence of the camera system shown in Figure 54. Figure 55 is a block diagram showing one example of the general configuration of a vehicle control system. Figure 56 is an explanatory diagram showing one example of the installation location of the vehicle exterior information detection unit and camera unit. Figure 57 is a diagram showing one example of the general configuration of an endoscopic surgical system. Figure 58 is a block diagram showing one example of the functional configuration of a camera head and CCU. Implementation

[0014] The following is a detailed description of the embodiments disclosed herein, based on the drawings. The description proceeds in the following order. Furthermore, in each of the following embodiments, repeated descriptions are omitted by assigning the same symbol to the same part. 1. First Implementation Form 2. Second Implementation Form 3. Third Implementation Form 4. Fourth Implementation Form 5. Fifth Implementation Form 6. Sixth Implementation Form 7. Seventh Implementation Form 8. Eighth Implementation Form 9. Ninth Implementation Form 10. Tenth Implementation Form 11. 11th Implementation Form 12. Twelfth Implementation Form 13. Thirteenth Implementation Form 14. Implementation Form 14 15. Applicable Examples 16. Examples of applications for moving bodies 17. Examples of the application of endoscopic surgical systems

[0015] (1. First Implementation) [Composition of Camera Components] Figure 1 is a diagram showing an example of the configuration of the light detection device according to an embodiment of the present disclosure. This figure is a block diagram showing an example of the configuration of the light detection device 1. The light detection device 1 is a semiconductor element that generates image data of a subject. The light detection device 1 includes: a pixel array unit 10, a vertical drive unit 20, a horizontal signal processing unit 30, and a control unit 40.

[0016] The pixel array section 10 is configured with a plurality of pixels 100. The pixel array section 10 in this figure represents an example of a two-dimensional matrix arrangement of a plurality of pixels 100. Here, each pixel 100 has a photoelectric conversion unit that performs photoelectric conversion of incident light, generating an image signal of the subject based on the incident light. For example, a photodiode can be used for this photoelectric conversion unit. Signal lines 11 and 12 are wired to each pixel 100. Pixel 100 is controlled by a control signal transmitted via signal line 11 to generate an image signal, and outputs the generated image signal via signal line 12. Furthermore, signal lines 11 are arranged in each column of the two-dimensional matrix shape and are commonly wired for a plurality of pixels 100 arranged in one column. Signal lines 12 are arranged in each row of the two-dimensional matrix shape and are commonly wired for a plurality of pixels 100 arranged in one row.

[0017] The vertical drive unit 20 generates control signals for the aforementioned pixel 100. In this figure, the vertical drive unit 20 generates control signals for each column of the two-dimensional matrix of the pixel array unit 10 and outputs them sequentially via signal lines 11.

[0018] The line signal processing unit 30 processes the image signals generated by the pixels 100. This line signal processing unit 30 simultaneously processes the image signals transmitted via signal lines 12 from a plurality of pixels 100 arranged in each column of the pixel array unit 10. This processing may include, for example, analog-to-digital conversion (APC) to convert the analog image signals generated by the pixels 100 into digital image signals, and correlated double sampling (CDS) to remove offset errors in the image signals. The processed image signal is output to external circuitry of the light detection device 1.

[0019] The control unit 40 controls the vertical drive unit 20 and the horizontal signal processing unit 30. In this figure, the control unit 40 outputs control signals via signal lines 41 and 42 respectively to control the vertical drive unit 20 and the horizontal signal processing unit 30. Furthermore, the pixel array unit 10 is an example of a light detection element described within the scope of the patent application. The horizontal signal processing unit 30 is an example of a processing circuit described within the scope of the patent application.

[0020] [Pixel Composition] Figure 2 is a diagram showing an example of the pixel configuration according to the first embodiment of this disclosure. This figure is a circuit diagram illustrating an example of the configuration of pixel 100. Pixel 100 in this figure includes: a front-end circuit 110, a constant current circuit 105, a signal level holding circuit 130, and a rear-end circuit 120. Signal lines OFG, TRG, FDG, RST, VB, PC, SW, S1, S2, RB, and SEL are wired in pixel 100. These signal lines constitute signal line 11. Furthermore, signal line VSL is connected to pixel 100. This signal line VSL constitutes signal line 12. In addition, power lines Vdd and Vreg are wired in pixel 100. Power line Vdd supplies power to pixel 100 and supplies the reset voltage to the first reset unit 116 described later. The power supply line Vreg is the power supply line that supplies the reset voltage to the second reset unit 121 described later. Furthermore, an n-channel MOS transistor can be used for the MOS transistor configured in this figure.

[0021] The front-end circuit 110 is a circuit that generates a signal corresponding to the incident light. The front-end circuit 110 outputs the generated signal to the first output node 101. The front-end circuit 110 in this figure includes: a photoelectric conversion unit 111, a charge holding unit 112, a second charge holding unit 113, a charge discharge unit 114, a charge transfer unit 115, a first reset unit 116, a coupling unit 117, an amplification unit 118, and a first selection unit 119.

[0022] The anode of the photoelectric conversion unit 111 is grounded, and the cathode is connected to the source of the charge discharge unit 114 and the source of the charge transfer unit 115. The drain of the charge discharge unit 114 is connected to the power supply line Vdd. The drain of the charge transfer unit 115 is connected to the source of the coupling unit 117, the gate of the amplification unit 118, and one end of the charge holding unit 112. The other end of the charge holding unit 112 is grounded. The drain of the coupling unit 117 is connected to the source of the first reset unit 116 and one end of the second charge holding unit 113. The other end of the second charge holding unit 113 is grounded. The drain of the first reset unit 116 is connected to the power supply line Vdd. The drain of the amplification unit 118 is connected to the power supply line Vdd, and its source is connected to the drain of the first selection unit 119. The source of the first selection unit 119 is connected to the first output node 101. Signal lines OFG, TRG, FDG, RST, and SW are respectively connected to the gates of the charge discharge section 114, the charge transfer section 115, the coupling section 117, the first reset section 116, and the first selection section 119.

[0023] The photoelectric conversion unit 111 is responsible for converting incident light into photoelectric light. The photoelectric conversion unit 111 may be composed of a photodiode formed on a semiconductor substrate.

[0024] The charge discharge section 114 is used to discharge and reset the charge accumulated in the photoelectric conversion section 111. In this figure, the charge discharge section 114 discharges the charge accumulated in the photoelectric conversion section 111 to the power line Vdd.

[0025] The charge transfer unit 115 transfers the charge from the photoelectric conversion unit 111 to the charge holding unit 112. The charge transfer unit 115 transfers the charge by making the photoelectric conversion unit 111 and the charge holding unit 112 conductive.

[0026] The charge holding section 112 retains the charge generated by photoelectric conversion by the photoelectric conversion section 111. The aforementioned floating diffusion layer can be used for the charge holding section 112.

[0027] The second charge holding section 113 holds the charge generated by photoelectric conversion by the photoelectric conversion section 111. The second charge holding section 113 holds the charge when coupled to the charge holding section 112.

[0028] The coupling portion 117 couples the charge holding portion 112 and the second charge holding portion 113. The coupling portion 117 couples the second charge holding portion 113 to the charge holding portion 112 by connecting the second charge holding portion 113 in parallel to the charge holding portion 112. This coupling increases the holding capacitance of the charge generated by the photoelectric conversion unit 111, allowing for sensitivity adjustment.

[0029] The first reset unit 116 resets the charge holding unit 112. This first reset unit 116 resets the charge holding unit 112 by discharging the charge from the charge holding unit 112 to the power line Vdd. In this figure, the first reset unit 116 resets the charge holding unit 112 via the coupling unit 117. Furthermore, the first reset unit 116 further resets the second charge holding unit 113.

[0030] The amplification unit 118 generates a signal corresponding to the charge held in the charge holding unit 112. The amplification unit 118 and the constant current circuit 105 connected via the first output node 101 together form a source follower circuit, which outputs the generated signal to the first output node 101.

[0031] The first selection unit 119 outputs the signal generated by the amplification unit 118 to the first output node 101. This first selection unit 119 is connected between the amplification unit 118 and the first output node 101, and transmits the signal from the amplification unit 118 to the first output node 101 by being itself conductive. By configuring the first selection unit 119 and setting it to a non-conductive state, the leakage current when the amplification unit 118 is in the off state can be reduced. Furthermore, the first selection unit 119 is one example of a selection unit described in the claims.

[0032] Furthermore, the second charge holding section 113 and the coupling section 117 can also be omitted. In this case, the first reset section 116 is directly connected to the charge holding section 112. Also, the first selection section 119 can also be omitted. In this case, the amplification section 118 is directly connected to the first output node.

[0033] The constant current circuit 105 is a constant current circuit that constitutes the load of the aforementioned amplification section 118. The constant current circuit 105 supplies a constant current sink current to the first output node 101. The constant current circuit 105 in this figure includes MOS transistors 109 and 108.

[0034] The drain of MOS transistor 109 is connected to the first output node 101, and its source is connected to the drain of MOS transistor 108. The source of MOS transistor 108 is grounded. The gates of MOS transistor 108 and MOS transistor 109 are connected to signal line VB and signal line PC, respectively.

[0035] Signal lines VB and PC respectively transmit bias voltages. MOS transistor 109 applies the bias voltage from signal line PC to its gate, supplying a constant current corresponding to the applied bias voltage. Similarly, MOS transistor 108 applies the bias voltage from signal line VB to its gate, supplying a constant current corresponding to the applied bias voltage. As shown in the figure, by connecting two MOS transistors in series and supplying different bias voltages to each gate, noise reduction can be achieved. Furthermore, output current fluctuations due to power supply voltage variations can be reduced. Alternatively, either MOS transistors 108 or 109 can be omitted.

[0036] The signal level holding circuit 130 is connected to the first output node 101 and is a circuit that holds the level of the signal output from the preceding circuit 110. The signal level holding circuit 130 in this figure includes: a first capacitor element 131, a second capacitor element 132, a first switch element 135, and a second switch element 136.

[0037] One end of the first capacitor element 131 and one end of the second capacitor element 132 are commonly connected to the first output node 101. The other ends of the first capacitor element 131 and the second capacitor element 132 are respectively connected to the source of the first switching element 135 and the source of the second switching element 136. The drain of the first switching element 135 and the drain of the second switching element 136 are commonly connected to the second output node 102. The gate of the first switching element 135 and the gate of the second switching element 136 are respectively connected to signal line S1 and signal line S2.

[0038] The first capacitor element 131 is a capacitor element that maintains the signal level during the reset performed by the first reset unit 116, i.e., the reset level.

[0039] The second capacitor element 132 is a capacitor element that holds the signal level, i.e. the image signal level, when the charge of the photoelectric conversion unit 111 is transferred to the charge holding unit 112 by the charge transfer unit 11 and held thereafter.

[0040] The first switching element 135 is used to control the current flowing through the first capacitor element 131. The first switching element 135 is connected between the first capacitor element 131 and the second output node 102.

[0041] The second switching element 136 is used to control the current flowing through the second capacitor element 132. The second switching element 136 is connected between the second capacitor element 132 and the second output node 102.

[0042] The downstream circuit 120 generates and outputs an image signal corresponding to the signal levels held at the first capacitor element 131 and the second capacitor element 132. The downstream circuit 120 in this figure includes a second reset unit 121, a second amplification unit 122, and a second selection unit 123.

[0043] The source of the second reset section 121 and the gate of the second amplification section 122 are commonly connected to the second output node 102. The drain of the second reset section 121 is connected to the power supply line Vreg. The drain of the second amplification section 122 is connected to the power supply line Vdd, and its source is connected to the drain of the second selection section 123. The source of the second selection section 123 is connected to the signal line VSL.

[0044] The second reset unit 121 resets the second output node 102. The second reset unit 121 performs the reset by applying the voltage of the power line Vreg to the second output node 102.

[0045] The second amplification unit 122 is a component that generates a signal corresponding to the voltage of the second output node 102. The second amplification unit 122 reads the reset level held at the first capacitor element 131 and the image signal level held at the second capacitor element 132, and generates them as the reset signal and the image signal, respectively.

[0046] The second selection unit 123 is a component that outputs the signal generated by the second amplification unit 122 to the signal line VSL. The second selection unit 123 is connected between the second amplification unit 122 and the signal line VSL, and transmits the signal from the second amplification unit 122 to the signal line VSL by being itself conductive. Furthermore, the circuitry of the second amplification unit 122 and the second selection unit 123 constitutes a readout circuit.

[0047] Furthermore, the configuration of pixel 100 is not limited to this example. For example, the charge discharge section 114 may be omitted. In this case, the charge of photoelectric conversion section 111 can be discharged by turning on the charge transfer section 115 and the first reset section 116.

[0048] [The Composition of a Pixel's Cross-Section] Figure 3 is a cross-sectional view showing an example of the configuration of a pixel according to the first embodiment of the present disclosure. The figure shows a cross-sectional view of an example of the configuration of pixel 100. The pixel 100 in the figure includes: a semiconductor substrate 150, insulating films 160 and 191, a wiring area 170, a color filter 192, a planarization film 193, and a crystal lens 194.

[0049] The semiconductor substrate 150 is a semiconductor substrate on which the diffusion layer of the element of the pixel 100 is disposed. The semiconductor substrate 150 may be made of, for example, silicon (Si). Elements such as the photoelectric conversion unit 111 may be disposed in the well region formed on the semiconductor substrate 150. For convenience, it is envisioned that the semiconductor substrate 150 in this figure is configured as a p-type well region. By disposing an n-type or p-type semiconductor region in this well region, the diffusion layer of the element can be formed. In this figure, the photoelectric conversion unit 111, the charge holding unit 112, the charge transport unit 115, and the charge discharge unit 114 are described as examples.

[0050] The photoelectric conversion unit 111 is composed of an n-type semiconductor region 141. Specifically, the photodiode formed by the pn junction of the n-type semiconductor region 142 and the surrounding p-type well region corresponds to the photoelectric conversion unit 111. During exposure, the charge generated by photoelectric conversion by the photoelectric conversion unit 111 is stored in the n-type semiconductor region 142. After the exposure period, the stored charge is transferred to the charge holding unit 112 by the charge transfer unit 115 and held therein.

[0051] The charge holding section 112 is composed of a semiconductor region 143. This semiconductor region is an n-type semiconductor region with a high impurity concentration. The semiconductor region 143 corresponds to the aforementioned floating diffusion layer.

[0052] The charge transfer section 115 is composed of a MOS transistor disposed between the photoelectric conversion section 111 and the charge holding section. Specifically, the charge transfer section 115 uses semiconductor regions 142 and 143 as the source region and drain region, respectively, and has a MOS transistor with a channel forming region between semiconductor regions 142 and 143. A gate 162 is disposed adjacent to the region forming the channel.

[0053] The charge discharge section 114 is composed of a MOS transistor disposed adjacent to the photoelectric conversion section 111. Specifically, the charge discharge section 114 is a MOS transistor that uses semiconductor region 142 and semiconductor region 144 as the source region and drain region, respectively, and has a channel forming region between semiconductor region 142 and semiconductor region 143. A gate 161 is disposed adjacent to the region forming the channel.

[0054] Furthermore, a semiconductor region 141 is further depicted on the semiconductor substrate 150 in this figure. This semiconductor region 141 is a p-type semiconductor region with a high impurity concentration. A well contact 107, which will be described later, is connected to this semiconductor region 141. Hereinafter, the semiconductor region connected to the well contact will be referred to as the well contact region.

[0055] The insulating film 160 is a film that insulates the front side of the semiconductor substrate 150. The insulating film 160 may be made of silicon oxide (SiO2) or silicon nitride (SiN). In addition, the insulating film 160 directly below the gates 161 and 162 constitutes the gate insulating film.

[0056] The wiring region 170 is disposed on the front side of the semiconductor substrate 150 and is the area where the wiring of the pixel 100 is disposed. The wiring region 170 includes wiring 172 and an insulating layer 171. Wiring 172 transmits signals of the elements of the pixel 100. Wiring 172 may be made of a conductor such as copper (Cu) or tungsten (W). Insulating layer 171 insulates wiring 172 and the like. Insulating layer 171 may be made of, for example, SiO2.

[0057] The wiring 172 can be connected to the semiconductor region 143 or gate 162 of the semiconductor substrate 150 via contact plugs 173. These contact plugs 173 can be made of, for example, columnar tungsten. Furthermore, wirings 172 disposed on different layers can be connected to each other via through-hole plugs 174. These through-hole plugs 174 can be made of, for example, columnar Cu.

[0058] A well contact 107 is disposed in the semiconductor region 141 constituting the well contact area. This well contact 107 supplies a reference potential to the well region of the semiconductor substrate 150. Here, the reference potential is a reference potential for the circuitry and signals of the pixel 100. For example, a ground potential can be used for this reference potential. Alternatively, a fixed potential other than the ground potential can be used as the reference potential. Furthermore, the well contact 107 is an example of a substrate contact described in the claims.

[0059] Furthermore, a first capacitor element 131 and a second capacitor element 132 are further configured in the wiring area 170 of the figure. Details of the configuration of these first capacitor elements 131 and second capacitor elements 132 will be described later.

[0060] The insulating film 191 insulates the back side of the semiconductor substrate 150. The insulating film 191 may be made of SiO2, for example.

[0061] Color filter 192 is an optical filter that allows light of a specific wavelength in the incident light to pass through. For example, color filters that allow red, green and blue light to pass through can be used for this color filter 192.

[0062] The planarization film 193 is a film that planarizes the surface of the color filter 192. The planarization film 193 can be made of the same material as the crystal lens 194 described later.

[0063] The crystal lens 194 is a lens that focuses incident light. The crystal lens 194 is configured in a hemispherical shape to focus incident light onto the photoelectric conversion unit 111.

[0064] The pixel 100 in this diagram is a component that detects light incident from the back side of the semiconductor substrate 150.

[0065] [Composition of a Capacitor Component] Figure 4 is a diagram showing an example of the configuration of a capacitor element according to an embodiment of the present disclosure. The figure is a cross-sectional view showing an example of the configuration of a first capacitor element 131. The first capacitor element 131 in the figure includes metal films 301 and 306, barrier metals 302 and 305, and insulating films 303 and 304.

[0066] Metal films 301 and 306 are films of metals such as Cu. In the figure, columnar protrusions are formed in metal film 301.

[0067] Barrier metals 302 and 305 are films disposed adjacent to metal films 301 and 306, respectively, to prevent the diffusion of Cu. These barrier metals 302 and 305 may be made of titanium nitride (TiN), for example.

[0068] The insulating film 303 is a dielectric disposed between the barrier metals 302 and 305. The insulating film 303 may be composed of, for example, a zirconium oxide (ZrO 2) or aluminum oxide (Al 2O 3) film.

[0069] The insulating film 304 is an insulating film for metal film 301, etc. The insulating film 304 can be made of the same SiO2 as the insulating layer 171 shown in FIG3.

[0070] As shown in the figure, a capacitor element is constructed by metal films 301 and 306 facing each other through an insulating film 303. By forming a plurality of protrusions on the metal film 301, the surface area can be increased, thereby improving the electrostatic capacitance. Furthermore, the second capacitor element 132 can also be configured in the same way. The first capacitor element 131 shown in the figure is referred to as a MIM (Metal Insulator Metal) structure.

[0071] [The Composition of a Pixel Plane] Figure 5 is a top view showing an example of the pixel configuration according to the first embodiment of this disclosure. This figure is a top view showing an example of the configuration of pixel 100. This figure shows the configuration of the front side of the semiconductor substrate 150 of pixel 100, and illustrates the arrangement of elements such as the photoelectric conversion unit 111. As shown in the figure, pixel 100 can be configured in a generally square shape. In this figure, the dotted shaded areas represent semiconductor regions. Also, the areas with a mesh-like shaded pattern represent gates. Also, the hollow areas in this figure represent separation regions. These separation regions are areas where the diffusion layer is electrically separated. These separation regions can be, for example, constructed using STI (Shallow Trench Isolation). Also, the dashed rectangles in this figure represent the first capacitor element 131 and the second capacitor element 132 disposed in the wiring region 170.

[0072] Furthermore, in this figure, "OFG", "PD", "TRG", "FD", "FDG", "RST", and "AMP1" represent the charge discharge section 114, the photoelectric conversion section 111, the charge transfer section 115, the charge holding section 112, the coupling section 117, the first reset section 116, and the amplification section 118, respectively. Also, in this figure, "SW", "PC", "VB", "RB", and "AMP2" represent the first selection section 119, the MOS transistor 109, the MOS transistor 108, the second reset section 121, and the second amplification section 122, respectively. Also, in this figure, "S1" and "S2" represent the first switching element 135 and the second switching element 136, respectively.

[0073] Furthermore, in this diagram, "SEL" and "WC" represent the second selector 123 and the contact area (semiconductor area 141), respectively. Also, "C1" and "C2" represent the first capacitor element 131 and the second capacitor element 132, respectively. Furthermore, "Vdd" represents the semiconductor area connected to the power line Vdd. "V1" and "V2" represent the semiconductor areas constituting the first output node 101 and the second output node 102, respectively.

[0074] As shown in the figure, a semiconductor region 142 of a photoelectric conversion unit 111 is disposed in the center of pixel 100. Below the photoelectric conversion unit 111 in this figure, the gate of a charge discharge unit 114 and the semiconductor region 144 are sequentially disposed. Hereinafter, the labels such as "below" in the top view of this figure indicate the orientation of the diagram. Above the photoelectric conversion unit 111, the gate of a charge transfer unit 115, the gate of a charge holding unit 112 (semiconductor region 143), and the gate of a coupling unit 117 are sequentially disposed. To the left of the coupling unit 117, the gate of a first reset unit 116 and a semiconductor region connected to the power line Vdd (the drain region of the first reset unit 116) are disposed. Below the semiconductor region, a second amplification unit 122 and a second selection unit 123 are sequentially disposed. Below the second selection unit 123, separated by a separation region, a second reset unit 121 is disposed.

[0075] Furthermore, on the right side of the coupling section 117, separated by a separation region, a semiconductor region (drain region of the amplification section 118), a gate region of the amplification section 118, and a semiconductor region (source region of the amplification section 118) connected to the power line Vdd are sequentially arranged. Below the source region of the amplification section 118, the gate of the first selection section 119, the first output node 101, the MOS transistor 109, and the MOS transistor 108 are sequentially arranged. Furthermore, a second switching element 136 is arranged between the photoelectric conversion section 111 and the MOS transistor 109, and a first switching element 135 is arranged below the second switching element 136. The semiconductor region between the gate of the first switching element 135 and the gate of the second switching element 136 constitutes the semiconductor region of the second output node 102. Furthermore, a semiconductor region 141 constituting the well contact region is arranged in the region between the charge holding section 112 and the second amplification section 122. Furthermore, the first capacitor element 131 and the second capacitor element 132 are respectively arranged on the left and right sides of the figure.

[0076] Thus, in this diagram, pixel 100 is adjacent to the charge holding section 112, and the coupling section 117 and the first reset section 116 are arranged adjacent to each other. This allows for efficient discharge of charge from the charge holding section 112. Compared to connecting the charge holding section 112 and the first reset section 116 via wiring 172, the charge remaining in the charge holding section 112 during reset is reduced. Furthermore, pixel 100 can share the power line between the first reset section 116 and the second selection section 123. Also, since the power line Vdd is shared between the first reset section 116 and the second magnification section 122, the area efficiency of pixel 100 is improved.

[0077] [Generation of Image Signals] Figures 6 and 7 are diagrams showing an example of image signal generation according to the first embodiment of this disclosure. Figures 6 and 7 are timing diagrams showing an example of image signal generation of pixel 100. Figure 6 shows the exposure sequence for image signal generation. The sequence in Figure 6 is the sequence executed simultaneously in all pixels 100 of the pixel array section 10. Furthermore, Figure 7 shows the readout sequence for image signal generation. The sequence in Figure 7 is the sequence executed in pixels 100 arranged in the selected column. In addition, the sequences in Figures 6 and 7 illustrate an example where the charge discharge section 114, the second charge holding section 113, and the coupling section 117 are omitted.

[0078] Furthermore, in Figures 6 and 7, "Vdd" represents the power supply voltage of the power supply line Vdd. "SW" represents the control signal of the first selection unit 119 transmitted via signal line SW. "RST" represents the control signal of the first reset unit 116 transmitted via signal line RST. "TRG" represents the control signal of the charge transfer unit 115 transmitted via signal line TRG. "PC" represents the bias voltage of the MOS transistor 109 transmitted via signal line PC. "SEL" represents the control signal of the second selection unit 123 transmitted via signal line SEL. "RB" represents the control signal of the second reset unit 121 transmitted via signal line RB. "S1" represents the control signal of the first switching element 135 transmitted via signal line S1. "S2" represents the control signal of the second switching element 136 transmitted via signal line S2. "V1" represents the voltage waveform of the first output node 101. "V2" represents the voltage waveform of the second output node 102. Furthermore, the dashed lines in the waveforms of Figures 6 and 7 represent the 0 V level.

[0079] Furthermore, in the following description, "on signal" refers to the control signal that sets the MOS transistor to the on state.

[0080] The sequence of steps during exposure is illustrated in Figure 6. Furthermore, different power supply voltages are supplied to the power line Vdd during the exposure and readout periods. Initially, the power supply voltage VDD2 is applied to the power line Vdd. A low-level voltage VM is applied to the signal line SW, and the first selection unit 119 is de-conducting. A signal of voltage VRST1 is applied to the signal line RST. This VRST1 signal turns on the first reset unit 116. This resets the charge holding unit 112. 0 V is applied to the signal line TRG, and the charge transfer unit 115 is de-conducting. 0 V is applied to the signal line PC, and the MOS transistor 109 is de-conducting. 0 V is applied to the signal line SEL, and the second selection unit 123 is de-conducting. A negative polarity signal is applied to the signal line S1, and the first switching element 135 is de-conducting. A negative polarity signal is also applied to the signal line S2, and the second switching element 136 is de-conducting. The first output node 101 has a voltage of 0 V. The second output node 102 is in the state of having the applied power supply voltage VREG at the power supply line Vreg.

[0081] In T1, the power supply voltage of the power line Vdd is VDD1, which is higher than VDD2. Furthermore, VDD1 is applied to the signal line SW, and the first selection unit 119 is turned on. Also, a conduction signal is applied to the signal line TRG, and the charge transfer unit 115 is turned on. Furthermore, a specific bias voltage VCAS is applied to the signal line PC, and the MOS transistor 109 supplies a constant current to the first output node 101. Since the first reset unit 116 and the charge transfer unit 115 are both turned on, the photoelectric conversion unit 111 and the charge holding unit 112 are reset. Furthermore, since the first selection unit 119 is turned on, the voltage of the first output node 101 increases.

[0082] During T2, a conduction signal is applied to signal line RB, and the second reset unit 121 is in a conducting state. Also, a conduction signal is applied to signal line S1, and the first switching element 135 is in a conducting state. Also, a conduction signal is applied to signal line S2, and the second switching element 136 is in a conducting state. During the period from T1 to T2, the charge holding unit 112 is reset, and the first capacitor element 131 and the second capacitor element 132 are also reset. Furthermore, the second output node 102 is set to the reset voltage VREG.

[0083] In T3, VRST2, the voltage between VRST1 and ground potential (0 V), is applied to signal line RST, and the first reset unit 116 is in a non-conductive state. Furthermore, the application of a conduction signal to signal line TRG is stopped, and the charge transfer unit 115 is in a non-conductive state. Also, the application of a conduction signal to signal line S2 is stopped, and the second switching element 136 is in a non-conductive state. Thus, the reset of photoelectric conversion unit 111 and charge holding unit 112 ends. This reset is equivalent to a global reset performed simultaneously in all pixels 100. During the exposure period that begins with the end of this reset, the charge generated by photoelectric conversion is stored in photoelectric conversion unit 111. The voltage of the first output node 101 is Vres. This Vres is equivalent to the voltage obtained by subtracting the gate-source voltage Vgs of amplification unit 118 and the voltage drop Vft of the first selection unit 119 from the power supply voltage VDD1 of power line Vdd. It is the voltage corresponding to the reset level. The first capacitor element 131 is charged to the reset level.

[0084] In T4, the conduction signal applied to the signal line RB is stopped, and the second reset unit 121 is in a non-conducting state. In this way, the reset level is maintained at the first capacitor element 131.

[0085] In T5, the conduction signal applied to signal line S1 is stopped, and the first switching element 135 is in a non-conducting state.

[0086] In T6, a conduction signal is applied to signal line TRG, and charge transfer unit 115 is turned on. This transfers the charge from photoelectric conversion unit 111 to charge holding unit 112. Furthermore, a conduction signal is applied to signal line RB, and second reset unit 121 is turned on. Also, a conduction signal is applied to signal line S2, and second switching element 136 is turned on. The voltage of first output node 101 decreases accordingly based on the charge transferred to charge holding unit 112.

[0087] In T7, the conduction signal applied to the signal line TRG is stopped, and the charge transfer unit 115 is in a non-conducting state. The voltage of the first output node 101 is Vsig, which corresponds to the voltage of the image signal level. The second capacitor element 132 is charged to the image signal level.

[0088] In T8, the conduction signal applied to the signal line RB is stopped, and the second reset unit 121 is in a non-conducting state. This maintains the image signal level at the second capacitor element 132.

[0089] In T9, the conduction signal to signal line S2 is stopped, and the second switching element 136 is in a non-conducting state.

[0090] In T10, the voltage of signal line SW changes from VDD1 to 0 V, i.e., VM. Therefore, the first selection unit 119 is in a non-conducting state. Furthermore, the applied voltage of signal line RST changes from VRST2 to VRST1. Therefore, the first reset unit 116 is in a conducting state. Therefore, the voltage of the first output node 101 decreases.

[0091] At time T11, the voltage across the power line Vdd changes to VDD2. This voltage is equivalent to the voltage obtained by subtracting Vgs and Vft from VDD1.

[0092] At time T12, the bias voltage applied to the signal line PC is stopped. This puts the MOS transistor 109 in a non-conducting state.

[0093] Based on the above steps, the first capacitor element 131 and the second capacitor element 132 can maintain the reset level and the image signal level for each pixel 100, respectively.

[0094] Using Figure 7, the sequence of steps during the readout period is illustrated. Additionally, during the readout period, VRST1 is applied to signal line RST. Signal lines TRG and PC are applied with 0V.

[0095] At time T20, VDD1 is applied to the signal line SW, and the first selection unit 119 is turned on. As a result, the voltage of the first output node 101 rises to be equal to that of VREG.

[0096] At time T21, a conduction signal is applied to signal line SEL, and the first selection unit 119 is in a conducting state. Also, a conduction signal is applied to signal line RB, and the second reset unit 121 is in a conducting state. This resets the second output node 102.

[0097] At time T22, the conduction signal applied to signal line RB is stopped, and the second reset unit 121 is in a non-conducting state. Meanwhile, a conduction signal is applied to signal line S1, and the first switching element 135 is in a conducting state. The second output node 102 is a voltage that superimposes the reset level onto VREG. An image signal corresponding to this voltage is generated by the second amplification unit 122 and output to signal line VSL. This image signal is equivalent to the image signal at the time of reset.

[0098] At time T23, the conduction signal applied to signal line S1 is stopped, and the first switching element 135 is in a non-conducting state. Then, a conduction signal is applied to signal line RB, and the second reset unit 121 is in a conducting state. This resets the second output node 102.

[0099] At time T24, the conduction signal applied to the signal line RB is stopped, and the second reset unit 121 is in a non-conducting state.

[0100] At time T25, a conduction signal is applied to signal line S2, and the second switching element 136 is in the conducting state. The second output node 102 is a voltage that superimposes the image signal level onto VREG. An image signal corresponding to this voltage is generated by the second amplification unit 122 and output as an image signal to signal line VSL.

[0101] At time T26, the application of the conduction signal to signal line SW is stopped, and the first selection unit 119 is in a non-conducting state. Also, the application of the conduction signal to signal line SEL is stopped, and the second selection unit 123 is in a non-conducting state. Also, the application of the conduction signal to signal line S2 is stopped, and the second switching element 136 is in a non-conducting state.

[0102] Steps T20 to T26 are executed sequentially for all columns of the pixel array section 10. This generates an image signal representing one frame fraction. Furthermore, CDS processing is performed by the line signal processing unit 30, which subtracts the reset image signal output from pixel 100 during T22 to T23 from the image signal output from pixel 100 during T25 to T26. Moreover, by maintaining the reset level and the image signal level at the first capacitor element 131 and the second capacitor element 132 respectively and performing the subtraction, the impact of pixel circuit offset errors can be reduced. For example, the error caused by charge generated from incident light leaking from the vicinity of the photoelectric conversion unit 111 is equivalent to this offset error. By performing the above-mentioned reduction process, the error caused by the offset error commonly generated by the first capacitor element 131 and the second capacitor element 132 can be reduced, thereby reducing the sensitivity based on the leaked incident light, i.e., parasitic light sensitivity (PLS).

[0103] According to the steps described above, an image signal can be generated. Furthermore, when using the charge discharge unit 114, it can be set to a conductive state during T1 to T3 in FIG. 6 to reset the photoelectric conversion unit 111. In this case, the charge transfer unit 115 can be set to a non-conductive state during T1 to T3.

[0104] Thus, in the first embodiment of the photodetector 1 disclosed herein, the charge holding section 112, the second reset section 121, and the coupling section 117 are arranged adjacent to each other. This reduces the residual charge in the charge holding section 112 during reset, thereby reducing noise.

[0105] (2. Second Implementation) The pixel 100 in the first embodiment described above includes a first capacitor element 131 and a second capacitor element 132. In contrast, the light detection device 1 in the second embodiment disclosed herein has four or more capacitor elements, which is different from the first embodiment described above.

[0106] [Pixel Composition] Figure 8 is a diagram showing an example of the pixel configuration of the second embodiment of this disclosure. This figure is a circuit diagram showing an example of the configuration of pixel 100, similar to Figure 2. The pixel 100 in this figure further includes a third capacitor element 133, a fourth capacitor element 134, a third switching element 137, and a fourth switching element 138, which differs from the pixel 100 in Figure 2. For the third switching element 137 and the fourth switching element 138, an n-channel MOS transistor can be used.

[0107] One end of the third capacitor element 133 is connected to the first output node 101, and the other end is connected to the source of the third switching element 137. The drain of the third switching element 137 is connected to the second output node 102, and the gate is connected to signal line S3. One end of the fourth capacitor element 134 is connected to the first output node 101, and the other end is connected to the source of the fourth switching element 138. The drain of the fourth switching element 138 is connected to the second output node 102, and the gate is connected to signal line S3.

[0108] The third capacitor element 133, like the first capacitor element 131, is a capacitor element that maintains the reset level. By simultaneously turning on the third switch element 137 and the first switch element 135, the reset level can be maintained at the first capacitor element 131 and the third capacitor element 133.

[0109] The fourth capacitor element 134, like the second capacitor element 132, is a capacitor element used to maintain the image signal level. By simultaneously turning on the fourth switch element 138 and the second switch element 136, the image signal level can be maintained between the second capacitor element 132 and the fourth capacitor element 134.

[0110] Thus, by connecting the third capacitor element 133 and the fourth capacitor element 134 in parallel with the first capacitor element 131 and the second capacitor element 132, the holding capacitance for the reset level and the image signal level can be increased. This allows for adjustment of the sensitivity.

[0111] [The Composition of a Pixel Plane] Figure 9 is a top view showing an example of the pixel configuration of the second embodiment of this disclosure. This figure, like Figure 5, shows an example of the pixel configuration 100. The pixel 100 in this figure further comprises a third capacitor element 133, a fourth capacitor element 134, a third switch element 137, and a fourth switch element 138, which differs from the pixel 100 in Figure 5.

[0112] In this diagram, "S3" and "S4" represent the third switching element 137 and the fourth switching element 138, respectively. Also, "C3" and "C4" represent the third capacitor element 133 and the fourth capacitor element 134, respectively.

[0113] A second switching element 136 is disposed between the photoelectric conversion unit 111 and the second selection unit 123, and a first switching element 135 is disposed below the second switching element 136. A fourth switching element 138 is disposed between the photoelectric conversion unit 111 and the MOS transistor 109, and a third switching element 137 is disposed below the fourth switching element 138. A first capacitor element 131 is disposed at the lower left of pixel 100. A second capacitor element 132 is disposed at the lower right of pixel 100. A third capacitor element 133 is disposed at the upper left of pixel 100. A fourth capacitor element 134 is disposed at the upper right of pixel 100.

[0114] [Another component of the pixel plane] Figures 10A and 10B are top views showing another configuration example of the pixel of the second embodiment of this disclosure. Figures 10A and 10B are top views showing a configuration example of pixel 100, similar to Figure 9. The pixel 100 in Figures 10A and 10B shows a configuration example of a pixel 100 with a large size.

[0115] In Figure 10A, a photoelectric conversion unit 111 is disposed in the center of pixel 100. A charge transfer unit 115 is disposed above the photoelectric conversion unit 111, and a charge discharge unit 114 is disposed to the left of the photoelectric conversion unit 111. A charge holding unit 112 and a coupling unit 117 are disposed sequentially on the upper right of the photoelectric conversion unit 111. A second amplification unit 122 and a second selection unit 123, a second switching element 136 and a first switching element 135, and a second reset unit 121 are disposed to the left of the photoelectric conversion unit 111 of pixel 100. An amplification unit 118 and a first selection unit 119, a fourth switching element 138 and a third switching element 137, and MOS transistors 109 and 108 are disposed to the right of the photoelectric conversion unit 111.

[0116] As shown in Figure 10A, pixel 100 in this figure has the charge transfer section 115 and the charge discharge section 114 arranged in an orthogonal direction. Furthermore, the first switching element 135, the second switching element 136, the third switching element 137, and the fourth switching element 138 are arranged at the corners of pixel 100. This reduces the influence of incident light on the first switching element 135, etc.

[0117] In Figure 10B, the second magnifying section 122, the second selecting section 123, the magnifying section 118, and the first selecting section 119 are arranged on the left side of the photoelectric conversion section 111. The fourth switching element 138, the third switching element 137, the second reset section 121, the second switching element 136, the first switching element 135, the MOS transistor 109, and the MOS transistor 108 are arranged on the right side of the photoelectric conversion section 111. Apart from this, since the arrangement is the same as that of the pixel 100 in Figure 10A, further explanation is omitted.

[0118] The configuration of the light detection device 1 other than that of the light detection device 1 in the first embodiment disclosed herein is the same, so the description is omitted.

[0119] Thus, the light detection device 1 of the second embodiment disclosed herein may further include a third capacitor element 133 and a fourth capacitor element 134 to adjust the sensitivity of the pixel 100.

[0120] (3. Third Implementation) The pixel 100 of the first embodiment described above includes: a front-end circuit 110, a constant current circuit 105, a signal level holding circuit 130, and a rear-end circuit 120. In contrast, the pixel 100 of the third embodiment disclosed herein differs from the first embodiment in that the plurality of pixels 100 share common constituent elements.

[0121] [Pixel Composition] Figure 11 is a diagram showing an example of the pixel configuration of the third embodiment of this disclosure. This diagram is a circuit diagram, similar to Figure 2, illustrating an example of the configuration of pixel 100. However, unlike the pixel 100 in Figure 2, this diagram shows that the plurality of pixels 100 share the same downstream circuit 120.

[0122] Pixel 100a in this diagram includes: a front-end circuit 110a, a constant current circuit 105a, and a signal level holding circuit 130a. Pixel 100b in this diagram includes: a front-end circuit 110b, a constant current circuit 105b, and a signal level holding circuit 130b. Furthermore, pixels 100a and 100b share a single rear-end circuit 120. Specifically, the second output node 102 of pixel 100a and the second output node 102 of pixel 100b are commonly connected to the rear-end circuit 120. Thus, this diagram illustrates an example where two pixels 100 share the rear-end circuit 120.

[0123] [The Composition of a Pixel Plane] Figure 12 is a top view showing an example of the pixel configuration of the third embodiment of this disclosure. This figure is a top view showing an example of the pixel 100 configuration, similar to Figure 5. The pixel 100 in this figure represents an example where two pixels 100 share a common ground connection 107, power line Vdd, power line Vreg, and ground line GND.

[0124] In this figure, pixels 100a and 100b are arranged adjacent to each other. A connection point 107 is disposed at the boundary between pixels 100a and 100b. Furthermore, semiconductor regions connected to power line Vdd, power line Vreg, and ground line GND are respectively disposed at the boundaries of pixels 100a and 100b. These connection points 107 are shared by pixels 100a and 100b.

[0125] Figure 13 is a top view showing another configuration example of the pixel according to the third embodiment of the present disclosure. This figure, like Figure 12, shows a top view of a configuration example of pixel 100. Pixel 100 in this figure illustrates an example where two pixels 100 share a back-end circuit 120 (second reset section 121, second magnification section 122, and second selection section 123), and also illustrates a layout example of a pixel 100 with the same configuration as the circuit diagram in Figure 11. Pixels 100a and 100b in this figure illustrate an example where they share the back-end circuit 120, the well contact 107, the power line Vdd, and the ground line GND. The second magnification section 122 and the second selection section 123 are arranged to the left of pixels 100a and 100b in this figure. Furthermore, the second reset section 121 is arranged to the left of pixel 100b in this figure.

[0126] The configuration of the light detection device 1 other than that of the light detection device 1 in the first embodiment disclosed herein is the same, so the description is omitted.

[0127] Thus, the light detection device 1 of the third embodiment disclosed herein shares constituent elements in two adjacent pixels 100. This simplifies the configuration of the light detection device 1.

[0128] (4. Fourth Implementation Form) In the third embodiment described above, pixels 100 share constituent elements in two pixels 100. In contrast, in the fourth embodiment disclosed herein, pixels 100 share constituent elements in four pixels 100, which differs from the third embodiment described above.

[0129] [Pixel Composition] Figure 14 is a diagram showing an example of the pixel configuration of the fourth embodiment of this disclosure. This diagram is a circuit diagram showing an example of the configuration of pixel 100, similar to Figure 11. However, this diagram differs from the pixel 100 in Figure 11 in that it further includes pixels 100c and 100d.

[0130] Pixel 100c in this diagram includes: a front-end circuit 110c, a constant current circuit 105c, and a signal level holding circuit 130c. Pixel 100d in this diagram includes: a front-end circuit 110d, a constant current circuit 105d, and a signal level holding circuit 130d. Furthermore, pixels 100a, 100b, 100c, and 100d share a single back-end circuit 120. Specifically, the second output node 102 of each of pixels 100a, 100b, 100c, and 100d is commonly connected to the back-end circuit 120. Thus, this diagram illustrates an example where four pixels 100 share a back-end circuit 120.

[0131] [The Composition of a Pixel Plane] Figure 15 is a top view showing an example of the pixel configuration of the fourth embodiment of this disclosure. This figure is a top view showing an example of the pixel 100 configuration, similar to Figure 13. The pixel 100 in this figure shows an example in which the four pixels 100 share the back circuit 120 (second reset section 121, second amplification section 122 and second selection section 123), the contact 107, the power line Vdd and the ground line GND.

[0132] The configuration of the light detection device 1 other than that of the light detection device 1 in the first embodiment disclosed herein is the same, so the description is omitted.

[0133] Thus, the light detection device 1 of the fourth embodiment disclosed herein shares constituent elements in the four pixels 100. This allows for a further simplification of the configuration of the light detection device 1.

[0134] (5. Fifth Implementation) The pixel 100 of the first embodiment described above is disposed on the semiconductor substrate 150. In contrast, the pixel 100 of the fifth embodiment disclosed herein is dispersedly disposed at points on a plurality of semiconductor substrates, which is different from the first embodiment described above.

[0135] [Pixel Composition] Figure 16 is a diagram showing an example of the pixel configuration of the fifth embodiment of this disclosure. This figure is a circuit diagram showing an example of the configuration of pixel 100, similar to Figure 2. This figure differs from pixel 100 in Figure 2 because the front-end circuit 110, constant current circuit 105, signal level holding circuit 130, and back-end circuit 120 are arranged on different semiconductor substrates.

[0136] In this figure, pixel 100 is divided into semiconductor substrate 150 and semiconductor substrate 250. As shown in the figure, the front-end circuit 110 is disposed on semiconductor substrate 150. On the other hand, the constant current circuit 105, the signal level holding circuit 130, and the back-end circuit 120 are disposed on semiconductor substrate 250. Thus, pixel 100 in this figure represents an example where the first output node 101 is divided into two.

[0137] [The Composition of a Pixel's Cross-Section] Figure 17 is a cross-sectional view showing an example of the pixel configuration of the fifth embodiment of this disclosure. This figure is a cross-sectional view of an example of the pixel 100 configuration, similar to Figure 3. The pixel 100 in this figure further includes a semiconductor substrate 250 and a wiring region 270, which is different from the pixel 100 in Figure 3.

[0138] Semiconductor substrate 250 is a semiconductor substrate in which the diffusion layer of the element of pixel 100 is disposed in the same manner as semiconductor substrate 150. On semiconductor substrate 250 in this figure, a constant current circuit 105 (not shown), a signal level holding circuit 130 and a back-end circuit 120 are disposed.

[0139] Wiring area 270 is a wiring area disposed on the front side of semiconductor substrate 250. Wiring area 270 includes insulating layer 271, wiring 272 and through-hole plug 274. Furthermore, a first capacitor element 131 and a second capacitor element 132 are disposed in wiring area 270.

[0140] Pixel 100 in this image is formed by stacking semiconductor substrate 150 and semiconductor substrate 250. During this stacking, wiring regions 170 and 270 of semiconductor substrate 150 are joined. Pads 179 are disposed in wiring regions 170 and 279, respectively. Pads 179 and 279 are joined and electrically connected. Pads 179 and 279 can be made of Cu. Such a connection achieved by Cu pads is called a Cu-Cu connection.

[0141] [Another component of the pixel's cross-section] Figure 18 is a cross-sectional view showing another configuration example of the pixel of the fifth embodiment of the present disclosure. This figure is a cross-sectional view of a configuration example of pixel 100, similar to Figure 17. The pixel 100 in this figure is located at the point on the back side of the semiconductor substrate 250 deposited on the surface side of the semiconductor substrate 150, which is different from the pixel 100 in Figure 17.

[0142] An interlayer film 175 is disposed on the front side of the semiconductor substrate 150, replacing the wiring region 170. This interlayer film 175 may be made of, for example, SiO2. The back side of the semiconductor substrate 250 is deposited through this interlayer film 175. A wiring region 270 is disposed on the front side of the semiconductor substrate 250. A first capacitor element 131 and a second capacitor element 132 are disposed in this wiring region 270.

[0143] The semiconductor region and gate of the semiconductor substrate 150 can be connected to the wiring 272 of the wiring region 270 via a through-hole 273. The through-hole 273 is disposed in a through-hole plug formed in the through-hole of the semiconductor substrate 250. The semiconductor substrate 250 in this figure is provided with a constant current circuit 105 (not shown), a signal level holding circuit 130, and a downstream circuit 120.

[0144] Thus, the pixel 100 of the fifth embodiment disclosed herein can also adopt any of the configurations shown in FIG. 17 and FIG. 18. Hereinafter, we envision the pixel 100 with the configuration shown in FIG. 18. Furthermore, the semiconductor substrate 250 is an example of the second semiconductor substrate described in the claims.

[0145] [The Composition of a Pixel Plane] Figures 19A and 19B are top views showing an example of pixel configuration according to the fifth embodiment of this disclosure. Figures 19A and 19B envision an example where the back-end circuitry 120 is shared across the four pixels 100, as illustrated in Figure 14. Figures 19A and 19B also show configuration examples where the charge discharge section 114 is omitted. Figure 19A shows an example of the configuration of the semiconductor substrate 150, and Figure 19B shows an example of the configuration of the semiconductor substrate 250. Furthermore, the square areas in Figures 19A and 19B represent through-holes 273.

[0146] In Figure 19A, as described above, front-end circuitry 110 is arranged for each of the four pixels 100 on the semiconductor substrate 150. These can all be configured identically. The configuration is illustrated using the pixel 100 in the lower left corner of Figure 19A as an example. A charge transfer unit 115 (TRG) is arranged in the center of the pixel 100. A photoelectric conversion unit 111 is arranged to its left. A charge holding unit 112 and a coupling unit 117 (FDG) are arranged to the right of the charge transfer unit 115 (TRG). A first reset unit 116 (RST) is arranged above the coupling unit 117 (FDG). A first selection unit 119 (SW) and an amplification unit 118 (AMP1) are arranged below the pixel 100. Furthermore, a contact point (not shown) is arranged on the semiconductor substrate 150 in this figure.

[0147] In Figure 19B, a constant current circuit 105, a signal level holding circuit 130, and a back-end circuit 120 are arranged on the semiconductor substrate 250. The back-end circuit 120 is shared by four pixels 100. The four pixels 100 of the semiconductor substrate 250 can be arranged symmetrically vertically. In the upper pixel 100 of this figure, a MOS transistor 108 (VB) is arranged on the upper side, and a MOS transistor 109 (PC) is arranged on the left side. A second switching element 136 (S2) is arranged below the pixel 100, and a first switching element 135 is arranged on the right side. The lower pixel 100 of this figure can have its components arranged symmetrically vertically with those of the upper pixel 100.

[0148] The well contact 107 (WC), the second reset section 121 (RB), the second amplification section 122 (AMP2), and the second selection section 123 (SEL) are arranged in the center of the upper and lower pixels 100. Thus, the downstream circuitry 120 shared by all four pixels 100 is arranged in the center of the second semiconductor substrate, and the MOS transistors 109 (PC) arranged in each pixel 100 are symmetrically arranged in the upper and lower pixels 100. This simplifies the layout.

[0149] Furthermore, as shown in Figure 19A, by arranging each pixel 100 of the semiconductor substrate 150 into a square shape when viewed from above, and by arranging each MOS transistor in the same direction, the periodicity of the continuously arranged pixels 100 can be improved. Even when the incident light is incident at an angle, the sensitivity of each pixel 100 can be made consistent.

[0150] [Another component of the pixel plane] Figures 20A and 20B are top views showing another configuration example of a pixel according to the fifth embodiment of this disclosure. Figures 20A and 20B illustrate a configuration example with a charge discharge section 114. The configuration is illustrated using the pixel 100 in the lower left of Figure 20A as an example. The charge discharge section 114 (OFG) is positioned above the charge transfer section 115 (TRG) in the center of pixel 100. Adjacent to the right of the charge discharge section 114, a semiconductor region connecting the power line Vdd and a first reset section 116 (RST) are sequentially arranged. Alternatively, the configuration can be the same as in Figure 19A. Furthermore, the semiconductor substrate 250 in Figure 20B can be configured in the same way as in Figure 19B.

[0151] [Another component of the pixel plane] Figures 21A and 21B are top views showing another example of the pixel configuration of the fifth embodiment of this disclosure. Figures 21A and 21B show variations in the configuration of the semiconductor substrate 250.

[0152] In Figure 21A, MOS transistors 109 (PC) and MOS transistors 108 (VB) are arranged side by side with the second switching element 136 (S2) and the first switching element 135 (S1).

[0153] In Figure 21B, the semiconductor region of the ground line GND of the MOS transistor 108 (VB) is shared by the adjacent pixels 100 above and below.

[0154] [A Reconstruction of the Pixel Plane] Figures 22A and 22B are top views showing another example of the pixel configuration of the fifth embodiment of this disclosure.

[0155] In Figure 22A, there is a first reset section 116 (RST) in the upper and lower pixels 100. This allows the through hole 273 to be reduced.

[0156] In Figure 22B, MOS transistors 108 (VB), MOS transistor 109 (PC), the first switching element 135 (S1), and the second switching element 136 (S2) are symmetrically arranged in four pixels 100. Furthermore, the semiconductor region connecting the ground line GND of MOS transistor 108 (VB) is shared by the left and right adjacent pixels 100. Also, the semiconductor region connecting the power line Vdd of the second reset section 121 (RB) and the second amplification section 122 (AMP2) is shared by the upper and lower pixels 100.

[0157] [A Reconstruction of the Pixel Plane] Figure 23 is a top view showing another example of the pixel configuration of the fifth embodiment of this disclosure. This figure illustrates an example of the arrangement of the pixel 100 on the semiconductor substrate 150. A charge holding portion 112 (FD) is disposed above the charge transfer portion 115 (TRG). A coupling portion 117 (FDG) is disposed to the right of the charge holding portion 112 (FD). This allows the charge transfer portion 115 (TRG), the charge holding portion 112 (FD), and the coupling portion 117 (FDG) to share a common diffusion layer. Furthermore, an amplification portion 118 (AMP1) can be disposed in the normal direction of the line connecting the charge holding portion 112 (FD) and the coupling portion 117 (FDG). This shortens the connection distance between the charge holding portion 112 (FD) and the amplification portion 118 (AMP1).

[0158] The configuration of the light detection device 1 other than that of the light detection device 1 in the first embodiment disclosed herein is the same, so the description is omitted.

[0159] Thus, by arranging the pixel 100 on the stacked semiconductor substrate 150 and semiconductor substrate 250, the size of the pixel 100 can be reduced.

[0160] (6. Sixth Implementation) The pixel 100 in the first embodiment described above uses a first capacitor element 131 and a second capacitor element 132. In contrast, the pixel 100 in the sixth embodiment disclosed herein has a MOS transistor disposed between the two capacitor elements and the first output node 101, which is different from the first embodiment described above.

[0161] [Pixel Composition] Figure 24 is a diagram showing an example of the pixel configuration according to the sixth embodiment of this disclosure. This figure, like Figure 2, shows a circuit diagram of an example of the pixel 100 configuration. The pixel 100 in this figure includes: a photoelectric conversion unit 511, a charge holding unit 512, a charge transfer unit 515, a first reset unit 516, a coupling unit 517, an amplification unit 518, a MOS transistor 509, a second amplification unit 522, and a selection unit 523. Furthermore, the pixel 100 in this figure further includes: a sampling unit 539, a first capacitor element 531, a second capacitor element 532, and a second selection unit 524. In addition, a second charge holding unit (not shown) (corresponding to the second charge holding unit 113 in Figure 2) is disposed between the first reset unit 516 and the coupling unit 517.

[0162] The photoelectric conversion unit 511, charge holding unit 512, charge transfer unit 515, first reset unit 516, and coupling unit 517 are the same as those in FIG2, so their descriptions are omitted. Similarly, the amplification unit 518, MOS transistor 509, second reset unit 521, second amplification unit 522, and selection unit 523 are the same as those in FIG2, so their descriptions are omitted.

[0163] The sampling unit 539 switches the connection between the first capacitor element 531 and the second capacitor element 532 and the source of the amplification unit 518. The first capacitor element 531 is connected between the sampling unit 539 and the second amplification unit 522. The second capacitor element 532 is connected between the source of the sampling unit 539 and the ground line. Furthermore, the second selection unit 524 is connected between the source of the amplification unit 518 and the output signal line VSL. In the circuit shown in the figure, the node connected to the source of the amplification unit 518 corresponds to the first output node 101, and the node between the second capacitor element 532 and the gate of the second amplification unit 522 corresponds to the second output node 102. Moreover, the sampling unit 539 is an example of the acquisition unit described in the claims.

[0164] [The Composition of a Pixel Plane] Figures 25A and 25B are top views showing an example of the pixel configuration of the sixth embodiment of this disclosure. Figures 25A and 25B are similar to Figure 5, showing an example of the pixel 100 configuration.

[0165] In Figure 25A, a semiconductor region 141 for arranging well contacts 107 is arranged in the upper right of pixel 100. A second reset section 521 (Cal) and a coupling section 517 (DCG) are sequentially arranged to the left of the semiconductor region 141. A coupling section 517 (RX) and a charge transfer section 515 (TX) are sequentially arranged below the coupling section 517 (DCG). An amplification section 518 (SF1) is arranged below the semiconductor region 141. A MOS transistor 509 (PC) is arranged to the left of the semiconductor region 141. Furthermore, a second amplification section 522 (SF2) and a selection section 523 (SEL) are sequentially arranged below the amplification section 518 (SF1). A second selection section 524 (SEL2) is arranged to the left of the selection section 523 (SEL). A sampling section 539 (Sample) is arranged in the center of pixel 100.

[0166] In Figure 25B, a second selection section 524 (SEL2) and a selection section 523 (SEL) are sequentially arranged below the semiconductor region 141. A second amplification section 522 (SF2) and an amplification section 518 (SF1) are sequentially arranged to the left of the selection section 523 (SEL). A MOS transistor 509 (PC) is arranged above the amplification section 518 (SF1). A sampling section 539 (Sample) is arranged in the area between the MOS transistor 509 (PC) and the second selection section 524 (SEL2).

[0167] In either Figure 25A or 25B, pixel 100 can be configured as a square shape. Furthermore, the second reset unit 521 (Cal) and the coupling unit 517 (DCG) can share a diffusion layer. Also, the magnifying unit 518 (SF1) and the second magnifying unit 522 (SF2) can share a diffusion layer. Furthermore, the selection unit 523 (SEL) and the second selection unit 524 (SEL2) can share a diffusion layer.

[0168] Furthermore, the configuration of pixel 100 is not limited to this example. For example, a charge discharge section that discharges the charge from photoelectric conversion unit 511 may also be configured. This charge discharge section may have the same configuration as the charge discharge section 114 in FIG2.

[0169] (7. Seventh Implementation) In the above-described embodiments, the configuration of pixel 100 has been explained. In contrast, in the seventh embodiment disclosed herein, the configuration of light detection device 1 has been explained.

[0170] [Composition of Camera Components] Figures 26A and 26B are diagrams showing an example of the configuration of the imaging element in the seventh embodiment of this disclosure. Figures 26A and 26B are diagrams illustrating the substrate configuration of the light detection device 1.

[0171] Figure 26A is a diagram illustrating an example of a photodetector 1 formed on a semiconductor substrate 150. Specifically, it illustrates an example of a pixel array 10 and logic circuit 50 formed on the semiconductor substrate 150. Here, the logic circuit 50 includes the vertical drive unit 20, horizontal signal processing unit 30, and control unit 40 circuits of Figure 1. The imaging element in Figure 26A illustrates an example where the pixel array 10 is arranged in the center of the semiconductor substrate 150, and the logic circuit 50 is arranged in the area outside the pixel array 10.

[0172] Figure 26B shows an example of a photodetector 1 composed of two stacked semiconductor substrates. The photodetector 1 in this figure is constructed by stacking a semiconductor substrate 150 on which a pixel array 10 is formed and a semiconductor substrate 350 on which a logic circuit 50 is formed.

[0173] Thus, the pixel array portion 10 of Figures 26A and 26B is formed on a single semiconductor substrate 150. In this pixel array portion 10, the pixels 100 illustrated in Figures 2 and 3 are arranged.

[0174] [Cross-section composition of an imaging element] Figure 27 is a cross-sectional view showing an example of the configuration of the imaging element according to the seventh embodiment of this disclosure. This figure is a cross-sectional view showing an example of the configuration of the light detection device 1, and is an example of the light detection device 1 in Figure 26A.

[0175] A separation portion 151 is disposed on the semiconductor substrate 150 at the boundary of pixel 100 in this figure. This separation portion 151 separates the electrical and optical properties of pixel 100. This separation portion 151 can be constructed, for example, by embedding an insulating material into the semiconductor substrate 150. The configuration of other pixels 100 is the same as in Figure 3, so it is omitted from the description. Furthermore, in this figure, the symbols for parts common to those in Figure 3, such as semiconductor region 142 and wiring 172, are omitted.

[0176] A logic circuit 50 is disposed adjacent to the pixel array section 10. Components such as MOS transistors constituting the logic circuit 50 are formed on a semiconductor substrate 150 in the region of the logic circuit 50. Furthermore, wiring 172 and the like, connecting to the MOS transistors of the logic circuit 50, are disposed in the wiring region 170 of the logic circuit 50 region. Additionally, a light-shielding film 195 is disposed on the back side of the semiconductor substrate 150 in the region of the logic circuit 50, replacing the color filter 192.

[0177] An opening 196 for wire bonding is provided at the end of the semiconductor substrate 150. The opening 196 is shaped to extend from the back side of the semiconductor substrate 150 to the wiring area 170. A pad 178 for wire bonding is provided at the bottom of the opening 196.

[0178] [Another aspect of the cross-section of a camera element] Figure 28 is a cross-sectional view showing another configuration example of the imaging element according to the seventh embodiment of this disclosure. This figure is a cross-sectional view showing a configuration example of the light detection device 1, and is an example of the light detection device 1 in Figure 26B.

[0179] Components such as MOS transistors constituting the logic circuit 50 are formed on the semiconductor substrate 350 shown in the figure. The MOS transistors, like those on the semiconductor substrate 150, have semiconductor regions 343 and gates 362 formed on the semiconductor substrate 350. Furthermore, an insulating layer 371 and wiring 372 connecting to the MOS transistors of the logic circuit 50 are disposed in the wiring region 370 of the semiconductor substrate 350. As shown in the figure, the wiring regions 170 and 370 of the semiconductor substrate 150 are joined together, and two semiconductor substrates 150 and 350 are stacked. The connection between the wiring regions 170 and 370 can be achieved using the CuCu connection described in Figure 17. Furthermore, the reference potentials of the semiconductor substrates 350 and 150 can be mutually transferred via this CuCu connection.

[0180] [Another component of a camera sensor] Figure 29 shows another configuration example of the imaging element according to the seventh embodiment of this disclosure. This figure illustrates the substrate configuration of the light detection device 1 in the same way as Figures 26A and 26B. The light detection device 1 in this figure differs from the light detection device 1 in Figures 26A and 26B in that it is divided into two semiconductor substrates 150 and 250 on which the pixel array portion 10 is stacked.

[0181] A pixel array section 10a is disposed on a semiconductor substrate 150, and a pixel array section 10b is disposed on a semiconductor substrate 250. The front-end circuit 110 shown in FIG. 16 can be disposed in the pixels 100 of the pixel array section 10a. Furthermore, the constant current circuit 105, the signal level holding circuit 130, and the back-end circuit 120 of FIG. 16 can be disposed in the pixels 100 of the pixel array section 10b. That is, the pixels 100 of the pixel array section 10 in this figure can adopt the configuration shown in FIG. 17 and 18. Furthermore, logic circuitry 50 is further disposed on the outer side of the pixel array section 10b on the semiconductor substrate 250 in this figure.

[0182] [A further reconstruction of the cross-section of a camera element] Figures 30 and 31 are cross-sectional views showing another configuration example of the imaging element according to the seventh embodiment of this disclosure. These figures show the cross-sectional configuration of the light detection device 1 of Figure 29.

[0183] Figure 30, similar to the pixel 100 in Figure 17, illustrates an example of a photodetector 1 comprising a pixel 100 formed by joining wiring regions 170 and 270. A logic circuit 50 is further disposed on the semiconductor substrate 250 in this figure. Also, similar to Figure 17, a wire bonding pad 178 is disposed on the wiring region 170 of the semiconductor substrate 150.

[0184] Figure 31 illustrates an example of a photodetector 1 comprising a pixel 100, which, like the pixel 100 in Figure 18, is formed by bonding the interlayer film 175 of the semiconductor substrate 150 to the back side of the semiconductor substrate 250. Similar to Figure 30, a logic circuit 50 is further disposed on the semiconductor substrate 250 in this figure. The semiconductor substrate 250 in this figure shows a semiconductor region 243 and a gate 262 of a MOS transistor constituting the elements of the logic circuit 50. Furthermore, the photodetector 1 in this figure has a bonding pad 278 disposed in the wiring region 270 of the semiconductor substrate 250.

[0185] [Another component of the camera element] Figure 32 shows another configuration example of the imaging element according to the seventh embodiment of this disclosure. This figure illustrates the substrate configuration of the light detection device 1 similarly to Figures 26A and 26B. The light detection device 1 in this figure differs from the light detection devices 1 in Figures 26A and 26B in that it is constructed by stacking semiconductor substrates 150, 250, and 350. A pixel array section 10a is disposed on semiconductor substrate 150, and a pixel array section 10b is disposed on semiconductor substrate 250. Furthermore, a logic circuit 50 is disposed on semiconductor substrate 350.

[0186] [A further reconstruction of the cross-section of a camera element] Figures 33 and 34 are cross-sectional views showing another configuration example of the imaging element according to the seventh embodiment of this disclosure. These figures show the cross-sectional configuration of the light detection device 1 of Figure 32.

[0187] Figure 33 illustrates an example of a photodetector 1 constructed by bonding the wiring region 370 of a semiconductor substrate 350 to the back side of a semiconductor substrate 250. An interlayer film 379 is disposed on the back side of the semiconductor substrate 250 in this figure. The wiring region 370 of the semiconductor substrate 350 is bonded to the semiconductor substrate 250 through the interlayer film 379. The wiring regions 270 and 270 of the semiconductor substrate 250 can be connected by through-holes 273. Furthermore, similar to the photodetector 1 in Figure 30, the semiconductor substrates 150 and 250 are laminated by bonding the wiring regions 170 and 270.

[0188] Figure 34 illustrates an example of a photodetector 1 constructed by bonding the wiring region 370 of semiconductor substrate 350 to the wiring region 270 of semiconductor substrate 250. For the connection between wiring regions 270 and 370, CuCu bonding can be used. Furthermore, similar to the photodetector 1 in Figure 31, the interlayer film 175 disposed on the front side of semiconductor substrate 150 and semiconductor substrate 250 is bonded and deposited to the back side of semiconductor substrate 250.

[0189] (8. Eighth Implementation) The pixel 100 of the first embodiment described above includes: a front-end circuit 110, a constant current circuit 105, a signal level holding circuit 130, and a rear-end circuit 120. In contrast, the pixel 100 of the eighth embodiment disclosed herein has a portion corresponding to the front-end circuit 110, which is different from the first embodiment described above.

[0190] To reduce the size of photodetectors, for example, a photodetector (image sensor) has been proposed that comprises: a photoelectric conversion unit disposed on a first semiconductor substrate, a signal readout circuit disposed on a second semiconductor substrate, and the semiconductor substrates being stacked together (e.g., International Publication No. 2019 / 131965). In this image sensor, a through wiring traversing the shape of the second semiconductor substrate is used to transmit signals between the first and second semiconductor substrates.

[0191] However, with the reduction in the size of the photodetector, there is a problem that the capacitance of the charge holding part that retains the charge generated by the photoelectric conversion unit is insufficient.

[0192] Therefore, a light detection device is proposed to increase the capacitance of the charge holding section.

[0193] [Pixel Composition] Figure 35 is a diagram showing an example of the configuration of the photodetector according to the eighth embodiment of this disclosure. This figure is a circuit diagram illustrating an example of the configuration of pixel 100. Pixel 100 in this figure includes: a photoelectric conversion unit 111, a charge holding unit 112, a charge transfer unit 115, a first reset unit 116, an amplification unit 118, and a first selection unit 119. Since pixel 100 in this figure is equivalent to the circuit in the preceding circuit 110 of Figure 2, except for the charge discharge unit 114, the coupling unit 117, and the second charge holding unit, the description of wiring is omitted. Furthermore, the wiring connecting the charge holding unit 112 and the amplification unit 118 is referred to as the charge holding unit wiring.

[0194] The figure shows the charge holding section wiring 180. A capacitor-attached wiring 280 is connected to this charge holding section wiring 180. The capacitor-attached wiring 280 is a wiring that attaches a capacitor to the charge holding section 112 via the charge holding section wiring 180. As will be described later, the capacitor-attached wiring 280 is configured in the same way as the through-hole 273 shown in Figure 18, forming a shape that penetrates the semiconductor substrate 250.

[0195] Furthermore, a signal processing circuit 90 is connected to the output (first output node 101) of pixel 100 in this figure. This signal processing circuit 90 processes the signal generated by pixel 100. For example, the signal processing circuit 90 may be configured with a constant current circuit 105, a signal level holding circuit 130, and a downstream circuit 120 as described in FIG2. Furthermore, pixel 100 is disposed on semiconductor substrate 150, and the downstream circuit, i.e., the signal processing circuit 90, is disposed on semiconductor substrate 250.

[0196] [The Composition of a Pixel Plane] Figure 36 is a top view showing an example of the pixel configuration of the eighth embodiment of this disclosure. This figure, like Figure 5, shows an example of the pixel 100 configuration. This figure illustrates an example of the arrangement of the constituent components of the pixel 100 on the surface of the semiconductor substrate 150. In this figure, the shaded area indicated by the diagonal lines represents the wiring disposed in the wiring region 170 of the semiconductor substrate 150. Otherwise, the same description as in Figure 5 is used.

[0197] A photoelectric conversion unit 111 (PD) is disposed at the center of pixel 100. A through-hole 273 is disposed at the upper right of the photoelectric conversion unit 111 via wiring. The wiring below the through-hole 273 is connected to a contact. A charge transfer unit 115 (TRG) is disposed adjacent to the left side of the photoelectric conversion unit 111. A charge holding unit 112 (FD) is disposed below the charge transfer unit 115. A first reset unit 116 (RST) is disposed to the right of the charge holding unit 112. A power line Vdd is disposed on the drain side of the first reset unit 116, and a through-hole 273 is disposed on the power line Vdd. A first selection unit 119 (SW) and an amplification unit 118 (AMP) are disposed on the left side of the photoelectric conversion unit 111. The wiring above the first selection unit 119 is connected to the output node 101 (Vo), and a through-hole 273 is disposed thereon. The source side of the amplifier section 118 is connected to the power supply line Vdd.

[0198] A charge-holding section wiring 180 is disposed between the gate of the amplification section 118 and the semiconductor region of the charge-holding section 112. A capacitor-attached wiring 280 is disposed on this charge-holding section wiring 180. Furthermore, as described later, the charge-holding section wiring 180 is composed of wiring 183 connecting the gate of the amplification section 118 and the charge-holding section 112, and contact plugs 181 and 182. For convenience, in the top view, the wiring connecting the gate of the amplification section 118 and the charge-holding section 112 is referred to as charge-holding section wiring 180.

[0199] [The Composition of a Pixel's Cross-Section] Figure 37 is a cross-sectional view showing an example of the pixel configuration according to the eighth embodiment of this disclosure. This figure, like Figure 18, shows an example of the pixel 100 configuration. For convenience, the color filter 192, the crystal lens 194, and the semiconductor region of the semiconductor substrate 150 are omitted. The pixel 100 in this figure is disposed on the semiconductor substrate 250 of the laminated semiconductor substrates 150 and 250. The figure shows the charge holding portion 112, the charge transport portion 115, and the amplification portion 118 in the pixel 100. As mentioned above, the charge holding portion 112 is composed of a semiconductor region 143 formed on the semiconductor substrate 150. Furthermore, the figure shows the gate 162 of the charge transport portion 115 and the gate 165 of the amplification portion 118.

[0200] The gate 162 of the charge transfer section 115 is connected to the wiring 172 via the contact plug 173. A through-hole 276 is connected to the wiring 172. The through-hole 276 passes through the semiconductor substrate 250 and is connected to the wiring (wiring 272) of the wiring area 270 of the semiconductor substrate 250.

[0201] A contact plug 181 is connected to the gate 165 of the amplification section 118. A contact plug 182 is also connected to the semiconductor region 143 of the charge holding section 112. These contact plugs 181 and 182 are commonly connected to wiring 183. These contact plugs 181 and 182, along with wiring 183, constitute the charge holding section wiring 180. A capacitor-attached wiring 280 is connected to wiring 183 of the charge holding section wiring 180. The capacitor-attached wiring 280, like the through-hole 276, is configured to penetrate the semiconductor substrate 250. Specifically, the capacitor-attached wiring 280 is disposed at an opening 259 formed in the semiconductor substrate 250, and a separation layer 258 is disposed around the capacitor-attached wiring 280 at the opening 259. This separation layer 258 separates the capacitor-attached wiring 280 from the semiconductor substrate 250. The separation layer 258 can be formed, for example, by a film of an oxide such as silicon oxide (SiO2) or a dielectric. In addition, the through hole 276 can also be formed in the same way as the capacitor additional wiring 280.

[0202] As described above, since the charge holding section 112 and the amplification section 118 are disposed on the semiconductor substrate 150, they can be connected using wiring in the wiring area 170 of the semiconductor substrate 150. Since the wiring is completed in the wiring area 170, the pixel 100 can be miniaturized. Conversely, when the amplification section 118 is disposed on the semiconductor substrate 250, there is a need to use through-hole 273 to connect the charge transfer section 115 and the amplification section 118.

[0203] Furthermore, a floating capacitor (parasitic capacitance) is formed between the charge holding section wiring 180 and the well region of the semiconductor substrate 150. Since this floating capacitor is connected in parallel with the charge holding section 112, the floating capacitance of the charge holding section wiring 180 is added to the charge holding section 112. This increases the capacitance of the charge holding section 112. However, since the charge holding section wiring 180 terminates in the wiring region 170 as described above, the floating capacitance is small, and the capacitance added to the charge holding section 112 is insufficient. If the capacitance of the charge holding section 112 is insufficient, the saturation charge decreases, and the dynamic range of the signal generated by the amplification section 118 narrows. When the output signal of the pixel 100 is used as the image signal, the image quality deteriorates.

[0204] Therefore, a capacitor-attached wiring 280 is connected to the charge holding section wiring 180. As shown in the figure, the capacitor-attached wiring 280 is formed into a columnar shape reaching the wiring region 270, thus increasing its surface area. This increases the floating capacitance. By connecting this capacitor-attached wiring 280 to the charge holding section wiring 180, the floating capacitance of the charge holding section wiring 180 increases, and the capacitance attached to the charge holding section 112 also increases.

[0205] [Construction of capacitor additional wiring] Figure 38 is a diagram showing an example of the configuration of the capacitor-attached wiring according to the eighth embodiment of this disclosure. This figure is a cross-sectional view showing an example of the configuration of the capacitor-attached wiring 280 in a portion of the opening 259 of the semiconductor substrate 250. As described above, the capacitor-attached wiring 280 is configured to pass through the shape formed in the opening 259 of the semiconductor substrate 250. A separation layer 258 is disposed between the opening 259 and the capacitor-attached wiring 280.

[0206] Thus, in the eighth embodiment disclosed herein, the pixel 100 has a capacitor-attached wiring 280 connected to the charge-holding wiring 180 connecting the charge-holding section 112 and the amplification section 118. This increases the capacitance attached to the charge-holding section 112.

[0207] (9. Ninth Implementation Form) In the eighth embodiment described above, the pixel 100 has a capacitor-attached wiring 280 disposed at the opening 259 of the semiconductor substrate 250. In contrast, the pixel 100 of the ninth embodiment disclosed herein further has other through-holes disposed at the opening 259 of the semiconductor substrate 250, which is different from the eighth embodiment described above.

[0208] [The Composition of a Pixel's Cross-Section] Figure 39 is a cross-sectional view showing an example of the pixel configuration of the ninth embodiment of this disclosure. This figure is a cross-sectional view of an example of the pixel 100 configuration, similar to Figure 37. Unlike the pixel 100 in Figure 37, the opening 259 of the semiconductor substrate 250 also has a through-hole 276 in addition to the capacitor additional wiring 280.

[0209] As shown in the figure, by concentrating the capacitor additional wiring 280 and the through hole 276 into a single opening 259, the area occupied by the opening can be reduced compared to forming multiple openings on the semiconductor substrate 250. This expands the area of ​​the semiconductor substrate 250 where the signal processing circuit 90 can be configured.

[0210] Furthermore, it is preferable to arrange the capacitor-attached wiring 280 and the through-hole 276 connected to the gate of the charge transfer section 115 in the same opening 259, as they are close to each other. This is because the coupling capacitance of the capacitor-attached wiring 280 and the through-hole 276 increases, thereby increasing the potential rise of the charge holding section 112 caused by the signal applied to the gate of the charge transfer section 115.

[0211] [Construction of capacitor additional wiring] Figures 40A and 40B are diagrams showing examples of the configuration of capacitor-attached wiring according to the ninth embodiment of this disclosure. These figures, like Figure 38, show examples of the configuration of capacitor-attached wiring 280 in the opening 259 of the semiconductor substrate 250.

[0212] Figure 40A shows an example of a case where a capacitor additional wiring 280 and a through-hole 276 are arranged in the opening 259. Figure 40B shows an example of a case where, in addition to the capacitor additional wiring 280 and the through-hole 276, a through-hole 273 is also arranged in the opening 259. The through-hole 273 is, for example, a through-hole for transmitting a reference potential (ground potential).

[0213] The configuration of the light detection device 1 other than that of the light detection device 1 in the eighth embodiment of this disclosure is the same, so the description is omitted.

[0214] Thus, in the ninth embodiment disclosed herein, the pixel 100 has a capacitor additional wiring 280 and a through hole disposed in the opening 259 of the semiconductor substrate 250. This reduces the area occupied by the opening of the semiconductor substrate 250 and expands the area where the signal processing circuit 90 can be disposed.

[0215] (10. Tenth Implementation) In the eighth embodiment described above, pixel 100 has a capacitor-attached wiring 280 connected to the charge holding section wiring 180. In contrast, in the tenth embodiment disclosed herein, pixel 100 connects a plurality of capacitor-attached wirings 280 to the points of the charge holding section wiring 180, which differs from the eighth embodiment described above.

[0216] [The Composition of a Pixel Plane] Figure 41 is a top view showing an example of the pixel configuration of the tenth embodiment of this disclosure. This figure, like Figure 36, shows an example of the pixel 100 configuration. The pixel 100 in this figure differs from the pixel 100 in Figure 36 in that the point where the capacitor supplementary wiring 280 and capacitor supplementary wiring 281 are connected to the charge holding section wiring 180 is different. Because a plurality of capacitor supplementary wirings (capacitor supplementary wirings 280 and 281) are connected to the charge holding section wiring 180, the capacitance added to the charge holding section 112 increases compared to the case where only capacitor supplementary wiring 280 is connected to the charge holding section wiring 180.

[0217] [The Composition of a Pixel's Cross-Section] Figure 42 is a cross-sectional view showing an example of the pixel configuration of the tenth embodiment of this disclosure. This figure, like Figure 37, shows an example of the pixel 100 configuration. The pixel 100 in this figure differs from the pixel 100 in Figure 37 in that it further configures a point connected to the capacitor-attached wiring 281 of the charge-holding portion wiring 180. Similar to the capacitor-attached wiring 280, the capacitor-attached wiring 281 is also disposed at an opening formed on the semiconductor substrate 250.

[0218] The configuration of the light detection device 1 other than that of the light detection device 1 in the eighth embodiment of this disclosure is the same, so the description is omitted.

[0219] Thus, in the tenth embodiment disclosed herein, pixel 100 has a plurality of capacitors additionally wired to charge holding section wiring 180. This allows for further increase in the capacitance attached to charge holding section 112.

[0220] (11. 11th Implementation) In the eighth embodiment described above, the pixel 100 retains the charge generated by the photoelectric conversion unit 111 in the charge holding unit 112. In contrast, the pixel 100 of the eleventh embodiment disclosed herein further includes a second charge holding unit 113 and a coupling unit 117, and retains the charge generated by the photoelectric conversion unit 111 at the point where the charge is held in the charge holding unit 112 and the second charge holding unit 113, which is different from the eighth embodiment described above.

[0221] [Pixel Composition] Figure 43 is a diagram showing an example of the configuration of the light detection device according to the 11th embodiment of this disclosure. This figure is a circuit diagram showing an example of the configuration of pixel 100, similar to Figure 35. Pixel 100 in this figure further includes a coupling portion 117 and a second charge holding portion 113, which differs from pixel 100 in Figure 35. The wiring of the coupling portion 117 and the second charge holding portion 113 is the same as in Figure 2, so its description is omitted. Furthermore, the wiring connecting the coupling portion 117 and the second charge holding portion 113 is referred to as the second charge holding portion wiring 185. The second charge holding portion wiring 185 is the wiring connected to the second charge holding portion 113. Capacitor additional wiring may also be further connected to the second charge holding portion wiring 185. The capacitor additional wiring 282 in this figure shows an example of a capacitor additional wiring connected to the second charge holding portion wiring 185.

[0222] [The Composition of a Pixel Plane] Figure 44 is a top view showing an example of the pixel configuration of the 11th embodiment of this disclosure. This figure, like Figure 36, shows an example of the pixel configuration 100. The pixel 100 in this figure further includes a coupling portion 117 (FDG) and a second charge holding portion 113 (FD2), which differs from the pixel 100 in Figure 36. Furthermore, a plurality of capacitor-attached wirings (capacitor-attached wirings 280 and 281) are arranged on the charge holding portion wiring 180 in this figure, and a plurality of through-holes (through-holes 290 and 291) are arranged on the gate wiring 187 of the charge transfer portion 115. These capacitor-attached wirings 280 and 281 and through-holes 290 and 291 are arranged alternately adjacent to each other. In this way, the coupling capacitance of the capacitor-added wiring 280 and wiring 187 is increased, which can further increase the potential rise of the charge holding part 112 caused by the signal applied to the gate of the charge transfer part 115.

[0223] Figures 45 and 46 are top views showing another configuration example of the pixel of the 11th embodiment of this disclosure. These figures, like Figure 44, show a top view of a configuration example of pixel 100. Figure 45 shows an example of capacitor-attached wirings 282 and 283 arranged in the second charge-holding section wiring 185. The capacitor-attached wirings 282 and 283, along with through-holes 290 and 291, are arranged alternately adjacent to each other.

[0224] Figure 46 shows an example where a capacitor additional wiring 280 is arranged in the charge holding section wiring 180 and a capacitor additional wiring 282 is arranged in the second charge holding section wiring 185. The capacitor additional wirings 280 and 282 and the through holes 290 and 291 are arranged alternately adjacent to each other.

[0225] The configuration of the light detection device 1 other than that of the light detection device 1 in the eighth embodiment of this disclosure is the same, so the description is omitted.

[0226] Thus, the pixel 100 in the 11th embodiment disclosed herein further includes a coupling portion 117 and a second charge holding portion 113. This allows for adjustment of the sensitivity of the pixel 100.

[0227] (12. Twelfth Implementation) The pixel 100 in the 11th embodiment described above includes a second charge holding portion 113 and a coupling portion 117, and the sensitivity of the pixel 100 is adjusted. In contrast, the pixel 100 in the 12th embodiment disclosed herein further includes a second coupling portion 410 and a third charge holding portion 411, which is different from the 11th embodiment described above.

[0228] [Pixel Composition] Figure 47 is a diagram showing an example of the configuration of the light detection device according to the 12th embodiment of this disclosure. This figure is a circuit diagram showing an example of the configuration of pixel 100, similar to Figure 43. The pixel 100 in this figure further includes a second coupling portion 410 and a third charge holding portion 411, which is different from the pixel 100 in Figure 35.

[0229] The second coupling section 410 couples the third charge holding section 411 to the second charge holding section 113. This second coupling section 410 can be constructed using an n-channel MOS transistor. The drain of the second coupling section 410 is connected to the source of the first reset section 116 and one end of the third charge holding section 411. The other end of the third charge holding section 411 is grounded. The source of the second coupling section 410 is connected to the drain of the coupling section 117. The gate of the second coupling section 410 is connected to the signal line FDG2.

[0230] The third charge holding section 411 is a charge holding section formed by a semiconductor region disposed on the semiconductor substrate 150, similar to the charge holding section 112. By making the coupling section 117 and the second coupling section 410 conductive, the third charge holding section 411 can be coupled to the charge holding section 112. In this way, the sensitivity of the pixel 100 of the image can be adjusted in three stages.

[0231] The wiring connecting the second coupling section 410 and the third charge holding section 411 is referred to as the third charge holding section wiring 186. The third charge holding section wiring 186 is the wiring connected to the third charge holding section 411. Additional capacitor wiring may also be connected to the third charge holding section wiring 186.

[0232] [The Composition of a Pixel Plane] Figures 48A-48C are top views showing an example of the pixel configuration of the 12th embodiment of this disclosure. These figures, like Figure 36, are top views showing an example of the pixel 100 configuration. Furthermore, the pixel 100 in these figures represents an example where the second coupling portion 410 and the third charge holding portion 411 of Figure 47 are omitted.

[0233] In Figure 48A, a coupling portion 117 (FDG) is disposed below the charge holding portion 112 (FD). A second charge holding portion 113 (FD2) is disposed below the coupling portion 117. A first reset portion 116 (RST) is disposed to the right of the second charge holding portion 113. Furthermore, a second charge holding portion wiring 185 is disposed on the second charge holding portion 113. The second charge holding portion wiring 185 in this figure is configured as a longer wiring. By arranging this second charge holding portion wiring 185, the capacitance attached to the second charge holding portion 113 can be increased.

[0234] Figure 48B shows an example of a case where the capacitor additional wiring 280 of the charge holding section wiring 180 is removed, and the capacitor additional wiring 282 is arranged on the second charge holding section wiring 185.

[0235] Figure 48C shows an example of a case where capacitor auxiliary wiring 282 and capacitor auxiliary wiring 283 are arranged in the second charge holding section wiring 185.

[0236] Figures 49A and 49B are top views showing an example of the pixel configuration of the 12th embodiment of this disclosure. These figures, like those in Figures 48A, show an example of the pixel 100 configuration. The arrangement of the second coupling portion 410 and the third charge holding portion 411 differs from that in Figures 48A.

[0237] In Figures 49A and 49B, a second coupling portion 410 (FDG2) is arranged to the right of the second charge holding portion 113. A third charge holding portion 411 (FD3) is arranged above the second coupling portion 410. A first reset portion 116 is arranged above the third charge holding portion 411. A second charge holding portion wiring 185 is arranged in the second charge holding portion 113. A third charge holding portion wiring 186 is arranged in the third charge holding portion 411. By arranging the third charge holding portion wiring 186, the capacitance attached to the third charge holding portion 411 can be increased. Figure 49A shows an example of arranging a capacitor additional wiring 282 in the second charge holding portion wiring 185. Figure 49B shows an example of arranging a capacitor additional wiring 284 in the third charge holding portion wiring 186.

[0238] The configuration of the light detection device 1 other than that of the light detection device 1 in the 11th embodiment of this disclosure is the same, so the description is omitted.

[0239] Thus, the pixel 100 in the 12th embodiment disclosed herein further includes a second coupling portion 410 and a third charge holding portion 411. This allows for adjustment of the sensitivity of the pixel 100 in three stages.

[0240] (13. 13th Implementation) The pixel 100 of the first embodiment described above includes a circuit that generates a signal corresponding to the charge of the charge holding section 112. In contrast, the pixel 100 of the 13th embodiment disclosed herein shares the same circuit for generating a signal corresponding to the charge of the charge holding section 112 among a plurality of pixels 100, which is different from the first embodiment described above.

[0241] [The Composition of a Pixel Plane] Figure 50 is a top view showing an example of the pixel configuration of the 13th embodiment of this disclosure. This figure illustrates an example where pixels 100a, 100b, 100c, and 100d, each equipped with a photoelectric conversion unit 111 (PD) and a charge transfer unit 115 (TRG), are arranged in two columns and two rows, and each has a common charge holding unit 112 (FD). Furthermore, a first reset unit 116, a coupling unit 117, a magnification unit 118, and a first selection unit 119 are arranged adjacent to pixels 100a-100d. Also, a charge holding unit wiring 180 is connected to the common charge holding unit 112 of pixels 100a-100d. A capacitor-attached wiring 280 is connected to this charge holding unit wiring 180.

[0242] Figures 51A and 51B are top views showing another configuration example of the pixels according to the 13th embodiment of this disclosure. These figures, like those in Figure 50, show a top view of a configuration example of pixels 100a-100d. The difference from pixels 100a-100d in Figure 50 lies in the inclusion of a second charge-holding section wiring 185. Figure 51A shows an example where a capacitor-attached wiring 282 is arranged in the second charge-holding section wiring 185. Figure 51B shows an example where a capacitor-attached wiring 280 is arranged in the charge-holding section wiring 180, and a capacitor-attached wiring 282 is arranged in the second charge-holding section wiring 185.

[0243] The configuration of the light detection device 1 other than that of the light detection device 1 in the 11th embodiment of this disclosure is the same, so the description is omitted.

[0244] Thus, in the 13th embodiment disclosed herein, the pixel 100 shares a circuit that generates a signal based on the charge holding part 112 among the plurality of pixels 100. This allows for a reduction in the size of the light detection device 1.

[0245] (14. Implementation Form 14) The changes to the capacitor additional wiring 280 are explained.

[0246] [The Composition of a Pixel's Cross-Section] Figures 52A-52C are cross-sectional views showing an example of the configuration of the capacitor-attached wiring according to the 14th embodiment of this disclosure. Figure 52A shows an example of the capacitor-attached wiring 280 connecting to the wiring 272 of the first layer of the wiring region 270. Figure 52B shows an example of the capacitor-attached wiring 280 connecting the wiring 272 of the first and second layers. The wirings disposed on different layers are connected to each other by through-hole plugs 274. Figure 52C shows an example of the capacitor-attached wiring 280 connecting the wiring 272 of the first to third layers.

[0247] Thus, by connecting wiring 272 to capacitor additional wiring 280, the floating capacitance of capacitor additional wiring 280 can be further increased.

[0248] (15. Application Examples) Figure 53 shows one example of the general configuration of the camera system 7 of the light detection device 1 having the above-described embodiments and variations thereof.

[0249] The camera system 7 includes, for example, a digital still camera or video camera, or a portable terminal device such as a smartphone or tablet. The camera system 7 may include: a light detection device 1 as described in the above embodiments and variations; an optical system including a lens driving mechanism 741 and an aperture mechanism 742; a DSP circuit 743; a frame memory 744; a display unit 745; a memory unit 746; an operation unit 747; and a power supply unit 748. In the camera system 7, the light detection device 1, lens driving mechanism 741, mechanism 742, DSP circuit 743, frame memory 744, display unit 745, memory unit 746, operation unit 747, and power supply unit 748 as described in the above embodiments and variations are interconnected via a bus cable 749.

[0250] The photodetector 1 in the above-described embodiments and variations outputs image data corresponding to the incident light. The DSP circuit 743 is a signal processing circuit that processes the signal (image data) output from the photodetector 1 in the above-described embodiments and variations. The frame memory 744 temporarily stores the image data processed by the DSP circuit 743 in frame units. The display unit 745 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro-luminescent) panel, and displays the animation or still image captured by the photodetector 1 in the above-described embodiments and variations. The memory unit 746 records the image data of the animation or still image captured by the photodetector 1 in the above-described embodiments and variations onto a recording medium such as a semiconductor memory or a hard disk. The operation unit 747 issues operation commands for various functions of the camera system 7 according to the user's operation. The power supply unit 748 will be used to supply various power supplies for the operation of the photodetector 1, DSP circuit 743, frame memory 744, display unit 745, memory unit 746 and operation unit 747 in the above-described embodiments and variations.

[0251] Secondly, the camera sequence of camera system 7 will be explained.

[0252] Figure 54 shows an example of a flowchart of the camera operation of the camera system 7. The user instructs the camera to start by operating the operation unit 747 (step S101). If so, the operation unit 747 sends the camera command to the light detection device 1 (step S102). When the light detection device 1 (specifically the system control circuit 36) receives the camera command, it performs camera operation in a specific camera mode (step S103).

[0253] The light detection device 1 outputs the image data acquired by imaging to the DSP circuit 743. Here, the image data refers to the data of all pixels of the pixel signal generated by the charge temporarily held by the floating diffuser FD. The DSP circuit 1243 performs specific signal processing (e.g., noise reduction processing) on ​​the image data input from the light detection device 1 (step S104). The DSP circuit 743 stores the image data that has undergone specific signal processing in the frame memory 744, and the frame memory 744 stores the image data in the memory unit 746 (step S105). In this way, imaging is performed by the imaging system 7.

[0254] In this applicable example, the light detection device 1 of the above-described embodiments and variations is applied to the camera system 7. This allows for the miniaturization or high-precision scaling of the light detection device 1, thus providing a compact or high-precision camera system 7.

[0255] (16. Application examples for moving bodies) The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0256] Figure 55 is a block diagram showing a schematic configuration example of a vehicle control system, which is one example of a mobile body control system to which the technology disclosed herein can be applied.

[0257] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 56, the vehicle control system 12000 includes: a drive system control unit 12010, a vehicle body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, the figure shows a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 as functional components of the integrated control unit 12050.

[0258] The drive system control unit 12010 controls the operation of devices associated with the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or drive motor for generating drive force for the vehicle, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0259] The vehicle system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for keyless access systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves emitted from a portable device that replaces the key or signals from various switches can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 accepts such input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0260] The exterior information detection unit 12030 detects information about the exterior of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing, such as detection of people, vehicles, obstacles, signs, or text on the road surface.

[0261] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0262] The in-vehicle information detection unit 12040 detects information inside the vehicle. A driver status detection unit 12041, for example, detecting the driver's state, is connected to the in-vehicle information detection unit 12040. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, and can also determine whether the driver is drowsy.

[0263] The microcomputer 12051 can calculate the control target values ​​of the drive force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing the functions of ADAS (Advanced Driver Assistance System), including collision avoidance or shock mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

[0264] Furthermore, the microcomputer 12051 controls the drive force generating device, steering mechanism, or braking device based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for purposes such as autonomous driving that does not rely on the driver's operation.

[0265] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control to prevent glare, such as controlling the headlights and switching the high beams to low beams, based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030.

[0266] The audio-visual output unit 12052 is an output device that can visually or audibly notify passengers or the outside of the vehicle of information. It transmits at least one of sound and image signals. In the example of Figure 56, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and an in-vehicle display system.

[0267] Figure 56 shows an example of the installation position of the camera unit 12031.

[0268] In Figure 56, camera units 12101, 12102, 12103, 12104, and 12105 are used as camera unit 12031.

[0269] Cameras 12101, 12102, 12103, 12104, and 12105 are located, for example, on the front bumper, rearview mirrors, rear bumper, tailgate, and above the windshield inside the vehicle. The camera 12101 on the front bumper and the camera 12105 above the windshield inside the vehicle primarily acquire images of the front of the vehicle. The cameras 12102 and 12103 on the rearview mirrors primarily acquire images of the sides of the vehicle. The camera 12104 on the rear bumper or tailgate primarily acquires images of the rear of the vehicle. The camera 12105 above the windshield inside the vehicle is mainly used for detecting vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lane markings ahead.

[0270] Furthermore, Figure 56 shows an example of the imaging range of camera units 12101 to 12104. Camera range 12111 represents the imaging range of camera unit 12101 located on the front bumper; camera ranges 12112 and 12113 represent the imaging ranges of camera units 12102 and 12103 located on the rearview mirrors, respectively; and camera range 12114 represents the imaging range of camera unit 12104 located on the rear bumper or tailgate. For example, by overlaying the image data captured by camera units 12101 to 12104, a top-down view of vehicle 12100 can be obtained.

[0271] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera containing a plurality of camera elements, or a camera element having pixels for phase difference detection.

[0272] For example, the microcomputer 12051 calculates the distances to various three-dimensional objects within the camera range 12111 to 12114 and the temporal changes of those distances (relative to the vehicle 12100's speed) based on distance information obtained from cameras 12101 to 12104. Specifically, it can capture the three-dimensional object closest to the vehicle 12100's path, and that is traveling in approximately the same direction as the vehicle 12100 at a specific speed (e.g., 0 km / h or higher), as the vehicle ahead. Furthermore, the microcomputer 12051 can set a pre-emptive distance to ensure a safe following distance to the vehicle ahead, and perform automatic braking control (including stop-and-go control), automatic acceleration control (including start-and-go control), etc. This enables coordinated control aimed at autonomous driving, where the driver's actions are not required to control the vehicle ahead.

[0273] For example, the microcomputer 12051 can classify and capture three-dimensional object data related to three-dimensional objects based on distance information obtained from cameras 12101 to 12104, categorizing them into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For instance, the microcomputer 12051 identifies obstacles around vehicle 12100 as those visible to the driver and those difficult to see. Furthermore, the microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. When a collision risk exceeds a set value and a collision is possible, the microcomputer 12051 outputs an alarm to the driver via audio speaker 12061 or display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010, thus providing driving support to avoid collisions.

[0274] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. Such pedestrian identification is performed by, for example, a process of extracting feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras, and a process of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay and display a square outline for emphasis on the identified pedestrian. Furthermore, the audio-visual output unit 12052 can also control the display unit 12062 to display icons representing pedestrians at desired locations.

[0275] The above description addresses an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein is applicable to the camera unit 12031 in the configuration described above. Specifically, the light detection device 1 of FIG1 can be applied to the camera unit 12031. By applying the technology disclosed herein to the camera unit 12031, the camera unit 12031 can be miniaturized.

[0276] (17. Examples of the application of endoscopic surgical systems) The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the technology disclosed herein can be applied to endoscopic surgical systems.

[0277] Figure 57 is a diagram showing one example of the schematic configuration of an endoscopic surgical system to which the technology disclosed herein (the technology) can be applied.

[0278] Figure 57 illustrates the situation where the surgeon (doctor) 11131 uses the endoscopic surgical system 11000 to perform surgery on the patient 11132 on the bed 11133. As shown, the endoscopic surgical system 11000 includes: an endoscope 11100, other surgical instruments 11110 such as an insufflator 11111 or energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a trolley 11200 equipped with various devices for endoscopic surgery.

[0279] Endoscope 11100 includes: a tube 11101, which is inserted into the body cavity of a patient 11132 for a specific length from its tip; and a camera head 11102, which is connected to the base of the tube 11101. In the illustrated example, the endoscope 11100 is configured as a rigid endoscope with a rigid tube 11101, but the endoscope 11100 can also be configured as a flexible endoscope with a flexible tube.

[0280] An opening for embedding an objective lens is provided at the front end of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100. The light generated by the light source device 11203 is guided by a light guide extending inside the endoscope tube 11101 to the front end of the endoscope tube, and then illuminates the object to be observed inside the body cavity of the patient 11132 via the objective lens. Furthermore, the endoscope 11100 can be a direct viewing endoscope, an oblique viewing endoscope, or a side viewing endoscope.

[0281] An optical system and an imaging element are disposed inside the camera head 11102. Reflected light from the observed object (observation light) is focused onto the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is sent as raw (RAW) data to the camera control unit (CCU) 11201.

[0282] The CCU 11201, composed of a CPU (Central Processing Unit) or GPU (Graphics Processing Unit), comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing operations on the image signals, such as developing (de-mosaicing), for displaying images based on those image signals.

[0283] The display device 11202 displays an image based on an image signal that has undergone image processing by the CCU 11201, under control from the CCU 11201.

[0284] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical site.

[0285] Input device 11204 is the input interface for endoscopic surgery system 11000. Users can input various information or instructions to endoscopic surgery system 11000 through input device 11204. For example, users can input instructions to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0286] The treatment device control device 11205 controls the drive of the energy treatment device 11112 used for cauterizing tissue, cutting, or sealing blood vessels. The pneumoperitoneum device 11206, for the purpose of ensuring the field of vision of the endoscope 11100 and ensuring the operator's working space, inflates the patient's 11132 body cavity by introducing gas into the cavity through the pneumoperitoneum tube 11111. The recorder 11207 is a device that can record various information related to the surgery. The printer 11208 is a device that can print various information related to the surgery in various forms such as text, images, or charts.

[0287] Furthermore, the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site may include, for example, an LED, a laser light source, or a white light source composed of a combination of such sources. When a white light source is composed of a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision, thus allowing for white balance adjustment of the photographic image within the light source device 11203. In this case, by illuminating the object of observation with laser light from each of the RGB laser light sources in a time-division manner, and controlling the driving of the imaging element of the camera head 11102 synchronously with the illumination timing, images corresponding to each of the RGB sources can also be captured in a time-division manner. According to this method, color images can be obtained even if a color filter is not provided on the imaging element.

[0288] Furthermore, the light source device 11203 can control the drive by changing the intensity of the output light at specific intervals. By controlling the drive of the imaging element of the camera head 11102 in sync with the timing of the light intensity changes, images are acquired in time-division multiplexing, and these images are combined to produce high dynamic range images that are free from underexposure and overexposure.

[0289] Furthermore, the light source device 11203 can be configured to supply light in a specific wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption by biological tissues, light with a narrower frequency band than the light used in general observation (i.e., white light) can be irradiated to perform so-called narrow-band imaging (narrow-band imaging) of specific tissues such as blood vessels on the mucosal surface, using high-contrast imaging. Alternatively, in special light observation, fluorescence observation can be performed using fluorescence generated by irradiating excitation light to obtain an image. In fluorescence observation, one can irradiate biological tissue with excitation light to observe the fluorescence from that biological tissue (autofluorescence observation), or locally inject a reagent such as indocyanine green (ICG) into biological tissue and irradiate the biological tissue with excitation light corresponding to the fluorescence wavelength of that reagent to obtain a fluorescence image. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0290] Figure 58 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 57.

[0291] Camera head 11102 includes: lens unit 11401, imaging unit 11402, drive unit 11403, communication unit 11404, and camera head control unit 11405. CCU 11201 includes: communication unit 11411, image processing unit 11412, and control unit 11413. Camera head 11102 and CCU 11201 can be communicatively connected to each other via transmission cable 11400.

[0292] Lens unit 11401 is an optical system disposed at the connection portion with lens barrel 11101. Observation light captured from the front end of lens barrel 11101 is guided to camera head 11102 and incident on lens unit 11401. Lens unit 11401 is composed of a plurality of lenses, including zoom lens and focusing lens.

[0293] The imaging element constituting the imaging unit 11402 can be a single unit (so-called single-plate type) or multiple units (so-called multi-plate type). When the imaging unit 11402 is configured as a multi-plate type, for example, each imaging element can generate an image signal corresponding to each of the RGB values, and a color image can be obtained by combining them. Alternatively, the imaging unit 11402 can be configured to have a pair of imaging elements for acquiring image signals for the right eye and left eye respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue at the surgical site. Furthermore, when the imaging unit 11402 is configured as a multi-plate type, multiple lens units 11401 can also be provided in a system corresponding to each imaging element.

[0294] Furthermore, the camera unit 11402 may not necessarily be located in the camera head 11102. For example, the camera unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0295] The drive unit 11403 includes an actuator that, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a specific distance along the optical axis. This allows for appropriate adjustment of the magnification and focus of the image captured by the imaging unit 11402.

[0296] The communication unit 11404 is a communication device used to send and receive various information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the camera unit 11402 as raw (RAW) data to the CCU 11201 via the transmission cable 11400.

[0297] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals may include, for example, information related to shooting conditions such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0298] Furthermore, the aforementioned image conditions, such as frame rate or exposure value, magnification, and focus, can be appropriately specified by the user, or automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 needs to be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0299] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0300] The communication unit 11411 is a communication device used to send and receive various information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0301] Furthermore, the communication unit 11411 sends control signals to the camera head 11102 to control the driving of the camera head 11102. The image signal or control signal can be transmitted via electrical communication or optical communication, etc.

[0302] The image processing unit 11412 performs various image processing operations on the raw (RAW) data, i.e., the image signal, sent by the camera head 11102.

[0303] The control unit 11413 performs various controls related to the endoscope 11100's imaging of the surgical site, etc., and the display of the image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0304] Furthermore, the control unit 11413 displays a camera image showing the surgical site, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition technologies to identify various objects within the camera image. For example, by detecting the shape or color of the edges of objects contained in the camera image, the control unit 11413 can identify surgical instruments such as forceps, specific biological sites, bleeding, and mist during the use of the energy treatment device 11112. When displaying the camera image on the display device 11202, the control unit 11413 can use the recognition results to overlay various surgical support information onto the image of the surgical site. By overlaying surgical support information, prompts are given to the surgeon 11131, reducing the surgeon's workload and allowing the surgeon to perform the surgery effectively.

[0305] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 can be an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable of the like.

[0306] In the example shown, wired communication can be achieved using transmission cable 11400, but communication between camera head 11102 and CCU 11201 can also be wireless.

[0307] The above description addresses an example of an endoscopic surgical system to which the technology disclosed herein is applicable. The technology disclosed herein can be applied to the endoscope 11100 or the imaging unit 11402 of the camera head 11102 in the configuration described above. Specifically, the light detection device 1 of FIG1 can be applied to the imaging unit 11402. By applying the technology disclosed herein to the imaging unit 11402, the imaging unit 11402 can be miniaturized.

[0308] Furthermore, this description is provided as an example for an endoscopic surgical system, but the techniques disclosed herein can also be applied to, for example, microscopic surgical systems.

[0309] Furthermore, the effects described in this instruction manual are ultimately illustrative and not limited to any particular effect, and may have other effects as well.

[0310] In addition, this technology can also be configured as follows. (1) A photodetector element having: A photoelectric conversion unit is formed on a semiconductor substrate and generates a charge corresponding to the incident light; A charge transfer unit that transfers the aforementioned charge to a charge holding unit that holds the aforementioned charge; The first reset unit is disposed adjacent to the aforementioned charge holding unit and resets the aforementioned charge holding unit; The amplification section generates a signal corresponding to the charge held in the aforementioned charge holding section and outputs it to a specific first output node; A constant current circuit is connected to the aforementioned first output node and constitutes the load of the aforementioned amplification section; The first capacitor element has one end connected to the aforementioned first output node and maintains the level of the aforementioned signal, i.e., the reset level, during the reset performed by the aforementioned first reset unit; The second capacitor element has one end connected to the first output node and maintains the level of the aforementioned signal, i.e., the image signal level, when the aforementioned charge is transferred to the aforementioned charge holding part; A first switching element is connected between the other end of the aforementioned first capacitor element and a specific second output node, and controls the current flowing through the aforementioned first capacitor element; A second switching element is connected between the other end of the aforementioned second capacitor element and the aforementioned second output node, and controls the current flowing through the aforementioned second capacitor element; The second reset section resets the aforementioned second output node; The readout circuit, connected to the aforementioned second output node, reads the reset level held by the aforementioned first capacitor element and the image signal level held by the aforementioned second capacitor element, and outputs them as the reset signal and the image signal, respectively; and The substrate contacts supply a reference potential to the aforementioned semiconductor substrate. (2) The photodetector as described in (1) further includes a charge discharge section for discharging the charge from the aforementioned photoelectric conversion section. (3) The optical detection element as described in (1) or (2) further comprises: The second charge holding part retains the aforementioned charge; and The coupling portion couples the aforementioned charge holding portion and the aforementioned second charge holding portion; and The aforementioned first reset unit resets the aforementioned charge holding unit via the aforementioned coupling unit. (4) The light detection element of any one of (1) to (3) above further has a selection section connected between the aforementioned amplification section and the aforementioned first output node. (5) The photodetector as described in any one of (1) to (4) above has a plurality of pixels, the plurality of pixels comprising: the aforementioned photoelectric conversion unit, the aforementioned charge transfer unit, the aforementioned first reset unit, the aforementioned amplification unit, the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switching element, the aforementioned second switching element, the aforementioned second reset unit, the aforementioned readout circuit and the aforementioned substrate contact. (6) As described in (5) above, the aforementioned substrate contacts are shared among adjacent aforementioned pixels, and the aforementioned photoelectric conversion unit, the aforementioned charge transfer unit, the aforementioned first reset unit, the aforementioned amplification unit, the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switch element, the aforementioned second switch element, the aforementioned second reset unit and the aforementioned readout circuit are arranged symmetrically to each other. (7) The light detection element as described in (5) above, wherein the aforementioned second reset part and the aforementioned readout circuit are shared in adjacent previously described pixels. (8) The optical detection element as described in any of (1) to (7) above further comprises: A second semiconductor substrate, deposited on the aforementioned semiconductor substrate, and comprising the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switching element, the aforementioned second switching element, and the aforementioned second reset portion; and The second substrate contact supplies a reference potential to the aforementioned second semiconductor substrate; and The aforementioned charge transfer section, the aforementioned first reset section, the aforementioned amplification section, and the aforementioned substrate contact are formed on the aforementioned semiconductor substrate. (9) As in the aforementioned photodetector (8), the aforementioned charge holding portion is composed of a semiconductor region, i.e., a floating diffusion layer, formed on the aforementioned semiconductor substrate. (10) As described in the aforementioned (9) light detection element, the aforementioned charge holding part is disposed between the aforementioned charge transfer part and the aforementioned first reset part. (11) As described in the aforementioned (9) light detection element, the aforementioned amplification part is disposed in the normal direction of the line connecting the aforementioned charge holding part and the aforementioned first reset part. (12) The optical detection element as described in (9) further comprises: A second charge-retaining portion is formed on the aforementioned semiconductor substrate and retains the aforementioned charge; and A coupling portion is formed on the aforementioned semiconductor substrate, and couples the aforementioned charge holding portion and the aforementioned second charge holding portion; and The aforementioned first reset unit resets the aforementioned charge holding unit via the aforementioned coupling unit. (13) As in the aforementioned (12) optical detection element, the aforementioned charge holding part is disposed between the aforementioned charge transfer part and the aforementioned coupling part. (14) As described in the aforementioned (12) light detection element, the aforementioned amplification part is disposed in the normal direction of the line connecting the aforementioned charge holding part and the aforementioned coupling part. (15) The photodetector element described in (9) further includes a charge discharge section formed on the aforementioned semiconductor substrate, which discharges the charge from the aforementioned photoelectric conversion section; and The aforementioned first reset section is formed in the same diffusion layer as the aforementioned charge discharge section. (16) As in the aforementioned (8) optical detection element, the aforementioned semiconductor substrate is stacked on the side of the aforementioned second semiconductor substrate on which the wiring area is formed. (17) As in the aforementioned (8) optical detection element, the aforementioned semiconductor substrate is stacked on the side of the aforementioned second semiconductor substrate that is different from the side on which the wiring area is formed. (18) The photodetector as described in any of (1) to (17) above, wherein the constant current circuit comprises two MOS transistors connected in series and applying bias voltages to the gates respectively. (19) A light detection device, comprising: A photoelectric conversion unit is formed on a semiconductor substrate and generates a charge corresponding to the incident light; A charge transfer unit that transfers the aforementioned charge to a charge holding unit that holds the aforementioned charge; The first reset unit is disposed adjacent to the aforementioned charge holding unit and resets the aforementioned charge holding unit; The amplification section generates a signal corresponding to the charge held in the aforementioned charge holding section and outputs it to a specific first output node; A constant current circuit is connected to the aforementioned first output node and constitutes the load of the aforementioned amplification section; The first capacitor element has one end connected to the aforementioned first output node and maintains the level of the aforementioned signal, i.e., the reset level, during the reset performed by the aforementioned first reset unit; The second capacitor element has one end connected to the first output node and maintains the level of the aforementioned signal, i.e., the image signal level, when the aforementioned charge is transferred to the aforementioned charge holding part; A first switching element is connected between the other end of the aforementioned first capacitor element and a specific second output node, and controls the current flowing through the aforementioned first capacitor element; A second switching element is connected between the other end of the aforementioned second capacitor element and the aforementioned second output node, and controls the current flowing through the aforementioned second capacitor element; The second reset section resets the aforementioned second output node; The readout circuit, connected to the aforementioned second output node, reads the reset level held by the aforementioned first capacitor element and the image signal level held by the aforementioned second capacitor element, and outputs them as the reset signal and the image signal, respectively. Substrate contacts that supply a reference potential to the aforementioned semiconductor substrate; and The processing circuit processes the aforementioned reset signal and the aforementioned image signal. (20) A photodetector element having: A photoelectric conversion unit is formed on a semiconductor substrate and generates a charge corresponding to the incident light; A charge transfer unit that transfers the aforementioned charge to a charge holding unit that holds the aforementioned charge; The first reset unit is disposed adjacent to the aforementioned charge holding unit and resets the aforementioned charge holding unit; The amplification section generates a signal corresponding to the charge held in the aforementioned charge holding section and outputs it to a specific first output node; A constant current circuit is connected to the aforementioned first output node and constitutes the load of the aforementioned amplification section; The first capacitor element maintains the level of the aforementioned signal during the reset performed by the first reset unit. The second capacitor element maintains the level of the aforementioned signal when the aforementioned charge is transferred to the aforementioned charge holding part; The acquisition unit transmits the aforementioned signal from the first output node to the first capacitor element and the second capacitor element. The second reset section resets the second output node connected to the other end of the aforementioned first capacitor element; The readout circuit, connected to the aforementioned second output node, reads the level of the signal held at the aforementioned first and second capacitor elements and outputs it as an image signal; and The substrate contacts supply a reference potential to the aforementioned semiconductor substrate. (twenty one) The photodetector as described in (20) further includes a charge discharge section for discharging the charge from the aforementioned photoelectric conversion section. (twenty two) The optical detection element as described in (20) further comprises: The second charge holding part retains the aforementioned charge; and The coupling portion couples the aforementioned charge holding portion and the aforementioned second charge holding portion; and The aforementioned first reset unit resets the aforementioned charge holding unit via the aforementioned coupling unit. (twenty three) As in the aforementioned (22) optical detection element, the aforementioned first reset portion and the aforementioned coupling portion are formed in a common diffusion layer. (twenty four) The light detection element of any one of (20) to (23) above, wherein the readout circuit is composed of a second amplification section and a first selection section, and the second amplification section generates a voltage signal corresponding to the signal level of the second output node as the aforementioned image signal, and the first selection section selects and outputs the aforementioned generated image signal. (25) As described in the aforementioned (24) optical detection element, the aforementioned amplification portion and the aforementioned second amplification portion are formed in a common diffusion layer. (26) The photodetector as described in (24) further includes a second selection unit that selects and outputs the level of the signal from the first output node. (27) As described in the aforementioned (26) light detection element, the aforementioned first selection portion and the aforementioned second selection portion are formed in a common diffusion layer. (28) The photodetector as described in (20) has a pixel, which includes: the aforementioned photoelectric conversion unit, the aforementioned charge transfer unit, the aforementioned first reset unit, the aforementioned amplification unit, the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned acquisition unit, the aforementioned second reset unit, the aforementioned readout circuit, and the aforementioned substrate contact. (29) As described in the light detection element (28) above, the aforementioned pixels are arranged in a square shape when viewed from above. (30) A photodetector element having: A photoelectric conversion unit is formed on the first semiconductor substrate and generates a charge corresponding to the incident light; A charge-retaining portion is formed on the aforementioned first semiconductor substrate and retains the aforementioned charge; The charge transfer unit transfers the charge from the aforementioned photoelectric conversion unit to the aforementioned charge holding unit; An amplification section, formed on the aforementioned first semiconductor substrate, generates a signal corresponding to the charge held in the aforementioned charge holding section, and outputs it to a specific output node; The reset section resets the aforementioned charge holding section; The substrate contact supplies a reference potential to the aforementioned first semiconductor substrate; A signal processing circuit is disposed on a second semiconductor substrate stacked on the side of the wiring area of ​​the aforementioned first semiconductor substrate, and processes the signal of the aforementioned output node; The charge holding section wiring connects the charge holding section and the amplification section wiring disposed in the aforementioned wiring region of the first semiconductor substrate; and A capacitor-attached wiring is connected to the aforementioned charge-holding portion wiring, which adds a capacitor to the aforementioned charge-holding portion and is configured as a through wiring that penetrates the aforementioned second semiconductor substrate. (31) The photodetector as described in (30) further has a separation layer disposed between the aforementioned capacitor additional wiring and the aforementioned second semiconductor substrate. (32) As described in the aforementioned (31) photodetector, the aforementioned separation layer is disposed at the opening formed in the aforementioned second semiconductor substrate; and A plurality of the aforementioned through wirings, including the aforementioned capacitor additional wirings, are disposed at the aforementioned opening. (33) The photodetector element, as described in any of (30) to (32) above, has a plurality of the aforementioned capacitor additional wirings connected to the aforementioned charge holding section wirings. (34) The optical detection element of any one of (30) to (33) mentioned above further has: A second charge-retaining portion is formed on the aforementioned first semiconductor substrate and retains the aforementioned charge; and A coupling portion is formed on the aforementioned first semiconductor substrate, and couples the aforementioned charge holding portion and the aforementioned second charge holding portion; and The aforementioned reset unit resets the aforementioned charge holding unit via the aforementioned coupling unit. (35) As described in the aforementioned (34) optical detection element, the aforementioned capacitor additional wiring is connected to the wiring of the second charge holding part, which is connected to the wiring of the aforementioned coupling part and the aforementioned second charge holding part disposed in the aforementioned wiring area of ​​the aforementioned first semiconductor substrate. (36) The optical detection element as described in any of (30) to (35) above has: A plurality of pixels, each having the aforementioned photoelectric conversion unit and the aforementioned charge transfer unit; and The aforementioned charge holding unit typically holds the charge of the aforementioned plurality of pixels. (37) The photodetector element of any of (30) to (36) above, wherein the aforementioned capacitor additional wiring is connected to the wiring area disposed on the aforementioned second semiconductor substrate.

[0311] 1: Optical detection device 7: Camera System 10, 10a, 10b: Pixel array section 11, 12, 41, 42, VSL: Signal lines 20: Vertical drive unit 30: Line Signal Processing Unit 40: Control Department 50: Logic Circuits 90: Signal processing circuit 100, 100a, 100b, 100c, 100d: pixels 101: First output node 102: Second output node 105, 105a, 105b, 105c, 105d: Constant current circuits 107: Well contact 108, 109, 509: MOS transistors 110, 110a, 110b, 110c, 110d: Front-end circuit 111,511: Photoelectric conversion unit 112,512: Charge holding section 113: Second charge holding section 114: Charge discharge section 115,515: Charge transfer section 116,516: First Reset Section 117,517: Coupling section 118,518: Enlarged section 119: First Selection Section 120: Rear Circuit 121,521: Second Reset Section 122,522: Second enlarged section 123,524: Second Choice Section 130, 130a, 130b, 130c, 130d: Signal level holding circuit 131,531: ​​First capacitor element 132,532: Second capacitor element 133: Third capacitor element 134: Fourth capacitor element 135: First switching element 136: Second switching element 137: Third Switching Element 138: Fourth Switching Element 141~144, 243, 343: Semiconductor region 150, 250, 350: Semiconductor substrate 151: Separation section 160, 191, 303, 304: Insulating film 161, 162, 165, 262, 362: Gate 170, 270, 370: Wiring area 171, 271, 371: Insulation layer 172, 183, 187, 272, 372: Wiring 173, 181, 182: Contact plugs 174,274: Through-hole plugs 175,379: Interlayer membrane 178,179,278,279: Pad 180: Wiring of charge holding section 185: Wiring of the second charge holding section 186: Wiring of the third charge holding section 192: Color Filter 193: Planarization film 194: Crystal-borne lens 195:Light-shielding film 196,259: Opening 258: Separation layer 273, 276, 290, 291: Through holes 280~284: Additional wiring for capacitors 301,306:Metal film 302,305: Barrier metal 410: Second coupling section 411: Third charge holding section 523: Selection Department 539: Sampling Section 741: Photographic lens drive mechanism 742: Aperture mechanism / mechanism 743: DSP Circuit 744: Frame Memory 745: Display Section 746: Memory Department 747: Operations Department 748: Power Supply Section 749: Busbar 11000: Endoscopic Surgical System 11100: Endoscopy 11101: Lens tube 11102: Camera head 11110: Surgical instruments 11111: Pneumoperitoneum tube 11112: Energy Disposal Equipment 11120: Support arm device 11131: Spellcaster (Doctor) 11132: Patient 11133: Hospital Bed 11200: Handcart 11201: Camera Control Unit / CCU 11202: Display device 11203: Light source device 11204: Input device 11205: Handling Equipment Control Device 11206: Pneumoperitoneum device 11207: Recorder 11208: Printer 11400: Transmission cable 11401: Lens Unit 11402, 12031, 12101~12105: Camera Department 11403: Drive Unit 11404: Communications Department 11405: Camera Head Control Unit 11411: Communications Department 11412: Image Processing Department 11413: Control Department 12000: Vehicle Control System 12001: Communication Network 12010: Drive system control unit 12020: Vehicle Body System Control Unit 12030: Exterior Information Detection Unit 12040: In-vehicle information detection unit 12041: Driver Status Monitoring Department 12050: Integrated Control Unit 12051: Microcomputer 12052: Audio and Image Output Unit 12053: In-vehicle network I / F 12061: Audio Speaker 12062: Display Unit 12063: Dashboard 12100: Vehicles 12111, 12112, 12113, 12114: Camera range AMP, AMP1: Enlarged section AMP2: Part 2 (Enlarged Version) C1: First capacitor element C2: Second capacitor element C3: Third capacitor element C4: Fourth capacitor element Cal: Second Reset Section DCG: Coupling section FD: Charge Holding Section / Floating Diffusion Section FD2: Second charge holding section FD3: Third charge holding section FDG: Signal line / coupler FDG2: Signal line / Second coupling section GND: Grounding wire OFG: Signal Line / Charge Discharge Section PC: Signal line / MOS transistor PD: Photoelectric conversion unit RB: Signal line / Second reset section RST: Signal line / First reset section RX: Coupling section Sample: Sampling section SEL: Signal line / selection section SEL2: Second Selection Section SF1: Enlarged section SF2: Part 2 (Enlarged) SW: Signal line / First selection section S1: Signal line / First switching element S2: Signal line / Second switching element S3: Signal line / 3rd switching element S4: Signal line / 4th switching element T1~T12, T20~T26: Step sequence TRG: Signal line / charge transfer section TX: Charge Transfer Unit V1: Semiconductor region of the first output node / Voltage waveform of the first output node V2: Semiconductor region of the second output node / Voltage waveform of the second output node VB: Signal line / MOS transistor VCAS: Bias voltage VDD1, VDD2, VREG: Power supply voltage Vdd, Vrge: Power cord Vft: Pressure Drop Vgs: Gate-source voltage VM,VRST1,VRST2,Vres,Vsig: Voltage Vo: Output node WC: Well Connection Point

Claims

1. A photodetector comprising: a photoelectric conversion section formed on a semiconductor substrate, generating a charge corresponding to incident light; a charge transfer section that transfers the charge to a charge holding section holding the charge; a first reset section disposed adjacent to the charge holding section, resetting the charge holding section; an amplification section that generates a signal corresponding to the charge held in the charge holding section and outputs it to a specific first output node; a constant current circuit connected to the first output node to form a load of the amplification section; a first capacitor element, one end of which is connected to the first output node and holds the level of the aforementioned signal, i.e., a reset level, when reset by the first reset section; a second capacitor element, one end of which is connected to the first output node and holds the level of the aforementioned signal, i.e., an image signal level, when the charge is transferred to the charge holding section; and a first switching element connected between the other end of the first capacitor element and a specific second output node, controlling the current flowing in the first capacitor element. A second switching element, connected between the other end of the aforementioned second capacitor element and the aforementioned second output node, controls the current flowing through the aforementioned second capacitor element; a second reset unit, which resets the aforementioned second output node; a readout circuit, connected to the aforementioned second output node, reads the aforementioned reset level held by the aforementioned first capacitor element and the aforementioned image signal level held by the aforementioned second capacitor element, and outputs them as a reset signal and an image signal; and a substrate contact, which supplies a reference potential to the aforementioned semiconductor substrate.

2. The photodetector element of claim 1 further comprises a charge discharge section for discharging the charge of the aforementioned photoelectric conversion section.

3. The photodetector element of claim 1 further comprises: a second charge holding portion that holds the aforementioned charge; and a coupling portion that couples the aforementioned charge holding portion and the aforementioned second charge holding portion; and the aforementioned first reset portion resets the aforementioned charge holding portion via the aforementioned coupling portion.

4. The light detection element of claim 1 further comprises a selection section connected between the aforementioned amplification section and the aforementioned first output node.

5. The photodetector element of claim 1, having a plurality of pixels, wherein the plurality of pixels comprises: the aforementioned photoelectric conversion unit, the aforementioned charge transfer unit, the aforementioned first reset unit, the aforementioned amplification unit, the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switching element, the aforementioned second switching element, the aforementioned second reset unit, the aforementioned readout circuit, and the aforementioned substrate contact.

6. The light detection element of claim 5, wherein the aforementioned substrate contacts are shared among adjacent aforementioned pixels, and the aforementioned photoelectric conversion unit, the aforementioned charge transfer unit, the aforementioned first reset unit, the aforementioned amplification unit, the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switching element, the aforementioned second switching element, the aforementioned second reset unit, and the aforementioned readout circuit are arranged symmetrically to each other.

7. The light detection element of claim 5, wherein the aforementioned second reset unit and the aforementioned readout circuit are shared in adjacent previously described pixels.

8. The photodetector as claimed in claim 1, further comprising: a second semiconductor substrate, which is deposited on the semiconductor substrate and includes the aforementioned constant current circuit, the aforementioned first capacitor element, the aforementioned second capacitor element, the aforementioned first switching element, the aforementioned second switching element and the aforementioned second reset portion; and a second substrate contact that supplies a reference potential to the aforementioned second semiconductor substrate; and the aforementioned charge transfer portion, the aforementioned first reset portion, the aforementioned amplification portion and the aforementioned substrate contact are formed on the aforementioned semiconductor substrate.

9. The photodetector element of claim 8, wherein the aforementioned charge holding portion is composed of a semiconductor region, i.e., a floating diffusion layer, formed on the aforementioned semiconductor substrate.

10. The photodetector element of claim 9, wherein the aforementioned charge holding section is disposed between the aforementioned charge transfer section and the aforementioned first reset section.

11. The light detection element of claim 9, wherein the aforementioned amplification portion is disposed in the normal direction of the line connecting the aforementioned charge holding portion and the aforementioned first reset portion.

12. The photodetector element of claim 9 further comprises: a second charge holding portion formed on the aforementioned semiconductor substrate to hold the aforementioned charge; and a coupling portion formed on the aforementioned semiconductor substrate to couple the aforementioned charge holding portion and the aforementioned second charge holding portion; and the aforementioned first reset portion resets the aforementioned charge holding portion via the aforementioned coupling portion.

13. The photodetector element of claim 12, wherein the aforementioned charge holding portion is disposed between the aforementioned charge transfer portion and the aforementioned coupling portion.

14. The photodetector element of claim 12, wherein the aforementioned amplification portion is disposed in the normal direction of the line connecting the aforementioned charge holding portion and the aforementioned coupling portion.

15. The photodetector element of claim 9 further comprises: a charge discharge section formed on the aforementioned semiconductor substrate for discharging the charge of the aforementioned photoelectric conversion section; and the aforementioned first reset section formed on the same diffusion layer as the aforementioned charge discharge section.

16. The photodetector element of claim 8, wherein the aforementioned semiconductor substrate is deposited on the side of the aforementioned second semiconductor substrate on which the wiring region is formed.

17. The photodetector element of claim 8, wherein the aforementioned semiconductor substrate is deposited on the side of the aforementioned second semiconductor substrate that is different from the side on which the wiring region is formed.

18. The photodetector as claimed in claim 1, wherein the aforementioned constant current circuit includes two MOS transistors connected in series and whose gates are respectively biased.

19. A light detection device comprising: a photoelectric conversion unit formed on a semiconductor substrate, generating a charge corresponding to incident light; a charge transfer unit that transfers the charge to a charge holding unit that holds the charge; a first reset unit disposed adjacent to the charge holding unit and resetting the charge holding unit; an amplification unit that generates a signal corresponding to the charge held in the charge holding unit and outputs it to a specific first output node; a constant current circuit connected to the first output node to form a load of the amplification unit; a first capacitor element, one end of which is connected to the first output node and holds the level of the aforementioned signal during the reset performed by the first reset unit, i.e., a reset level; a second capacitor element, one end of which is connected to the first output node and holds the level of the aforementioned signal when the charge is transferred to the charge holding unit, i.e., an image signal level; and a first switching element connected between the other end of the first capacitor element and a specific second output node to control the current flowing in the first capacitor element. A second switching element, connected between the other end of the aforementioned second capacitor element and the aforementioned second output node, controls the current flowing through the aforementioned second capacitor element; a second reset unit, which resets the aforementioned second output node; a readout circuit, connected to the aforementioned second output node, reads the aforementioned reset level held at the aforementioned first capacitor element and the aforementioned image signal level held at the aforementioned second capacitor element, and outputs them as a reset signal and an image signal; a substrate contact, which supplies a reference potential to the aforementioned semiconductor substrate; and a processing circuit, which processes the aforementioned reset signal and the aforementioned image signal.

Images