Pixel cell having Anti-blooming structure and image sensor

Abstract

A pixel unit is formed on a semiconductor substrate having a front surface. The pixel unit includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region, thereby controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate electrode and a pair of vertical gate electrodes disposed on the front surface of the semiconductor substrate. Each vertical gate electrode extends from the planar gate electrode to a gate depth in the semiconductor substrate. The first junction depth is greater than the gate depth.

Description

Pixel units and image sensors with anti-highlight-blowout structure This disclosure is generally related to complementary metal-oxide-semiconductor (CMOS) image sensors, and specifically, but not exclusively, to a specular spill-proof structure for a pixel unit and an image sensor. Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through device architecture design and image acquisition and processing. A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel circuit array with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge in the process. The image charge generated by the photosensitive elements can be transferred to a floating diffuser within the pixel circuit. The image charge transferred to the floating diffuser can be read from the pixel circuit via an analog output image signal on the row bits, the image charge varying according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and this amount of image charge is read out as an analog image signal from the row bits and converted into a digital value to provide information representing the external scene. In some imaging scenarios, highlight blowout artifacts degrade the quality of images captured by image sensors containing vertical gates. Highlight blowout is a type of electrical crosstalk that occurs when the number of photoelectrons accumulated in the photodiode of a pixel in response to incident light exceeds the pixel's saturation level (full-well capacity) (e.g., under very bright lighting conditions), causing the excess photoelectrons to be detected by one or more neighboring pixels. The embodiments disclosed herein address this problem by increasing the interface depth of one of the floating diffusion regions to introduce a buried highlight blowout prevention path between a photodiode and an associated floating diffusion region. This buried highlight blowout prevention path provides a leakage path that allows excess photoelectrons generated in the photodiode of a pixel unit to overflow from the photodiode to the floating diffusion region of the pixel unit during the integration (or exposure) cycle in which the associated transfer gate of the photodiode is turned off (e.g., negatively biased). Therefore, excess photoelectrons are detected without causing highlight blowout artifacts. This document describes an embodiment of a pixel unit structure for use in an imaging sensor to improve specular overflow. In the following description, numerous specific details are set forth to provide a thorough understanding of one embodiment. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects. Throughout this specification, the reference to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the invention. The appearance of the phrase "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, particular features, structures, or characteristics may be combined in one or more examples in any suitable manner. The following description of specific examples of components and configurations simplifies this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. It will be further understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or segments, such elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another, and do not limit or prescribe an order. Therefore, without departing from the teachings of the inventive concept, a first element, component, area, layer, or segment discussed below may be referred to as a second element, component, area, layer, or segment. For ease of description, spatial relative terms such as “below,” “below,” “under,” “below,” “above,” “upper,” and the like may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the illustrative terms “below” and “below” may cover both the above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers. It will be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediary element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediary element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "proximately" and "directly adjacent," etc.). It will be understood that when an element or layer is said to be "formed on" another element or layer, it may be formed directly or indirectly on the other element or layer. That is, for example, an intermediary element or layer may exist. Conversely, when an element or layer is said to be "directly formed on" another element, there is no intermediary element or layer. Other terms used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.). It should be understood that the term "photodiode region" can correspond to a region within a semiconductor substrate that is doped, for example, by ion implantation to have a charge carrier type (i.e., conductivity type) opposite to one of the majority of charge carrier types of the semiconductor substrate, such that an outer periphery of the doped region (e.g., referred to herein as a photodiode region) forms a PN junction or a PIN junction of a photodiode. For example, an N-doped region formed in a P-type semiconductor substrate forms a corresponding photodiode region. In some embodiments, a given pixel may further include a pinned region (e.g., a doped region disposed on one side of the semiconductor substrate between a photodiode region having a conductivity type opposite to that of the photodiode region) to form a pinned photodiode. For example, the pinned region has a P-type conductivity, while the photodiode region has an N-type conductivity. Several technical terms are used throughout this specification. These terms have their ordinary meaning in the technical field from which they are derived, unless expressly defined herein or otherwise indicated by the context in which they are used. Figure 1 illustrates an example block diagram of an imaging system 10 including an image sensor 100 according to the teachings of this disclosure. The image sensor 100 of the imaging system 10 is one possible embodiment of an image sensor having at least one pixel unit as illustrated in Figures 2A-2B, 3, 4A-4D and 5. The image sensor 100 includes a pixel array 110, control circuitry 130, readout circuitry 140 and functional logic 150. In one embodiment, the pixel array 110 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2..., Pn). As illustrated, photodiodes are arranged in columns (e.g., columns R1 to Ry) and rows (e.g., rows C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to present an image or video of the person, place, object, etc. However, photodiodes do not necessarily have to be configured in columns and rows, and other configurations can be used. In one embodiment, after each photodiode or image sensor pixel 112 in pixel array 110 has acquired its image data or image charge, the image data is read out by readout circuitry 140 and then transferred to functional logic 150. In various instances, readout circuitry 140 may include amplification circuitry, analog-to-digital converter (ADC) circuitry, or other circuitry. Functional logic 150 may simply store the image data, or even manipulate the image data by applying post-image effects (e.g., autofocus, cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.). In the same or another embodiment, readout circuitry 140 may read out a line of image data one at a time along readout line 120, or may use various other techniques (not shown) to read out the image data, such as simultaneous serial readout or fully parallel readout of all pixels. In one embodiment, control circuitry 130 is coupled to pixel array 110 to control the operation of a plurality of photodiode or image sensor pixels 112 in pixel array 110. For example, control circuit 130 may generate a shutter signal for controlling image acquisition. In some embodiments, control circuit 130 transmits signals through a plurality of contact pads in a bonding pad (BPAD) region surrounding pixel array 110 to control the operation of a plurality of photodiode or image sensor pixels 112 in pixel array 110. It should be understood that the imaging system 10 may be included in a digital camera, cell phone, laptop computer, surveillance camera, automotive camera, endoscope, or the like. The imaging system 10 may be coupled to other hardware, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash, electrical inputs (keyboard, touch display, touchpad, mouse, microphone, etc.) and / or display. Other hardware may send instructions to the imaging system 10 to retrieve image data from the imaging system 10 or to manipulate the image data supplied by the imaging system 10. It should be further understood that although the block diagram shown in FIG1 depicts the pixel array 110, readout circuitry 140, functional logic 150, and control circuitry 130 as separate and distinct elements from the pixel array, this is not necessarily the case, as such features may be directly combined with the pixel array or otherwise incorporated (e.g., within and / or between individual pixels, in the form of a stacked substrate, or in other forms). For example, according to an embodiment of this disclosure, readout circuitry 140 may include one or more transistors (e.g., associated with 3T, 4T, 5T, or other pixel architectures for reading image charge from individual pixels), and such elements may be disposed between segments of individual photodiodes. In some embodiments, the pixel array 110, readout circuit 140, functional logic 150, and control circuit 130 may all be formed on a single wafer (e.g., on the same die). For example, the pixel array 110 and readout circuit 140 are formed in an active region of a wafer, and the functional logic 150 and control circuit 130 are formed in a peripheral region surrounding the active region of the wafer. In some embodiments, the pixel array 110, readout circuitry 140, functional logic 150, and control circuitry 130 may be formed on separate wafers and bonded together via oxide bonding or hybrid bonding to form a stacked die structure. For example, the pixel array 110 is formed on a first wafer, while the readout circuitry 140, functional logic 150, and control circuitry 130 are formed on a second wafer, wherein the first and second wafers are bonded together, for example, by Cu-Cu bonding, oxide-to-oxide bonding, or hybrid bonding, thereby forming a two-layer stacked structure. In another example, the pixel array 110 is formed on a first wafer, the readout circuitry 140 is formed on a second wafer, and the functional logic 150 and control circuitry 130 are formed on a third wafer, wherein the first, second, and third wafers are bonded together, for example, by Cu-Cu bonding, oxide-to-oxide bonding, or hybrid bonding, thereby forming a three-layer stacked structure. Furthermore, the image sensor 100 may include features not explicitly shown or discussed but known to those skilled in the art, such as color filter arrays, microlens arrays, a metal grid, and the like. Additionally, it should be understood that the image sensor 100 may be manufactured using conventional CMOS manufacturing techniques known to those skilled in the art, including but not limited to photolithography, chemical vapor deposition, physical vapor deposition, ion implantation or diffusion, thermal oxidation, reactive ion etching, wet chemical etching, chemical mechanical polishing, and the like. The program described above can be implemented using software and / or hardware. The described techniques can be configured as machine-executable instructions embodied in a tangible or non-transitory machine-readable storage medium, which, when executed by a machine, will cause the machine to perform the described operations. Furthermore, the program can be embodied in hardware, such as an application-specific integrated circuit (“ASIC”), a field-programmable gate array (FPGA), or others. A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible to a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device having one or more processors, etc.). For example, a machine-readable storage medium includes recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). Figure 2A illustrates a plan view of an example pixel unit 200 having a vertical gate structure for an image sensor according to the teachings of the present invention. In various embodiments, the pixel unit 200 is one of a plurality of pixel units disposed in a pixel array of an image sensor. The pixel unit 200 is formed on a semiconductor substrate 210 (e.g., silicon, silicon-germanium alloy, germanium, silicon carbide alloy, gallium indium arsenide alloy, any other alloy formed of III-V compounds, other semiconductor materials or alloys, combinations thereof, such substrate, such doped substrate, such bulk substrate or such wafer) having a front surface (or front surface) and a back surface (or back surface) opposite to the front surface. Pixel unit 200 may include a plurality of photodiodes including photodiodes 212A, 212B, 212C and 212D, a plurality of transfer gates including a transfer gate 230A, a transfer gate 230B, a transfer gate 230C and a transfer gate 230D, a floating diffusion region 220, an isolation well region 223, a deep trench isolation structure 227 and a plurality of pixel transistors including at least a reset transistor 242, a source follower transistor 244 and a column select transistor 246. A plurality of photodiodes (e.g., photodiodes 212A, 212B, 212C, and 212D) are disposed in a semiconductor substrate 210. Each of photodiodes 212A, 212B, 212C, and 212D may be buried beneath the front surface of the semiconductor substrate 210. Note that in the illustrated example, pixel unit 200 includes four photodiodes 212A, 212B, 212C, and 212D. However, it should be understood that in other examples, pixel unit 200 may include more or fewer photodiodes. For example, in another example, pixel unit 200 may include eight photodiodes, while in another example, pixel unit 200 may include one photodiode. In another example, pixel unit 200 may contain nine photodiodes, while in another example, pixel unit 200 may contain two photodiodes. Each of photodiodes 212A, 212B, 212C, and 212D may include a photodiode region (or charge collection region) within the semiconductor substrate 210 for accumulating photogenerated image charges (e.g., electrons or holes) in response to incident light received during an integration or exposure cycle of the image sensor. The photodiode region may be formed by one or more implanted doped regions. The photodiode region has a conductivity type opposite to that of the semiconductor substrate 210. For example, the photodiode region may be an N-type doped region, while the semiconductor substrate 210 is a P-type doped substrate. Alternatively, the photodiode region may be a P-type doped region, while the semiconductor substrate 210 is an N-type doped substrate. Each of the transfer gates 230A, 230B, 230C, and 230D is positioned close to the front surface of the semiconductor substrate 210. Each of the transfer gates 230A, 230B, 230C, and 230D can be positioned between its respective photodiode 212A, 212B, 212C, 212D and the floating diffusion region 220. Each of the transfer gates 230A, 230B, 230C, and 230D couples one of the plurality of photodiodes 212A, 212B, 212C, 212D to the floating diffusion region 220, thereby controlling the charge flow between the plurality of photodiodes 212A, 212B, 212C, 212D and the floating diffusion region 220. Each of the plurality of transfer gates 230A, 230B, 230C and 230D is coupled in response to a respective transfer control signal to transfer the photogenerated image charge in the respective photodiode region of each photodiode 212A, 212B, 212C or 212D toward the front surface of the semiconductor material 210 and to the common floating diffusion region 220. Each of the transfer gates 230A, 230B, 230C, and 230D includes a planar gate electrode and a pair of vertical gate electrodes disposed on the front surface of the semiconductor substrate 210. These extend relative to the front surface from the corresponding planar gate electrode toward their respective underlying buried photodiodes 212A, 212B, 212C, or 212D into the semiconductor substrate 210 to a gate depth. Taking transfer gate 230B as an example, transfer gate 230B has a planar gate electrode 232 and a pair of vertical gate electrodes including a first vertical gate electrode 234A and a second vertical gate electrode 234B. The planar gate electrode 232 is disposed on the front surface of the semiconductor material 210. The first vertical gate electrode 234A and the second vertical gate electrode 234B each extend from the planar gate electrode 232 toward the photodiode 212B (e.g., the photodiode region toward the photodiode 212B) into the semiconductor substrate 210. The first vertical gate electrode 234A and the second vertical gate electrode 234B may be arranged in parallel and laterally spaced from each other. A floating diffusion region 220 is disposed in a semiconductor substrate 210 adjacent to a plurality of transfer gates 230A, 230B, 230C, and 230D. Each of the plurality of transfer gates 230A, 230B, 230C, and 230D can be configured between its respective photodiodes 212A, 212B, 212C, and 212D and the floating diffusion region 220. In an example, the floating diffusion region 220 is shared among the plurality of photodiodes 212A, 212B, 212C, and 212D. The floating diffusion region 220 is configured to store the charge transferred from each of the plurality of photodiodes 212A, 212B, 212C, and 212D through its respective transfer gates 230A, 230B, 230C, and 230D. The floating diffusion region 220 has the same conductivity type as the photodiode regions of the plurality of photodiodes 212A, 212B, 212C, and 212D. The floating diffusion region 220 is further coupled to a source of the reset transistor 242 and a source follower gate SF of the source follower transistor 244 via respective metal contacts 250 and one or more metal interconnects in one or more metallization layers (not shown). The source follower transistor 244 is coupled to modulate an image signal based on the voltage of the floating diffusion region 220. The image signal corresponds to the amount of photogenerated image charge accumulated in the respective photodiodes 212A to 212D during an integration period, transferred to the floating diffusion region 220 during a charge transfer period, and output from the floating diffusion region 220 to the source follower gate SF. Under the control of a column select signal RS_SIG, the column select transistor 246 selectively couples the output (e.g., the image signal) of the source follower transistor 244 to a row bit line (e.g., the readout row line 120 of FIG1) via corresponding metal contacts 250 and one or more metal interconnects in one or more metallization layers. It should be further understood that the illustrated pixel circuit architecture is only one example, and other pixel control architectures known in this art can also be used. For example, one drain of the reset transistor 242 and one drain of the source follower transistor 244 can be formed by a common doped region shared by the reset transistor 242 and the source follower transistor 244 to reduce the amount of space required for the pixel transistor. The isolation well region 223 includes an inner isolation well region 223A (or a first isolation well region) and an outer isolation well region 222B (or a second isolation well region). The inner isolation well region 223A is disposed in the semiconductor substrate 210 between adjacent photodiodes within the pixel unit 200 region, thereby providing electrical isolation between adjacent photodiodes. The inner isolation well region 223A provides internal isolation within the photodiodes within the pixel unit 200. For example, the inner isolation well region 223A is disposed between photodiode 212A and adjacent photodiodes, electrically isolating the photodiode region of photodiode 212A from the photodiode regions of adjacent photodiodes 212B, 212C, and 212D. An outer isolation region 223B may be disposed around the outer periphery of one of the pixel units 200, thereby providing electrical isolation between the photodiodes 212A to 212D of the pixel unit 200 and the photodiodes of adjacent pixel units 200. The outer isolation region 223B may surround a plurality of photodiodes 212A to 212D and further provide electrical isolation between the photodiodes and pixel transistors. For example, the outer isolation region 223B separates photodiodes 212C and 212D from pixel transistors (such as source follower transistor 244, reset transistor 246, and column select transistor 242) associated with the pixel unit 200. In an embodiment, the inner isolation well region 223A and the outer isolation well region 223B of the isolation well 223 may each be formed by a doped well region having a conductivity type opposite to that of the floating diffusion region 220 and the photodiode regions contained in each of the plurality of photodiodes 212A to 212D. For example, each of the inner isolation well region 223A and the outer isolation well region 223B is a P-type (such as a boron-doped region), i.e., a P-type well region, while the floating diffusion region 220 and the photodiode regions of the plurality of photodiodes are N-type doped regions (such as phosphorus and / or arsenic-doped regions). Each of the inner isolation well region 223A and the outer isolation well region 223B may have the same conductivity type as the semiconductor substrate 210, and each has a concentration higher than that of the semiconductor substrate 210. In one embodiment, the outer isolation well region 223B may be arranged in a grid across the pixel array of the image sensor, thereby providing isolation between adjacent pixel units. In one embodiment, the inner isolation well region 223A is electrically connected to the outer isolation well region 223B. The inner isolation well region 223A and the outer isolation well region 223B may be coupled to a ground through corresponding metal contacts in one or more metallization layers and one or more metal interconnects. In an embodiment, the substrate region of a pixel unit 200 containing a plurality of photodiodes 212A to 212D may be referred to as an active region 202 of the pixel unit 200, and the substrate region of a pixel unit 200 containing pixel transistors (such as a reset transistor 242, a source follower transistor 244, and a column select transistor 246) may be referred to as a transistor region 204 of the pixel 200. The transistor region 204 may be disposed on one side of the active region 202, for example, on a bottom side relative to the illustrated coordinate system 295. The pixel transistors in the transistor region 204 may be placed laterally along the x-direction of a coordinate system 295. It should be understood that the configuration and orientation of the transistor region 204 to the active region 202 may depend on pixel layout requirements; for example, the transistor region 204 may be disposed on the top, left, or right side relative to the active region 202, wherein the pixel transistors are placed along the y-direction of the coordinate system 295. Similarly, multiple transistor regions 204 can be arranged along different sides of the active region 202. The active region 202 is separated from the transistor regions 204 by an outer isolation well region 223B. Pixel unit 200 may include a buried channel implantation region 240 disposed in semiconductor substrate 210 below the front surface of semiconductor substrate 210 and close to the corresponding photodiode region of each photodiode 212A, 212B, 212C or 212D. The buried channel implantation region 240 is disposed between the first vertical gate electrode 234A and the second vertical gate electrode 234B of each transfer gate 230A to 230D to promote coupling between each of photodiodes 212A, 212B, 212C and 212D and the floating diffusion region 220. The buried channel implantation region 240 is implanted in such a manner that it forms a buried channel region in a substrate region of the semiconductor substrate 210 between the first vertical gate electrode 234A and the second vertical gate electrode 234B of each corresponding transfer gate 230A to 230B. The formed buried channel region extends from the floating diffusion region 220 toward the photodiode region of each photodiode 212A, 212B, 212C or 212D along one of the channel directions of each transfer gate 230A to 230D, thereby realizing a first anti-high-light overflow or overflow path between each of the photodiodes 212A, 212B, 212C and 212D and the floating diffusion region 220. Therefore, when the plurality of transfer gates 230A to 230D are turned off (e.g., negatively biased) during the integration period, excess photogenerated charge from each of photodiodes 212A, 212B, 212C or 212D can overflow to the floating diffusion region 220 through the first anti-high-gloss overflow path, rather than overflowing to the adjacent photodiode, thereby reducing high-gloss overflow associated with pixel unit 200. In an embodiment, as described below, the floating diffusion region 220 may include multiple doped regions, wherein the deepest junction depth is greater than the gate depth of one of the individual vertical gate electrodes of the transfer gate (i.e., greater than the gate depth of the first vertical gate electrode 234A or the second vertical gate electrode 234B), thereby providing a second anti-high-light overflow path between the photodiode regions of the plurality of photodiodes 212A, 212B, 212C, 212D and the floating diffusion region 220, for allowing excess photogenerated charge to overflow from the individual photodiodes 212A, 212B, 212C or 212D to the floating diffusion region 220, further improving high-light overflow. Figure 2B illustrates another plan view of an example pixel unit 200 for an image sensor according to the teachings of the present invention. Figure 2A illustrates a plan view of the example pixel unit 200 as viewed from the front surface of the semiconductor substrate 210, and Figure 2B may illustrate a plan view of the example pixel unit 200 as viewed from the back surface of the semiconductor substrate 210. A deep trench isolation structure 227 extends from the back surface of the semiconductor substrate 210 toward the front surface of the semiconductor substrate 210. The deep trench isolation structure 227 can be configured in the form of a trench grid and disposed between adjacent photodiodes 212A to 212D and between adjacent pixel units, thereby providing electrical and / or optical isolation between adjacent photodiodes 212A to 212D within the pixel unit 200 and between photodiodes of adjacent pixel units. The deep trench isolation structure 227 extends from the back surface of the semiconductor substrate 210 to a depth within the semiconductor substrate 210. The depth of the deep trench isolation structure 227 extending into the semiconductor substrate 210 can be less than or equal to a thickness of the semiconductor substrate 210. The deep trench isolation structure 227 may further extend into the first isolation well region 223A and the second isolation well region 223B, respectively. The deep trench isolation structure 227 may be at least partially surrounded by the first isolation well region 223A and the second isolation well region 223B, respectively. The deep trench isolation structure 227 may be filled with oxide (e.g., SiO2) disposed within the semiconductor substrate 210. 2) Or a metal-filled (e.g., aluminum or tungsten) isolation structure. The deep trench isolation structure 227 may also be a combination of an oxide-filled isolation structure and a metal-filled isolation structure disposed within the semiconductor substrate 210. Figure 3 depicts a circuit diagram of a quad transistor ("4T") circuit, which is a candidate pixel circuit architecture for pixel unit 200. Pixel circuit 300 includes a plurality of photodiodes 312A to 312D, a plurality of transfer transistors 330A to 330D, a floating diffusion region 320, a reset transistor 342, a source follower transistor 344, and a row of select transistors 346. In response to corresponding transfer control signals TX1_SIG to TX4_SIG received at the respective gates of the plurality of transfer transistors 330A to 330D, each of the plurality of transfer transistors 330A to 330D selectively couples its respective photodiodes 312A to 312D to the floating diffusion region 320. In an embodiment, photodiode 312A and the floating diffusion region 320 are respectively a source and a drain of transfer transistor 330A, photodiode 312B and the floating diffusion region 320 are respectively a source and a drain of transfer transistor 330B, photodiode 312C and the floating diffusion region 320 are respectively a source and a drain of transfer transistor 330C, and photodiode 312D and the floating diffusion region 320 are respectively a source and a drain of transfer transistor 330D. The floating diffusion region 320 is shared among the plurality of photodiodes 312A to 312D. Each of photodiodes 312A to 312D is at least partially buried in a semiconductor substrate (e.g., semiconductor substrate 210) and configured to generate and accumulate photogenerated image charge in response to incident light (illumination) thereon, which enters, for example, from one of the illuminated surfaces of semiconductor substrate 210 (e.g., the back surface of semiconductor substrate 210) during an integration cycle of one of the image sensors. More specifically, the electrical connection of each photodiode 312A, 312B, 312C, or 312D to the floating diffusion region 320 depends on the voltage applied to one of the transfer gates (e.g., transfer gates 230A to 230D in FIG. 2A) of the respective transfer transistors (e.g., transfer transistors 330A to 330D). The charge (e.g., photogenerated electrons or holes) accumulated in the photodiode region of the individual photodiodes 312A, 312B, 312C, or 312D can be selectively transferred to the floating diffusion region 320, for example, during a charge transfer cycle following an integration cycle, depending on the voltage applied to the corresponding transfer gate of the respective transfer transistor (e.g., transfer transistors 330A to 330D). Each of the plurality of photodiodes 312A to 312D can be in various configurations, including pinned photodiode configurations and partially pinned photodiode configurations. One of the transfer gates of each transfer transistor 330A to 330D (e.g., transfer gates 230A to 230D in FIG2A) may have a vertical gate portion formed by one or more vertical gate electrodes (e.g., a first vertical gate electrode 234A and a second vertical gate electrode 234B) formed in a respective trench defined by a substrate surface (e.g., the front side surface of semiconductor substrate 210). A reset transistor 342, a source follower transistor 344, and a column select transistor 346 are shared among a plurality of photodiodes 312A to 312D. The reset transistor 342 is coupled between a power line and a floating diffusion region 320 to reset under the control of a reset signal RST_SIG during a reset or precharge cycle (e.g., discharging residual charge in the floating diffusion region 320 and charging the floating diffusion region 320 to a preset voltage, e.g., a power supply voltage VDD). The reset transistor 342 is further coupled to individual photodiodes 312A to 312D via respective transfer transistors 330A to 330D to reset the respective photodiodes 312A to 312D to a preset voltage during a reset cycle. The floating diffusion region 320 is coupled to a gate of the source follower transistor 344. The source follower transistor 344 is coupled between a power line and a column select transistor 346. One drain of the source follower transistor 344 is coupled to a power supply line to receive the power supply voltage VDD, and one source of the source follower transistor 344 is coupled to one drain of the column select transistor 346. The source follower transistor 344 operates to modulate an image signal based on the voltage of the floating diffusion region 320, wherein the image signal corresponds to the amount of photogenerated charge accumulated in the corresponding photodiodes 312A to 312D during the integration period. The column select transistor 346 selectively couples the output of the source follower transistor 344 (e.g., the image signal) to a readout line 348 under the control of a column select signal RS_SIG. During operation, during the integration period (also referred to as an exposure or accumulation period), each photodiode 312A to 312D detects or absorbs light incident upon it and generates one or more charges in the corresponding photodiode region. Each of the transfer transistors 330A to 330D is turned off; that is, the transfer gate of each transfer transistor 330A to 330D receives a cutoff signal (e.g., transfer control signals TX1_SIG to TX4_SIG each have a negative bias voltage level). The photogenerated charge accumulated in each photodiode 312A to 312D indicates the amount of light incident upon it. Excess photogenerated charge in each photodiode 312A to 312D can overflow or leak into the floating diffusion region 320 through the aforementioned first or second anti-high-light-overflow path. After the integration period, each of the transfer transistors 330A to 330D is turned on, forming a conduction channel along one of the corresponding pairs of vertical gate electrodes and below the planar gate electrodes. Upon receiving a transfer signal (e.g., transfer control signals TX1_SIG to TX4_SIG, each with a positive bias voltage level), one or more photogenerated charges are transferred from each photodiode 312A to 312D to the floating diffusion region 320 through the conduction channel. The source follower transistor 344 generates an image signal based on the charges transferred to the floating diffusion region 320. Then, the column select transistor 346 coupled to the source follower transistor 344 selectively reads the signal onto the corresponding row bit line 348 for subsequent image signal processing, such as correlated double sampling, analog-to-digital conversion, and signal segmentation. In the embodiments, the transfer transistor system with a vertical gate structure disclosed herein is a portion of a common pixel unit, wherein the floating diffusion region 320 is shared by multiple photodiodes. The transfer transistor with a vertical gate structure and a high-light overflow prevention mechanism disclosed herein can be applied to any of various additional or alternative types of pixel units, such as a four-transistor pixel unit, a five-transistor pixel unit, or a six-transistor pixel unit. Figure 4A illustrates an exemplary cross-sectional view of Figure 2A according to the teachings of this disclosure. In various instances, similar to pixel unit 200, pixel unit 400A is one of a plurality of pixel units arranged in a pixel array of an image sensor (e.g., image sensor 100). The cross-section shown in Figure 4A is parallel to the xz plane according to a coordinate system 295. Unless otherwise specified, the height of an object herein refers to the extent of the object along the z-axis, and a width refers to the extent of the object along the x-axis or y-axis, and a vertical direction is along the z-axis. Pixel unit 400A is formed on a semiconductor substrate 410 (e.g., silicon, silicon-germanium alloy, germanium, silicon carbide alloy, gallium indium arsenide alloy, any other alloy formed of III-V compounds, other semiconductor materials or alloys, combinations thereof, a substrate thereof, a doped substrate thereof, a bulk substrate thereof, or a wafer thereof). Semiconductor substrate 410 may also be a semiconductor substrate (e.g., a silicon substrate) having an epitaxial layer grown thereon. Semiconductor substrate 410 has a front surface (or front surface) 403 and a back surface (or back surface) 405 opposite to the front surface 403. In embodiments, front surface 403 may be referred to as a non-illuminated surface of an image sensor, and back surface 405 may be referred to as an illuminated surface of an image sensor. The thickness of semiconductor substrate 410 may range from about 2.5 µm to about 7 µm, depending on the application of the implemented image sensor pixel unit 400A. For long-wavelength detection applications, such as infrared or near-infrared detection, the thickness of the semiconductor substrate 410 can be configured to be in the range of 6 µm to 7 µm. Pixel unit 400A includes a plurality of photodiodes including a first photodiode 412 and a second photodiode 414, a plurality of transfer gates including a first transfer gate 430A and a second transfer gate 430B, a floating diffusion region 420, an isolation well region 423, a deep trench isolation structure 427, a dielectric layer 436, and a plurality of contacts 450 disposed within an interlayer dielectric (not shown), which connects the elements of the pixel circuit (e.g., the floating diffusion region 420, transfer gates 430A, 430B) to one or more metallization layers (not shown). Photodiode 412 is coupled to floating diffusion region 420 through first transfer gate 430A. Photodiode 414 is coupled to floating diffusion region 420 through second transfer gate 430B. Each of the first transfer gate 430A and the second transfer gate 430B includes a planar gate electrode 432 and a pair of vertical gate electrodes including a first vertical gate electrode 434A and a second vertical gate electrode 434B. Planar gate electrode 432 is disposed on front surface 403 of semiconductor substrate 410. Planar gate electrode 432 of first transfer gate 430A may be disposed on front surface 403 of semiconductor substrate 410 above a portion of first photodiode 412. Planar gate electrode 432 of second transfer gate 430B may be disposed on front surface 403 of semiconductor substrate 410 above a portion of second photodiode 414. The first vertical gate electrode 434A and the second vertical gate electrode 434B each extend from their respective planar gate electrode 432 in a depth direction relative to the front surface 403 (e.g., the z-direction according to coordinate system 295) into the semiconductor substrate 410 to a gate depth D. G Gate depth D G The distance relative to the front surface 403 can range from approximately 250 nanometers to approximately 400 nanometers. The first vertical gate electrode 434A and the second vertical gate electrode 434B are spaced apart from each other. Each of the first vertical gate electrode 434A and the second vertical gate electrode 434B can be a pillar structure. Each of the first vertical gate electrode 434A and the second vertical gate electrode 434B can have a cross-sectional shape of one of the following: circular, square, elliptical, rectangular, or other polygonal shapes. The first vertical gate electrode 434A and the second vertical gate electrode 434B can be referred to as vertical transfer gates. Dielectric layer 436 is made of oxide-based material (e.g., SiO2). 2) Formed and disposed on the front surface 403 of the semiconductor substrate 410. The dielectric layer 436 serves as a gate insulating layer between the first transfer gate 430A and the second transfer gate 430B. The dielectric layer 436 is disposed between the planar gate electrode 432 and the front surface 403, between the first vertical gate electrode 434A and the semiconductor substrate 410, and between the second vertical gate electrode 434B and the semiconductor substrate 410. Each of the first photodiode 412 and the second photodiode 414 includes a photodiode region having a top photodiode region TPD and a bottom photodiode region BPD disposed in the semiconductor substrate 410. The top photodiode region TPD may be disposed adjacent to the first and second vertical gate electrodes of the first transfer gate 430A. The top photodiode region TPD is formed at a top photodiode depth 481 relative to the front surface 403, and the top photodiode depth 481 is less than the gate depth D of the first vertical gate electrode 434A of the corresponding transfer gate (e.g., the first transfer gate 430A or the second transfer gate 430B). G Or the gate depth D of the second vertical gate electrode 434B G The top photodiode region TPD extends toward the back surface 405. The bottom photodiode region BPD is located below the first and second vertical gate electrodes of their respective transfer gates (e.g., below the first transfer gate 430A or the second transfer gate 430B). The bottom photodiode region BPD is adjacent to the top photodiode region TPD. The bottom photodiode region BPD begins at a bottom photodiode depth 483 and extends from the top photodiode region TPD toward the back surface 405. The bottom photodiode depth 483 is greater than (or deeper than) the top photodiode depth 481 of the top photodiode region TPD. The bottom photodiode depth 483 is further greater than the gate depth D. GThe bottom photodiode region (BPD) may have a width 417 exceeding the width 415 of the top photodiode region (TPD) (e.g., along the x-direction according to coordinate system 295). Multiple ion implantations with different doses and / or implantation energies may be used to form the top photodiode region (TPD) and bottom photodiode region (BPD) of their respective photodiodes. The top photodiode region (TPD) and bottom photodiode region (BPD) have the same conductivity type, such as n-type, which is opposite to the conductivity type of the isolation well region 423 and the semiconductor substrate 410. The depth E2 of the bottom photodiode region extending from the bottom photodiode depth 483 may be greater than the depth E1 of the top photodiode region (TPD) extending from the top photodiode depth 481 along the z-direction according to coordinate system 295) (e.g., the extension depth E1 refers to the distance between the top photodiode depth 481 and the bottom photodiode depth 483). In the illustrated embodiment, photodiodes 412 and 414 are pinned photodiodes and each includes a pinning region 460 disposed between the corresponding photodiode region of the individual photodiode 412 and 414 and the front surface 403 of the semiconductor substrate 410. The pinning region 460 may be disposed between the top photodiode region TPD of the individual photodiode 412 and 414 and the front surface 403 of the semiconductor substrate 410. It should be understood that in some embodiments, the pinning region 460 has a cross-sectional area (e.g., an area in the xy plane) at least larger than one cross-sectional area of ​​the top photodiode region TPD of the associated photodiode (i.e., the pinning region 460 associated with photodiode 412 has a cross-sectional area larger than one cross-sectional area of ​​the top photodiode region TPD of photodiode 412 in the xy plane). Pinning region 460 may have the same conductivity type as isolation well region 423 but the opposite conductivity type to that of the associated photodiode regions (e.g., top photodiode region TPD and bottom photodiode region BPD). Pinning region 460 may be grounded, for example, coupled to an electrical ground. Similar to isolation well region 223, isolation well region 423 includes an inner isolation well region (or first isolation well region) 423A and an outer isolation well region (or second isolation well region) 423B disposed in semiconductor substrate 410. The inner isolation well region 423A is disposed or configured between adjacent photodiodes 412 and 414 within pixel unit 400A. For example, the inner isolation well region 423A is located between the photodiode region of photodiode 412 and the photodiode region of photodiode 414, thereby providing electrical isolation between them. The outer isolation well region 423B is disposed or configured between the photodiodes 412 and 414 of pixel unit 400A and adjacent photodiodes of pixel unit 400A. The outer isolation well region 423B may surround each of photodiodes 412 and 414, electrically isolating the photodiode region associated with each of photodiodes 412 and 414 from the photodiode region of the adjacent photodiode in the adjacent pixel unit. The outer isolation well region 423B may further electrically isolate each of photodiodes 412 and 414 from the pixel transistor associated with pixel unit 400A or the adjacent pixel unit. In an embodiment, similar to the inner isolation well region 223A and outer isolation well region 223B shown in FIG. 2A, the inner isolation well region 423A and outer isolation well region 423B may be interconnected to form an isolation grid surrounding each of photodiodes 412 and 414. Each of the inner isolation well region 423A and the outer isolation well region 423B may extend from the front surface 403 toward the back surface 405 along the z-direction according to coordinate system 295. In an embodiment, each of the inner isolation well region 423A and the outer isolation well region 423B may be formed by multiple ion implantation procedures using different implantation energies at the same or different doses. The inner isolation well region 423A and the outer isolation well region 423B may be grounded, for example, connected to a ground voltage. In an embodiment, the pinning region 460 may be electrically connected to the inner isolation well region 423A and / or the outer isolation well region 423B of the isolation well region 423. As shown in Figure 4A, a substrate region exists between the inner isolation well region 423A and the corresponding bottom photodiode regions BPD of photodiodes 412 and 414. It should be understood that in some embodiments, the inner isolation well region 423A is adjacent to the bottom photodiode region BPD of photodiode 412 and the bottom photodiode region BPD of photodiode 414. Similarly, the outer isolation well region 423B is adjacent to the corresponding top and bottom photodiode regions BPD of photodiodes 412 and 414. Pixel unit 400A may be included in semiconductor substrate 410 and disposed as a first buried channel doped region 440A and a second buried channel doped region 440B near one of the front surfaces 403. The first buried channel doped region 440A and the second buried channel doped region 440B may be part of the buried channel implantation region 240. Each of the first buried channel doped region 440A and the second buried channel doped region 440B has a buried channel interface depth 486 relative to one of the front surfaces 403, which is less than the gate depth D of the first vertical gate electrode 434A. G Or the gate depth D of the second vertical gate electrode 434B G The depth of the buried channel interface 486 is less than or the same as the depth of the corresponding top photodiode 481 of each photodiode 412 or 414. The buried channel doped region 440A is positioned close to the top photodiode region TPD of the photodiode 412. The buried channel doped region 440A is positioned between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430A to promote coupling between the photodiode 412 and the floating diffusion region 420. The buried channel doped region 440A can be implanted in such a manner that it forms a buried channel region between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430A. The formed buried channel region extends from the floating diffusion region 420 toward the corresponding top photodiode region TPD of the photodiode 412 through the gap (or substrate region) between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430A, thereby realizing a first anti-high-light overflow path 470A between the photodiode 412 and the floating diffusion region 420. The buried channel doped region 440B is positioned close to the top photodiode region TPD of the photodiode 414. A buried channel doped region 440B is disposed between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430B to promote coupling between the photodiode 414 and the floating diffusion region 420. The buried channel doped region 440B can be implanted in such a way that it forms a buried channel region between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430B, and the formed buried channel region extends from the floating diffusion region 420 toward the corresponding top photodiode region TPD of the photodiode 414 through the gap (or substrate region) between the first vertical gate electrode 434A and the second vertical gate electrode 434B of the transfer gate 430B, thereby realizing a first anti-high-light overflow path 470B between the photodiode 414 and the floating diffusion region 420 (Figure 4B). Each of the first buried channel doped region 440A and the second buried channel doped region 440B has the same conductivity type as the photodiode regions (e.g., the top photodiode region TPD and the bottom photodiode region BPD) of the corresponding photodiodes 412 and 414. By using 1E12 ions / cm 2 A dopant (e.g., arsenic or phosphorus) with the same conductivity type as the photodiode regions of photodiodes 412 and 414 is implanted at a dose of one order to form a first buried channel doped region 440A and a second buried channel doped region 440B. The first buried channel doped region 440A and the second buried channel doped region 440B may each have a conductivity of 1E18 ions / cm². 3 Up to 1E20 ions / cm 3 The concentration is within one of the ranges. It should be understood that in some embodiments, the concentration of the first buried channel doped region 440A and the concentration of the second buried channel doped region 440B may be different, for example, adjusted individually based on acceptable high light overflow level and dark current noise level. The floating diffusion region 420 may be formed by two or more doped regions, each with a different junction depth relative to the front surface 403. The doped region with the deepest junction depth is greater than the gate depth D of the first vertical gate electrode 434A associated with the transfer gate 430A (or transfer gate 430B). G Or the gate depth D of the second vertical gate electrode 434B G This makes the doped region with the deepest junction depth of the floating diffusion region 420 close to the photodiode region of the corresponding photodiode 412, 414 (e.g., the bottom photodiode region BPD). In the embodiment illustrated in FIG4A, the floating diffusion region 420 includes a first doped region 422, a second doped region 424, and a third doped region 426. The first doped region 422, the second doped region 424, and the third doped region 426 are disposed in the semiconductor substrate 410. The first doped region 422 has a first interface depth 485 relative to one of the front surfaces 403 and a first interface width J along the x-direction. W1 The first doped region 422 extends from the front surface 403 to a first junction depth 485. The first junction depth 485 is greater than the gate depth D of the first vertical gate electrode 434A relative to the front surface 403. GOr the gate depth D of the second vertical gate electrode 434B G The first junction depth 485 can be in the range of about 400 nanometers to about 500 nanometers, and can be configured based on the bottom photodiode depth 483. The first doped region 422 may extend toward the photodiode region (e.g., the bottom photodiode region BPD) of photodiodes 412 and 414. The first doped region 422 may extend and be adjacent to the bottom photodiode region BPD of photodiodes 412 and 414. The first doped region 422 may extend and be adjacent to (or directly contact) the inner isolation well region 423A. To reiterate, the first doped region 422 is located between the front surface 403 and the inner isolation well region 423A, such that the first doped region 420 does not directly contact the individual photodiodes 412 and 414, for example, it does not directly contact the bottom photodiode region BPD of each photodiode 412 and 414. In an embodiment, a portion of the first doped region 422 of the floating diffusion region 420 may be disposed in the z-direction above a portion of the bottom photodiode region (BPD) of each photodiode 412, 414, as illustrated by a box OL. To reiterate, a portion of the first doped region 422 is located between the bottom photodiode region (BPD) of each photodiode 412, 414 and the front surface 403. A portion of the first doped region 422 is formed along the z-direction above a portion of the bottom photodiode region BPD of each photodiode 412, 414, while being separated from the bottom photodiode region BPD of each photodiode 412, 414 to promote electrical coupling between the bottom photodiode region BPD of each photodiode 412, 414 and the first doped region 422 of the floating diffusion region 420. A second anti-high light overflow path is formed between each of the photodiodes 412, 414 and the floating diffusion region 420, so that during the integration period when the respective transfer gates 430A and 430B are turned off (e.g., with a negative bias voltage signal), excess photogenerated charge can overflow into the floating diffusion region 420. For example, excess photogenerated charge can overflow from the bottom photodiode region BPD of photodiode 412 through the second anti-high-light-escape path 472A to the first doped region 422 and be stored in the floating diffusion region 420 (e.g., in the depletion region associated with the first doped region 422, the second doped region 424, and the third doped region 426). Similarly, excess photogenerated charge can overflow from the bottom photodiode region BPD of photodiode 414 through the second anti-high-light-escape path 472B to the first doped region 422 and be stored in the floating diffusion region 420 (e.g., in the depletion region associated with the first doped region 422, the second doped region 424, and the third doped region 426). In this embodiment, a separation distance exists between the first doped region 422 and the bottom photodiode region (BPD) of each photodiode 412, 414, and this separation distance is smaller than the distance between the first doped region 422 and the top photodiode region (TPD) of each photodiode 412, 414. The separation distance can be in the range of approximately 100 nanometers to approximately 300 nanometers. The separation distance is configured between the first doped region 422 and the bottom photodiode region (BPD) of each photodiode 412, 414 to control the leakage level of the second anti-high-light overflow paths 472A, 472B and the total well capacity of each of the photodiodes 412, 414. It should be understood that if the separation distance is configured to be too small, for example, less than 100 nanometers, the leakage levels of the second anti-high light overflow paths 472A and 472B will become too high, and may adversely affect the low total well capacity of the photodiodes 412 and 414. The first buried channel doped region 440A and the second buried channel doped region 440B are positioned close to the front surface 403. Observation shows that the higher the concentration of each of the first buried channel doped region 440A and the second buried channel doped region 440B, the lower the high-light overflow level, but the higher the dark current induced in their respective photodiodes 412 or 414. It is necessary to tune the concentrations of the first buried channel doped region 440A and the second buried channel doped region 440B to provide a high-light overflow prevention path for the corresponding photodiodes 412 and 414 at an acceptable dark current noise level. Compared to the first anti-brightness overflow paths 470A and 470B, the second anti-brightness overflow paths 472A and 472B, induced by the first doped region 422, are located deeper away from the front surface 403 (i.e., away from the silicon oxide surface, which contains surface defects that may cause unwanted dark current noise that could affect the sensitivity of the photodiode), thus providing a charge leakage path for brightness overflow control without negatively impacting dark current noise compared to the first anti-brightness overflow paths 470A and 470B. Therefore, the existence of the second anti-brightness overflow paths 472A and 472B between the photodiodes 412 and 414 and the floating diffusion region 420 allows each of the first buried channel doped region 440A and the second buried channel doped region 440B to be configured with a lower concentration (e.g., a concentration that results in an acceptable dark current noise level) without degrading the brightness overflow performance. The second doped region 424 has a second junction depth 487 relative to one of the front surfaces 403 and a second junction width J along the x-direction. W2The second doped region 424 extends from the front surface 403 to the second junction depth 487. The second junction depth 487 relative to the front surface 403 is less than the first junction depth 485. The second junction depth 487 relative to the front surface 403 is further less than the gate depth D of the first vertical gate electrode 434A. G Or the gate depth D of the second vertical gate electrode 434B G For example, the width J of the second junction of the second doped region 424 along the x-direction. W2 The width J of the first junction is smaller than that of the first doped region 422 W1 The second doped region 424 is disposed within the first doped region 422. The second doped region 424 may be surrounded by the first doped region 422. The second doped region 424 may be embedded in the first doped region 422. The third doped region 426 has a third junction depth 489 relative to the front surface 403 and a third junction width J along the x-direction. W3 The third doped region 426 extends from the front surface 403 to a third junction depth 489. The third junction depth 489 relative to the front surface 403 is less than the first junction depth 485. The third junction depth 489 relative to the front surface 403 is also less than the second junction depth 487. The third doped region 426 is disposed within the first doped region 422. The third doped region 426 may be surrounded by the second doped region 424. The third doped region 426 is embedded in the second doped region 424. The width J of the third junction of the third doped region 426 is... W3 The width J of the second junction is smaller than that of the second doped region 424. W2 The third doped region 426 can be configured to provide an ohmic contact surface 426T for contacting the floating diffusion region 420 and to form an electrical connection between the floating diffusion region 420 and other pixel elements (such as the gate SF of the source follower transistor 492). In an embodiment, the third doped region 426 may have a higher concentration than either the first doped region 422 or the second doped region 424. The first doped region 422 may be configured with a concentration of approximately 1E12 ions / cm³. 2 One-order-of-magnitude dose implantation of a dopant (e.g., arsenic or phosphorus) having the same conductivity type as the photodiode regions of photodiodes 412 and 414 is used to form the first doped region 422. The first doped region 422 may have approximately 1E18 ions / cm². 3The concentration is on the order of one. The second doped region 424 can have a higher concentration than the first doped region 422 and is around 1E19 ions / cm². 3 One order of magnitude concentration. The second doped region 424 can be achieved at approximately 1E13 ions / cm². 2 Approximately 1E14 ions / cm 2 A third doped region 426 is formed by implanting a dopant with the same conductivity type as the photodiode regions of photodiodes 412 and 414. The third doped region 426 can be formed by using a dopant with approximately 1E15 ions / cm². 2 One of the highest doses is formed by implanting a dopant with the same conductivity type as the photodiode regions of photodiodes 412 and 414 using a single-ion or multi-ion implementation. The third doped region 426 may have a conductivity of approximately 1E20 ions / cm². 3 Up to 1E21 ions / cm 3 The concentration distribution of the first doped region 422 and the second doped region 424 is configured to allow the transfer of image signal charge during charge transfer or the overflow of excess charge during integration to be stored in a floating diffusion region 420 associated with the depletion region near the front surface 403 for subsequent readout operations. It should be understood that, similar to the third doped region 426, each of the first doped region 422 and the second doped region 424 can be formed in one or more ion implantation procedures with one or more implantation energies and one or more doses to achieve a target concentration. For example, the first doped region 422, which is one of the doped regions with the deepest junction depth in the floating diffusion region 420, can be positioned by performing one or more implantation procedures with various implantation energies (e.g., each in the range of about 15 keV to about 600 keV) to extend the first doped region 420 to the first junction depth 485. It should be understood that the number of implantation procedures and individual implantation procedure conditions (e.g., implantation energy and dose) can be optimized to form the first doped region 422 of the floating diffusion region 420 with a target deepest junction depth and a specific concentration, achieving optimized high light spillover performance of the pixel unit 400A (e.g., controlling the leakage conditions between the bottom photodiode regions BPD of each photodiode 412, 414 and the floating diffusion region 420). During operation, when the transfer gates 430A and 430B are turned off (e.g., negatively biased) during the integration period, excess photogenerated charge from each of photodiodes 412 and 414 can overflow into the floating diffusion region 420 through their respective first anti-high-light-overflow paths 470A and 470B and / or second anti-high-light-overflow paths 472A and 472B, instead of overflowing into adjacent photodiodes. For example, during the integration period, excess photogenerated charge can overflow from the top photodiode region TPD of photodiode 412 into the floating diffusion region 420 through the first anti-high-light-overflow path 470A, and / or overflow from the bottom photodiode region BPD of photodiode 412 into the floating diffusion region 420 through the second anti-high-light-overflow path 472A. Similarly, excess photogenerated charge can overflow from the top photodiode region TPD of photodiode 414 to the floating diffusion region 420 through the first anti-high-light-overflow path 470B, and / or overflow from the bottom photodiode region BPD of photodiode 414 to the floating diffusion region 420 through the second anti-high-light-overflow path 472B. Therefore, the occurrence of high-light overflow between adjacent photodiodes can be effectively reduced. The plurality of contacts 450 may include contacts configured to electrically connect the first transfer gate 430A and the second transfer gate 430B to a control circuit (e.g., control circuit 130 of FIG1) to receive transfer control signals (i.e., transfer signals or cut-off signals) through one or more metallization layers, and contacts that electrically connect the floating diffusion region 420 to one of the gates SF of the source follower transistor 492 (FIG. 4C) through one or more metal interconnects. In the embodiment, each of the inner isolation well region 423A and the outer isolation well region 423B has a conductivity type opposite to that of the photodiode region and the floating diffusion region 420 of the photodiodes 412 and 414. A deep trench isolation structure 427 is disposed within the semiconductor substrate 410 near the back surface 405. The deep trench isolation structure 427 extends from the back surface 405 toward the front surface 403 into the semiconductor substrate 410 to a depth, wherein the depth of the deep trench isolation structure 427 in the semiconductor substrate 410 may be less than or equal to a thickness of the semiconductor substrate 410. The deep trench isolation structure 427 may extend from the back surface 405 into either the inner isolation well region 423A or the outer isolation well region 423B, such that the deep trench isolation layer 427 is surrounded by either the inner isolation well region 423A or the outer isolation well region 423B. The deep trench isolation structure 427 is disposed between photodiode regions of adjacent photodiodes within the same pixel unit (e.g., between photodiode regions of adjacent photodiodes in pixel unit 400A) or between photodiode regions of adjacent photodiodes within adjacent pixel units (e.g., between photodiode regions of photodiodes 412, 414 and corresponding photodiode regions located in adjacent pixel units), thereby providing electrical and / or optical isolation between any adjacent photodiodes. Similar to deep trench isolation structure 227, deep trench isolation structure 427 can be an oxide-filled isolation structure, a metal-filled isolation structure, or a combination of both. Deep trench isolation structure 427 can be configured in a grid pattern to isolate photodiode regions adjacent to photodiodes. Deep trench isolation structure 427 surrounds each of photodiodes 412 and 414, thereby providing internal photodiode isolation within pixel unit 400A and inter-photodiode isolation between adjacent pixel units. Figure 4B is a cross-sectional view of another example of a pixel unit 400B with a floating diffusion section having multiple doped regions for highlight overflow control, according to the teachings of the present invention. Note that the pixel unit 400B of Figure 4B may be another cross-sectional view of Figure 2A, and the elements with similar names and numbers referred to below are coupled and function as described above. In fact, it should be understood that the pixel unit 400B of Figure 4B shares many similarities with the cross-sectional view of the pixel unit 400 depicted in Figure 4A. Therefore, it should be understood that, for the sake of brevity and to avoid obscuring the teachings of the present invention, the differences between pixel units 400A and 400B will be described in detail herein. One difference between pixel unit 400B in Figure 4B and pixel unit 400 in Figure 4A is that the floating diffusion region of pixel unit 400B in Figure 4B may contain only two doped regions with different junction depths. As illustrated, a floating diffusion region 420' includes a first doped region 422 and a second doped region 424. The first doped region 422 has a first junction depth 485 relative to the front surface 403, which is greater than a buried channel junction depth 486 associated with the first buried channel doped region 440A or the second buried channel doped region 440B. The first junction depth 485 is also greater than the gate depth D of the first vertical gate electrode 434A or the second vertical gate electrode 434B associated with the transfer gate 430A or the transfer gate 430B. G The second doped region 424 has a second junction depth 487 relative to one of the front surfaces 403, which is less than the gate depth D of the first vertical gate electrode 434A or the second vertical gate electrode 434B associated with the transfer gate 430A or the transfer gate 430B. GThe second junction depth 487 is less than the first junction depth 485. The second junction depth 487 may be further less than the buried channel junction depth 486 associated with the first buried channel doped region 440A or the second buried channel doped region 440B. Each of the first buried channel doped region 440A and the second buried channel doped region 440B is positioned close to the top photodiode region TPD of the corresponding photodiodes 412 and 414, so that first high-light overflow prevention paths 470A and 470B can be formed to allow excess photogenerated charge to overflow from the top photodiode region TPD of each photodiode 412 and 414 to the floating diffusion region 420'. The second doped region 424 is positioned close to the bottom photodiode region BPD of each of the photodiodes 412 and 414, thereby forming second anti-high-light overflow paths 472A and 472B to allow excess photogenerated charge to overflow from the bottom photodiode region BPB of each of the individual photodiodes 412 and 414 to the floating diffusion region 420'. The corresponding contact 450 contacts the first doped region 422. In the illustrated embodiment, the second doped region 424 may have a concentration greater than that of the first doped region 422. Pixel unit 400B may further include a plurality of shallow trench isolation structures 425. Each of the shallow trench isolation structures 425 may be positioned close to the front side surface 403 surrounding pixel unit 400B. Each of the shallow trench isolation structures 425 may be an oxide-filled (e.g., silicon oxide-filled) trench isolation structure. Each of the shallow trench isolation structures 425 may extend into an isolation well region 423. For example, each extends from the front side surface 403 into the semiconductor substrate 410, entering an outer isolation well region 423B of the isolation well region 423. In some embodiments, a pair of vertically aligned shallow trench isolation structures 425 and deep trench isolation structures 427 are disposed within the isolation well region 423 to form an isolation structure for pixel unit 400B. It should be understood that in some embodiments, the first buried channel doped region 440A and the second buried channel doped region 440B may be omitted to reduce manufacturing complexity and to tune the concentration of the first buried channel doped region 440A and the second buried channel doped region 440B to balance dark current issues and specular overflow. Using the illustrated floating diffusion region structure, second specular overflow paths 472A and 472B are provided between the floating diffusion region 420' and photodiodes 412 and 414, respectively. Even without the first buried channel doped region 440A and the second buried channel doped region 440B, the desired or target specular overflow performance of an image sensor can be achieved, while minimizing or preventing white pixel issues caused by dark current associated with the buried channel doped regions 440A and 440B. Figure 4C is a cross-sectional view of another example of a pixel unit 400C with a floating diffusion section having multiple doped regions for highlight overflow control, according to the teachings of the present invention. Note that the pixel unit 400C of Figure 4C may be another cross-sectional view of Figure 2A, and the similarly named and numbered elements referred to below are coupled and function as described above. In fact, it should be understood that the pixel unit 400C of Figure 4C and the cross-sectional view of the pixel unit 400A depicted in Figure 4A share many similarities. One difference between pixel unit 400C in Figure 4C and pixel unit 400A in Figure 4A is that pixel unit 400C omits the first buried channel doped region 440A and the second buried channel doped region 440B, and only includes the second anti-high light overflow paths 472A and 472B formed by the electrical coupling between the first doped region 422 of a floating diffusion region 420 and each of the photodiodes 412 and 414, thereby allowing excess photogenerated charge to overflow from the respective photodiodes 412 and 414 into the floating diffusion region 420. Figure 4D is a cross-sectional view of another example of a pixel unit 400D with a floating diffusion section having multiple doped regions for highlight overflow control, according to the teachings of the present invention. Note that the pixel unit 400D of Figure 4D may be another cross-sectional view of Figure 2A, such as along a section line W-W', and the elements with similar names and numbers referred to below are coupled and function as described above. Pixel unit 400D includes a plurality of shallow trench isolation structures 425 disposed in semiconductor substrate 410 between a photodiode and a pixel transistor associated with a corresponding pixel unit 400D or a neighboring pixel unit, and between a floating diffusion region 420 and the pixel transistor. Each of the plurality of shallow trench isolation structures 425 may have an isolation depth D relative to a front surface 403 of semiconductor substrate 410. STI Isolation depth D STI It can be in the range of about 200 nanometers to about 300 nanometers. In the illustrated embodiment, the pixel transistor includes a source follower transistor 492 and a row of select transistors 494 associated with the pixel unit 400D. A floating diffusion region 420 can be coupled to a gate SF of a source follower transistor 492 via a corresponding contact 450 and one or more metallization layers (e.g., one of the metal interconnects 452 in a first metallization layer). A source / drain 493SD is shared between the source follower transistor 492 and the column select transistor 494, wherein the source / drain 493SD can be used as a source of the source follower transistor 492 and a drain of the column select transistor 494. A source / drain 495SD can be used as a source of the column select transistor 494 and coupled to a row bit line (e.g., read row bit line 120) via a corresponding contact 450 and one or more metallization layers. The first doped region 422 may have a first junction depth 485 greater than one of the source-drain junction depths 490 of the source / drain 493SD or 495SD. Although not shown, the source follower transistor 492 may include a drain having a junction depth (e.g., the respective source-drain junction depth) less than the first junction depth 485. The first junction depth 485 is further greater than the isolation depth D of the respective shallow trench isolation structure 425. STI The second doped region 424 may have the same source-drain junction depth 490 as the source / drain 493SD or 495SD, but less than the isolation depth D of the respective shallow trench isolation structure 425. STI The second junction depth is 487. The source / drain concentrations of 493SD and 495SD can reach approximately 1E20 ions / cm³. 3 On the order of magnitude, the concentration of either the source / drain 493SD or 495SD can be greater than the concentration of the first doped region 422. Figure 5 is a cross-sectional view of another example of a pixel unit 500 having a floating diffusion region structure according to the teachings of the present invention. Pixel units 500, similar to pixel units 200, 400A to 400C, may be one of a plurality of pixel units disposed in a pixel array of an image sensor (e.g., image sensor 100). It should be understood that the example pixel unit 500 of Figure 5 may be an example of pixel unit 400A with an added metallization layer, color filter array, and microlens array, and the elements with similar names and numbers referred to below are coupled and function as described above. Photodiodes 412 and 414 are positioned close to one of the front surfaces (or front surfaces) 403 of a semiconductor substrate 410 to generate image charges in response to incident light 515 directed to the individual photodiodes 412 and 414 through one of the back surfaces (or back surfaces) 405 of the semiconductor layer 410. The pixel unit 500 shown in Figure 5 includes an interlayer dielectric layer 550 and one or more metallization layers 560. The interlayer dielectric layer 550 is disposed close to the front surface 403 of the semiconductor substrate 410 (e.g., such that a dielectric layer 436 is disposed between the interlayer dielectric layer 550 and the semiconductor substrate 410). The interlayer dielectric layer 550 at least partially encapsulates the contact 450 and the gate electrode (e.g., the transfer gates 430A and 430B shown in Figure 4A). Although not shown, it should be understood that the interlayer dielectric layer 550 may also at least partially encapsulate a gate SF of a source follower transistor 492, a gate RS of a select transistor 494, or a gate RST of a reset transistor. One or more metallization layers 560 may be embedded in a multilayer intermetallic dielectric layer 562 and disposed on the interlayer dielectric layer 550. The plurality of contacts 450 can electrically connect corresponding pixel elements (e.g., floating diffusion region 420, transfer gates 430A, 430B, gates or source / drains associated with pixel transistors, etc.) to one or more metallization layers 560 (e.g., a first metallization layer among one or more metallization layers 560) for signal routing and necessary connections to support pixel operation. Pixel unit 500 further includes a multilayer dielectric stack 510 formed over the back surface 405 of semiconductor substrate 410. The multilayer dielectric stack 510 may include a buffer layer (e.g., an oxide layer) and an anti-reflective layer formed over the buffer layer. The anti-reflective layer may include one or more dielectric materials, such as silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, or other suitable materials or combinations thereof. Optionally, a passivation layer (not shown) may be disposed between the multilayer dielectric stack 510 and the back surface 403 of semiconductor substrate 410 for surface passivation to reduce dark current and white pixels. The passivation layer may be formed of a high-k material, such as aluminum oxide, hafnium oxide, or tantalum oxide. A color filter array layer 520 comprising a plurality of color filters is formed above a multilayer dielectric stack 510. In one example, the plurality of color filters may have a configuration based on a Bayer pattern. In one example, the plurality of color filters may include a combination of red, blue, and green color filters. In another example, the plurality of color filters may include a combination of red, blue, and transparent color filters. In yet another example, the plurality of color filters may include a combination of red, blue, green, and infrared color filters. In the depicted example, a metal grid 525 is formed between the individual color filters of the color filter array layer 520. The metal grid 525 may be perpendicularly aligned with a deep trench isolation structure 427 and defines a plurality of apertures aligned with the photosensitive areas of photodiodes 412, 414. A microlens array comprising a plurality of microlenses 530 is formed above the color filter layer 520. In the illustrated embodiment, each of the plurality of microlenses 530 is aligned with its respective photodiode 412, 414. It should be understood that in some embodiments, a microlens 530 may be configured to be formed above a plurality of photodiodes in a pixel unit for specific imaging applications, such as phase detection. For example, a single microlens 530 may be positioned to cover the entire photosensing area of ​​the pixel unit 500 to guide incident light to the photodiodes 412, 414. In operation, incident light 515 is guided through a microlens 530, a color filter, a multilayer dielectric stack 510, a back surface 405, and a semiconductor layer 410 to individual photodiodes 412 and 414. Excess photogenerated charge in each of the photodiodes 412 and 414 can overflow through their respective anti-high-light-overflow paths 472A and 472B to the floating diffusion region 420, enter a first doped region 422 of the floating diffusion region 420, and be stored in the floating diffusion region 420 (e.g., in a depletion region associated with the first doped region 422, the second doped region 424, and the third doped region 426), reducing or even preventing high-light-overflow, thereby improving the overall imaging quality of the image sensor. The above description of the illustrated examples of the present invention (including the content described in the abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. As those skilled in the art will recognize, although specific examples of the invention have been described herein for illustrative purposes, various modifications are possible within the scope of the invention. Based on the detailed description above, such modifications can be made to the present invention. The terminology used in the following claims should not be construed as limiting the invention to the specific instances disclosed in the specification. In fact, the scope of the invention will be determined entirely by the following claims, which will be interpreted according to established theories of patent application interpretation. 100: Image sensor; 110: Pixel array; 120: Readout lines; 130: Control circuit; 140: Readout circuit; 150: Functional logic; 200: Pixel unit; 202: Active region; 204: Transistor region; 210: Semiconductor substrate; 212A to 212D: Photodiode; 220: Floating diffusion region; 223: Isolation well region; 223A: Inner isolation well region; 223B: Outer isolation well region; 227: Deep trench isolation structure; 230A to 230D: Transfer gate; 232: Planar gate electrode; 234A: First vertical gate electrode; 234B: Second vertical gate electrode; 240: Buried channel implantation region; 242: Reset transistor; 244: Source follower electrode. 246: Column select transistor; 250: Metal contact; 295: Coordinate system; 300: Pixel circuit; 312A to 312D: Photodiode; 320: Floating diffusion region; 330A to 330D: Transfer transistor; 342: Reset transistor; 344: Source follower transistor; 346: Column select transistor; 348: Read row line / row bit line; 400A: Pixel unit; 400B: Pixel unit; 400C: Pixel unit; 400D: Pixel unit; 403: Front surface; 405: Back surface; 410: Semiconductor substrate / semiconductor layer; 412: First photodiode; 414: Second photodiode; 415: Width; 417: Width; 420: Floating diffusion region; 42 0': Floating diffusion region 422: First doped region 423: Isolation well region 423A: Inner isolation well region 423B: Outer isolation well region 424: Second doped region 425: Shallow trench isolation structure 426: Third doped region 426T: Ohmic contact surface 427: Deep trench isolation structure 430A: First transfer gate 430B: Second transfer gate 432: Planar gate electrode 434A: First vertical gate electrode 434B: Second vertical gate electrode 436: Dielectric layer 440A: First buried channel doped region 440B: Second buried channel doped region 450: Contact 452: Metal interconnect 460: Pinned region 470A: First anti-highlight overflow Path 470B: First Anti-Highlight Overflow Path 472A: Second Anti-Highlight Overflow Path 472B: Second Anti-Highlight Overflow Path 481: Top Photodiode Depth 483: Bottom Photodiode Depth 485: First Junction Depth 486: Buried Channel Junction Depth 487: Second Junction Depth 489: Third Junction Depth 490: Source-Drain Junction Depth 492: Source Follower Transistor 494: Column Select Transistor 493SD: Source / Drain 495SD: Source / Drain 500: Pixel Unit 510: Multilayer Dielectric Stack 515: Incident Light 520: Color Filter Array Layer 525: Metal Grid 530: Microlens 550: Interlayer Dielectric Layer560: Metallization layer; 562: Multilayer intermetallic dielectric layer D G Gate depth E1: Extension depth E2: Extension depth J W1 :First interface width J W2 :Second joint width J W3 :Third joint width The invention is described with reference to the following figures, which are non-limiting and non-exhaustive examples, wherein the same element symbols refer to the same parts throughout the various views unless otherwise specified. Figure 1 illustrates an example of an imaging system according to one embodiment of the present disclosure. Figures 2A and 2B respectively illustrate a front and a back side view of an example of a common pixel layout of one of four photodiodes sharing a common floating diffusion region, according to the teachings of this disclosure. Figure 3 depicts an example pixel circuit associated with a pixel unit of Figure 2A according to the teachings of this disclosure. Figures 4A to 4D are example cross-sectional views of the pixel unit of Figure 2A according to the teachings of this disclosure. Figure 5 shows a cross-sectional view of an example of a color filter array and a microlens array according to the teachings of this disclosure. Throughout the various views of the drawings, corresponding reference characters indicate the corresponding components. Those skilled in the art will understand that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-understood elements that are useful or necessary in a commercially viable embodiment are generally not depicted in order to facilitate a less obstructed observation of one of these various embodiments of the invention. 400A: Pixel unit 403: Front surface 405: Backside surface 410: Semiconductor substrate / semiconductor layer 412: First photodiode 414: Second photodiode 415: Width 417: Width 420: Floating diffusion zone 422: First doped region 423: Isolation Well Area 423A: Internal Isolation Well Area 423B: External Isolation Well Area 424: Second doped region 426: Third doped region 426T: Ohmic contact surface 427: Deep trench isolation structure 430A: First Transfer Gate 430B: Second Transfer Gate 432: Planar gate electrode 434A: First vertical gate electrode 434B: Second vertical gate electrode 436: Dielectric layer 440A: First buried channel doped region 440B: Second buried channel doped region 450: Contact element 460: Pinning Zone 470A: First Anti-Highlight Overflow Path 472A: Second Anti-Highlight Overflow Path 472B: Second Anti-Highlight Overflow Path 481: Depth of top photodiode 483: Bottom photodiode depth 485: First interface depth 486: Buried Channel Interface Depth 487: Second joint depth 489: Depth of the third interface D G Gate depth E1: Extension Depth E2: Extension Depth J W1 : First interface width J W2 :Second joint width J W3 :Third joint width

Claims

1. A pixel unit disposed on a semiconductor substrate having a front surface and a back surface, the pixel unit comprising: A photodiode disposed in the semiconductor substrate, the photodiode including a photodiode region having a second conductivity type opposite to a first conductivity type of the semiconductor substrate; a first doped region disposed in the semiconductor substrate, the first doped region extending from the front surface to have a first junction depth in the semiconductor substrate along a depth direction perpendicular to the front surface, wherein the first doped region has the second conductivity type; The device comprises: a second doped region having one of the second conductivity types, extending from the front surface to have a second junction depth in the semiconductor substrate, the second junction depth being less than the first junction depth relative to the front surface; wherein the second doped region is coupled to the first doped region and is surrounded by the first doped region; and a transfer gate selectively coupling the photodiode to the first doped region, the transfer gate being configured to transfer image charge from the photodiode to the first doped region, the transfer gate having a planar gate electrode and at least one vertical gate electrode on the front surface of the semiconductor substrate, the at least one vertical gate electrode extending from the planar gate electrode along the depth direction into the semiconductor substrate to a gate depth; wherein the first junction depth is greater than the gate depth; wherein both the first doped region and the second doped region are separated from the photodiode region of the photodiode; and wherein a first concentration of the first doped region is less than a second concentration of the second doped region.

2. The pixel unit as described in claim 1 further includes: The second doped region is disposed within the first doped region; the second junction depth of the second doped region is less than the gate depth relative to the at least one vertical gate electrode of the front surface; and the first doped region and the second doped region form a floating diffusion region for storing image charge and overflow charge received from the photodiode.

3. The pixel unit of claim 2, wherein the floating diffusion region further includes a third doped region disposed in the second doped region, the third doped region extending from the front surface to have a third junction depth in the semiconductor substrate along the depth direction, wherein the third junction depth is less than the second junction depth, and the third doped region has a third concentration greater than at least one of a first concentration of the first doped region and a second concentration of the second doped region; wherein the third doped region is surrounded by the first doped region.

4. The pixel unit of claim 1, wherein the photodiode region comprises: (i) a bottom photodiode region extending along the depth direction from the bottom photodiode depth to an extension depth greater than the first junction depth at a bottom photodiode depth greater than the gate depth of the at least one vertical gate electrode relative to the front surface; and (ii) a top photodiode region adjacent to the at least one vertical gate electrode, starting at a top photodiode depth less than the gate depth, extending along the depth direction toward and adjacent to the bottom photodiode region, wherein the top photodiode region and the bottom photodiode region have the same conductivity type as the first doped region, wherein the first junction depth of the first doped region and the second junction depth of the second doped region are each greater than the top photodiode depth and less than the bottom photodiode depth relative to the front surface.

5. The pixel unit of claim 4, wherein the bottom photodiode region has a cross-sectional width in a direction parallel to the front surface that is greater than the cross-sectional width of the top photodiode region and the width of the first junction of the first doped region.

6. The pixel unit of claim 5, wherein only a portion of the bottom photodiode region of the photodiode is located between the first doped region and the back surface, and the first doped region is separated from the top photodiode region by a first distance, the first distance being greater than a second distance between the first doped region and the bottom photodiode region of the photodiode, thereby enabling excess photoelectrons to leave from the bottom photodiode region of the photodiode and go to the first doped region.

7. For the pixel unit of claim 1, the separation distance between the first doped region and the photodiode region of the photodiode is between 100 nanometers and 300 nanometers.

8. A pixel unit on a semiconductor substrate having a first conductivity type, the semiconductor substrate having a front surface and a back surface, the pixel unit comprising: A first photodiode having a second conductivity type opposite to the first conductivity type is disposed in the semiconductor substrate; A second photodiode having the second conductivity type is adjacent to the first photodiode; a floating diffusion region is disposed between the first photodiode and the second photodiode, the floating diffusion region including a first doped region having one of the second conductivity types and a second doped region having one of the second conductivity types disposed within the first doped region, wherein the first doped region extends from the front surface to have a first junction depth in a first direction perpendicular to the front surface of the semiconductor substrate, and the second doped region extends from the front surface to have a second junction depth in the first direction perpendicular to the front surface, the second doped region being surrounded by the first doped region; a first transfer gate having a first pair of vertical gate electrodes disposed between the first photodiode and the floating diffusion region along a second direction perpendicular to the first direction, each of the first pair of vertical gate electrodes extending along the first direction into the semiconductor substrate to a first gate depth, the first transfer gate selectively coupling the first photodiode to the floating diffusion region; A second transfer gate having a second pair of vertical gate electrodes disposed along the second direction between the second photodiode and the floating diffusion region, each of the second pair of vertical gate electrodes extending along the first direction into the semiconductor substrate to a second gate depth, the second transfer gate selectively coupling the second photodiode to the floating diffusion region; and a first buried channel doped region configured to extend along the second direction from the first doped region of the floating diffusion region through a substrate region contained between one of the first vertical transfer gate electrodes and the second vertical transfer gate electrode toward the photodiode region of the first photodiode, the first buried channel doped region having a first buried channel junction depth relative to the front surface that is smaller than the first junction depth; wherein each of the first gate depth and the second gate depth is smaller than the first junction depth relative to the front surface; wherein the first buried channel doped region has the same second conductivity type as the first doped region of the floating diffusion region. The first doped region and the second doped region are separated from the photodiode region of the photodiode; wherein the first concentration of one of the first doped regions is less than the second concentration of one of the second doped regions.

9. The pixel unit of claim 8, wherein the second doped region is disposed in and surrounded by the first doped region.

10. The pixel unit of claim 8 further includes: A source follower transistor has a gate, a source, and a drain coupled to the floating diffusion region, each of the source and the drain having a source-drain junction depth less than the first junction depth of the first doped region.

11. The pixel unit of claim 10 further includes a shallow trench isolation structure disposed between the source follower transistor and the floating diffusion region, the shallow trench isolation structure having an isolation trench depth less than the first junction depth of the first doped region.

12. The pixel unit of claim 8, wherein each of the first photodiode and the second photodiode further comprises: The device includes a top photodiode region and a bottom photodiode region. The top photodiode region extends towards the bottom photodiode region at a depth less than the gate depth and is adjacent to the bottom photodiode region at a depth greater than the gate depth. A first doped region has a portion that vertically overlaps with the bottom photodiode region of the device. The first doped region is laterally separated from the top photodiode region and vertically separated from the bottom photodiode region. A vertical distance between the first doped region and the bottom photodiode region is less than a vertical distance between the second doped region and the bottom photodiode region.

13. The pixel unit of claim 8 further includes: A second buried channel doped region is configured to extend along the second direction from the first doped region of the floating diffusion region toward the second photodiode, the second buried channel doped region having a second buried channel junction depth less than the first junction depth; a pinning region of the first conductivity type is disposed between the front surface of the semiconductor substrate and the first buried channel doped region; wherein the first doped region is electrically coupled to the first photodiode to form a first anti-blooming path between the first photodiode and the first doped region of the floating diffusion region when the first transfer gate is turned off; wherein the first buried channel doped region forms a first buried channel between a first vertical gate electrode and a second vertical gate electrode of a first pair of vertical gate electrodes to provide a second anti-blooming path between the first photodiode and the floating diffusion region; The first doped region is electrically coupled to the second photodiode to form a third anti-high-light overflow path between the second photodiode and the first doped region of the floating diffusion region when the second transfer gate is turned off; the second buried channel doped region forms a second buried channel between the first vertical gate electrode and the second vertical gate electrode of the second pair of vertical gate electrodes to provide a fourth anti-high-light overflow path between the second photodiode and the first doped region.

14. The pixel unit of claim 8, wherein the first doped region of the floating diffusion region is located between the first transfer gate and the second transfer gate, and the first doped region is separated from each of the first photodiode and the second photodiode.

15. An image sensor comprising a plurality of pixel units formed on a semiconductor substrate having a first conductivity type, the semiconductor substrate having a front surface and a back surface, each pixel unit comprising: A plurality of photodiodes, each having a second conductivity type opposite to the first conductivity type, are disposed in the semiconductor substrate; A floating diffusion region disposed in the semiconductor substrate; a plurality of transfer gates, disposed on the front surface of the semiconductor substrate, the plurality of transfer gates selectively coupling a plurality of photodiodes to the floating diffusion region, each of the transfer gates having a planar gate electrode and a pair of vertical gate electrodes, each of the pair of vertical gate electrodes extending from the planar gate electrode along a first direction perpendicular to the front surface into the semiconductor substrate to a gate depth; and a floating diffusion region having the second conductivity type disposed in the semiconductor substrate, comprising: a first doped region having a first junction depth relative to the front surface greater than the gate depth, wherein the first doped region is spaced apart from each photodiode included in the plurality of photodiodes along a second direction perpendicular to the first direction; and a second doped region having a second junction depth disposed in and surrounded by the first doped region, the second junction depth being less than the gate depth; The first concentration of one of the first doped regions is less than the second concentration of one of the second doped regions.

16. The image sensor of claim 15, wherein each of the plurality of photodiodes includes: A photodiode region having the second conductivity type is disposed in the semiconductor substrate, the photodiode region comprising: (i) a bottom photodiode region at a bottom photodiode depth greater than the gate depth; and (ii) a top photodiode region starting at a top photodiode depth less than the gate depth, extending toward and adjacent to the bottom photodiode region, wherein the top photodiode depth is less than the first junction depth of the floating diffusion region, and the bottom photodiode depth is greater than the first junction depth of the floating diffusion region; wherein a first doped region and a second doped region are separated from the top photodiode region in the second direction, and the first doped region is further separated from the bottom photodiode region in the first direction by a separation distance between 100 nanometers and 300 nanometers, such that the first doped region is separated from both the top photodiode region and the bottom photodiode region.

17. The image sensor of claim 15, wherein each pixel unit further includes a well region having one of the first conductivity types, the well region being disposed (i) between adjacent photodiodes and (ii) between the first doped region and the back surface.

18. The image sensor of claim 15, wherein each of the plurality of photodiodes further comprises: A pinned region of the first conductivity type is disposed between the front surface and one of the buried channel doped regions contained in a plurality of buried channel doped regions.

19. The image sensor of claim 15, wherein the first doped region and the second doped region are separated from each of the plurality of photodiodes by a corresponding photodiode region, wherein the first doped region is between the front surface and a portion of the corresponding photodiode region of each of the plurality of photodiodes.

Images