Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its fabrication process are provided. The semiconductor structure disclosed herein includes a first die and a second die, the first die having a front surface and a rear surface, and the second die being bonded to the rear surface of the first die. The first die includes a plurality of trenches adjacent to the rear surface, and the plurality of trenches are filled with liquid.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a method for forming the same, and in particular to a semiconductor structure with a trench and a method for forming the same. Prior Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each featuring smaller and more complex circuits than the previous one. Throughout the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Three-dimensional (3D) packaging or chip stacking generally refers to stacking and attaching chips vertically to improve efficiency and better utilize available space. This enables heterogeneous integration of multiple dies with different chip sizes and / or functions. An example of a 3D packaging implementation is a system on integrated chip (SoIC) device or a high-performance computing (HPC) device. Dense packaging and vertical integration pose challenges to heat dissipation, as heat accumulation can degrade performance. While existing 3D packaging structures are generally adequate for their intended purpose, they are not always satisfactory. Summary of the Invention

[0004] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first interconnect structure, a first substrate, a second interconnect structure, and a second substrate. The first substrate is disposed on the first interconnect structure, the second interconnect structure is disposed on the first substrate, and the second substrate is disposed on the second interconnect structure. The first substrate includes a first plurality of trenches extending from a surface adjacent to the second interconnect structure into the first substrate. The first plurality of trenches are filled with a liquid.

[0005] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first die, a bonding layer, and a second die. The first die includes a first interconnect structure, a first substrate, and a first plurality of heat distribution lines, wherein the first substrate is disposed on the first interconnect structure, and the first plurality of heat distribution lines are disposed in the first substrate. The bonding layer is disposed on the first substrate. The second die is disposed on the bonding layer and includes a second interconnect structure, a second substrate, and a second plurality of heat distribution lines, wherein the second substrate is disposed on the second interconnect structure, and the second plurality of heat distribution lines are disposed in the second substrate.

[0006] In another exemplary aspect, the present disclosure relates to a method comprising receiving a first workpiece, the first workpiece comprising a first die mounted on a first carrier substrate, the first die comprising a first substrate and a through-substrate via; selectively etching the first substrate until a portion of the through-substrate via is higher than the first substrate; forming a first plurality of trenches in the first substrate; injecting a liquid into the first plurality of trenches; depositing a first sealing layer over the first workpiece to seal the liquid in the first plurality of trenches; and, after depositing the first sealing layer, planarizing the first workpiece to expose the through-substrate via. Simple diagram description

[0007] The following detailed description, taken in conjunction with the accompanying drawings, provides a complete disclosure. It should be noted that, in accordance with common industry practice, the illustrations are not necessarily drawn to scale. In fact, the dimensions of elements may be arbitrarily enlarged or reduced for clarity of illustration. FIG. 1 is a flow chart illustrating an embodiment of a method for forming a package structure according to various aspects of the present disclosure. 2 through 17 are partial cross-sectional views of a workpiece undergoing operations of the method of FIG. 1 according to various aspects of the present disclosure. Implementation Method

[0008] The following disclosure provides many different embodiments or examples for implementing the various features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, this may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, the following disclosure may reuse the same reference symbols and / or designations in different examples. This repetition is for simplicity and clarity and is not intended to define a specific relationship between the different embodiments and / or structures discussed.

[0009] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms are used to facilitate describing the relationship of one element or feature to another element or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0010] Furthermore, when using the terms "about," "approximate," or the like to describe a number or a range of numbers, such terms are intended to encompass numbers within a reasonable range that takes into account variations inherently occurring during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having the characteristic associated with such number, a numerical quantity or range encompasses a reasonable range encompassing the described quantity, such as within + / - 10% of the described quantity. For example, a material layer having a thickness of "approximately 5 nanometers" may encompass a range of dimensions from 4.25 nanometers to 5.75 nanometers, where manufacturing tolerances associated with depositing material layers are known by those skilled in the art to be + / - 15%. Furthermore, this disclosure may repeat reference symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0011] Three-dimensional (3D) packaging, or die stacking, generally refers to stacking and attaching dies vertically to improve efficiency and better utilize available space. This allows for heterogeneous integration of multiple dies with varying die sizes and / or functionalities. An example of a 3D package is a system-on-chip (SoIC) device or a high-performance computing (HPC) device. Due to vertical integration, heat generated in a 3D package is primarily dissipated through conduction through the semiconductor substrate. The fabrication of 3D package structures includes thinning the die substrate to reduce the resistance of through-substrate vias (TSVs). Without substrate thinning, it can be difficult to satisfactorily fill high-aspect-ratio TSV openings, resulting in voids that increase resistance. However, substrate thinning also reduces heat dissipation capabilities. Without adequate heat dissipation, the performance of the 3D package may be compromised. Furthermore, high-power-density areas within the 3D package may form hot spots, which can locally reduce carrier mobility.

[0012] The present disclosure provides a packaging structure that improves heat dissipation through the semiconductor substrate of a bare die within the package structure. According to the present disclosure, a plurality of trenches are formed in the substrate of the bare die integrated within the package structure. The trenches are filled with a liquid or a highly thermally conductive metal. Once the trenches are filled with the liquid, a sealing layer is deposited over the trenches to seal the liquid within the trenches. Including the liquid or highly thermally conductive metal within the substrate increases heat dissipation and improves heat distribution within the package structure.

[0013] Various aspects of the present disclosure will now be described in greater detail with reference to the accompanying drawings. In this regard, FIG. 1 is a flow chart illustrating a method 100 for forming a package structure including at least a first die and a second die according to various aspects of the present disclosure. Method 100 is merely an example and is not intended to limit the present disclosure to the content explicitly described in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail herein. Method 100 is described below in conjunction with FIG. 2 through FIG. 17 , which are partial cross-sectional views of a first workpiece 200 at various stages of fabrication according to various embodiments of method 100. For the avoidance of doubt, the X, Y, and Z directions in FIG. 2 through FIG. 16 are perpendicular to each other. Throughout this disclosure, like reference numerals denote like features unless otherwise expressly stated.

[0014] 1 and 2 , method 100 includes block 102, wherein a first workpiece 200 is received, the first workpiece 200 including a first die 250, a second die 260, and a gapfill layer 204. In the embodiment shown in FIG. 2 , the first workpiece 200 includes the first die 250 and the second die 260 mounted on a first carrier substrate 202. It should be understood that the first workpiece 200 shown in FIG. 2 is merely an example, and depending on design requirements, the first workpiece 200 may include only one die or more than two dies. Each of the first die 250 and the second die 260 may be a logic die, a system-on-chip (SOC) die, or a memory die (e.g., a dynamic random access memory (DRAM) die). First die 250 includes a first substrate 252, a first transistor 254 formed on first substrate 252, a first through-substrate via (TSV) 256 extending through first substrate 252, and a first interconnect structure 258. First interconnect structure 258 is disposed on the front surface of first substrate 252, and first die 250 is flipped upside down to be mounted on first carrier substrate 202. It should be noted that first die 250 includes more transistors than first transistor 254 and more TSVs than first TSVs 256. For ease of illustration and explanation, the figures of this disclosure only show first transistor 254 and first TSVs 256. Similarly, second die 260 includes a second substrate 262, a second transistor 264, a second through-substrate via (TSV) 266, and a second interconnect structure 268. Second transistor 264 is formed on second substrate 262, and second through-substrate via (TSV) 266 extends through second substrate 262. Second interconnect structure 268 is disposed on the front surface of second substrate 262, and second die 260 is inverted for mounting on first carrier substrate 202. It should be noted that second die 260 includes more transistors than second transistor 264 and more TSVs than second TSVs 266. For ease of illustration and explanation, the figures of this disclosure only show second transistor 264 and second TSVs 266.

[0015] In some embodiments, both the first substrate 252 and the second substrate 262 include silicon (Si). Alternatively, the first substrate 252 and the second substrate 262 may include a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb)), an alloy semiconductor (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof. Alternatively, the first substrate 252 and the second substrate 262 may be a semiconductor-on-insulator (SOS) substrate (e.g., a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate). The semiconductor-on-insulator substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. The first substrate 252 and the second substrate 262 may include various doped regions (not shown) depending on design requirements. In some embodiments, the first substrate 252 and the second substrate 262 include p-type doped regions (e.g., p-type wells) doped with a p-type dopant (e.g., boron (e.g., BF2), indium, other p-type dopants, or combinations thereof) and n-type doped regions (e.g., n-type wells) doped with an n-type dopant (e.g., phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof). The various doped regions can be formed directly on and / or within the first substrate 252 and the second substrate 262, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form various doped regions.

[0016] The first transistor 254 and the second transistor 264 can be planar transistors or multi-gate transistors, such as fin-like field effect transistors (FinFETs) or gate-all-around (GAA) transistors. Planar transistors include a gate structure that induces a planar channel region along one surface of their active region, hence the name. FinFETs include a fin-shaped active region extending from a substrate and a gate structure disposed on the top surface and sidewalls of the fin active region. GAA transistors include at least one channel member extending between two source / drain features and a gate structure completely surrounding the at least one channel member. Because the gate structure of a GAA transistor surrounds the channel member, GAA transistors are also referred to as surrounding gate transistors (SGTs). Depending on its shape and orientation, the channel element in a gate-all-around transistor can be referred to as a nanosheet, semiconductor wire, nanowire, nanostructure, nanopost, nanobeam, or nanobridge. In some cases, a gate-all-around transistor can be referred to by the shape of the channel element. For example, a gate-all-around transistor with one or more nanosheet channel elements can also be called a nanosheet transistor or a nanosheet field-effect transistor.

[0017] Still referring to FIG. 2 , the first interconnect structure 258 and the second interconnect structure 268 may each include eight (8) to nineteen (19) metal layers. Each of the metal layers may include an etch stop layer (ESL) and an intermetal dielectric (IMD) layer disposed on the etch stop layer. The etch stop layer may include silicon carbide, silicon nitride, or silicon oxynitride. The intermetal dielectric layer may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric material, other suitable dielectric materials, or combinations thereof. Examples of low-k materials include carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. Each of the metal layers includes a plurality of longitudinally extending vias and horizontal metal lines. The first interconnect structure 258 includes a first top metal feature 290 adjacent to the surface of the first carrier substrate 202. The second interconnect structure 268 includes a second top metal feature 292 adjacent to the surface of the first carrier substrate 202. The first top metal feature 290 and the second top metal feature 292 may also be referred to as a first contact pad 290 and a second contact pad 292, respectively. The contact vias and metal lines in the first interconnect structure 258 and the second interconnect structure 268 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In one embodiment, the contact vias and metal lines include copper (Cu). The top metal features (i.e., first contact pad 290 and second contact pad 292) may include copper (Cu), aluminum (Al), or alloys thereof. In one embodiment, the top metal features (i.e., first contact pad 290 and second contact pad 292) may include an alloy of aluminum and copper. Although not explicitly shown, the contact vias, metal lines, and top metal features may further include a barrier layer to interface with the oxygen-containing intermetallic dielectric.The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), manganese nitride (MnN), or other transition metal nitrides.

[0018] In some embodiments illustrated in FIG. 2 , a first through-substrate via 256 extends through first substrate 252, and a second through-substrate via 266 extends through second substrate 262. The first through-substrate via 256 and the second through-substrate via 266 may comprise copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In one embodiment, the first through-substrate via 256 and the second through-substrate via 266 comprise copper (Cu) and may be formed using an electroplating process. In an exemplary process, a seed layer is first deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD), followed by a metal fill layer deposited using electroplating. Although not explicitly shown in the figures, a barrier layer may be formed to separate the metal fill layer of the first through-substrate via 256 and the second through-substrate via 266 from the etch stop layer and intermetallic dielectric in the first interconnect structure 258 or the second interconnect structure 268. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), manganese nitride (MnN), or other transition metal nitrides.

[0019] As shown in FIG. 2 , the first workpiece 200 may further include a gapfill layer 204 and a photoresist layer 206 overlying the gapfill layer 204. The gapfill layer 204 serves to fill the gap between the first die 250 and the second die 260, as well as the gaps around the first die 250 and the second die 260. The photoresist layer 206 may be used to selectively remove the gapfill layer 204 over the first die 250 and the second die 260 to prevent the formation of an uneven surface during a subsequent planarization process. In some embodiments, the gapfill layer 204 comprises silicon oxide and may be deposited using chemical vapor deposition (CVD), flowable CVD (FCVD), or spin coating. The first carrier substrate 202 may comprise silicon or glass. As will be described further below, the first carrier substrate 202 may be removed at a later stage and will not become part of the final package structure.

[0020] Referring to FIG. 1 and FIG. 3 through FIG. 6 , method 100 includes block 104 , in which gapfill layer 204 is removed from surfaces of first die 250 and second die 260 . Block 104 includes multiple steps to remove gapfill layer 204 from first die 250 and second die 260 without forming recesses in the remaining gapfill layer 204 . Block 104 begins by patterning photoresist layer 206 using lithography. In one exemplary process, photoresist layer 206 may undergo a pre-exposure bake process, exposure to radiation reflected from or transmitted through a photomask, a post-exposure bake process, and a development process to form patterned photoresist layer 206 , as shown in FIG. 3 . The patterned photoresist layer 206 includes a first opening 2060 and a second opening 2062. The first opening 2060 exposes the gapfill layer 204 directly above the first die 250, and the second opening 2062 exposes the gapfill layer 204 directly above the second die 260. Referring to FIG. 4 , the patterned photoresist layer 206 is then used as an etch mask to etch the gapfill layer 204. As shown in FIG. 4 , the gapfill layer 204 is etched until the first substrate 252 of the first die 250 and the second substrate 262 of the second die 260 are exposed. The etching process for the gapfill layer 204 can be a dry etching process using an inert gas (e.g., Ar), a fluorine-containing gas (e.g., CF₄, C₂F₆, SF₆, or NF₃), other suitable gases, and / or plasma, and / or combinations thereof. After etching the gapfill layer 204, the patterned photoresist layer 206 can be removed by ashing or selective etching, as shown in FIG5 . After removing the patterned photoresist layer 206, the first workpiece 200 is planarized using, for example, a chemical mechanical polishing (CMP) process to provide a substantially flat top surface, as shown in FIG6 . It should be noted that because the planarization process tends to remove the gapfill layer 204 more quickly than the first substrate 252 or the second substrate 262, directly planarizing the first workpiece 200 shown in FIG2 may result in recesses between and around the first die 250 and the second die 260. This is why block 104 includes the aforementioned steps to planarize the first workpiece 200.

[0021] Referring to FIG. 1 and FIG. 7 , method 100 includes block 106 , wherein first substrate 252 and second substrate 262 are selectively recessed. In some embodiments, the selective recessing may be performed using a dry etching process using an oxygen-containing gas (e.g., O 2 ), an inert gas (e.g., Ar), a fluorine-containing gas (e.g., CF 4 , C 2 F 6 , SF 6 , or NF 3 ), other suitable gases, and / or plasma, and / or combinations thereof. As shown in FIG. 7 , the selective recessing is performed until the top portions of first through-substrate via 256 and second through-substrate via 266 are above the top surfaces of first substrate 252 and second substrate 262 . As shown in FIG. 7 , gapfill layer 204 may be recessed along with first substrate 252 and second substrate 262 .

[0022] Referring to FIG. 1 and FIG. 8 , method 100 includes block 108 , wherein a plurality of trenches 272 are formed in a first substrate 252 and a second substrate 262 . Each of the plurality of trenches 272 may include a width W along the X-direction and a depth D along the Z-direction (i.e., the longitudinal direction). In some embodiments, the depth D may be between approximately 1 micron and approximately 500 microns. The width W of the trenches 272 may have a wide range, depending on the space available for the trenches 272 and how the trenches 272 are formed. The plurality of trenches 272 may be formed using a mechanical saw, a laser saw, or a dry etching process. In the depicted embodiment, the first die 250 and the second die 260 are square or rectangular in shape when viewed from above (i.e., along the Z-direction) and may have a width along the Y-direction. The trenches 272 in FIG. 8 also extend lengthwise along the Y-direction. The length of the trenches 272 extends over a portion of the width of the first die 250 and the second die 260 . In some embodiments, one or more trenches 272 may extend substantially the entire width of the first die 250 and the second die 260. In other words, one or more of the plurality of trenches 272 may traverse or span substantially the entire Y-direction width of the first die 250 and the second die 260.

[0023] Referring to FIG. 1 and FIG. 9 , method 100 includes block 110 , where a liquid 274 is injected into a plurality of trenches 272 . In some embodiments, liquid 274 is water. In some alternative embodiments, liquid 274 may be a liquid suitable for high heat flux immersion cooling. In these alternative embodiments, liquid 274 includes various properties that make it suitable for use in the semiconductor structures disclosed herein. For example, liquid 274 may be dielectric and have a low dielectric constant to prevent leakage and parasitic capacitance. In some cases, liquid 274 may have a low surface tension to better wet the surfaces of trenches 272 . Suitable liquids 274 should also have a high boiling point or low vapor pressure to prevent damage to the device due to high vapor pressure. Examples of liquids 274 for these alternative embodiments may include hydrocarbons or fluorocarbons. Example hydrocarbons include polyethers. Example fluorocarbons include perfluoropolyether (PFPE) and 1-n-butyl-3-methylimidazolium hexafluorophosphate (BMIM-PF 6). At block 110, liquid 274 may be atomized and injected onto first workpiece 200 to fill trench 272. Alternatively, liquid 274 may be deposited onto trench 272 using spin coating. In some alternative embodiments, liquid 274 is replaced by a highly thermally conductive metal, such as aluminum (Al). When a highly thermally conductive metal is used instead of liquid 274, the metal may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition.

[0024] Referring to FIG. 1 and FIG. 10 , method 100 includes block 112 , wherein a sealing layer 276 is deposited on first workpiece 200 to seal liquid 274 in trench 272 . In some embodiments, sealing layer 276 may include silicon, silicon nitride, or silicon oxide. In one embodiment, sealing layer 276 includes silicon nitride. Sealing layer 276 may be deposited using atomic layer deposition, chemical vapor deposition, or flow chemical vapor deposition (FCVD). If a highly thermally conductive metal is used instead at block 110 , block 112 may be omitted. After depositing sealing layer 276 , first through-substrate via 256 and second through-substrate via 266 may be completely covered by sealing layer 276 .

[0025] 1 and 11 , method 100 includes block 114, in which sealing layer 276 is planarized to expose a portion of first through-substrate vias 256 and second through-substrate vias 266. At block 114, first workpiece 200 is planarized to remove excess sealing layer 276 until sealing layer 276 above the top surfaces of first substrate 252 and second substrate 262 is removed and first through-substrate vias 256 and second through-substrate vias 266 are partially elevated above sealing layer 276. As shown in FIG. 11 , at the conclusion of block 114, a plurality of trenches 272 are substantially filled with liquid 274 and sealing layer 276. Sealing layer 276 and liquid 274 sealed in trenches 272 by sealing layer 276 can be collectively referred to as first thermal profile 280. In some embodiments shown in FIG. 11 , because the planarization process can remove first substrate 252, second substrate 262, and sealing layer 276 faster than first through-substrate via 256 and second through-substrate via 266, first through-substrate via 256 and second through-substrate via 266 can be higher than the top planar surface of first workpiece 200 in FIG. 11 . In an alternative embodiment, when liquid 274 is replaced by a highly thermally conductive metal, plurality of trenches 272 are substantially filled with the metal to form first heat distribution features 280.

[0026] Referring to FIG. 1 and FIG. 12 , method 100 includes block 116 , in which an isolation layer 282 is formed over first workpiece 200 . The operations at block 116 include depositing isolation layer 282 over first workpiece 200 and planarizing isolation layer 282 to expose top surfaces of first through-substrate via 256 and second through-substrate via 266 . In some embodiments, isolation layer 282 may include silicon nitride, silicon oxide, silicon oxynitride, or silicon oxycarbonitride. In the depicted embodiment, isolation layer 282 includes silicon nitride. Isolation layer 282 may be conformally deposited using chemical vapor deposition or a suitable method. Following deposition of isolation layer 282, isolation layer 282 may be disposed on sidewalls and top surfaces of first through-substrate via 256 and second through-substrate via 266 . The deposited isolation layer 282 is then planarized using a chemical mechanical polishing (CMP) process. As shown in FIG. 12 , after planarization, the top surfaces of the first through-substrate via 256 and the second through-substrate via 266 are exposed and are substantially coplanar with the top surface of the isolation layer 282 .

[0027] Referring to FIG. 1 and FIG. 13 , method 100 includes block 118 , wherein a bonding layer 285 is formed over a first die 250 and a second die 260 . One function of the bonding layer 285 is to provide an aligned communication interface. The first die 250 and the second die 260 may have contact patterns that differ from the die to be bonded above them. The bonding layer 285 redirects the contact patterns of the first die 250 and the second die 260 so that they align with the contact patterns of the die to be stacked above them. Furthermore, the bonding layer 285 allows the first die 250 and the second die 260 to be bonded to an overlying die via direct bonding. Direct bonding requires a high level of surface flatness and a high density of dummy and functional bonding metal features. The bonding layer 285 is configured to be flat and include the necessary dummy metal features. 13 , the bonding layer 285 includes an etch stop layer (ESL) 284, an intermetallic dielectric (IMD) layer 286, and a plurality of metal features 288 disposed within and extending through the etch stop layer 284 and the IMD layer 286. The etch stop layer 284 may include silicon nitride or silicon oxynitride. The IMD layer 286 may include silicon oxide, tetraethoxysilane (TEOS) oxide, undoped silica glass (USG), doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), a low-k material, other suitable dielectric materials, or combinations thereof. Examples of low-k materials include carbon-doped silicon oxide, xerogels, aerogels, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. The plurality of metal features 288 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), combinations thereof, or alloys thereof. In one embodiment, the plurality of metal features 288 may include copper (Cu). To form the bonding layer 285, an etch stop layer 284 is first deposited on the first workpiece 200 using chemical vapor deposition. An intermetallic dielectric layer 286 is then deposited on the etch stop layer 284 using chemical vapor deposition, flow chemical vapor deposition (FCVD), or spin coating. An opening is then formed through the etch stop layer 284 and the intermetallic dielectric layer 286. A metal fill layer is then deposited in the opening. After removing excess metal fill layer using chemical mechanical polishing, the plurality of metal features 288 are formed.

[0028] Referring to FIG. 1 and FIG. 14 , method 100 includes block 120 , in which a second workpiece 300 is bonded to a first workpiece 200 to form a third workpiece 400 . In some embodiments, the second workpiece 300 includes a third die 350 and a fourth die 360 ​​, which are mounted on a second carrier substrate 302 similar to the first carrier substrate 202 . It should be understood that the second workpiece 300 shown in FIG. 14 is merely an example, and depending on design requirements, the second workpiece 300 may include only one die or more than two dies. Each of the third die 350 and the fourth die 360 ​​may be a logic die, a system-on-chip (SOC) die, or a memory die (e.g., a dynamic random access memory (DRAM) die). The third die 350 includes a third substrate 352 , a third transistor 354 formed on the third substrate 352 , and a third interconnect structure 358 . The third interconnect structure 358 is disposed on the front surface of the third substrate 352 . It should be noted that third die 350 includes more transistors than third transistor 354. For ease of illustration and explanation, the figures of this disclosure only show third transistor 354. Similarly, fourth die 360 ​​includes a fourth substrate 362, a fourth transistor 364 formed on fourth substrate 362, and a fourth interconnect structure 368. Fourth interconnect structure 368 is disposed on the front surface of fourth substrate 362. It should be noted that fourth die 360 ​​includes more transistors than fourth transistor 364. For ease of illustration and explanation, the figures of this disclosure only show fourth transistor 364.

[0029] At block 120, the second workpiece 300 is inverted and bonded to the first workpiece 200 to define a third workpiece 400 or a multilayer semiconductor structure 400. Although not explicitly shown in the figures, the second workpiece 300 may also include a bonding layer having metal features corresponding to the metal features in the bonding layer 285. To ensure a strong bond between the bonding layers, the surfaces of the two bonding layers are cleaned to remove organic and metallic contaminants. In an exemplary process, a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or both may be used to remove organic contaminants from the bonding layer. A mixture of hydrochloric acid and hydrogen peroxide (SC2) may be used to remove metallic contaminants. In addition to cleaning, the bonding surfaces of the two bonding layers may be treated with argon plasma or nitrogen plasma to activate their surfaces. After the bonding layer is longitudinally aligned, an anneal is performed to promote van der Waals bonding of the intermetallic dielectric layer and surface-activated bonding (SAB) of the metal features in the bonding layer. In some cases, the anneal comprises a temperature between about 200° C. and about 300° C.

[0030] 1 and 15 , method 100 includes block 122 , wherein the second carrier substrate 302 is removed and the operations of blocks 108 , 110 , and 112 are performed on the second workpiece 300 . After the second workpiece 300 is bonded to the first workpiece 200 at block 120 , the second carrier substrate 302 is removed to expose the surfaces of the third substrate 352 and the fourth substrate 362 . With the third substrate 352 and the fourth substrate 362 exposed, operations similar to those described at blocks 108 , 110 , and 112 may be performed on the second workpiece 300 to form second thermal features 380 . Similar to the first thermal features 280 , each of the second thermal features 380 includes a liquid 374 sealed in a groove by a sealing layer 376 . As described above, in some alternative embodiments, the liquid 374 and the sealing layer 376 may be replaced with a highly thermally conductive metal, such as aluminum (Al). Since the material and formation of liquid 374 and sealing layer 376 are similar to those of liquid 274 and sealing layer 276 , detailed description thereof is omitted for the sake of brevity.

[0031] Referring to FIG. 1 , FIG. 16 , and FIG. 17 , method 100 includes block 124 , where further processing is performed. Such further processing may include bonding a third workpiece 400 to a third carrier substrate 382 , removing the first carrier substrate 202 , and forming bump features. In some embodiments shown in FIG. 16 , an isolation layer 304 similar to isolation layer 282 may be formed over the second workpiece 300 . The third carrier substrate 382 may have the same composition as the first carrier substrate 202 . In some embodiments, the third carrier substrate 382 may include silicon or glass. To bond the third carrier substrate 382 to the second workpiece 300 , a silicon oxide-containing layer is formed over the third carrier substrate 382 , and the isolation layer 304 may be directly bonded to the silicon oxide-containing layer. In alternative embodiments, a die attach film may be used to bond the third carrier substrate 382 to the second workpiece 300 . To form bump features on the front side surface (facing downward in FIG. 16 ) of the first workpiece 200, the first carrier substrate 202 is removed using a die separation or lift-off process. Referring now to FIG. 17 , before forming bump features to couple to the first contact pads 290 in the first interconnect structure 258 and the second contact pads 292 in the second interconnect structure 268 , a first passivation layer 402 and a second passivation layer 404 are deposited on the front surface of the first workpiece 200 (now part of the inverted third workpiece 400). In some embodiments, the first passivation layer 402 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be deposited using chemical vapor deposition. The second passivation layer 404 may be a polymer layer. In some cases, the second passivation layer 404 may include epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a suitable polymeric material. The second passivation layer 404 may be deposited using chemical vapor deposition, flow chemical vapor deposition, or spin coating.

[0032] The first passivation layer 402 and the second passivation layer 404 may be collectively referred to as a passivation structure. After forming the passivation structure, an opening is formed through the passivation structure directly above the first contact pad 290 and the second contact pad 292. A copper pillar 406 is then formed in the opening to couple to the first contact pad 290 and the second contact pad 292. The copper pillar 406 may comprise copper (Cu), nickel (Ni), cobalt (Co), or a copper alloy. Although not explicitly shown in the figures, an under-bump metallization (UBM) may be formed before forming the copper pillar 406. The UBM layer may comprise a barrier layer and a seed layer. The barrier layer may comprise titanium nitride or tantalum nitride. The seed layer may comprise copper (Cu), silver (Ag), chromium (Cr), tin (Sn), gold (Au), or combinations thereof. After forming the copper pillar 406, a bump feature 408 is formed on the copper pillar 406. The bump feature 408 may include a Sn-Cu alloy, a Sn-Ag alloy, or a Sn-Cu-Ag alloy. The bump feature 408 may be a controlled collapse chip connection (C4) connection or a microbump.

[0033] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first interconnect structure, a first substrate, a second interconnect structure, and a second substrate. The first substrate is disposed on the first interconnect structure, the second interconnect structure is disposed on the first substrate, and the second substrate is disposed on the second interconnect structure. The first substrate includes a first plurality of trenches extending from a surface adjacent to the second interconnect structure into the first substrate. The first plurality of trenches are filled with a liquid.

[0034] In some embodiments, the liquid comprises water, a hydrocarbon, or a fluorocarbon. In some embodiments, the second substrate comprises a second plurality of trenches extending from a surface distal from the second interconnect structure into the second substrate. The second plurality of trenches are filled with a liquid. In some embodiments, the first substrate further comprises at least one through-substrate via (TSV) extending completely through the first substrate. In some cases, the first plurality of trenches are further filled with a sealing layer, and a top surface of the sealing layer is coplanar with a top surface of the first substrate. In some embodiments, the semiconductor structure further comprises a dielectric structure and an isolation film, the dielectric structure surrounding and contacting the first interconnect structure and the first substrate, the isolation film being disposed on the first substrate, the sealing layer, and the dielectric structure. In some cases, the semiconductor structure further comprises a dielectric layer and a plurality of contact features, the dielectric layer being disposed on the isolation film, and the plurality of contact features being embedded in the dielectric layer. In some embodiments, the sealing layer comprises silicon nitride.

[0035] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first die, a bonding layer, and a second die. The first die includes a first interconnect structure, a first substrate, and a first plurality of heat distribution lines, wherein the first substrate is disposed on the first interconnect structure, and the first plurality of heat distribution lines are disposed in the first substrate. The bonding layer is disposed on the first substrate. The second die is disposed on the bonding layer and includes a second interconnect structure, a second substrate, and a second plurality of heat distribution lines, wherein the second substrate is disposed on the second interconnect structure, and the second plurality of heat distribution lines are disposed in the second substrate.

[0036] In some embodiments, each of the first plurality of heat distribution lines and the second plurality of heat distribution lines comprises a liquid and a sealing layer over the liquid. In some embodiments, the sealing layer comprises silicon oxide, silicon nitride, or silicon. In some embodiments, the bonding layer comprises a first plurality of metal features. The second interconnect structure comprises a second plurality of metal features. Each of the first plurality of metal features is longitudinally aligned with one of the second plurality of metal features. In some cases, each of the first plurality of heat distribution lines and the second plurality of heat distribution lines comprises a metal. In some embodiments, the metal comprises aluminum (Al).

[0037] In another exemplary aspect, the present disclosure relates to a method comprising receiving a first workpiece, the first workpiece comprising a first die mounted on a first carrier substrate, the first die comprising a first substrate and a through-substrate via; selectively etching the first substrate until a portion of the through-substrate via is higher than the first substrate; forming a first plurality of trenches in the first substrate; injecting a liquid into the first plurality of trenches; depositing a first sealing layer over the first workpiece to seal the liquid in the first plurality of trenches; and, after depositing the first sealing layer, planarizing the first workpiece to expose the through-substrate via.

[0038] In some embodiments, the first sealing layer comprises silicon oxide, silicon nitride, or silicon. In some embodiments, forming the first plurality of trenches comprises using a mechanical saw. In some embodiments, forming the first plurality of trenches comprises using a laser saw. In some cases, the method further comprises bonding a second workpiece to the first workpiece, the second workpiece comprising a second die mounted on a second carrier substrate, the second die comprising a second substrate; removing the second carrier substrate; forming a second plurality of trenches in the second substrate after removing the second carrier substrate; injecting a liquid into the second plurality of trenches; depositing a second sealing layer on the second workpiece to seal the liquid in the second plurality of trenches; and planarizing the second workpiece after depositing the second sealing layer. In some embodiments, the method further comprises depositing an isolation layer on the second workpiece after planarizing the second workpiece; and bonding a third carrier substrate to the isolation layer.

[0039] The foregoing text summarizes the features of many embodiments, enabling those skilled in the art to better understand the present disclosure from various perspectives. Those skilled in the art will readily understand and be able to use this disclosure as a basis for designing or modifying other processes and structures that achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

[0040] 100: Method 102,104,106,108,110,112,114,116,118,120,122,124: Blocks 200: First workpiece 202: first carrier substrate 204: Gap filling layer 206: Photoresist layer / patterned photoresist layer 2060: First opening 2062: Second opening 250: First Bare Crystal 252: first substrate 254: First transistor 256: First substrate through hole 258: First interconnection structure 260: Second Bare Crystal 262: Second substrate 264: Second transistor 266: Second substrate through hole 268: Second interconnection structure 272: Groove 274:Liquid 276: Sealing layer 280: First heat distribution characteristics 282,304: Isolation layer 284: Etch stop layer 285: Bonding layer 286: Intermetallic dielectric layer 288:Metal Characteristics 290: first contact pad 292: Second contact pad 300: Second workpiece 302: second carrier substrate 350: The third bare crystal 352: Third base material 354: The third transistor 358: Third interconnection structure 360: The fourth bare crystal 362: Fourth base material 364: Fourth transistor 368: Fourth interconnection structure 374:Liquid 376: Sealing layer 380: Second thermal distribution characteristics 382: third carrier substrate 400: The third workpiece 402: first passivation layer 404: second passivation layer 406: Copper Pillar 408: Bump feature D: Depth W: width

Claims

1. A semiconductor structure, comprising: First interconnect structure; A first substrate is disposed on the first interconnect structure; A second interconnect structure is disposed on the first substrate; The first substrate is disposed on the second interconnect structure. The first substrate includes a first plurality of trenches extending from a surface adjacent to the second interconnect structure into the first substrate. The first plurality of trenches are filled with a liquid, and the first plurality of trenches are further filled with a sealing layer above the liquid, thereby sealing and retaining the liquid in the first plurality of trenches. The first substrate further includes at least one substrate via extending completely through the first substrate. A top surface of the sealing layer is coplanar with a top surface of the first substrate, and a top portion of the at least one substrate via is higher than the top surface of the first substrate. The semiconductor junction further includes: an isolation layer disposed on the first substrate and the sealing layer, wherein the sidewalls of the at least one substrate via are surrounded by the isolation layer, and a top surface of the at least one substrate via is coplanar with a top surface of the isolation layer.

2. The semiconductor structure of claim 1, wherein the liquid comprises water, hydrocarbon or fluorocarbon, wherein the first plurality of trenches extend along a first direction for a portion of the width of the first substrate.

3. The semiconductor structure as described in claim 1, wherein, The second substrate includes a second plurality of trenches extending from a surface away from the second interconnect structure into the second substrate; wherein the second plurality of trenches are filled with the liquid.

4. The semiconductor structure as described in claim 1 further includes: A dielectric structure surrounds and contacts the first interconnect structure and the first substrate; And a bonding layer disposed on the isolation layer and the at least one substrate via, the bonding layer comprising: a dielectric layer disposed on the isolation layer; And multiple metallic features are embedded in the dielectric layer.

5. A semiconductor structure, comprising: A first bare die includes: a first interconnect structure; a first substrate disposed on the first interconnect structure, wherein the first substrate includes at least one substrate via extending completely through the first substrate; a first plurality of heat distribution lines disposed in the first substrate; and an isolation layer disposed on the first plurality of heat distribution lines and the first substrate, wherein a top portion of the at least one substrate via is above a top surface of the first substrate and extends into the isolation layer; a bonding layer disposed on the isolation layer and the at least one substrate via; and a second bare die disposed on the bonding layer, and includes: a second interconnect structure; a second substrate disposed on the second interconnect structure; and a second plurality of heat distribution lines disposed in the second substrate, wherein each of the first plurality of heat distribution lines and the second plurality of heat distribution lines includes a liquid and a sealing layer on the liquid, thereby sealing and retaining the liquid in the first substrate or the second substrate.

6. The semiconductor structure as described in claim 5, wherein, The bonding layer includes a first plurality of metal features; wherein the second interconnect structure includes a second plurality of metal features; wherein each of the first plurality of metal features is longitudinally aligned with one of the second plurality of metal features.

7. A method for forming a semiconductor structure, comprising: The process involves receiving a first workpiece, the first workpiece including a first bare die mounted on a first carrier substrate, the first bare die including a first substrate and a substrate via; selectively etching the first substrate until a top portion of the substrate via is above the first substrate; forming a first plurality of trenches in the first substrate; injecting a liquid into the first plurality of trenches; depositing a first sealing layer on the first workpiece to seal the liquid in the first plurality of trenches, thereby sealing and retaining the liquid in the first plurality of trenches; and after depositing the first sealing layer, planarizing the first workpiece to expose the substrate via and make the top portion of the substrate via above a top surface of the first substrate. And after planarizing the first workpiece, an isolation layer is deposited on the top surface of the first substrate, such that the top portion of the through-hole of the substrate is embedded in the isolation layer.

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