Package structure and method for forming the same

Abstract

An encapsulation structure includes: an interposer, a control unit, a plurality of arithmetic units, a signal transmission layer, and an optoelectronic material. The control unit is bonded to the interposer. The arithmetic units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the arithmetic units. The optoelectronic material is formed within the control unit and the arithmetic units, and overlaps with the signal transmission layer.

Description

Package Structure and Method of Manufacturing the Same Embodiments of the present disclosure relate to a package structure and a method of manufacturing the same, and more particularly to a package structure provided with an optoelectronic material overlapping a signal transmission layer and a method of manufacturing the same. The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Individual dies are usually packaged separately. Packaging not only provides protection for semiconductor devices from environmental contamination, but also provides a connection interface for the semiconductor devices packaged therein. Three-dimensional integrated circuits (3DICs) are the latest development in semiconductor packaging, in which multiple semiconductor dies are stacked on top of each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. Some three-dimensional integrated circuits are prepared at the semiconductor wafer level by placing dies on top of dies. Due to, for example, the shortening of the interconnect length between stacked dies, three-dimensional integrated circuits provide improved integration density and other advantages, such as faster speed and higher bandwidth. However, there are still many challenges associated with three-dimensional integrated circuits. Embodiments of the present disclosure provide a package structure including an interposer, a control unit, a plurality of arithmetic units, a signal transmission layer, and an optoelectronic material. The control unit is bonded to the interposer. The arithmetic units are disposed around the control unit and connected to the control unit. The signal transmission layer is formed in the control unit and the arithmetic units. The optoelectronic material is formed in the control unit and the arithmetic units, and the optoelectronic material overlaps the signal transmission layer. Embodiments of the present disclosure provide a package structure including an interposer, a signal transmission layer formed in the interposer, an optoelectronic material formed in the interposer, a control unit bonded to the interposer, and a plurality of arithmetic units. The optoelectronic material overlaps the signal transmission layer. The arithmetic units are bonded to the interposer and connected to the control unit through the signal transmission layer. An embodiment of the present disclosure provides a method for manufacturing a packaging structure, including forming an interposer, which includes forming a plurality of through-substrate via (TSV) structures in a substrate, and forming a substrate material above the substrate. Forming the interposer includes forming a plurality of conductive features in the substrate material. The conductive features are electrically connected to the through-substrate via structures. Forming the interposer includes forming a signal transmission layer in the substrate material. The signal transmission layer is isolated from the conductive features. Forming the interposer includes forming an optoelectronic material in the substrate material. The optoelectronic material overlaps with the signal transmission layer. This method includes bonding a control unit and a plurality of arithmetic units to the interposer. The arithmetic units are separated from the control unit, and the arithmetic units are connected to the control unit through the signal transmission layer. This method includes filling underfill in the gap between the control unit and the arithmetic units. The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Reference numerals and / or letters may be reused in the various examples described in the present disclosure. These repetitions are for the purpose of simplicity and clarity, and do not themselves indicate any relationship between the various embodiments and / or configurations disclosed. In addition, the following describes specific examples of components and configurations to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only illustrative and not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which additional features are formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, spatially relative terms may be used herein. For example, "under", "below", "lower", "above", "higher" and similar terms are used to facilitate the description of the relationship between one element or feature shown in the drawings and another (or some) element or feature. In addition to the orientation shown in the drawings, these spatially relative terms are intended to include different orientations of the device during use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted in the same way accordingly. Embodiments of a packaging structure and a method for forming the same are provided. The packaging structure includes a control unit and a plurality of arithmetic units surrounding the control unit. Therefore, the connection between the control unit and each arithmetic unit can be shortened, and the manufacturing cost can be reduced. In addition, by adding an optoelectronic material overlapping with the signal transmission layer to change the characteristics of the transmitted optical signal, the overall performance of the packaging structure can be improved. The optoelectronic material can be disposed in the interposer or in the control unit and the arithmetic units. In this way, a diversified packaging structure design can be adopted. FIGS. 1A to 1D are cross-sectional views illustrating various stages of forming a packaging structure 100 according to some embodiments of the present disclosure. Referring to FIG. 1A, a substrate 50 is provided, and a plurality of through-substrate via (TSV) structures 51 may be formed in the substrate 50. In some embodiments, the substrate 50 may include a non-organic interlayer material, such as a silicon-based dielectric material (e.g., silicon oxide, porous or non-porous organosilicate glass, silicon carbonitride, silicon nitride, or any other non-organic interconnect-level dielectric material). In some embodiments, more than one non-organic interlayer material layer may be deposited to form the substrate 50 by spin-coating and drying the corresponding non-organic dielectric material. For example, the substrate 50 may be formed in a series of steps, such as by sequentially forming the through-substrate via structures 51 in each layer of the substrate 50. The through-substrate via structures 51 may be initially formed as via structures within the substrate 50, where the vertical dimension of the through-substrate via structures 51 is less than the thickness of the substrate 50. Subsequently, the back side of the substrate 50 may be removed, such that the "through-silicon" configuration of the substrate 50 is as shown in FIG. 1D. In some embodiments, a hard mask layer (not shown, such as a silicon nitride layer and / or a borosilicate glass layer) and a patterned photoresist layer may be formed on and / or above the front-side surface of the substrate 50. Anisotropic etching using the hard mask (and optionally the patterned photoresist layer) as an etching mask may be performed to form deep trenches extending vertically from the front-side surface of the substrate 50 toward the back side of the substrate 50. The photoresist layer may be consumed during the anisotropic etching process and may subsequently be removed, for example, using a wet etching process. Thus, the deep trenches may extend vertically from the front-side surface of the substrate 50 to the back-side surface of the substrate 50. Generally, the lateral dimension of the deep trenches may be selected to be large enough to provide deep etching of the substrate 50 and may be selected to be small enough to provide filling of the deep trenches for forming the through-substrate via structures 51. At least one conductive material (e.g., a metal material and / or a heavily doped semiconductor material) may be deposited in the deep trenches to form the through-substrate via structures 51. For example, the conductive material may include copper, nickel, or a stack of copper and nickel. Other suitable materials are also contemplated within the scope of the present disclosure. Referring to FIG. 1B, a substrate 52 and conductive features 53 can be formed over a substrate 50. In some embodiments, the substrate 52 can be deposited over the exposed surface of the substrate 50 through a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, laser ablation, etc.). In some embodiments, the substrate 52 can include an organic material, such as a dielectric polymer material of polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). In some embodiments, conductive features 53 can be formed in the substrate material 52, and the conductive features 53 include a conductive material (such as a metal material and / or a heavily doped semiconductor material). For example, the conductive material can include copper, nickel, or a stack of copper and nickel. However, other suitable materials are also within the scope contemplated by this disclosure. In some embodiments, the conductive features 53 can be formed using the same method or material as the substrate via structure 51. In addition, a signal transmission layer 140 is formed in the base material 52, and an optoelectronic material 150 is formed on the signal transmission layer 140. The signal transmission layer 140 may include a nitride-based material, such as silicon nitride (SiN). The signal transmission layer 140 can be used to transmit optical signals between a subsequently formed control unit 120 and an arithmetic unit 130 (as shown in FIG. 1C for example). In some embodiments, the optoelectronic material 150 overlaps with the signal transmission layer 140 in the vertical direction (for example, the direction parallel to the Z-axis). For example, the optoelectronic material 150 includes aluminum nitride, hexagonal boron nitride, graphene, or a combination of the foregoing materials. The arrangement of the optoelectronic material 150 can change the characteristics of the signals transmitted in the signal transmission layer 140, thereby improving the operating quality or performance of the packaging structure 100. In the present embodiment, the signal transmission layer 140 is located below and in contact with the optoelectronic material 150, which means that the signal transmission layer 140 is formed prior to the optoelectronic material 150. However, the present disclosure is not limited thereto. In some other embodiments, the signal transmission layer 140 is located above and in contact with the optoelectronic material 150. The conductive pad 55 can be formed on the base material 52 and includes a conductive material (such as a metal material and / or a heavily doped semiconductor material). For example, the conductive material may include copper, nickel, or a stack of copper and nickel. However, other suitable materials are also within the scope considered in the present disclosure. In some embodiments, the conductive pad 55 can be formed using the same method or material as the conductive feature 53 or the base via structure 51. As described above, the interposer 110 is formed, and a redistribution structure 115 composed of the base via structure 51, the conductive feature 53, and the conductive pad 55 is formed in the interposer 110. It should be noted that the redistribution structure 115 is isolated from the signal transmission layer 140 and the optoelectronic material 150. For the sake of brevity, some internal structures of the interposer 110 will not be labeled in the following diagrams, and will not be described in detail in the following paragraphs. As shown in FIG. 1C, the control unit 120 and a plurality of arithmetic units 130 are bonded to the interposer 110. More specifically, the control unit 120 and the arithmetic units 130 are physically and electrically connected to the conductive pad 55. In some embodiments, the arithmetic units 130 are arranged around the control unit 120 and connected to the control unit 120. In some embodiments, the control unit 120 and the arithmetic units 130 are aligned with the regions where the signal transmission layer 140 and the optoelectronic material 150 are located in the interposer 130. In other words, the control unit 120 and the arithmetic units 130 overlap with the signal transmission layer 140 and the optoelectronic material 150 in the interposer 110 in the vertical direction (for example, parallel to the Z-axis). In some embodiments, the control unit 120 includes an integrated circuit 121 on an interconnect structure 122. The interconnect structure 122 includes a plurality of dielectric layers 123, a plurality of semiconductor devices 124 formed in the dielectric layers 123, and conductive features 125 electrically connected to the semiconductor devices 124. The conductive features 125 are aligned with and electrically connected to the conductive pads 55. In addition, at least one signal transmission layer 145 is formed in the interconnect structure 122. The signal transmission layer 145 may include a nitride-based material, such as silicon nitride (SiN). The signal transmission layer 145 may be configured to transmit optical signals to the control unit 120. In some embodiments, the signal transmission layer 145 may be formed using the same method or material as the signal transmission layer 140. Similarly, each arithmetic unit 130 includes an integrated circuit 131 on an interconnect structure 132. The interconnect structure 132 includes a plurality of dielectric layers 133, a plurality of semiconductor devices 134 formed in the dielectric layers 133, and conductive features 135 electrically connected to the semiconductor devices 134. The conductive features 135 are aligned with and electrically connected to the corresponding conductive pads 55. In addition, at least one signal transmission layer 145 is formed in the interconnect structure 132 and is configured to transmit optical signals to the arithmetic unit 130. In addition, a plurality of signal sources 170 are bonded to the interposer 110, and the signal sources 170 are respectively connected to the control unit 120 or the arithmetic unit 130 via the signal transmission layer 140. In some embodiments, the signal sources 170 are configured to receive electrical signals, convert the received electrical signals into optical signals, and transmit the optical signals to the control unit 120 or the arithmetic unit 130 through the signal transmission layer 140. Therefore, the control unit 120 and the arithmetic unit 130 can operate based on the transmitted optical signals to execute instructions. After the control unit 120, the arithmetic unit 130, and the signal source 170 are each positioned on the interposer 110, the underfill 160 can be dispensed on the interposer 110 to encapsulate the control unit 120, the arithmetic unit 130, and the signal source 170. In some embodiments, the arithmetic unit 130 is separated from the control unit 120 by the underfill 160. In some embodiments, the underfill 160 can be formed above the top surfaces of the control unit 120, the arithmetic unit 130, and the signal source 170. Subsequently, the portion of the underfill 160 that is higher than the control unit 120, the arithmetic unit 130, and the signal source 170 (e.g., directly above the top surfaces of the control unit 120, the arithmetic unit 130, and the signal source 170) can be removed by a suitable planarization process (such as chemical mechanical polishing (CMP)). Thus, the top surface of the underfill 160 is substantially coplanar with the top surfaces of the control unit 120, the arithmetic unit 130, and the signal source 170. As shown in FIG. 1D, the interposer 110 is thinned such that the substrate via structure 51 is exposed on the back side of the interposer 110. In some embodiments, the bump structure 57 can be a conductive spherical structure (such as a ball grid array (BGA)), a conductive columnar structure, or a conductive paste structure that is mounted on the interposer 110 and electrically coupled to the interposer 110 during a bonding process. In embodiments where the interposer 110 includes Controlled Collapse Chip Connection (C4) pads, the bump structure 57 can be a Controlled Collapse Chip Connection solder ball, i.e., a spherical solder portion that can be used for Controlled Collapse Chip Connection bonding. In embodiments where the interposer 110 includes a microbump array for Chip connection (C2) bonding, the bump structure 57 can be a solder cap that wets the entire planar end surface of the corresponding microbump and has a generally hemispherical shape. Although embodiments using the bump structure 57 represented by spherical Controlled Collapse Chip Connection solder balls are used to illustrate the present disclosure, the present disclosure also expressly contemplates embodiments where the bump structure 57 is a solder cap having a hemispherical shape. FIG. 2 is a top view of the packaging structure 100 according to some embodiments of the present disclosure. As shown in FIG. 2, the computing units 130 are located on each side of the control unit 120. In other words, the control unit 120 is surrounded by the computing units 130. However, the present disclosure is not limited thereto. In some embodiments, the computing units 130 are linearly arranged along the edge of the control unit 120. Since the control unit 120 is located at the center of the computing units 130, the connection between the control unit 120 and the computing units 130 (such as the signal transmission layer 140 connecting the control unit 120 and the computing units 130) can be shortened. Therefore, the manufacturing cost can be reduced, and the overall performance of the packaging structure 100 can be improved. FIG. 3 is a cross-sectional view illustrating a packaging structure 200 according to some embodiments of the present disclosure. It should be noted that the packaging structure 200 of this embodiment may include elements that are the same as or similar to those of the packaging structure 100 shown in FIG. 1D. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 3, the packaging structure 200 includes an interposer 110, a control unit 120, and a plurality of computing units 130. The control unit 120 and the computing units 130 are bonded to the interposer 110. The signal transmission layer 140 is formed in the interposer 110. In this embodiment, a signal transmission layer 145 is formed in the control unit 120 and the computing units 130, and an optoelectronic material 155 is formed in the control unit 120 and the computing units 130. The optoelectronic material 155 overlaps with the signal transmission layer 145. The optoelectronic material 155 changes the characteristics of the signals transmitted in the signal transmission layer 145, improving the operating quality or performance of the packaging structure 200. FIG. 4A is a cross-sectional view illustrating the signal transmission layer 145 and the optoelectronic material 155 in the computing unit 130 according to some embodiments of the present disclosure. As shown in FIG. 4A, the width of the optoelectronic material 155 may be different from the width of the signal transmission layer 145. For example, the width of the optoelectronic material 155 may be longer than the width of the signal transmission layer 145. However, the present disclosure is not limited thereto. In some embodiments, the width of the optoelectronic material 155 may be less than or equal to the width of the signal transmission layer 145. In some embodiments, the sidewalls of the optoelectronic material 155 are vertically aligned with the sidewalls of the signal transmission layer 145. FIG. 4B is a top view showing the signal transmission layer 145 and the optoelectronic material 155 in the arithmetic unit 130 according to some embodiments of the present disclosure. As shown in FIG. 4B, a part of the signal transmission layer 145 is annular, and the optoelectronic material 155 is rectangular. In some embodiments, the signal transmission layer 145 and / or the optoelectronic material 155 may be an elongated shape, circular or rectangular, etc. with or without rounded corners. In the top view, the signal transmission layer 145 overlaps the optoelectronic material 155. For example, the area of the signal transmission layer 145 that overlaps the optoelectronic material 155 does not exceed 5%. In some embodiments, the shapes of the signal transmission layer 145 and the optoelectronic material 155 may be similar or the same. FIG. 5 is a cross-sectional view showing the packaging structure 300 according to some embodiments of the present disclosure. FIG. 6 is a top view showing the packaging structure 300 according to some embodiments of the present disclosure. It should be noted that the packaging structure 300 of this embodiment may include elements that are the same as or similar to the packaging structure 200 shown in FIG. 3. These elements will be represented by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 5, the packaging structure 300 includes an interposer 110, a plurality of control units 120, a plurality of arithmetic units 130, and a plurality of signal sources 170. The control units 120 are respectively integrated with the arithmetic units 130, and the signal sources 170 are each bonded to be adjacent to the arithmetic units 130. In this embodiment, a signal transmission layer 140 is formed in the interposer 110, a signal transmission layer 145 is formed in the control units 120 and the arithmetic units 130, and an optoelectronic material 155 is formed in the control units 120 and the arithmetic units 130. Since the control units 120 and the arithmetic units 130 are each integrated into one body, the setting flexibility of the control units 120 and the arithmetic units 130 can be improved. As shown in FIG. 6, the arithmetic units 130 are arranged in an array above the interposer 110, and the control units 120 are located in the corresponding arithmetic units 130. In this way, the density of the arithmetic units 130 per unit area can be increased, thereby reducing the area occupied by the control units 120 and the arithmetic units 130 to achieve miniaturization of the packaging structure 300. The signal sources 170 are respectively arranged adjacent to the arithmetic units 130 and are connected to the arithmetic units 130 through the signal transmission layer 140. In some embodiments, the signal sources 170 are arranged between adjacent arithmetic units 130. FIG. 7 is a cross-sectional view illustrating a packaging structure 400 according to some embodiments of the present disclosure. FIG. 8 is a top view illustrating the packaging structure 400 according to some embodiments of the present disclosure. It should be noted that the packaging structure 400 of the present embodiment may include elements that are the same as or similar to those of the packaging structure 200 shown in FIG. 3. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 7, the packaging structure 400 includes an interposer 110, a control unit 120, and a plurality of computing units 130. The control unit 120 and the computing units 130 are bonded to the interposer 110. A signal transmission layer 140 is formed in the interposer 110. In the present embodiment, a signal transmission layer 145 is formed in the control unit 120 and the computing units 130, and an optoelectronic material 155 is formed in the control unit 120 and the computing units 130. In the present embodiment, a processor 180 and a plurality of memory devices 185 are bonded to the interposer, and the memory devices 185 are located near the processor 180. In some embodiments, the processor 180 and the memory devices 185 are connected to the control unit 120 via a redistribution structure 115 in the interposer 110. In some embodiments, the processor 180 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or other types of processing elements. The processor 180 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, the processor 180 includes one or more processors that can be programmed to perform one or more operations or processes described elsewhere in the present disclosure. In some embodiments, each of the memory devices 185 includes vertically stacked static random access memory dies and provides a high bandwidth defined under the JEDEC (Joint Electron Device Engineering Council) standard (i.e., the standard defined by the JEDEC Solid State Technology Association). Thus, the memory devices 185 can be referred to as high bandwidth memories and store information, instructions, and / or software (such as one or more software applications) related to the operation of the packaging structure 400. FIG. 9 is a cross-sectional view illustrating a packaging structure 500 according to some embodiments of the present disclosure. FIG. 10 is a top view illustrating the packaging structure 500 according to some embodiments of the present disclosure. It should be noted that the packaging structure 500 of the present embodiment may include elements identical or similar to those of the packaging structure 200 shown in FIG. 3. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIGS. 9 and 10, the packaging structure 500 includes an interposer 110, a control unit 120, and a plurality of arithmetic units 130. The control unit 120 and the arithmetic units 130 are bonded to the interposer 110. A signal transmission layer 140 is formed in the interposer 110. In the present embodiment, a signal transmission layer 145 is formed in the control unit 120 and the arithmetic units 130, and an optoelectronic material 155 is formed in the control unit 120 and the arithmetic units 130. In some embodiments, an optical element 190 is bonded to the interposer 110 and connected to the control unit 120 and the arithmetic units 130 via the signal transmission layer 140 and the redistribution structure 115. The optical element 190 can receive an optical signal (such as light) and convert the received optical signal into an electrical signal, and transmit the electrical signal to the control unit 120 or the arithmetic units 130 through the signal transmission layer 140 and the redistribution structure 115. Therefore, the control unit 120 and the arithmetic units 130 can operate based on the transmitted electrical signal to execute instructions. FIG. 11 is a top view illustrating a packaging structure 600 according to some embodiments of the present disclosure. It should be noted that the packaging structure 600 of the present embodiment may include elements identical or similar to those of the packaging structure 500 shown in FIG. 10. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 11, the packaging structure 600 includes an interposer 110, a control unit 120, and a plurality of arithmetic units 130. The control unit 120 and the arithmetic units 130 are bonded to the interposer 110. In some embodiments, a plurality of optical elements 190 are bonded to the interposer 110 and connected to the control unit 120 and the arithmetic units 130 through the signal transmission layer 140 and the redistribution structure 115. The configuration of the plurality of optical elements 190 can improve the flexibility of designing the packaging structure 600 because the separated optical elements 190 can occupy less area compared to a single optical element 190. In some embodiments, the optical elements 190 are located on a single side of the interposer 110. However, the present disclosure is not limited thereto. In some other embodiments, the optical elements 190 are located on different sides or different corners of the interposer 110. FIG. 12 is a top view illustrating a packaging structure 700 according to some embodiments of the present disclosure. It should be noted that the packaging structure 700 of this embodiment may include elements that are the same as or similar to those of the packaging structure 500 shown in FIG. 10. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 12, the packaging structure 700 includes an interposer 110, a control unit 120, and a plurality of computing units 130. The control unit 120 and the computing units 130 are bonded to the interposer 110. In some embodiments, an optical element 190 is disposed in and integrated with the control unit 120, and the optical element 190 is connected to the computing units 130 via a signal transmission layer 140. In this way, the connection between the optical element 190 and the computing units 130 (such as the signal transmission layer 140 connecting to the optical element 190 and the computing units 130) can be shortened, and the signal transmission layer 140 connecting to the optical element 190 and the control unit 120 can be omitted. Therefore, the manufacturing cost can be reduced, and the overall performance of the packaging structure 700 can be improved. FIG. 13 is a cross-sectional view illustrating a packaging structure 800 according to some embodiments of the present disclosure. It should be noted that the packaging structure 800 of this embodiment may include elements that are the same as or similar to those of the packaging structure 100 shown in FIG. 1D. These elements will be denoted by the same or similar reference numerals and will not be described in detail in the following paragraphs. As shown in FIG. 13, the packaging structure 800 includes an interposer 110, a control unit 120, and a plurality of computing units 130. The control unit 120 and the computing units 130 are bonded to the interposer 110. A signal transmission layer 140 and a optoelectronic material 150 are formed in the interposer 110. In addition, a signal transmission layer 145 is formed in the control unit 120 and the computing units 130, and an optoelectronic material 155 is formed in the control unit 120 and the computing units 130. By the arrangement of the plurality of optoelectronic materials 150 and 155, the design flexibility of the packaging structure 800 can be improved. For example, the control units 120 and the computing units 130 without the optoelectronic material 155 can also be bonded to the same interposer as the control units 120 and the computing units 130 with the optoelectronic material 155. As described above, the present disclosure is related to a packaging structure and a method of forming the same. The packaging structure includes a control unit and a plurality of computing units surrounding the control unit. Therefore, the connection between the control unit and each computing unit can be shortened, thereby reducing the manufacturing cost. In addition, by increasing the optoelectronic material overlapping with the signal transmission layer to change the characteristics of the transmitted optical signal, the overall performance of the packaging structure can be improved. The optoelectronic material can be disposed in the interposer or in the control unit and the computing units, so a diversified packaging structure design can be adopted. In addition, a signal source, a processor, a memory device, and an optical element can also be bonded to the interposer having the control unit and the computing units for more functions. According to some embodiments, a packaging structure includes an interposer, a control unit, a plurality of arithmetic units, a signal transmission layer, and an optoelectronic material. The control unit is bonded to the interposer. The arithmetic units are disposed around the control unit and connected to the control unit. The signal transmission layer is formed in the control unit and the arithmetic units. The optoelectronic material is formed within the control unit and the arithmetic units, and the optoelectronic material overlaps with the signal transmission layer. In some embodiments, the arithmetic units are separated from the control unit by an underfill, and the arithmetic units are connected to the control unit through another signal transmission layer in the interposer. In some embodiments, the packaging structure further includes a signal source bonded to the interposer, wherein the signal source is connected to the control unit or the arithmetic units through the signal transmission layer. In some embodiments, the packaging structure further includes an optical component disposed within the control unit and connected to the arithmetic units through the signal transmission layer. In some embodiments, the width of the optoelectronic material is different from the width of the signal transmission layer. In some embodiments, the optoelectronic material includes aluminum nitride, hexagonal boron nitride, graphene, or a combination of aluminum nitride, hexagonal boron nitride, and graphene. According to some embodiments, a packaging structure includes an interposer, a signal transmission layer formed in the interposer, an optoelectronic material formed in the interposer, a control unit bonded to the interposer, and a plurality of arithmetic units. The optoelectronic material overlaps with the signal transmission layer. The arithmetic units are bonded to the interposer and connected to the control unit through the signal transmission layer. In some embodiments, the arithmetic units are separated from the control unit by an underfill, and the arithmetic units are linearly arranged along the edge of the control unit. In some embodiments, the signal transmission layer is located above the optoelectronic material and in contact with the optoelectronic material. In some embodiments, the signal transmission layer is located below the optoelectronic material and in contact with the optoelectronic material. In some embodiments, the packaging structure further includes a redistribution structure formed in the interposer, wherein the redistribution structure is isolated from the signal transmission layer. In some embodiments, the packaging structure further includes a processor and a memory device. The processor is bonded to the interposer. The memory device is bonded to the interposer and adjacent to the processor, wherein the processor and the memory device are connected to the control unit through the redistribution structure. In some embodiments, the packaging structure further includes an optical component bonded to the interposer and configured to be connected to the control unit and the arithmetic units through the signal transmission layer and the redistribution structure. In some embodiments, the control unit and the arithmetic unit further include a second signal transmission layer and a second optoelectronic material, formed in the control unit and the arithmetic unit, wherein the second optoelectronic material overlaps with the second signal transmission layer. In some embodiments, the sidewalls of the optoelectronic material are vertically aligned with the sidewalls of the signal transmission layer. According to some embodiments, a method of forming a packaging structure includes forming an interposer layer, which includes forming a plurality of through-silicon via (TSV) structures in a substrate, and forming a substrate material above the substrate. Forming the interposer layer includes forming a plurality of conductive features in the substrate material. The conductive features are electrically connected to the TSV structures. Forming the interposer layer includes forming a signal transmission layer in the substrate material. The signal transmission layer is isolated from the conductive features. Forming the interposer layer includes forming an optoelectronic material in the substrate material. The optoelectronic material overlaps with the signal transmission layer. The method includes bonding a control unit and a plurality of arithmetic units to the interposer layer. The arithmetic units are separated from the control unit, and the arithmetic units are connected to the control unit through the signal transmission layer. The method includes filling underfill in the gap between the control unit and the arithmetic units. In some embodiments, the method further includes bonding a signal source to the interposer layer, wherein the signal source is adjacent to the arithmetic unit and surrounded by the underfill. In some embodiments, the method further includes bonding an optical element to the interposer layer, wherein the optical element is adjacent to the signal source and laterally surrounded by the underfill. In some embodiments, forming the optoelectronic material in the interposer layer further includes forming an optoelectronic material in contact with the signal transmission layer. In some embodiments, bonding the control unit and the arithmetic units to the interposer layer further includes aligning the control unit and the arithmetic units with the regions in the interposer layer where the signal transmission layer and the optoelectronic material are located. The features of many embodiments are outlined above, enabling those of ordinary skill in the art to which the present disclosure pertains to better understand the various embodiments of the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purposes and / or reach the same advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present disclosure pertains should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure. Various changes, substitutions, and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims. 50: Substrate 51: Substrate via hole structure 52: Base material 53: Conductive feature 55: Conductive pad 57: Bump structure 100: Packaging structure 110: Interposer 115: Redistribution structure 120: Control unit 121: Integrated circuit 122: Interconnection structure 123: Dielectric layer 124: Semiconductor device 125: Conductive feature 130: Arithmetic unit 131: Integrated circuit 132: Interconnection structure 133: Dielectric layer 134: Semiconductor device 135: Conductive feature 140, 145: Signal transmission layer 150, 155: Optoelectronic material 160: Underfill 170: Signal source 180: Processor 185: Memory device 190: Optical element 200, 300, 400, 500, 600, 700, 800: Packaging structure The concepts of the embodiments of the present disclosure can be better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to the standard convention in this industry, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clear illustration. Similar features are denoted by similar reference numerals throughout the specification and the drawings. FIGS. 1A to 1D are cross-sectional views illustrating various stages of forming a packaging structure according to some embodiments of the present disclosure. FIG. 2 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 3 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. FIG. 4A is a cross-sectional view of a signal transmission layer and an optoelectronic material in an arithmetic unit according to some embodiments of the present disclosure. FIG. 4B is a top view of a signal transmission layer and an optoelectronic material in an arithmetic unit according to some embodiments of the present disclosure. FIG. 5 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. FIG. 6 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 7 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. FIG. 8 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 9 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. FIG. 10 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 11 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 12 is a top view of a packaging structure according to some embodiments of the present disclosure. FIG. 13 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. 51: Substrate via hole structure 52: Base material 57: Bump structure 100: Packaging structure 110: Interposer 115: Redistribution structure 120: Control unit 121: Integrated circuit 122: Interconnection structure 123: Dielectric layer 124: Semiconductor device 125: Conductive feature 130: Arithmetic unit 131: Integrated circuit 132: Interconnection structure 133: Dielectric layer 134: Semiconductor device 135: Conductive feature 140,145: Signal transmission layer 150: Optoelectronic material 160: Underfill 170: Signal source

Claims

1. A packaging structure, comprising: One intermediary layer; A control unit is attached to the intermediary layer; A plurality of computing units are configured to be connected to the control unit, wherein the control unit is located between at least two of the computing units; a signal transmission layer is located in the control unit and the computing units; and a photoelectric material is located in the control unit and the computing units, wherein the photoelectric material overlaps with the signal transmission layer and a width of the photoelectric material is greater than a width of the signal transmission layer.

2. The packaging structure as claimed in claim 1, wherein the computing units and the control unit are separated by a bottom filler, and the computing units are connected to the control unit through another signal transmission layer in the interposer layer.

3. As in the encapsulation structure of request item 1, it further includes: A signal source is coupled to the intermediary layer, wherein the signal source is connected to the control unit or the computing unit through the signal transmission layer.

4. As with the encapsulation structure of request item 1, it further includes: An optical element is disposed within the control unit and connected to the computing units through the signal transmission layer.

5. The packaging structure of claim 1, wherein the optoelectronic material includes aluminum nitride, hexagonal boron nitride, graphene, or a combination of the foregoing materials.

6. A packaging structure, comprising: One intermediary layer; A signal transmission layer is located within this intermediary layer; A photoelectric material is located in the interposer layer, wherein the photoelectric material overlaps with the signal transmission layer; a control unit is attached to the interposer layer; a plurality of computing units are attached to the interposer layer and connected to the control unit through the signal transmission layer, wherein the control unit is located between at least two of the computing units; and an additional signal transmission layer and an additional photoelectric material are located in the control unit and the computing units.

7. As in the encapsulation structure of request item 6, it further includes: A redistribution structure is formed in the intermediary layer, wherein the redistribution structure is isolated from the signal transmission layer.

8. The packaging structure of claim 6, wherein one sidewall of the optoelectronic material is perpendicularly aligned with one sidewall of the signal transmission layer.

9. A method for manufacturing a packaging structure, comprising: Forming an interposer layer includes: forming a plurality of substrate via structures in a substrate; forming a substrate above the substrate; forming a plurality of conductive features in the substrate, wherein the conductive features are electrically connected to the substrate via structures; forming a signal transmission layer in the substrate, wherein the signal transmission layer is isolated from the conductive features; and forming a photoelectric material in the substrate, wherein the photoelectric material overlaps with the signal transmission layer; bonding a control unit and a plurality of computing units to the interposer layer, wherein the computing units are separated from the control unit, the control unit is located between at least two of the computing units, and the computing units are connected to the control unit through the signal transmission layer, wherein an additional signal transmission layer and an additional photoelectric material are located in the control unit and the computing units; and filling a gap between the control unit and the computing units with a bottom filler.

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