Electronic device

Abstract

An electronic device is provided. The electronic device includes a substrate, a first insulating layer, a semiconductor oxide layer, a second insulating layer, and a gate electrode. The first insulating layer is disposed on the substrate. The semiconductor oxide layer is disposed on the first insulating layer and has a first portion and a second portion adjacent to the first portion. The second insulating layer is disposed on the semiconductor oxide layer. The gate electrode is disposed on the substrate and overlaps with the first portion of the semiconductor oxide layer. Wherein, in a spectrum measured by time-of-flight secondary ion mass spectrometry, H at the first interface between the second insulating layer and the first portion... - The concentration is greater than that of H in the central part of the first section. -concentration.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to an improved electronic device. Prior Art

[0002] Electronic products including chips, such as monitors, smartphones, tablets, laptops and TVs, have become indispensable necessities in modern society. With the booming development of such electronic products, consumers have high expectations for the quality, functions or prices of these electronic products.

[0003] Electronic products often include transistors to perform operations. However, since doping is required in the process of manufacturing transistors, it may cause unnecessary diffusion of dopants and reduce the stability of the transistor. Therefore, these electronic products do not meet the expectations of consumers in all aspects, and there are still some problems with electronic products. Developing improved electronic devices is still one of the current goals. Summary of the invention

[0004] In some embodiments, an electronic device is provided. The electronic device includes a substrate, a first insulating layer, a semiconductor oxide layer, a second insulating layer, and a gate electrode. The first insulating layer is disposed on the substrate. The semiconductor oxide layer is disposed on the first insulating layer and has a first portion and a second portion adjacent to the first portion. The second insulating layer is disposed on the semiconductor oxide layer. The gate electrode is disposed on the substrate and overlaps with the first portion of the semiconductor oxide layer. In a spectrum measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS), the H- concentration at the first interface between the second insulating layer and the first portion is greater than the H- concentration at the central portion of the first portion.

[0005] The electronic device disclosed herein can be applied to various types of electronic devices. To make the features and advantages of the present disclosure more obvious and easy to understand, various embodiments are specifically cited below, and detailed descriptions are given in conjunction with the accompanying drawings as follows. Simple diagram description

[0006] Through the following detailed description and the accompanying drawings, we can better understand the concept of the disclosed embodiments. It is worth noting that according to standard industry practices, some features may not be drawn to scale. In fact, the sizes of different features may be increased or reduced for clear discussion. FIG. 1 is a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG. 2 to FIG. 8 are schematic diagrams showing elemental analysis of electronic devices according to some embodiments of the present disclosure. Implementation

[0007] The following is a detailed description of the electronic devices of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not intended to limit the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements in order to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0008] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in various embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side. The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure.

[0009] Furthermore, when a first material layer is said to be located on or over a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0010] In addition, it should be understood that the ordinal numbers used in the specification and the patent application, such as "first", "second", etc., are used to modify the elements, and they are not intended to imply any previous ordinal numbers of the (or those) elements, nor do they represent the order of one element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make the element with a certain name clearly distinguishable from another element with the same name. The patent application and the specification may not use the same words, for example, the first element in the specification may be the second element in the patent application.

[0011] In some embodiments of the present disclosure, terms such as "connect", "interconnect", "bond", etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures disposed between the two structures. Such terms of connection and bonding may also include situations where both structures are movable, or where both structures are fixed. In addition, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0012] In the text, the terms "approximate", "about", "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of a specific description of "about", "approximately", "substantially", the meaning of "about", "approximately", "substantially" can still be implied. The term "within the range of a first value to a second value" or "first value~second value" means that the range includes the first value, the second value and other values between them. Furthermore, there may be a certain error between any two values or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0013] Certain words are used throughout the specification and claims of this disclosure to refer to specific components. It should be understood by those with ordinary knowledge in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, the words "comprise", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to...". Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of this disclosure, they specify the existence of corresponding parts, regions, steps, operations and / or elements, but do not exclude the existence of one or more corresponding parts, regions, steps, operations and / or elements.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those having ordinary knowledge in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0015] In the present disclosure, the directions are not limited to the three axes of the rectangular coordinate system such as the X-axis, the Y-axis and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following, the X-axis direction is the first direction D1, and the Z-axis direction is the second direction D2. In some embodiments, the cross-sectional schematic diagrams described herein are cross-sectional schematic diagrams for observing the XZ plane. In some embodiments, the normal direction of the substrate can be the second direction D2.

[0016] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the relative setting relationship, depth, thickness, width or height of each element, or the spacing or distance between elements. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the element to be measured, and measure the depth, thickness, width or height of each element, or the spacing or distance between elements.

[0017] It should be understood that according to some embodiments of the present disclosure, time of flight secondary ion mass spectrometer (TOF-SIMS) or other suitable mass spectrometry methods can be used to quantitatively analyze and / or qualitatively analyze the elements in each component. According to some embodiments, a sample including the component to be measured can be obtained from an electronic device, and the elements in the sample can be analyzed. In some embodiments, the sample can be analyzed using TOF-SIMS in negative ion mode, TOF-SIMS in positive ion mode, or a combination thereof. In some embodiments, the concentration of the sample that can be obtained depends on the accuracy of the analytical method used, and different analytical methods may have different minimum analyzable values. When the concentration of an element in the sample is less than the minimum analyzable value, only the presence of the element can be qualitatively analyzed, and the relative content relationship between the element and other elements can be described, but the concentration of the element cannot be quantitatively analyzed. In other words, the sample may substantially not include the element, that is, the concentration of the element is substantially equal to 0, or the sample may substantially include the element, that is, the concentration of the element is substantially greater than 0, but the concentration of the element is lower than the minimum analyzable value.

[0018] It should be understood that, hereinafter, the unit of concentration "atoms / cc" represents the number of atoms included in one cubic centimeter. hereinafter, when it is described that "the concentration of an element in a first element (or in a first portion, or at a first interface) is greater than the concentration of the element in a second element (or in a second portion, or at a second interface)", it means that the concentration of the element measured at an arbitrary point in the first element (or in a first portion, or at a first interface) is greater than the concentration of the element measured at an arbitrary point in the second element (or in a second portion, or at a second interface). For example, the concentration of the element at half the thickness of the first element is greater than the concentration of the element at half the thickness of the second element. For example, the maximum concentration of the element in the first element is greater than the maximum concentration of the element in the second element, but the present disclosure is not limited thereto. For example, the concentration of the element measured at the first point in the first element is greater than the concentration of the element measured at the second point in the second element, and the concentration of the element measured at the third point in the first element that is different from the first point may be less than or equal to the concentration of the element measured at the second point in the second element. In addition, when describing "the concentration of an element in the first element is greater than the concentration of the element in the second element", it includes the case where the second element does not substantially include the element, in other words, the concentration of the element in the first element is greater than the concentration of the element in the second element, and the concentration of the element in the second element is substantially zero.

[0019] In the present disclosure, the electronic device may include a display module, a backlight module, an antenna module, a sensing module or a splicing module, but not limited thereto. The electronic device may be a bendable or flexible electronic device. The display module may be a non-self-luminous display module or a self-luminous display module. The antenna module may be a liquid crystal antenna module or a non-liquid crystal antenna module, and the sensing module may be a sensing module for sensing capacitance, light, heat or ultrasound, but not limited thereto. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum dot LED), but not limited thereto. The splicing module may be, for example, a display splicing module or an antenna splicing module, but not limited thereto.

[0020] In addition, the appearance of the electronic device can be rectangular, circular, polygonal, with curved edges or other suitable shapes. The electronic device can have peripheral systems such as a processing system, a driving system, a control system, a light source system, a shelf system, etc. to support the display module or the splicing module.

[0021] It should be understood that for the sake of clarity, some elements of the electronic device may be omitted in the drawings, and only some elements are schematically depicted. In some embodiments, additional elements may be added to the electronic device described below. In other embodiments, some elements of the electronic device described below may be replaced or omitted.

[0022] Referring to FIG. 1 , a cross-sectional schematic diagram of an electronic device 1 according to some embodiments of the present disclosure is shown. In some embodiments, as shown in FIG. 1 , the electronic device 1 may include an active area AA and a peripheral area PA adjacent to the active area AA. In some embodiments, the active area AA may include a transistor TA, and the peripheral area PA may include a transistor TP. In some embodiments, the electronic device 1 may include a substrate 100, a first insulating layer 300, a semiconductor oxide layer 310, a second insulating layer 320, and a gate electrode 334. In some embodiments, the first insulating layer 300 may be disposed on the substrate 100, the semiconductor oxide layer 310 may be disposed on the first insulating layer 300, and the second insulating layer 320 may be disposed on the semiconductor oxide layer 310. In some embodiments, the gate electrode 334 may be disposed on the substrate 100. In some embodiments, the gate electrode 334 may be disposed on the second insulating layer 320 so that the electronic device 1 includes a top gate transistor TA. In some other embodiments, the gate electrode 334 may be disposed between the substrate 100 and the first insulating layer 300 , so that the electronic device 1 includes a bottom gate transistor TA.

[0023] Hereinafter, the electronic device 1 is described in detail.

[0024] In some embodiments, as shown in FIG. 1 , a substrate 100 is provided. In some embodiments, the substrate 100 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may include a light-transmitting substrate, a semi-transmitting substrate or an opaque substrate.

[0025] In some embodiments, as shown in FIG. 1 , a first conductive layer 110 and a first conductive layer 112 may be formed on a substrate 100. In some embodiments, the first conductive layer 110 may be disposed in the peripheral area PA, and the first conductive layer 112 may be disposed in the peripheral area PA and the active area AA. In some embodiments, the first conductive layer 110 and the first conductive layer 112 may be formed in the same process or in different processes. In some embodiments, the first conductive layer 110 and the first conductive layer 112 may be a zero metal layer (M0 layer).

[0026] In some embodiments, the first conductive layer 110 and the first conductive layer 112 may include a conductive material. In some embodiments, the conductive material may include a metal, a metal nitride, a semiconductor material, other suitable conductive materials or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include Au, nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys thereof, compounds thereof or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the conductive material may include a transparent conductive oxide (TCO). For example, the transparent conductive oxide may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials or combinations thereof, but the present disclosure is not limited thereto.

[0027] In some embodiments, the first conductive layer 110 and the first conductive layer 112 may be formed by a deposition process, an etching process, a patterning process, other suitable processes or combinations thereof. For example, the deposition process may include a chemical vapor deposition (CVD) process, a sputtering process, an evaporation process, a physical vapor deposition (PVD) process, other suitable deposition processes or combinations thereof, but the present disclosure is not limited thereto. For example, the etching process may include dry etching, a wet etching process, other suitable etching processes or combinations thereof, but the present disclosure is not limited thereto.

[0028] In some embodiments, as shown in FIG. 1 , a dielectric layer 120 may be formed on the substrate 100, the first conductive layer 110, and the first conductive layer 112. In some embodiments, the dielectric layer 120 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, other suitable buffer materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the dielectric layer 120 may be formed by the aforementioned deposition process or other suitable processes. For example, the dielectric layer 120 may include silicon nitride. In some embodiments, as shown in FIG. 1 , a dielectric layer 140 may be formed on the dielectric layer 120. In some embodiments, the material and the formation method of the dielectric layer 140 may be the same as or different from the material and the formation method of the dielectric layer 120. For example, the dielectric layer 140 may include silicon oxide.

[0029] In some embodiments, as shown in FIG. 1 , a semiconductor layer 150 may be formed on the dielectric layer 140 and in the peripheral area PA. In some embodiments, the semiconductor layer 150 may include amorphous silicon (a-Si), low temperature polysilicon (LTPS), indium gallium zinc oxide (IGZO), metal oxide, other suitable semiconductor materials or combinations thereof, but the present disclosure is not limited thereto. For example, the semiconductor layer 150 may include low temperature polysilicon (LTPS). In some embodiments, as shown in FIG. 1 , a dielectric layer 160 may be formed on the dielectric layer 140 and the semiconductor layer 150. In some embodiments, the material and formation method of the dielectric layer 160 may be the same as or different from the material and formation method of the dielectric layer 120. For example, the dielectric layer 160 may include silicon oxide.

[0030] In some embodiments, as shown in FIG. 1 , a third insulating layer 200 may be formed on the dielectric layer 160. In some embodiments, the material and the forming method of the third insulating layer 200 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the third insulating layer 200 may include silicon nitride. In some embodiments, the third insulating layer 200 may serve as a barrier layer for water vapor.

[0031] In some embodiments, as shown in FIG. 1 , a first insulating layer 300 may be formed on the third insulating layer 200. In some embodiments, the material and the forming method of the first insulating layer 300 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the first insulating layer 300 may include silicon oxide. In some embodiments, the first insulating layer 300 may serve as a bottom insulating layer of the transistor TA in the active region AA. In some embodiments, in the normal direction of the substrate 100, the first insulating layer 300 may have a first thickness T300. In some embodiments, the first thickness T300 may be greater than or equal to 1000 angstroms (Å) and less than or equal to 3000 angstroms (Å). For example, the first thickness T300 may be 1000Å, 1200Å, 1400Å, 1500Å, 1600Å, 1800Å, 2000Å, 3000Å, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto.

[0032] In some embodiments, as shown in FIG. 1 , a semiconductor oxide layer 310 may be formed on the first insulating layer 300. In some embodiments, the semiconductor oxide layer 310 may include ITO, IGO, AZO, SnO, ZnO, IZO, IGZO, ITZO, ATO, other suitable semiconductor oxide materials or combinations thereof, but the present disclosure is not limited thereto. For example, the semiconductor oxide layer 310 may include IGZO.

[0033] In some embodiments, as shown in FIG. 1 , the semiconductor oxide layer 310 may have a first portion 310a and a second portion 310b adjacent to the first portion 310a. In some embodiments, along the first direction D1, the first portion 310a may be disposed between the second portions 310b. In some embodiments, along the normal direction (second direction D2) of the substrate 100, the first portion 310a of the semiconductor oxide layer 310 may correspond to a gate electrode to be formed subsequently. In some embodiments, the projection range of the gate electrode to be formed subsequently on the semiconductor oxide layer 310 is the range of the first portion 310a. In other words, a portion of the semiconductor oxide layer 310 on which the gate electrode is disposed may be referred to as the first portion 310a, and the remaining portion of the semiconductor oxide layer 310 on which the gate electrode is not disposed may be referred to as the second portion 310b. In some embodiments, the first portion 310a of the semiconductor oxide layer 310 may serve as a channel region of the transistor TA in the active region AA, and the second portion 310b of the semiconductor oxide layer 310 may serve as a conductive region of the transistor TA. In some embodiments, the second portion 310b may be a doped region, such as an N-type heavily doped region (N+ region) doped with N-type dopants, so that the semiconductor oxide layer 310 is electrically connected to other elements, but the present disclosure is not limited thereto.

[0034] In some embodiments, as shown in FIG. 1 , a second insulating layer 320 may be formed on the first insulating layer 300 and the semiconductor oxide layer 310. In some embodiments, the material and the forming method of the second insulating layer 320 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the second insulating layer 320 may include silicon oxide. In some embodiments, the second insulating layer 320 may serve as a gate insulating layer. In some embodiments, the second insulating layer 320 may have a second thickness T320 in the normal direction of the substrate 100. In some embodiments, the second thickness T320 may be greater than or equal to 300 angstroms (Å) and less than or equal to 1500 angstroms (Å). For example, the second thickness T320 may be 300Å, 400Å, 500Å, 600Å, 700Å, 800Å, 1000Å, 1500Å, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto.

[0035] In some embodiments, the second thickness T320 of the second insulating layer 320 may be less than the first thickness T300 of the first insulating layer 300. In some embodiments, the ratio of the second thickness T320 to the first thickness T300 (second thickness T320 / first thickness T300) may be greater than or equal to 0.3 and less than or equal to 0.7. For example, the ratio of the second thickness T320 to the first thickness T300 may be 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto. For example, the ratio of the second thickness T320 to the first thickness T300 may be in the range of 0.3 to 0.7, in the range of 0.3 to 0.6, in the range of 0.4 to 0.5, or a numerical range consisting of any values between the aforementioned values, but the present disclosure is not limited thereto.

[0036] In some embodiments, as shown in FIG. 1 , a second conductive layer 330, a second conductive layer 332, and a gate electrode 334 may be formed on the second insulating layer 320. In some embodiments, the second conductive layer 330 and the second conductive layer 332 may be disposed in the peripheral area PA, and the gate electrode 334 may be disposed in the active area AA. In some embodiments, in the normal direction of the substrate 100, the gate electrode 334 may overlap with the first portion 310a of the semiconductor oxide layer 310, and the gate electrode 334 does not overlap with the second portion 310b of the semiconductor oxide layer 310. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may include the aforementioned conductive material. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may be formed in the same process or in different processes. In some embodiments, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334 may be a first metal layer (M1 layer). In some embodiments, the second conductive layer 330 can be used as a source electrode of the transistor TP in the peripheral area PA, and the second conductive layer 332 can be used as a drain electrode of the transistor TP in the peripheral area PA. In some embodiments, the gate electrode 334 can be a gate electrode of the transistor TA in the active area AA.

[0037] In some embodiments, as shown in FIG. 1 , a dielectric layer 340 may be formed on the second insulating layer 320, the second conductive layer 330, the second conductive layer 332, and the gate electrode 334. In some embodiments, the material and the forming method of the dielectric layer 340 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the dielectric layer 340 may include silicon oxide. In some embodiments, as shown in FIG. 1 , a fourth insulating layer 400 may be formed on the dielectric layer 340. In some embodiments, the material and the forming method of the fourth insulating layer 400 may be the same as or different from the material and the forming method of the third insulating layer 200. For example, the fourth insulating layer 400 may include silicon nitride. In some embodiments, the fourth insulating layer 400 may serve as a barrier layer for water vapor.

[0038] In some embodiments, as shown in FIG. 1 , a dielectric layer 420 may be formed on the fourth insulating layer 400. In some embodiments, the material and the forming method of the dielectric layer 420 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the dielectric layer 420 may include silicon oxide. In some embodiments, as shown in FIG. 1 , a third conductive layer 430 may be formed on the dielectric layer 420. In some embodiments, the material and the forming method of the third conductive layer 430 may be the same as or different from the material and the forming method of the first conductive layer 110. In some embodiments, the third conductive layer 430 may serve as a source electrode of the transistor TA in the active region AA. In some embodiments, as shown in FIG. 1 , a dielectric layer 440 may be formed on the dielectric layer 420 and the third conductive layer 430. In some embodiments, the material and the forming method of the dielectric layer 440 may be the same as or different from the material and the forming method of the dielectric layer 120. For example, the dielectric layer 440 may include silicon oxide. In some embodiments, as shown in FIG. 1 , a third conductive layer 450 may be formed on the dielectric layer 440. In some embodiments, the material and formation method of the third conductive layer 450 may be the same as or different from the material and formation method of the first conductive layer 110. For example, the third conductive layer 450 may include ITO. In other embodiments, the third conductive layer 450 may be disposed on the same layer as the third conductive layer 430. For example, the third conductive layer 450 and the third conductive layer 430 may be disposed on the dielectric layer 420. In some embodiments, the third conductive layer 450 may serve as a drain electrode of the transistor TA in the active area AA. In some embodiments, the third conductive layer 430 and the third conductive layer 450 may be a second metal layer (M2 layer).

[0039] In some embodiments, the oxygen (O) concentration in the aforementioned layer including silicon oxide (e.g., the first insulating layer 300, the second insulating layer 320) may be 6E+21~9E+21 atoms / cm3 (atoms / cc). For example, the oxygen (O) concentration in the layer including silicon oxide may be 6E+21, 7E+21, 8E+21, 9E+21, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto. In some embodiments, the O concentration in the aforementioned layer including silicon nitride (e.g., the third insulating layer 300, the fourth insulating layer 400) may be 6E+20~8E+20 atoms / cm3 (atoms / cc). For example, the oxygen (O) concentration in the layer including silicon nitride may be 6E+20, 7E+20, 8E+20, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto. In some embodiments, the ratio of the O concentration in the silicon oxide layer to the O concentration in the silicon nitride layer (O concentration in the silicon oxide layer / O concentration in the silicon nitride layer) may be 7 to 15. For example, the ratio of the O concentration in the silicon oxide layer to the O concentration in the silicon nitride layer may be 7, 8, 9, 10, 11, 12, 13, 14, 15, or any value between the aforementioned values or a numerical range consisting of any values, but the present disclosure is not limited thereto. Accordingly, since water vapor is not easy to diffuse from the low O concentration layer to the high O concentration layer, the third insulating layer 200 and the fourth insulating layer 400 can serve as a barrier layer for water vapor to protect the semiconductor oxide layer 310 disposed between the third insulating layer 200 and the fourth insulating layer 400 from being damaged by water vapor. Furthermore, since the density of the silicon nitride layer is higher than that of the silicon oxide layer, the third insulating layer 200 and the fourth insulating layer 400 can physically isolate moisture to protect the semiconductor oxide layer 310 from being damaged by moisture.

[0040] In the following, the electronic device 1 is used as an example to illustrate the results of elemental analysis, but the present disclosure is not limited thereto. For ease of explanation, different elements are marked in the subsequent Figures 2 to 8, but the subsequent Figures 2 to 8 substantially represent the same analysis results.

[0041] Referring to FIG. 2 to FIG. 8, they respectively show schematic diagrams of elemental analysis of the electronic device 1 according to some embodiments of the present disclosure. Wherein, FIG. 2 to FIG. 8 respectively show schematic diagrams of elemental analysis of TOF-SIMS analysis in negative ion mode along the cross section I-I' of the electronic device 1 shown in FIG. 1. Wherein, the minimum analyzable value of the concentration analyzed by TOF-SIMS in negative ion mode is in the range of 1.0E+19 atoms / cc to 1.0E+20 atoms / cc. Wherein, the concentration of hydrogen (H -) ions refers to the vertical axis coordinate on the left (concentration (atoms / cc)), and its concentration is the concentration after quantitative analysis. The contents of O -, Si -, SiN -, ZnO -, GaO - and InO - refer to the vertical axis coordinate on the right (intensity (counts)), and the intensity is the count after quantitative analysis. Wherein, the horizontal axis coordinate represents the depth (um) along the direction opposite to the second direction D2. For example, the horizontal axis represents the direction from the gate electrode 334 toward the third insulating layer 200. In some embodiments, the concentration of hydrogen (H -) ions analyzed by TOF-SIMS in negative ion mode is equivalent to the concentration of hydrogen.

[0042] In some embodiments, as shown in FIG. 1 and FIG. 2, in the spectrum measured by TOF-SIMS, the H- concentration at the first interface S1 between the second insulating layer 320 and the first portion 310a of the semiconductor oxide layer 310 is greater than the H- concentration at the central portion 312 of the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the central portion 312 of the first portion 310a is defined as a position corresponding to the peak of the intensity of InO- shown in FIG. 2. That is, the central portion 312 of the first portion 310a may correspond to the maximum value of the intensity of InO-. In some embodiments, the first interface S1 may be defined as a position corresponding to 80% of the peak of the intensity of InO- shown in FIG. 2 and having a depth less than the central portion 312. That is, the first interface S1 may correspond to 80% of the maximum value of the intensity of InO-, and the first interface S1 is farther away from the substrate than the central portion 312, but the present disclosure is not limited thereto.

[0043] In some embodiments, as shown in FIG. 1 and FIG. 3, in the spectrum measured by TOF-SIMS, the H- concentration at the second interface S2 between the first insulating layer 300 and the first portion 310a of the semiconductor oxide layer 310 is greater than the H- concentration at the central portion 312 of the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the second interface S2 may be defined as a position corresponding to 80% of the peak value of the intensity of InO- as shown in FIG. 3 and having a depth greater than the central portion 312. For example, the second interface S2 may correspond to 80% of the maximum value of the intensity of InO-, and the second interface S2 is closer to the substrate than the central portion 312, but the present disclosure is not limited thereto.

[0044] In some embodiments, as shown in FIG. 1 and FIG. 4 , in the spectrum measured by TOF-SIMS, the H-concentration at the first interface S1 is less than the H-concentration at the second interface S2. Accordingly, since the channel region of the transistor TA in the active area AA is formed on the first interface S1, when the H-concentration at the first interface S1 is low, the threshold voltage (Vth) of the transistor TA can be prevented from shifting to a negative voltage.

[0045] In some embodiments, as shown in FIG. 1 and FIG. 5, in some embodiments, the first insulating layer 300 is divided into an upper portion 300T and a lower portion 300B by a first thickness T300 of the first insulating layer 300 in the second direction D2, and the H-concentration of the upper portion 300T may be less than the H-concentration of the lower portion 300B. In some embodiments, in the spectrum measured by TOF-SIMS, the H-concentration at the bottom surface of the first insulating layer 300 is greater than the H-concentration at the second interface S2 between the first insulating layer 300 and the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the bottom surface of the first insulating layer 300 is defined as the position of the maximum slope of the H-concentration relative to the depth in the lower portion 300B of the first insulating layer 300. That is, the bottom surface of the first insulating layer 300 is the position of the maximum slope in the lower portion 300B of the first insulating layer 300 in the H-concentration curve.

[0046] In detail, since the semiconductor oxide layer 310 is easily affected by the H-concentration in the adjacent element, it is necessary to adjust the H-concentration in the elements adjacent to the semiconductor oxide layer 310. When the H-concentration in the adjacent element is too high and diffuses into the semiconductor oxide layer 310, the conductivity of the first portion 310a of the semiconductor oxide layer 310 will be too high, thereby causing the first portion 310a of the semiconductor oxide layer 310 to generate unnecessary conduction, thereby degrading the transistor TA in the active area AA. Once the first portion 310a of the semiconductor oxide layer 310 as the channel region generates unnecessary conduction, the switching of the transistor TA cannot be controlled by the gate electrode 334. Therefore, the present disclosure improves the electrical performance and / or stability of the transistor by controlling the H-concentration in each element. For example, after performing a reliability test under high temperature and high humidity conditions, unnecessary conduction still does not occur. Accordingly, the present disclosure prevents H − in the upper portion 300T of the first insulating layer 300 near the semiconductor oxide layer 310 from diffusing into the semiconductor oxide layer 310 by adjusting the H − concentration in the first insulating layer 300 .

[0047] Furthermore, since H - in the lower portion 300B of the first insulating layer 300 far from the semiconductor oxide layer 310 is not likely to affect the semiconductor oxide layer 310, the speed of initially forming the first insulating layer 300 can be increased, thereby reducing the process time. For example, when initially forming the first insulating layer 300, N 2 can be used to catalyze the reaction of SiH 4 and N 2O to increase the speed of forming the first insulating layer 300. Then, when the first insulating layer 300 is not yet completed, N 2 is removed (without using N 2 catalysis), and SiH 4 and N 2O react to reduce the H - concentration in the upper portion 300T of the first insulating layer 300 adjacent to the semiconductor oxide layer 310.

[0048] In some embodiments, as shown in FIG. 1 and FIG. 6, in some embodiments, the second insulating layer 320 is divided into an upper portion 320T and a lower portion 320B by a second thickness T320 of the second insulating layer 320 in the second direction D2, and the H-concentration of the upper portion 320T may be greater than the H-concentration of the lower portion 320B. In the spectrum measured by TOF-SIMS, the H-concentration at the top surface of the second insulating layer 320 is greater than the H-concentration at the first interface S1 between the second insulating layer 320 and the first portion 310a of the semiconductor oxide layer 310. In some embodiments, the top surface of the second insulating layer 320 is defined as the position of the maximum slope of the H-concentration relative to the depth in the upper portion 320T of the second insulating layer 320. That is, the top surface of the second insulating layer 320 is the position of the maximum slope in the upper portion 320T of the second insulating layer 320 in the H-concentration curve. Accordingly, the present disclosure prevents H − in the lower portion 320B of the second insulating layer 320 near the semiconductor oxide layer 310 from diffusing into the semiconductor oxide layer 310 by adjusting the H − concentration in the second insulating layer 320 .

[0049] Furthermore, since the H concentration of the upper portion 320T of the second insulating layer 320 can be greater than the H concentration of the lower portion 320B of the second insulating layer 320, the second insulating layer 320 can effectively passivate the dangling bonds at the first interface S1 between the semiconductor oxide layer 310 and the second insulating layer 320, thereby avoiding defects in the semiconductor oxide layer 310, thereby improving the electrical performance and / or stability of the transistor TA.

[0050] In some embodiments, as shown in FIG. 1 and FIG. 7 , the slope of the H -concentration in the first insulating layer 300 may be smaller than the slope of the H -concentration in the second insulating layer 320. In some embodiments, in the spectrum measured by TOF-SIMS, the first difference DIF1 between the H -concentration at the first interface S1 and the H -concentration at the first position P1 600Å above the first interface S1 may be greater than the second difference DIF2 between the H -concentration at the second interface S2 and the H -concentration at the second position P2 600Å below the second interface S2. Since the H - in the first insulating layer 300 does not need to be used to passivate the dangling bonds at the second interface S2, the first difference DIF1 may be greater than the second difference DIF2. Accordingly, the H - in the first insulating layer 300 and the second insulating layer 320 near the semiconductor oxide layer 310 is prevented from diffusing into the semiconductor oxide layer 310, and the dangling bonds are effectively passivated.

[0051] In some embodiments, as shown in FIG. 1 and FIG. 8 , in the spectrum measured by TOF-SIMS, the first insulating layer 300 has an upper portion 300T and a lower portion 300B, and the intensity of SiN - at the lower portion 300B is greater than the intensity of SiN - at the upper portion 300T. In some embodiments, the two interfaces defined by the aforementioned bottom surface of the first insulating layer 300 and the second interface S2 are used as the upper interface and the lower interface of the first insulating layer 300, and the first insulating layer 300 is divided into the upper portion 300T and the lower portion 300B by the first thickness T300 of the first insulating layer 300 in the second direction D2. In some embodiments, the SiN - at the lower portion 300B may come from the SiN - bond generated by using N 2 catalysis when the first insulating layer 300 is initially formed. Accordingly, the speed of forming the first insulating layer 300 can be increased.

[0052] In some embodiments, as shown in FIG. 1 and FIG. 8, in some embodiments, in the spectrum measured by TOF-SIMS, the gate electrode 334 may have an upper portion 334T, a lower portion 334B, and a middle portion 334C disposed between the upper portion 334T and the lower portion 334B. In some embodiments, the gate electrode 334 is divided into an upper portion 334T, a middle portion 334C, and a lower portion 334B by the thickness of the gate electrode 334 in the second direction D2. In some embodiments, the H-concentration at the lower portion 334B is greater than the H-concentration at the middle portion 334C. In some embodiments, the H-concentration at the upper portion 334T is greater than the H-concentration at the middle portion 334C. In some embodiments, the H-concentration at the lower portion 334B is greater than the H-concentration at the upper portion 334T.

[0053] In summary, according to some embodiments of the present disclosure, an electronic device is provided. The electronic device can improve the electrical performance and / or stability of the electronic device by adjusting the parameters (e.g., material type, H-concentration, SiN-concentration) of the components (e.g., the first insulating layer, the second insulating layer, the gate electrode, the third insulating layer, the fourth insulating layer) adjacent to the semiconductor oxide layer. For example, the first insulating layer and the second insulating layer of the present disclosure can prevent the semiconductor oxide layer in the transistor from degrading and / or prevent the threshold voltage from shifting to a negative voltage. For example, the third insulating layer and the fourth insulating layer of the present disclosure can prevent moisture from causing the semiconductor oxide layer to degrade.

[0054] The features of the embodiments of the present disclosure may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand from the content of the present disclosure that the processes, machines, manufacturing, material compositions, devices, methods and steps currently or developed in the future can be used according to the present disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope defined by the scope of the patent application. Any embodiment or claim of the present disclosure is not required to achieve all the purposes, advantages and / or features disclosed in the present disclosure.

[0055] Several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the concepts of the embodiments of the present disclosure. Those with ordinary knowledge in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

[0056] 1: Electronic devices 100:Substrate 110, 112: first conductive layer 120, 140, 160, 340, 420, 440: Dielectric layer 150: Semiconductor layer 200: The third insulation layer 300: first insulating layer 300B, 320B, 334B: Lower 300T, 320T, 334T: Upper 310: Semiconductor oxide layer 310a: Part I 310b: Part 2 312: Center 320: Second insulation layer 330, 332: second conductive layer 334: Gate electrode 334C: Middle 400: Fourth insulation layer 430, 450: third conductive layer AA: Active Area D1: First direction D2: Second direction DIF1: First difference DIF2: Second difference I-I': Section P1: First position P2: Second position PA: Surrounding area S1: First interface S2: Second interface T300: First thickness T320: Second thickness TA, TP: Transistor

Claims

1. An electronic device comprising: One substrate; A first insulating layer is disposed on the substrate; A semiconductor oxide layer is disposed on the first insulating layer and has a first portion and a second portion adjacent to the first portion; a second insulating layer is disposed on the semiconductor oxide layer; and a gate electrode is disposed on the substrate and overlaps with the first portion of the semiconductor oxide layer, wherein, in a spectrum measured by time-of-flight secondary ion mass spectrometry (TOF-SIMS), the H- concentration at a first interface between the second insulating layer and the first portion is greater than the H- concentration at a central portion of the first portion.

2. The electronic device as claimed in claim 1, wherein, In the spectrum measured by TOF-SIMS, the H- concentration at a second interface between the first insulating layer and the first portion is greater than the H- concentration at the central portion of the first portion.

3. The electronic device as claimed in claim 2, wherein, In the spectrum measured by TOF-SIMS, the H- concentration at the first interface is less than the H- concentration at the second interface.

4. The electronic device as claimed in claim 2, wherein, In the spectrum measured by TOF-SIMS, the H- concentration at a bottom surface of the first insulating layer is greater than the H- concentration at the second interface between the first insulating layer and the first portion.

5. The electronic device as claimed in claim 4, wherein, In the spectrum measured by TOF-SIMS, the H- concentration at one top surface of the second insulating layer is greater than the H- concentration at the first interface between the second insulating layer and the first portion.

6. The electronic device as claimed in claim 2, wherein, In the spectrum measured by TOF-SIMS, the difference between the H- concentration at the first interface and the H- concentration at a first location 600 Å above the first interface is greater than the difference between the H- concentration at the second interface and the H- concentration at a second location 600 Å below the second interface.

7. The electronic device as claimed in claim 2, wherein, In the spectrum measured by TOF-SIMS, the first insulating layer has an upper part and a lower part, and the intensity of SiN- at the lower part is greater than the intensity of SiN- at the upper part.

8. The electronic device of claim 1 further includes a third insulating layer disposed below the first insulating layer, wherein the first insulating layer comprises silicon oxide and the third insulating layer comprises silicon nitride.

9. The electronic device of claim 1 further includes a fourth insulating layer disposed on the second insulating layer, wherein the second insulating layer comprises silicon oxide and the fourth insulating layer comprises silicon nitride.

10. The electronic device of claim 1, wherein the first insulating layer has a first thickness, the second insulating layer has a second thickness, and the second thickness is less than the first thickness.

11. The electronic device as claimed in claim 10, wherein a ratio of the second thickness to the first thickness is in the range of 0.3 to 0.

7.

12. The electronic device as claimed in claim 11, wherein, The ratio is in the range of 0.3 to 0.

6.

13. The electronic device as claimed in claim 12, wherein, The ratio is in the range of 0.4 to 0.

5.

14. The electronic device as claimed in claim 1, wherein, In the spectrum measured by TOF-SIMS, the gate electrode has an upper part, a lower part and an intermediate part disposed between the upper part and the lower part, and the H- concentration at the lower part is greater than the H- concentration at the intermediate part.

15. The electronic device as claimed in claim 14, wherein, In the spectrum measured by TOF-SIMS, the H- concentration in the upper part is greater than the H- concentration in the middle part.

16. The electronic device as claimed in claim 15, wherein, In the spectrum measured by TOF-SIMS, the H- concentration at the lower part is greater than the H- concentration at the upper part.

17. The electronic device as claimed in claim 1, wherein the gate electrode is disposed on the second insulating layer.

18. The electronic device of claim 1, wherein the gate electrode is disposed between the substrate and the first insulating layer.

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