Semiconductor devices and manufacturing methods thereof

Abstract

The objective of this invention is to provide a semiconductor device with less non-uniformity and stable electrical characteristics. The semiconductor device of this invention includes a gate electrode, a gate insulating layer above the gate electrode, a polycrystalline oxide semiconductor layer above the gate insulating layer, a source electrode and a drain electrode above the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode, and a second region in contact with the interlayer insulating layer. The difference in film thickness between the first region and the second region is 5 nm or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel. Furthermore, one embodiment of the present invention relates to a method for manufacturing a semiconductor device. Prior Technology

[0002] In recent years, semiconductor devices using oxide semiconductor films as channels, replacing silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and monocrystalline silicon, have been developed (see, for example, Patent Documents 1-6). Semiconductor devices incorporating oxide semiconductor films, like those incorporating amorphous silicon films, can be simply constructed and formed using low-temperature processes. It is known that semiconductor devices incorporating oxide semiconductor films have higher field-effect mobility than those incorporating amorphous silicon films. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2021-141338 [Patent Document 2] Japanese Patent Application Publication No. 2014-099601 [Patent Document 3] Japanese Patent Application Publication No. 2021-153196 [Patent Document 4] Japanese Patent Application Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Publication No. 2016-184771 [Patent Document 6] Japanese Patent Application Publication No. 2021-108405 Summary of the Invention

[0004] [The problem the invention aims to solve]

[0005] However, in previous semiconductor devices containing oxide semiconductor films, the oxide semiconductor films had relatively low etch resistance and it was difficult to control their shape. In particular, in semiconductor devices manufactured using large-area substrates, the inhomogeneity of the oxide semiconductor film shape caused uneven electrical characteristics of the semiconductor device, leading to a decrease in yield.

[0006] One embodiment of the present invention provides a semiconductor device with less non-uniformity and stable electrical characteristics. Furthermore, one objective of another embodiment of the present invention is to provide a method for manufacturing a semiconductor device with reduced non-uniformity and improved yield. [Technical means to solve the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes a gate electrode, a gate insulating layer above the gate electrode, an oxide semiconductor layer having a polycrystalline structure above the gate insulating layer, a source electrode and a drain electrode above the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode, and a second region in contact with the interlayer insulating layer. The difference in film thickness between the first region and the second region is less than 5 nm.

[0008] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes the following steps: forming a gate electrode; forming a gate insulating layer on the gate electrode; forming an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; forming a conductive film on the oxide semiconductor layer; patterning the conductive film by etching to form a source electrode and a drain electrode; and forming an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer; the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode, and a second region in contact with the interlayer insulating layer, wherein the difference in film thickness between the first region and the second region is less than 5 nm. Simple Explanation of the Diagram

[0009] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. Figure 2 is a schematic top view showing the configuration of a semiconductor device according to one embodiment of the present invention. Figure 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 4 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 5 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 6 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 8 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 11 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 12 is a schematic top view showing an outline of a display device according to one embodiment of the present invention. Figure 13 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. Figure 14 is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. Figure 15 is a schematic cross-sectional view showing the configuration of a display device according to one embodiment of the present invention. Figure 16 is a circuit diagram showing the pixel circuit of a display device according to one embodiment of the present invention. Figure 17 is a schematic cross-sectional view showing the configuration of a display device according to one embodiment of the present invention. Figure 18 shows the electrical characteristics (Id-Vg characteristics) of samples A to C in Example 2. Implementation

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be readily conceived by the art by appropriately changing the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. For clarity, the width, film thickness, shape, etc. of each part are sometimes shown in a patterned manner in the drawings compared to the actual form. However, the shapes shown are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, the same symbols are sometimes used for components that are the same as those described above with respect to the figures shown, and detailed descriptions are appropriately omitted.

[0011] In this specification and other materials, "semiconductor device" refers to any device that can function by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are included in one form of semiconductor device. The semiconductor device in the embodiments shown below may be, for example, a transistor used in integrated circuits (ICs) such as display devices, microprocessors (MPUs), or memory circuits.

[0012] In this specification and other materials, "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes it refers to a structure obtained by mounting other optical components (such as polarizing components, backlight devices, touch panels, etc.) onto a display unit. Unless there is a technical inconsistency, "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, in the embodiments, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are described as examples of display devices. However, the structure described in the embodiments can be applied to display devices that include the other electro-optical layers mentioned above.

[0013] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for ease of explanation, the terms "up" or "below" are used, but the vertical relationship between the substrate and the oxide semiconductor layer can be configured with orientations different from those shown in the illustrations. Furthermore, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer; other components may also be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure with multiple layers. When expressed as a pixel electrode above a semiconductor device, the semiconductor device and the pixel electrode may be in a non-overlapping position when viewed from above. On the other hand, when expressed as a pixel electrode vertically above a semiconductor device, it refers to the overlapping position of the semiconductor device and the pixel electrode when viewed from above. Furthermore, "viewing from above" refers to observation from a direction perpendicular to the substrate surface.

[0014] In this specification and other materials, the terms "membrane" and "layer" may be used interchangeably as appropriate.

[0015] In this specification and other documents, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", or "α includes one of the groups selected from A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C unless explicitly stated otherwise. Furthermore, these expressions do not exclude the possibility that α includes other constituent elements.

[0016] Furthermore, the following implementation methods can be combined with each other unless they create technical contradictions.

[0017] <First Implementation> Referring to Figures 1 to 11, a semiconductor device 10 according to one embodiment of the present invention will be described.

[0018] [Composition of Semiconductor Device 10] Referring to Figures 1 and 2, the configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 1 is a cross-sectional view showing a schematic configuration of the semiconductor device 10 according to one embodiment of the present invention. Figure 2 is a schematic top view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. The cross-sectional view shown in Figure 1 corresponds to the cross-section when cut along line A1-A2 shown in Figure 2.

[0019] As shown in Figure 1, a semiconductor device 10 is disposed on a substrate 11. The semiconductor device 10 includes a gate electrode 12GE, gate insulating layers 14 and 16, an oxide semiconductor layer 26, a source electrode 32S, a drain electrode 32D, and interlayer insulating layers 34 and 38. When not specifically distinguishing between the source electrode 32S and the drain electrode 32D, they are sometimes collectively referred to as the source electrode and drain electrode 32. Furthermore, the gate electrode 12GE, gate insulating layers 14 and 16, and oxide semiconductor layer 26 are sometimes referred to as transistors. The semiconductor device 10 is a so-called bottom-gate transistor with the gate electrode 12GE disposed below the oxide semiconductor layer 26.

[0020] In this embodiment, a bottom-gate transistor is exemplified as the semiconductor device 10, but the semiconductor device 10 is not limited to a bottom-gate transistor. For example, the semiconductor device 10 may also be a dual-gate transistor with gate electrodes disposed above and below the oxide semiconductor layer 26.

[0021] A gate electrode 12GE is disposed on a substrate 11. Gate insulating layers 14 and 16 are disposed on the substrate 11 and the gate electrode 12GE. Gate insulating layers 14 and 16 have a stacked structure, with gate insulating layer 16 disposed on top of gate insulating layer 14. An oxide semiconductor layer 26 is disposed on gate insulating layers 14 and 16. A source electrode 32S and a drain electrode 32D are disposed on oxide semiconductor layer 26. Interlayer insulating layers 34 and 38 are disposed on oxide semiconductor layer 26, and on source electrode 32S and drain electrode 32D. Interlayer insulating layers 34 and 38 have a stacked structure, with interlayer insulating layer 38 disposed on top of interlayer insulating layer 34. That is, interlayer insulating layers 34 and 38 cover source electrode 32S and drain electrode 32D, and interlayer insulating layer 34 is connected to oxide semiconductor layer 26.

[0022] As shown in Figure 2, from a top view, the oxide semiconductor layer 26 overlaps with the gate electrode 12GE. The D1 direction connects the source electrode 32S and the drain electrode 32D, and the D2 direction is orthogonal to the D1 direction. In the semiconductor device 10, the channel length L corresponds to the length of the region (channel region) of the oxide semiconductor layer 26 between the source electrode 32S and the drain electrode 32D in the D1 direction, and the channel width W corresponds to the width of the channel region in the D2 direction. From a top view, the region of the oxide semiconductor layer 26 overlapping with the source electrode 32S is the source region, and the region of the oxide semiconductor layer 26 overlapping with the drain electrode 32D is the drain region. That is, the channel region is located between the source region and the drain region.

[0023] Wiring 12W and wiring 32W function as gate wiring. Wiring 32W is electrically connected to wiring 12W via contact hole 15. Details will be described later. Wiring 12W is formed on the same layer as the gate electrode 12GE. Wiring 32W is formed on the same layer as the source electrode 32S and drain electrode 32D. Furthermore, wiring 32W is sometimes not disposed on wiring 12W.

[0024] The oxide semiconductor layer 26 is transparent and has a polycrystalline structure comprising a plurality of grains. Details will be described later. The oxide semiconductor layer 26 with a polycrystalline structure can be formed using Poly-OS (Poly-crystalline Oxide Semiconductor) technology. Therefore, the oxide semiconductor contained in the oxide semiconductor layer 26 will sometimes be referred to as Poly-OS.

[0025] Poly-OS contains two or more metal elements, including indium, with indium accounting for 50% or more of the total metal elements. Other metal elements besides indium can be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanides. Elements other than those mentioned above can also be used as the oxide semiconductor layer 26.

[0026] The grain size of the crystals contained in the Poly-OS is 0.1 μm or more, preferably 0.3 μm or more, and even more preferably 0.5 μm or more. The grain size can be obtained, for example, by observing the oxide semiconductor layer 26 using SEM (scanning electron microscope), TEM (transmission electron microscope), or electron backscattered diffraction (EBSD) method.

[0027] As described above, the grain size of the grains contained in Poly-OS is 0.1 μm or more. Therefore, in the oxide semiconductor layer 26 with a film thickness of 10 nm or more and 30 nm or less, there exists a region containing only one grain along the film thickness direction.

[0028] Poly-OS exhibits excellent etch resistance. Details will be described later. Poly-OS demonstrates excellent etch resistance to the etchant or etching gas used in the formation of the source electrode 32S and drain electrode 32D. Therefore, the oxide semiconductor layer 26 is hardly etched during the formation of the source electrode 32S and drain electrode 32D. Consequently, the film thickness of the first region (i.e., the source region or drain region) of the oxide semiconductor layer 26 overlapping with one of the source electrode 32S and drain electrode 32D, and the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 not overlapping with the source electrode 32S and drain electrode 32D are substantially the same. In other words, the difference between the film thickness of the first region and the film thickness of the second region is 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less.

[0029] The film thickness of the channel region affects the electrical characteristics of the semiconductor device. If the film thickness in the channel region is significantly uneven, a semiconductor device with stable electrical characteristics cannot be provided. That is, the yield of the semiconductor device decreases. On the other hand, since the film thickness of the channel region of the oxide semiconductor layer 26 can be controlled in the semiconductor device 10, the semiconductor device 10 has stable electrical characteristics. For example, even when the gate insulating layers 14 and 16 in the semiconductor device 10 have a large film thickness of 300 nm or more, a field-effect mobility (field-effect mobility in the linear region) of 15 cm² / Vs or more, and further 20 cm² / Vs or more, can be obtained within the range of a channel length L of 2 μm or more and a channel width of 2 μm or more and a channel width of 25 μm or more. Therefore, the breakdown voltage of the semiconductor device 10 is improved, and it has stable electrical characteristics even at high voltages.

[0030] [Manufacturing Method of Semiconductor Device 10] Referring to Figures 3 to 11, a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3 is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 11 are schematic cross-sectional views showing a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Hereinafter, each step of the flowchart shown in Figure 3 will be described sequentially.

[0031] In step S1001 ("Forming GE") of FIG3, a gate electrode 12GE is formed on the substrate 11 (see FIG4).

[0032] As substrate 11, rigid substrates with light transmittance, such as glass substrates, quartz substrates, and sapphire substrates, can be used. When substrate 11 needs to be flexible, polyimide substrates, acrylic resin substrates, silicone alkyl boards, fluororesin substrates, or substrates containing resin can be used as substrate 11. When using a resin-containing substrate as substrate 11, impurity elements can be introduced into the resin to improve the heat resistance of substrate 11. Furthermore, when the semiconductor device 10 is used in an integrated circuit, semiconductor substrates such as silicon substrates, silicon carbide substrates, and compound semiconductor substrates, or conductive substrates such as stainless steel substrates, which are not light transmittance, can also be used as substrate 11.

[0033] The gate electrode 12GE is formed by processing a conductive film deposited by sputtering. Metallic materials can be used as the gate electrode 12GE. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof can be used as the gate electrode 12GE. These metallic materials can be used in a single layer or in a multilayer configuration.

[0034] In step S1002 ("Forming GI") of Figure 3, gate insulating layers 14 and 16 are formed on the gate electrode 12GE (see Figure 4). Gate insulating layers 14 and 16 are formed by CVD (Chemical Vapor Deposition) or sputtering. Insulating materials can be used as gate insulating layers 14 and 16. For example, inorganic insulating materials such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), and silicon oxynitride (SiNxOy) can be used as insulating materials for gate insulating layers 14 and 16. SiOxNy is a silicon compound containing a nitrogen (N) concentration less than oxygen (O) (x>y). SiNxOy is a silicon compound containing an oxygen concentration less than nitrogen (x>y).

[0035] Preferably, a gate insulating layer 14 using a nitrogen-containing insulating material and a gate insulating layer 16 using an oxygen-containing insulating material are sequentially formed on the substrate 11. By using a nitrogen-containing insulating material as the gate insulating layer 14, impurities diffusing from the substrate 11 to the oxide semiconductor layer 26 can be blocked. Furthermore, by using an oxygen-containing insulating material as the gate insulating layer 16, oxygen can be released by heat treatment. The temperature of the heat treatment for releasing oxygen from the oxygen-containing insulating material is, for example, below 500°C, below 450°C, or below 400°C. Moreover, the oxygen-containing insulating material can release oxygen during heating in any step of the manufacturing process of the semiconductor device 10.

[0036] The thickness of the gate insulating layer 14 is preferably greater than the thickness of the gate insulating layer 16. In this embodiment, for example, silicon nitride of 300 nm is formed as the gate insulating layer 14. For example, silicon oxide of 100 nm is formed as the gate insulating layer 16.

[0037] In step S1004 ("film formation OS") of Figure 3, an oxide semiconductor film 22 is formed on the gate insulating layers 14 and 16 (see Figure 5). The oxide semiconductor film 22 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 22 is 10 nm to 50 nm, preferably 10 nm to 40 nm, and more preferably 10 nm to 30 nm.

[0038] As the oxide semiconductor film 22, a metal oxide with semiconductor properties can be used. For example, as the oxide semiconductor film 22, an oxide semiconductor containing two or more metal elements including indium (In) can be used. Furthermore, the ratio of indium to the two or more metal elements is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanides can be used. The oxide semiconductor film 22 preferably contains group 13 elements. Furthermore, elements other than those mentioned above can also be used as the oxide semiconductor film 22.

[0039] When the oxide semiconductor film 22 is crystallized by OS annealing (described later), it is preferable that the oxide semiconductor film 22 after film formation and before OS annealing has an amorphous structure (e.g., a structure with less crystalline content in oxide semiconductors that are determined to be amorphous in XRD (X-ray diffraction)). That is, the oxide semiconductor film 22 is preferably formed under conditions that minimize crystallization of the oxide semiconductor film 22 immediately after film formation. For example, when the oxide semiconductor film 22 is formed by sputtering, the oxide semiconductor film 22 is formed while controlling the temperature of the object to be formed (substrate 11 and the structure formed thereon).

[0040] When a film is formed on an object by sputtering, the temperature of the object increases as the film-forming process progresses due to collisions between ions generated in the plasma and atoms bounced off the sputtering target. As the temperature of the object rises during the film-forming process, microcrystals may be present in the oxide semiconductor film 22 immediately after film formation. When microcrystals are present in the oxide semiconductor film 22, the grain size cannot be increased by subsequent OS annealing. To control the temperature of the object, film formation can be performed simultaneously with cooling the object. For example, the temperature of the film-forming surface (hereinafter referred to as the "film-forming temperature") can be set to below 100°C, 70°C, 50°C, or 30°C, and the object can be cooled from the side opposite to the film-forming surface. In particular, the film-forming temperature of the oxide semiconductor film 22 is preferably below 50°C. By forming an oxide semiconductor film 22 while cooling the substrate 11, an oxide semiconductor film 22 with less crystalline content can be obtained immediately after film formation.

[0041] In the sputtering process, an oxide semiconductor film 22 with an amorphous structure is formed under conditions where the oxygen partial pressure is below 10%. When the oxygen partial pressure is high, the excess oxygen contained in the oxide semiconductor film 22 will cause microcrystals to be present in the oxide semiconductor film 22 immediately after formation. Therefore, it is preferable to form the oxide semiconductor film 22 under conditions where the oxygen partial pressure is low. For example, the oxygen partial pressure is 1% to 5%, preferably 2% to 4%. When the oxygen partial pressure is below 1%, the oxygen distribution in the film forming apparatus tends to become uneven. As a result, the oxygen composition in the oxide semiconductor film also becomes uneven, resulting in an oxide semiconductor film containing a large number of microcrystals, or an oxide semiconductor film that does not crystallize even after subsequent OS annealing.

[0042] In step S1005 of Figure 3 ("Forming the pattern of OS"), a pattern of oxide semiconductor layer 24 is formed (see Figure 6). The pattern of oxide semiconductor layer 24 is formed using photolithography. For example, a resist mask (not shown) is formed on oxide semiconductor film 22, and the oxide semiconductor film 22 is etched using the resist mask. Wet etching or dry etching can be used to etch the oxide semiconductor film 22. For wet etching, an acidic etchant can be used. Examples of etchants include oxalic acid, PAN (phosphoric-acetic-nitric acid, a mixed solution of phosphoric acid, acetic acid, and nitric acid), sulfuric acid, hydrogen peroxide, or hydrofluoric acid. This forms an oxide semiconductor layer 24 with a specific pattern. The resist mask is then removed.

[0043] The formation of the oxide semiconductor layer 24 with a specific pattern (i.e., the patterning of the oxide semiconductor film 22) is preferably performed before OS annealing. Poly-OS after OS annealing has higher etch resistance, making it difficult to perform patterning by etching. Furthermore, by performing OS annealing after the formation of the oxide semiconductor layer 24, damage caused during the formation of the oxide semiconductor layer 24 (such as oxygen defects in the oxide semiconductor layer 24) can be repaired by OS annealing.

[0044] In step S1006 ("OS annealing") of Figure 3, an oxide semiconductor layer 26 is formed by heat treatment (OS annealing) of the oxide semiconductor layer 24 after its formation (see Figure 7). During OS annealing, the oxide semiconductor layer 24 is held at a specific arrival temperature for a specific time. The specific arrival temperature is 300°C to 500°C, preferably 350°C to 450°C. Furthermore, the holding time at the arrival temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. Through OS annealing, the amorphous oxide semiconductor layer 24 crystallizes, forming a polycrystalline oxide semiconductor layer 26. That is, through OS annealing, an oxide semiconductor layer 26 comprising Poly-OS is formed.

[0045] In step S1008 ("forming contact holes") of Figure 3, contact holes are formed in the gate insulation layers 14 and 16 (see Figure 8). This exposes the upper surface of the wiring 12W. Furthermore, if it is not necessary to connect the wiring 32W to the wiring 12W, step S1008 can be omitted.

[0046] In step S1009 ("Forming SD") of Figure 3, a source electrode 32S, a drain electrode 32D, and a wiring 32W are formed (see Figure 9). The source electrode 32S, drain electrode 32D, and wiring 32W are formed by etching a conductive film formed by sputtering to pattern the film. The source electrode 32S and drain electrode 32D can be made of the same conductive material as the gate electrode 12GE. The conductive material can be used as a single layer or as a multilayer for the source electrode 32S, drain electrode 32D, and wiring 32W. In this embodiment, examples are a multilayer structure of MoW alloy, Al, and MoW alloy (MoW / Al / MoW structure), a single-layer structure of MoW alloy (MoW structure), a single-layer structure of Ti (Ti structure), and a multilayer structure of Ti, Al, and Ti (Ti / Al / Ti structure).

[0047] To form the source electrode 32S, drain electrode 32D, and wiring 32W, patterning is performed using wet etching or dry etching. In wet etching, an etching solution is used. For example, as the etching solution, a solution containing at least two of the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, and oxalic acid can be used. Specifically, as the etching solution, a mixed acid etching solution mainly composed of phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, a mixed solution of hydrogen peroxide and ammonia (hereinafter referred to as "H₂O₂ / NH₃ solution") can also be used. In dry etching, an etching gas is used. For example, as the etching gas, gases containing fluorine such as sulfur hexafluoride (SF₆) (hereinafter referred to as "fluorine-based gases") or gases containing chlorine such as chlorine (Cl₂) (hereinafter referred to as "chlorine-based gases") can be used.

[0048] Poly-OS exhibits excellent etch resistance. Specifically, the etching rate of the etchant or etching gas used in the formation of the source electrode 32S and drain electrode 32D is very low. This means that Poly-OS is almost not etched by the etchant or etching gas. Therefore, in the semiconductor device 10, even if a conductive film is directly formed on the oxide semiconductor layer 26 and the source electrode 32S and drain electrode 32D are formed by patterning the conductive film, the channel region of the oxide semiconductor layer 26 is almost not etched.

[0049] For example, the etching rate of the etchant used in the formation of the source electrode 32S and the drain electrode 32D of the oxide semiconductor layer 26 is 0.1 nm / sec or less, or 0.01 nm / sec or less. Furthermore, the etching rate of the etching gas used in the formation of the source electrode 32S and the drain electrode 32D of the oxide semiconductor layer 26 is 0.5 nm / sec or less, or 0.1 nm / sec or less. For example, the etching rate of the oxide semiconductor layer 26 for chlorine-based gases is 0.1 nm / sec or less.

[0050] In semiconductor devices using oxide semiconductors without polycrystalline structures, such as IGZO, as the oxide semiconductor layer, the oxide semiconductor layer is etched during the etching of the source and drain electrodes when the source and drain electrodes are formed on the oxide semiconductor. Specifically, IGZO has an etching rate of 1.0 nm / sec for chlorine-containing gases. Considering that the channel region will be etched at this rate, it is necessary to pre-deposit a relatively thick oxide semiconductor film. For example, in the case of manufacturing a semiconductor device where the thickness of the channel region of the oxide semiconductor layer is less than 40 nm, it is necessary to pre-deposit an oxide semiconductor film with a thickness of about 65 nm, and adjust the etching time to ensure that the thickness of the channel region is less than 40 nm when forming the source and drain electrodes. However, when the etching rate is high, it is difficult to precisely control the thickness of the channel region by the etching time. In this case, the unevenness of the thickness of the channel region increases.

[0051] Furthermore, when the film thickness in the channel region is significantly reduced, recesses will form on the upper surface of the oxide semiconductor layer. Although the interlayer insulating layer disposed on the oxide semiconductor layer is formed to cover the recesses, when the depth of the recesses is large, the interlayer insulating layer cannot fully cover them. That is, gaps may occur between the oxide semiconductor layer and the interlayer insulating layer, or between the source electrode and the drain electrode and the interlayer insulating layer. This will not only lead to non-uniform electrical characteristics of the semiconductor device, but also non-uniform reliability.

[0052] In contrast, the polycrystalline oxide semiconductor layer 26 exhibits an etching rate of 0.00 nm / sec to 0.1 nm / sec, preferably 0.00 nm / sec to 0.06 nm / sec, in both dry and wet etching processes. That is, the polycrystalline oxide semiconductor layer 26 has a lower etching rate and higher etch resistance compared to oxide semiconductor layers using IGZO. Therefore, the thickness of the channel region can be controlled without considering the reduction in oxide semiconductor layer thickness due to etching. Thus, an oxide semiconductor film thickness of 10 nm to 30 nm can be formed. Furthermore, the selectivity of the conductive material that can be used as the source electrode 32S, drain electrode 32D, and wiring 32W is improved. For example, even when wet etching is performed on conductive films using MoW / Al / MoW or MoW structures to form source electrodes 32S and drain electrodes 32D, the reduction in the thickness of the oxide semiconductor layer 26 can be suppressed.

[0053] As described above, the etching rate of the oxide semiconductor layer 26 for the etchant used in the formation of the source electrode 32S and the drain electrode 32D is very low. Therefore, the film thickness of the first region (i.e., the source region or drain region) of the oxide semiconductor layer 26 that overlaps with one of the source electrode 32S and the drain electrode 32D, and the film thickness of the second region (i.e., the channel region) of the oxide semiconductor layer 26 that does not overlap with the source electrode 32S and the drain electrode 32D are substantially the same. In other words, the difference between the film thickness of the first region and the film thickness of the second region can be controlled to be 5 nm or less, preferably 3 nm or less, and more preferably 1 nm or less. That is, the unevenness of the film thickness in the channel region is suppressed.

[0054] In step S1010 ("Forming SiOx") of Figure 3, an interlayer insulating layer 34 is formed on the oxide semiconductor layer 26, the source electrode 32S, and the drain electrode 32D. Preferably, an oxygen-containing insulating material is used as the interlayer insulating layer 34. For example, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) can be used as the interlayer insulating layer 34. Furthermore, it is preferable to use an insulating film with fewer defects as the interlayer insulating layer 34. For example, when comparing the oxygen composition ratio in the interlayer insulating layer 34 with the oxygen composition ratio in an insulating film with the same composition as the interlayer insulating layer 34 (hereinafter referred to as "other insulating films"), the oxygen composition ratio in the interlayer insulating layer 34 is closer to the stoichiometry relative to the insulating film than the oxygen composition ratio in the other insulating film. For example, when silicon oxide (SiO₂x) is used in both the interlayer insulating layer 34 and the gate insulating layer 16, the interlayer insulating layer 34 has a composition ratio that is closer to the stoichiometry of silicon oxide (SiO₂) than that of the gate insulating layer 16. The interlayer insulating layer 34 may also be a layer in which no defects were observed during evaluation by electron spin resonance (ESR).

[0055] The interlayer insulating layer 34 can be formed using the same film-forming method as the gate insulating layers 14 and 16. To increase the oxygen content in the interlayer insulating layer 34, film formation can be performed at a relatively low temperature (e.g., a film-forming temperature below 350°C). Furthermore, to form an insulating film with fewer defects as the interlayer insulating layer 34, the interlayer insulating layer 34 can also be formed at a film-forming temperature above 350°C. Moreover, after forming the interlayer insulating layer 34, a partial oxygen implantation treatment can be performed on a portion of the interlayer insulating layer 34.

[0056] The thickness of the interlayer insulating layer 34 is 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0057] In step S1011 ("film formation MO") of Figure 3, a metal oxide film 36 is formed on the interlayer insulating layer 34 (see Figure 10). The metal oxide film 36 is formed by sputtering or atomic layer deposition (ALD).

[0058] As the metal oxide film 36, a metal oxide film with aluminum as the main component can be used. For example, inorganic insulating films such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), and aluminum nitride (AlNx) can be used as the metal oxide film 36. A metal oxide film with aluminum as the main component refers to a metal oxide film in which the proportion of aluminum is 1% or more of the total metal oxide film. The proportion of aluminum contained in the metal oxide film 36 can be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide film 36. The above proportions can be mass ratios or weight ratios.

[0059] The thickness of the metal oxide film 36 is 1 nm to 50 nm, preferably 1 nm to 30 nm. Aluminum oxide is preferably used as the metal oxide film 36. Aluminum oxide possesses high barrier properties for gases such as oxygen or hydrogen. Here, barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen through the aluminum oxide. That is, it means that gases such as oxygen or hydrogen in the layer below the aluminum oxide film will not move to the layer above the aluminum oxide film. Or, it means that gases such as oxygen or hydrogen in the layer above the aluminum oxide film will not move to the layer below the aluminum oxide film.

[0060] Furthermore, metal oxides with metals other than aluminum as the main component can also be used as the metal oxide film 36. For example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) can be used as the metal oxide film 36.

[0061] In step S1012 ("oxidation annealing") of Figure 3, a heat treatment is performed while the interlayer insulating layer 34 and the metal oxide film 36 are formed on the oxide semiconductor layer 26 (see Figure 10). Here, the oxidation annealing can be performed, for example, at a temperature of 300°C or higher and 450°C or lower. This supplies oxygen released from the interlayer insulating layer 34 to the oxide semiconductor layer 26. By providing the metal oxide film 36 in a manner that covers the substrate 11, the release of oxygen released from the interlayer insulating layer 34 to the outside of the metal oxide film 36 can be suppressed.

[0062] During the process of forming the oxide semiconductor layer 26 and the interlayer insulating layer 34 on the oxide semiconductor layer 26, a large number of oxygen defects are generated in the oxide semiconductor layer 26. However, through the oxidation annealing in step S1012, the oxygen released from the interlayer insulating layer 34 is supplied to the oxide semiconductor layer 26, thereby repairing the oxygen defects.

[0063] In step S1013 ("Removing MO") of Figure 3, the metal oxide film 36 is removed (see Figure 11). For example, the metal oxide film 36 can be removed simply by using diluted hydrofluoric acid (DHF).

[0064] In step S1014 ("SiNx film formation") of Figure 3, an interlayer insulating layer 38 is formed on the interlayer insulating layer 34. Preferably, a nitrogen-containing insulating material is used as the interlayer insulating layer 38. For example, silicon nitride (SiNx) or silicon oxynitride (SiNxOy) can be used as the interlayer insulating layer 38. The interlayer insulating layer 38 can be formed using the same film formation method as the gate insulating layers 14 and 16.

[0065] By following the steps above, the semiconductor device 10 shown in Figure 1 can be manufactured.

[0066] In the semiconductor device 10 manufactured by the above-described manufacturing method, the shape inhomogeneity of the oxide semiconductor layer 26 is suppressed. In particular, the film thickness inhomogeneity in the channel region is reduced. As a result, the semiconductor device 10 has stable electrical characteristics. Therefore, the manufacturing inhomogeneity of the semiconductor device 10 is reduced, and the yield is improved.

[0067] <Second Implementation Method> Referring to FIGS. 12 to 15, a display device 20 using a semiconductor device 10 according to one embodiment of the present invention will be described. In the embodiments shown below, the configuration of a circuit in which the semiconductor device 10 described in the first embodiment is applied to a liquid crystal display device will be described.

[0068] [Overview of Display Device 20] Figure 12 is a schematic top view showing an outline of a display device 20 according to one embodiment of the present invention. As shown in Figure 12, the display device 20 includes an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. A plurality of pixel circuits 301 are arranged in a matrix in a liquid crystal region 220 surrounded by the sealing portion 310. The liquid crystal region 220 is the region that overlaps with the liquid crystal element 311 described later in the top view.

[0069] The sealing region 240, with the sealing portion 310, is the area surrounding the liquid crystal region 220. The FPC 330 is disposed on the terminal region 260. The terminal region 260 is the area of ​​the array substrate 300 exposed from the opposing substrate 320, and is disposed outside the sealing region 240. The outside of the sealing region 240 refers to the area with the sealing portion 310 and the area surrounded by the sealing portion 310. The IC chip 340 is disposed on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0070] [Circuit configuration of display device 20] Figure 13 is a block diagram showing the circuit configuration of a display device 20 according to one embodiment of the present invention. As shown in Figure 13, a source driving circuit 302 is provided adjacent to the liquid crystal region 220 where the pixel circuit 301 is disposed in the second direction D2 (row direction), and a gate driving circuit 303 is provided adjacent to the liquid crystal region 220 in the first direction D1 (column direction). The source driving circuit 302 and the gate driving circuit 303 are disposed in the aforementioned sealed region 240. However, the region where the source driving circuit 302 and the gate driving circuit 303 are disposed is not limited to the sealed region 240, and can be any region, as long as it is outside the region where the pixel circuit 301 is disposed.

[0071] The source wiring 304 extends from the source driving circuit 302 along the second direction D2 and is connected to the plurality of pixel circuits 301 arranged along the second direction D2. The gate electrode 12GE extends from the gate driving circuit 303 along the first direction D1 and is connected to the plurality of pixel circuits 301 arranged along the first direction D1.

[0072] A terminal section 306 is provided in the terminal area 260. The terminal section 306 is connected to the source drive circuit 302 via a connecting wire 307. Similarly, the terminal section 306 is connected to the gate drive circuit 303 via a connecting wire 307. An FPC 330 is connected to the terminal section 306, thereby connecting the external device connected to the FPC 330 to the display device 20, and driving the pixel circuits 301 set in the display device 20 by the signals from the external device.

[0073] The semiconductor device 10 shown in the first embodiment can be used as a transistor contained in the pixel circuit 301, the source driving circuit 302, and the gate driving circuit 303.

[0074] [Pixel circuit 301 of display device 20] Figure 14 is a circuit diagram showing the pixel circuit 301 of a display device 20 according to one embodiment of the present invention. As shown in Figure 14, the pixel circuit 301 includes components such as a semiconductor device 10, a holding capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 12GE, an oxide semiconductor layer 26, a source electrode 32S, and a drain electrode 32D. The gate electrode 12GE is connected to the gate wiring 305. The source electrode 32S is connected to the source wiring 304. The drain electrode 32D is connected to the holding capacitor 350 and the liquid crystal element 311.

[0075] [Composition of display device 20] Figure 15 is a schematic cross-sectional view of a display device 20 according to one embodiment of the present invention. A semiconductor device 10 is used in the display device 20 shown in Figure 15.

[0076] As shown in Figure 15, a gate electrode 12GE is provided on the substrate 11. Gate insulating layers 14 and 16 are provided on the gate electrode 12GE. An oxide semiconductor layer 26 is provided on the gate insulating layers 14 and 16. A source electrode 32S and a drain electrode 32D are provided on the oxide semiconductor layer 26.

[0077] Interlayer insulating layers 34 and 38 are provided on the source electrode 32S and drain electrode 32D. An insulating layer 39 is provided on the interlayer insulating layers 34 and 38. The insulating layer 39 is provided to mitigate the unevenness generated by the semiconductor device 10. Contact holes are formed on the interlayer insulating layers 34, 38 and the insulating layer 39 such that the upper surface of the source electrode 32S is exposed. A common electrode 42C, which is commonly disposed on a plurality of pixels, is provided on the insulating layer 39. An insulating layer 44 is provided on the common electrode 42C. An insulating layer 44 is provided inside the contact holes. By forming the insulating layer 44 with a silicon nitride film, moisture can be prevented from seeping in through the contact holes via the insulating layer 44. A pixel electrode 46P is provided on the insulating layer 44 and inside the contact holes. The pixel electrode 46P is connected to the drain electrode 32D.

[0078] Furthermore, a wiring 12C is provided on the substrate 11, and the wiring 12C is connected to the wiring 32C via contact holes provided in the gate insulating layers 14 and 16. The wiring 12C and the wiring 32C function as capacitor wiring. Furthermore, an electrode 46C is provided on the insulating layer 39 and inside the opening. The common electrode 42C, the insulating layer 44, and the electrode 46C form a holding capacitor 350.

[0079] Although the semiconductor device 10 is illustrated in this embodiment for use in the pixel circuit 301, the semiconductor device 10 can also be used in peripheral circuits including the source drive circuit 302 and the gate drive circuit 303.

[0080] <Third Implementation Method> Referring to FIGS. 16 and 17, a display device 20 using a semiconductor device 10 according to one embodiment of the present invention will be described. In this embodiment, the configuration of the circuit of the semiconductor device 10 described in the first embodiment applied to an organic EL display device will be described. The outline and circuit configuration of the display device 20 are the same as those shown in FIGS. 12 and 13, so the description will be omitted.

[0081] [Pixel circuit 301 of display device 20] Figure 16 is a circuit diagram showing the pixel circuit of a display device 20 according to one embodiment of the present invention. As shown in Figure 16, the pixel circuit 301 includes components such as a driving transistor 110, a selecting transistor 120, a holding capacitor 210, and a light-emitting element DO. The driving transistor 110 and the selecting transistor 120 have the same configuration as the semiconductor device 10. The source electrode of the selecting transistor 120 is connected to the signal line 211, and the gate electrode of the selecting transistor 120 is connected to the gate line 212. The source electrode of the driving transistor 110 is connected to the anode power line 213, and the drain electrode of the driving transistor 110 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the driving transistor 110 is connected to the drain electrode of the selecting transistor 120. The holding capacitor 210 is connected to the gate electrode and the drain electrode of the driving transistor 110. The signal line 211 is supplied with a grayscale signal that determines the light intensity of the light-emitting element DO. Gate line 212 is supplied with a signal that selects the pixel column to be written into the grayscale signal.

[0082] [Cross-sectional structure of display device 20] Figure 17 is a schematic cross-sectional view showing the configuration of a display device 20 according to one embodiment of the present invention. The configuration of the display device 20 shown in Figure 17 is similar to that of the display device 20 shown in Figure 15, but the structure above the insulating layer 39 in the display device 20 shown in Figure 17 is different from that in the display device 20 shown in Figure 15. Hereinafter, in the configuration of the display device 20 shown in Figure 17, the configurations that are the same as those in the display device 20 shown in Figure 15 will be omitted from the description, and the differences between the two will be explained.

[0083] As shown in Figure 17, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating layer 39. The pixel electrode 390 is disposed above the insulating layer 39 and inside the contact holes formed in the interlayer insulating layers 34, 38 and the insulating layer 39. An insulating layer 362 is provided above the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to the light-emitting area. That is, the insulating layer 362 defines the pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed through the opening 363. For each pixel, a pixel electrode 390 and a light-emitting layer 392 are provided individually. On the other hand, the common electrode 394 is commonly disposed in a plurality of pixels. The light-emitting layer 392 uses a material different according to the display color of the pixel.

[0084] Although the second and third embodiments illustrate configurations obtained by applying the semiconductor device 10 described in the first embodiment to a liquid crystal display device and an organic EL display device, the semiconductor device 10 can also be applied to display devices other than these (e.g., self-emissive display devices or electronic paper display devices other than organic EL display devices). Furthermore, the semiconductor device 10 can be applied to a wide range of display devices, from small and medium-sized to large-scale. Even when manufacturing using a large-area substrate, the shape uniformity of the oxide semiconductor layer 26 in the semiconductor device 10 is relatively small. Therefore, when the semiconductor device 10 is applied to the display device 20, display unevenness can be reduced. Furthermore, the yield rate during the manufacturing of the display device 20 can be improved. [Example]

[0085] (Example 1) In this embodiment, the results of the etch resistance test of an oxide semiconductor layer having a polycrystalline structure are described.

[0086] The sample used in this embodiment will be described. An oxide semiconductor layer (Poly-OS) with a polycrystalline structure of 30 nm is formed on a silicon wafer. Subsequently, a conductive film is formed on the oxide semiconductor layer. As the conductive film, four structures are used: MoW structure, MoW / Al / MoW structure, Ti structure, and Ti / Al / Ti structure.

[0087] For the conductive film and oxide semiconductor layer of the MoW structure, samples were prepared by wet etching with mixed acid etching solution, samples by wet etching with H2O2 / NH3 solution, and samples by dry etching with fluorine gas.

[0088] For the conductive film and oxide semiconductor layer of the MoW / Al / MoW structure, samples are prepared by wet etching with a mixed acid etching solution.

[0089] For the conductive film and oxide semiconductor layer with Ti structure, samples were prepared by wet etching with H 2O 2 / NH 3 solution, samples by dry etching with fluorine gas, and samples by dry etching with chlorine gas.

[0090] For the conductive film and oxide semiconductor layer with Ti / Al / Ti structure, samples were prepared by wet etching of Ti with H2O2 / NH3 solution, wet etching of Al with mixed acid etching solution, wet etching of Ti with H2O2 / NH3 solution, and dry etching with chlorine gas.

[0091] Furthermore, the mixed acid etching solution used was "Mixed Acid AT-2F (product name)" manufactured by Rasa Industries Co., Ltd. The phosphoric acid content in the mixed acid etching solution was approximately 65%. Also, the temperature of the mixed acid etching solution used for etching each sample was set to 40°C (temperature adjusted), and the temperature of the H₂O₂ / NH₃ solution was set to 22°C (temperature not adjusted, room temperature).

[0092] Next, the samples used in the comparative examples will be described. A 40 nm IGZO oxide semiconductor layer was formed on a silicon wafer. Subsequently, a conductive film was formed on the oxide semiconductor layer. Ti was used as the conductive film. Samples were prepared by dry etching the Ti conductive film and the oxide semiconductor layer with chlorine-based gas.

[0093] In this embodiment, the etching rate (unit: nm / sec) of the polycrystalline oxide semiconductor layer relative to the estimated over-etching time after processing various conductive films is shown in Table 1.

[0094] [Table 1] wet etching Dry etching Mixed acid etching solution H₂O₂ / NH₃ solution Fluorine gases Chlorine-based gases MoW Construction 0.00 0.02 0.00 - MoW / Al / MoW structure 0.00 - - - Ti structure - 0.06 0.05 0.22 Ti / Al / Ti structure 0.02 - 0.30

[0095] Regarding the comparative example, the etching rate of the oxide semiconductor layer (IGZO) relative to the estimated over-etching time after processing the conductive film of the Ti structure is 1.00 nm / sec.

[0096] As shown in Table 1, the etch resistance of the polycrystalline oxide semiconductor layer is higher than that of the amorphous oxide semiconductor layer (IGZO). Furthermore, the etch rates are shown to be 0.00 nm / sec to 0.06 nm / sec when etched with a mixed acid etching solution, an H₂O₂ / NH₃ solution, and a fluorine-based gas. This indicates that even when etched with a chlorine-based gas, the etch resistance is significantly higher than that of the oxide semiconductor layer (IGZO).

[0097] (Example 2) Next, the measurement results of the electrical characteristics of the semiconductor device 10 manufactured according to the flowchart shown in FIG3 of the first embodiment will be explained.

[0098] The samples A to C, which were fabricated as semiconductor devices 10 in Example 2, will be described. In the fabrication of samples A to C, step S1008 of the flowchart showing the manufacturing method of semiconductor device 10 shown in FIG3 is omitted.

[0099] A gate electrode 12GE is formed on a substrate, and gate insulating layers 14 and 16 are formed on the gate electrode 12GE. A 30 nm oxide semiconductor film 22 is formed on the gate insulating layers 14 and 16. An oxide semiconductor layer 24 is formed by processing the oxide semiconductor film 22, and a polycrystalline oxide semiconductor layer 26 (Poly-OS) is formed by performing OS annealing with the temperature controlled within the range of 350°C to 450°C.

[0100] A MoW / Al / MoW structure is formed on the oxide semiconductor layer 26 as a conductive film. The conductive film is then wet-etched using a mixed acid etching solution to form the source electrode 32S and drain electrode 32D. Next, a silicon oxide layer is formed as an interlayer insulating layer 34, followed by the formation of a 10 nm aluminum oxide layer as a metal oxide film 36. After oxidation annealing, the metal oxide film 36 is removed. Finally, an interlayer insulating layer 38 is formed on the interlayer insulating layer 34.

[0101] The film-forming temperatures of the interlayer insulating layer 34 in samples A through C are different. The film-forming temperatures of the interlayer insulating layer 34 in samples A through C are 300℃, 325℃, and 350℃, respectively.

[0102] In samples A to C, the thickness of the oxide semiconductor layer 26 was measured. The results showed that the difference between the thickness of the channel region and the thickness of the source or drain region was less than 2 nm.

[0103] Next, the electrical properties of samples A through C were measured. The conditions for measuring the electrical properties are shown in Table 2.

[0104] [Table 2] Size of the passage area W / L=6.0 μm / 6.0 μm Source-drain voltage 0.1 V, 10 V Gate voltage -40 V to +40 V (0.2 V Step) Environmental measurement Room temperature, dark room

[0105] Figure 18 is a graph showing the electrical characteristics (Id-Vg characteristics) of samples A to C in Example 2. The horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current (Id). Table 3 shows the field-effect mobility (field-effect mobility in the linear region) and threshold calculated based on the electrical characteristics shown in Figure 18.

[0106] [Table 3] Field effect mobility (cm² / Vs) Threshold (V) Sample A 24.24 1.07 Sample B 25.23 -0.06 Sample C 24.34 -0.35

[0107] As can be understood from Figure 18 and Table 3, in samples A to C, even when the interlayer insulating layer 34 with different film formation temperatures is connected to the polycrystalline oxide semiconductor layer (Poly-OS), a stable field-effect mobility can still be obtained. That is, the semiconductor device 10 can obtain stable electrical characteristics by controlling the shape of the oxide semiconductor layer 26 (especially the film thickness of the channel region).

[0108] Furthermore, as the film-forming temperature of the interlayer insulating layer 34 increases, the threshold of the electrical characteristics shifts to the negative side. Therefore, in the electrical characteristics of the semiconductor device 10, when the threshold is set to the enhancement type, it is preferable to form the interlayer insulating layer 34 at a temperature below 300°C.

[0109] Unless they contradict each other, the various embodiments and variations described above can be appropriately combined and implemented as embodiments of the present invention. Furthermore, any additions, deletions, or design changes to constituent elements, or additions, omissions, or changes to processes or conditions, based on the various embodiments and variations, are also included within the scope of the present invention as long as they possess the essence of the present invention.

[0110] Even if the effects are different from those brought about by the above-described embodiments, the effects that are clearly defined according to the description in this specification, or the effects that can be easily predicted by the operator, should of course be understood as the effects brought about by the present invention.

[0111] 10: Semiconductor devices 11:Substrate 12C: Wiring 12GE: Gate electrode 12W: Wiring 14: Gate insulation layer 15: Contact hole 16: Gate insulation layer 20: Display device 22: Oxide semiconductor film 24: Oxide semiconductor layer 26: Oxide semiconductor layer 32C: Wiring 32D: Drain electrode 32S: Source electrode 32W: Wiring 34: Interlayer insulation layer 36: Metal oxide film 38: Interlayer insulation layer 39: Insulation layer 42C: Common electrode 44: Insulation layer 46C: Electrode 46P: Pixel Electrode 110: Driving transistor 120: Select Transistor 210: Holding Capacitor 211: Signal line 212: Gate line 213: Anode power supply line 214: Cathode power line 220: LCD area 240: Sealed area 260: Terminal area 300: Array substrate 301: Pixel Circuit 302: Source drive circuit 303: Gate drive circuit 304: Source Wiring 305: Gate wiring 306: Terminal section 307: Wiring Connection 310: Sealing part 311: Liquid Crystal Components 320: Opposing substrate 330: Flexible Printed Circuit Board 340: Chip 350: Holding capacitor 362: Insulation layer 363: Opening 390: Pixel Electrode 392: Emissive layer 394: Common Electrode D1: Direction 1 D2: Second Direction DO: Light-emitting element L: Channel length S1001: Steps S1002: Steps S1004: Steps S1005: Steps S1006: Steps S1008: Steps S1009: Steps S1010: Steps S1011: Steps S1012: Steps S1013: Steps S1014: Steps W: Channel width

Claims

1. A semiconductor device comprising: a gate electrode, a gate insulating layer above the gate electrode, an oxide semiconductor layer having a polycrystalline structure above the gate insulating layer, a source electrode and a drain electrode above the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer includes a region comprising only one grain having a grain size of 0.5 μm or more along the film thickness direction, the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode, and a second region in contact with the interlayer insulating layer, the boundary between the first region and the second region substantially coincides with the end of one of the source electrode and the drain electrode, and the difference in film thickness between the first region and the second region is 5 nm or less.

2. The semiconductor device of claim 1, wherein the etching rate of the oxide semiconductor layer for the etching solution used to form the source electrode and the drain electrode is 0.1 nm / sec or less.

3. The semiconductor device of claim 2, wherein the etching solution comprises a solution of at least two selected from the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, and oxalic acid.

4. The semiconductor device of claim 1, wherein the etching rate of the oxide semiconductor layer for the etching gas used to form the source electrode and the drain electrode is 0.5 nm / sec or less.

5. The semiconductor device of claim 4, wherein the etching gas system contains a fluorine gas and the etching rate is 0.1 nm / sec or less.

6. The semiconductor device of claim 1, wherein the film thickness of the first region is 10 nm or more and 30 nm or less.

7. The semiconductor device of claim 1, wherein the oxide semiconductor layer comprises indium and at least one metal element, and the ratio of indium to the indium and at least one metal element is 50% or more.

8. A method for manufacturing a semiconductor device, comprising the following steps: forming a gate electrode; forming a gate insulating layer on the gate electrode; forming an oxide semiconductor layer having a polycrystalline structure on the gate insulating layer; forming a conductive film on the oxide semiconductor layer; patterning the conductive film by etching to form a source electrode and a drain electrode; and forming an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer; wherein the oxide semiconductor layer includes a region comprising only one grain having a grain size of 0.5 μm or more along the film thickness direction, the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode, and a second region in contact with the interlayer insulating layer, the boundary between the first region and the second region substantially coincides with the end of one of the source electrode and the drain electrode, and the difference in film thickness between the first region and the second region is 5 nm or less.

9. A method for manufacturing a semiconductor device as claimed in claim 8, wherein an etchant is used in the etching process, and the etching rate of the oxide semiconductor layer to the etchant is 0.1 nm / sec or less.

10. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the etching solution comprises a solution of at least two selected from the group consisting of phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, and oxalic acid.

11. The method for manufacturing a semiconductor device as claimed in claim 8, wherein an etching gas is used in the etching process, and the etching rate of the oxide semiconductor layer to the etching gas is 0.5 nm / sec or less.

12. The method for manufacturing a semiconductor device as claimed in claim 11, wherein the etching gas system contains a fluorine gas and the etching rate is 0.1 nm / sec or less.

13. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the film thickness of the first region is 10 nm or more and 30 nm or less.

14. The method for manufacturing a semiconductor device as claimed in claim 8, wherein the oxide semiconductor layer comprises indium and at least one metal element, and the ratio of indium to the indium and at least one metal element is 50% or more.

15. A method for manufacturing a semiconductor device as claimed in claim 14, wherein the oxide semiconductor layer is formed by heat treatment of an oxide semiconductor film having an amorphous structure.

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