Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure configured to control the channel structure; a back-side source / drain contact structure connected to the bottom surface of the first source / drain region; a back-side isolation structure located at a lower portion of the semiconductor device; and a first contact spacer located on the back-side source / drain contact structure, wherein the first contact spacer is configured to isolate the back-side source / drain contact structure from another circuit element in the back-side isolation structure.

Description

A semiconductor device including a back source / drain contact structure having a contact spacer and a back gate contact structure The devices and methods related to the present disclosure relate to a semiconductor device in which a back gate contact structure is formed in a self-aligned manner and a contact spacer is provided on the back source / drain contact structure. In order to reduce the footprint of a semiconductor device including field effect transistors, the distance between the gate contact structure and the source / drain contact structure has been reduced during the manufacture of the semiconductor device. However, as semiconductor devices gradually have higher and higher device integration densities, the short distance between the gate contact structure and the source / drain contact structure may increase the risk of short circuit between the gate contact structure and the source / drain contact structure. FIG. 1A illustrates a top plan view of a semiconductor device in which a plurality of gate structures and source / drain regions are formed to constitute corresponding field effect transistors. FIG. 1B illustrates a cross-sectional view of the semiconductor device shown in FIG. 1A according to an embodiment in the D1 direction along the line I-I' shown in FIG. 1A. It should be understood here that the D1 direction is the channel length direction that intersects the D2 direction as the channel width direction and the D3 direction as the vertical direction. Referring to FIGS. 1A and 1B, the semiconductor device 10 includes first gate structures G1 to sixth gate structures G6 and first source / drain regions SD1 to fifth source / drain regions SD5 formed on a substrate 101, wherein a bottom isolation layer 102 is located between the first gate structures G1 to G6 and the first source / drain regions SD1 to SD5 and the substrate 101. The source / drain regions SD1 to SD6 are isolated from the gate structures G1 to G6 by inner spacers 104, and the gate structures G1 to G6 are protected by gate spacers 108 formed on the upper side surfaces of the gate structures G1 to G6. The gate structures G1 to G6 extend in the D2 direction and are arranged in the D1 direction. The gate structures G1 to G6 surround the multiple nanosheet channel layers 110 of the channel structure connecting two adjacent source / drain regions to form corresponding nanosheet transistors. The nanosheet transistors are also referred to as gate-all-around (GAA) transistors and multi-bridge channel field-effect transistors (MBCFETs). The gate structures G1 to G6 can control the current flowing between the two source / drain regions via the channel structure. For example, the first nanosheet transistor NT1 is formed by the first source / drain region SD1 and the second source / drain region SD2 connected to each other via the channel layer 110 and the gate structure G2 surrounding the channel layer 110 between the two source / drain regions SD1 and SD2. Similarly, the second nanosheet transistor NT2 is formed by the fourth source / drain region SD4 and the fifth source / drain region SD5 connected to each other via the channel layer 110 and the gate structure G5 surrounding the channel layer 110 between the two source / drain regions SD4 and SD5. The semiconductor device 10 further includes first to fifth source / drain contact structures CA1 to CA5 respectively formed on the top surfaces of the first to fifth source / drain regions SD1 to SD5 to connect these source / drain regions to a voltage source or another circuit element inside or outside the semiconductor device 10. The semiconductor device 10 also includes a first gate contact structure CB1 and a second gate contact structure CB2 respectively formed on the top surface of the second gate structure G2 and the top surface of the fifth gate structure G5 to receive a gate input signal and deliver the gate input signal to these gate structures. The contact structures CA1 to CA5 are isolated from each other and from the gate structures CB1 and CB2 via an isolation structure 116. However, as the distance DT1 between the first gate contact structure CB1 and each of the adjacent source / drain contact structures CA1 and CA2 in the semiconductor device 10 becomes smaller and smaller, the risk of short circuit between the first gate contact structure CB1 and each of the adjacent source / drain contact structures CA1 and CA2 increases. The same short-circuit risk also exists between the fifth gate contact structure CB5 and each of the adjacent source / drain contact structures CA4 and CA5. In the semiconductor device 10, the substrate 101 may be a silicon substrate or a silicon-on-insulator (SOI), but is not limited thereto. The channel layer 110 may be formed of silicon (Si) or silicon germanium (SiGe). The gate structures G1 to G6 may be formed of one or more materials including, for example, copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. The source / drain regions SD1 to SD5 may include one or more materials such as silicon (Si), silicon germanium (SiGe) doped with impurities. The contact structures CA1 to CA5, CB1, and CB2 may be formed of one or more materials such as copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), etc.). The bottom isolation layer 102 that suppresses leakage current from the gate structures G1 to G6 and the source / drain regions SD1 to SD5 may be formed of, for example, silicon oxide (such as SiO 2 ), but is not limited thereto. The one or more materials forming the bottom isolation layer 102, the inner spacer 104, and the gate spacer 108 may include, for example, silicon oxide (such as, SiO 2 ), or silicon nitride (Si 3 N 4 ). The isolation structure 116 may be formed of, for example, silicon oxide (such as SiO or SiO 2 ). The information disclosed in this background art section is known to the inventor or has been derived by the inventor before or during the process of achieving the embodiments of this application, or the information disclosed in this background art section is the technical information obtained during the process of achieving the embodiments. Therefore, the information disclosed in this background art section may contain information that does not form the prior art that is well known to the public. This disclosure provides a semiconductor device including a backside source / drain contact structure having a contact spacer thereon and a backside gate contact structure isolated from the backside source / drain contact structure by the contact spacer. According to an embodiment, a semiconductor device is provided, which may include: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure configured to control the channel structure; a backside source / drain contact structure connected to a bottom surface of the first source / drain region; a backside isolation structure located at a lower portion of the semiconductor device; and a first contact spacer located on the backside source / drain contact structure, wherein the first contact spacer is configured to isolate the backside source / drain contact structure from another circuit element in the backside isolation structure. The first contact spacer may be formed on a side surface of the backside source / drain contact structure and include an isolation material, and the semiconductor device may further include a backside gate contact structure connected to a bottom surface of the gate structure. According to an embodiment, a semiconductor device is provided, which may include: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure configured to control the channel structure; and a backside gate contact structure connected to a bottom surface of the gate structure, wherein the backside gate contact structure is not aligned with the bottom surface of the gate structure and is closer to the second source / drain region than the first source / drain region. The semiconductor device may further include: a backside source / drain contact structure connected to a bottom surface of the first source / drain region; and a first contact spacer located on the backside source / drain contact structure, the first contact spacer being configured to isolate the backside source / drain contact structure from another circuit element in the backside isolation structure. According to an embodiment, a method of manufacturing a semiconductor device is provided. The method may include: forming an occupation structure on a bottom surface of a source / drain region; forming a contact spacer on the occupation structure; forming a backside gate contact structure on a bottom surface of a gate structure; and replacing the occupation structure with a backside source / drain contact structure such that the backside source / drain contact structure is surrounded by the contact spacer. The embodiments of the disclosure described herein are exemplary embodiments, and thus the disclosure is not limited thereto and can be implemented in various other forms. Each of the embodiments provided in the following description does not exclude being associated with one or more features of another example or another embodiment provided herein or not provided herein but consistent with the disclosure. For example, even if an item described in a particular example or embodiment is not elaborated in different examples or embodiments, the item can still be understood as being related to or combined with the different examples or embodiments, unless otherwise mentioned in the description of the item. Additionally, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of the disclosure are intended to encompass their structural and functional equivalents. Additionally, these equivalents should be understood to include not only currently well-known equivalents but also equivalents to be developed in the future, i.e., all devices invented for performing the same function, regardless of their structures. For example, the channel layer, sacrificial layer, and isolation layer described herein can be of different types or forms as long as the disclosure is applicable to the channel layer, sacrificial layer, and isolation layer. It will be understood that when an element, component, layer, pattern, structure, region, etc. (collectively referred to as "element") of a semiconductor device is said to be "over", "above", "on", "below", "under", "beneath", "connected to", or "coupled to" another element of the semiconductor device, the element can be directly over, above, on, below, under, beneath, connected to, or coupled to the other element, or there can be intervening elements. In contrast, when an element of a semiconductor device is said to be directly "over", "above", "on", "below", "under", "beneath", "directly connected to", or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout the disclosure, like numbers refer to like elements. For ease of explanation, in this document, spatial relative terms such as "above", "over", "on", "upper", "below", "under", "beneath", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc., and similar terms may be used to describe the relationship between one component and another component, as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, the spatial relative terms are also intended to encompass different orientations of the semiconductor device during use or operation. For example, if the semiconductor device in the figure is inverted, a component described as being "below" or "beneath" another component will then be oriented as being "above" the said another component. Therefore, the term "below" can encompass both the upper and lower orientations. The semiconductor device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are accordingly interpreted. For another example, when a device or structure including a "left" component and a "right" component has different orientations, the components referred to as the "left" component and the "right" component may be the "right" component and the "left" component. Therefore, in the following description, the "left" component and the "right" component may also be referred to as the "first" component or the "second" component, as long as the structural relationship can be clearly understood in the context of this description. Similarly, the terms "lower" component and "upper" component may be referred to as the "first" component and the "second" component respectively, and it is necessary to make an explanation to distinguish the two components. It will be understood that although terms such as "first", "second", "third", "fourth", "fifth", "sixth", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component, and this does not depart from the teachings of this disclosure. Expressions such as "at least one of..." used herein, when preceding a series of components, modify the entire series of components and do not modify individual components in the series. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the terms "same" or "equal" are used to compare the sizes of two or more components, these terms may cover "substantially the same" or "substantially equal" sizes. In addition, when the terms "coplanar" or "aligned" are used to compare the positional relationship between two or more components, these terms may also cover "substantially coplanar" or "substantially aligned" sizes. It should also be understood that even if a step or operation of a manufacturing apparatus or structure is described as being later than another step or operation, the step or operation may still be performed later than the other step or operation, unless it is stated that the other step or operation is to be performed after the step or operation. Many embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments (and intermediate structures). Accordingly, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments are not to be construed as limited to the specific shapes of regions illustrated herein, but include deviations in shapes due to, for example, manufacturing. The various regions illustrated in the figures are schematic in nature and the shapes of the various regions are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the present disclosure. Additionally, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Accordingly, it is to be understood that when examining any of the structures described herein via scanning electron microscopy (SEM), transmission electron microscopy (TEM), focused ion beam (FIB) microscopy, etc., these schematic illustrations do not reflect the actual images. For simplicity, conventional elements, structures or layers of semiconductor devices, including nanosheet transistors, fin field-effect transistors, and the materials forming the conventional elements, structures or layers may or may not be described in detail herein. For example, when an isolation layer or structure of a semiconductor device is not relevant to the novel features of the present embodiment, this layer or structure and the materials forming this layer or structure may be omitted herein. Also, when the materials of well-known structural elements forming a semiconductor device are not relevant to the novel features of the present embodiment, the description of these materials may be omitted herein. A backside power distribution network (BSPDN) has been introduced in semiconductor devices to address the heavy traffic of signal lines and power rails at the front side of the semiconductor device. The BSPDN may also help reduce the contact resistance between circuit elements formed at the front side of the semiconductor device. Here, the front side refers to the side on which transistors are formed with respect to the top surface of the substrate, and the back side refers to the side opposite the front side. The BSPDN is formed on the back side of the semiconductor device and may include backside metal lines (such as buried power rails) and backside source / drain contact structures formed on the bottom surfaces of the source / drain regions of field-effect transistors (e.g., nanosheet transistors or fin field-effect transistors (FinFETs)), and the backside metal lines may connect the backside contact structures to a voltage source or another circuit element for signal routing. In the embodiments described below, the BSPDN is expanded to include a backside gate contact structure to address the risk of short circuits between the gate contact structures formed at the front side of the semiconductor device and other circuit elements (such as source / drain contact structures) also formed on the front side of the semiconductor device. FIG. 2 illustrates a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to an embodiment. Referring to FIG. 2, the semiconductor device 20 may include the same structural elements as the semiconductor device 10 shown in FIGS. 1A and 1B, such as source / drain regions SD1 to SD6, gate structures G1 to G5, channel layer 110, inner spacers 104, gate spacers 108, and isolation structure 116. However, the semiconductor device 20 may include contact structures different from those of the semiconductor device 10. Therefore, although its repeated description may be omitted, the differences of the semiconductor device 20 are described below. In the semiconductor device 20, some selected source / drain contact structures and gate contact structures may be formed on the backside, while other contact structures remain on the front side. For example, a first backside source / drain contact structure BC1, a second backside source / drain contact structure BC2, and a third backside source / drain contact structure BC3 may be formed on the bottom surfaces of the second source / drain region SD2, the third source / drain region SD3, and the fifth source / drain region SD5, respectively, and are surrounded by contact spacers 103. In addition, a first backside gate contact structure BG1 and a second backside gate contact structure BG2 may be formed on the bottom surfaces of the second gate structure G2 and the fifth gate structure G5, respectively. In addition, a first source / drain contact structure CA1 and a fourth source / drain contact structure CA4 may be formed on the top surfaces of the first source / drain region SD1 and the fourth source / drain region SD4, respectively. These backside contact structures BC1 to BC3, BG1, and BG2 of the semiconductor device 20 may be formed of the same materials as the channel structures CA1 to CA5, CB1, and CB2 forming the semiconductor device 10, and the channel structures CA1 to CA5, CB1, and CB2 are front side contact structures herein. The backside contact structures BC1 to BC3, BG1, and BG2 may be buried in the backside isolation structure 106, and the bottom surfaces of the backside contact structures BC1 to BC3, BG1, and BG2 are exposed by the bottom surface of the backside isolation structure 106. The backside isolation structure 106 may have replaced the substrate 101 in a backside process to form the BSPDN of the semiconductor device 20, as will be described later with reference to FIGS. 4A to 4O. Similar to the isolation structure 116 as the front side isolation structure, the backside isolation structure 106 may be formed of, for example, silicon oxide (such as SiO or SiO2). Although not shown in the figures, one or more backside metal lines may be formed on the backside of the semiconductor device 20 to connect to the backside gate contact structures BG1 and BG2, thereby delivering the corresponding gate input signals or a common gate input signal to the gate structures G2 and G5 via the backside gate contact structures BG1 and BG2, respectively. Also, one or more additional backside metal lines may be formed on the backside of the semiconductor device 20 to connect to the backside source / drain contact structures BC1 to BC3 to connect the source / drain regions SD2, SD3, and SD5 to one or more voltage sources or other circuit elements via the backside source / drain contact structures BC1 to BC3, respectively. When the selected contact structures are formed at the backside as described herein instead of at the front side, congestion and increased contact resistance of the contact structures and interconnects at the front side of the semiconductor device 20 can be alleviated, as previously described. In addition, when the first backside gate contact structure BG1 is formed as sufficiently far away from the first source / drain contact structure CA1 as described herein, the risk of short circuit between these two contact structures can be removed. Similarly, the risk of short circuit between the second backside gate contact structure BG2 and the fourth source / drain contact structure CA4 can also be removed. The semiconductor device 20 may also include a first placeholder structure P1 formed on the bottom surface of the first source / drain region SD1 and a fourth placeholder structure P4 formed on the bottom surface of the fourth source / drain region SD4. The placeholder structures P1 and P4 may be formed of a material including silicon germanium (SiGe) or silicon oxide (such as SiO, SiO 2 etc.), but are not limited thereto. Since the first source / drain contact structure and the fourth source / drain contact structure may have been formed on the first source / drain region SD1 and the fourth source / drain region SD4, respectively, rather than being formed as backside source / drain contact structures, before the start of the backside process of the semiconductor device 20, the placeholder structures P1 and P4 may have been formed to reserve space for the formation of the backside source / drain contact structures and the placeholder structures P1 and P4 remain in the semiconductor device 20. However, the second placeholder structure P2, the third placeholder structure P3, and the fifth placeholder structure P5 formed together with the first placeholder structure P1 and the fourth placeholder structure P4 are replaced with the backside source / drain contact structures BC1 to BC3 in the same backside process. Although the current embodiment of the semiconductor device 20 includes the placeholder structures P1 and P5, according to another embodiment, the semiconductor device 20 may be configured not to include these two placeholder structures. This is because the corresponding front side source / drain channel structures CA1 and CA4 are formed to connect the first source / drain region and the fourth source / drain region to a voltage source or other circuit elements, and thus backside source / drain contact structures are not required to replace the placeholder structures P1 and P5. In addition to the backside contact structures BC1 to BC3, BG1 and BG3, and the dummy structures P1 and P4, the semiconductor device 20 further includes the contact spacer 103 briefly described previously. The contact spacer 103 may include side spacers 103A and bottom spacers 103B surrounding each of the backside source / drain contact structures BC1 to BC3 and the dummy structures P1 and P4. The side spacers 103A may be formed on the side surfaces of each of the backside source / drain contact structures BC1 to BC3 and the dummy structures P1 and P4, except for a small upper portion in contact with the bottom isolation layer 102. In contrast, the bottom spacers 103B may be formed on the bottom surfaces of each of the dummy structures P1 and P4 and surrounded by the side spacers 103A. However, the bottom spacers 103B may also have been formed at the corresponding positions before the formation of the backside source / drain contact structures BC1 to BC3 and surrounded by the side spacers 103A located on the side surfaces of each of the backside source / drain contact structures BC1 to BC3. However, during the backside process of the semiconductor device 20, the bottom spacers 103B may have been removed to form the backside source / drain contact structures BC1 to BC3, as will be described later. By the above structural formation of the backside contact structures BC1 to BC3, BG1 and BG2, and the side spacers 103A and the bottom spacers 103B, their bottom surfaces may be coplanar with each other. The contact spacer 103 may be formed of one or more materials including silicon nitride (such as SiN, SiBCN, SiOCN, etc.) to provide an additional or alternative isolation profile to the backside of the semiconductor device 20. The side spacers 103A and the bottom spacers 103B may have been formed at different steps in the backside process, as will be described later. Therefore, even if the side spacers 103A and the bottom spacers 103B are formed of the same material, there may still be a boundary, a connection surface, or a contact surface between the side spacers 103A and the bottom spacers 103B. According to another embodiment, the side spacers 103A and the bottom spacers 103B may be formed of different silicon nitride materials. For example, the side spacers 103A may include SiOCN, and the bottom spacers 103B may include SiN to have an etching selectivity relative to each other. In addition, the thickness TH2 of the bottom spacers 103B may be greater than the thickness TH1 of the side spacers 103A to support the self-aligned etching process to form the backside gate contact structures BG1 and BG2, as will be described later. Since the contact spacer 103 can prevent metal diffusion from the back-side source / drain contact structures BC1 to BC3, the contact spacer 103 can be used as an additional or alternative isolation structure between the first back-side source / drain contact structure BC1 and the adjacent back-side gate contact structure BG1 and between the third back-side source / drain contact structure BC3 and the adjacent second back-side gate contact structure BG2 in the back-side isolation structure 106 formed earlier than the contact spacer 103. In addition, during the back-side process of the semiconductor device 20, the contact spacer 103 can enable the back-side gate contact structures BG1 and BG2 to be formed in a self-aligned manner to contact the bottom surfaces of the second gate structure G2 and the fifth gate structure G5, respectively. For example, since the back-side isolation structure 106 has an etching selectivity with respect to the contact spacer 103, the contact spacer 103 can function in the back-side process of the semiconductor device 20 by compensating for possible masking / etching / deposition misalignments between the first back-side gate contact structure BG1 and the bottom surface of the second gate structure G2 and between the second back-side gate contact structure BG2 and the bottom surface of the fifth gate structure G5, as described below with reference to FIG. 3. FIG. 3 illustrates a semiconductor device including a back-side source / drain contact structure and a back-side gate contact structure according to another embodiment. Referring to FIG. 3, the semiconductor device 30 includes the same structural elements as the semiconductor device 20, including the back-side source / drain contact structures BC1 to BC3 having the contact spacer 103 thereon. Therefore, repeated descriptions may be omitted hereinafter. However, the semiconductor device 30 may be different from the semiconductor device 20 in that the first back-side gate contact structure BG1' and the second back-side gate contact structure BG2 are not precisely aligned with the bottom surfaces of the second gate structure G2 and the fifth gate structure G5, respectively. However, regardless of this misalignment, the back-side gate contact structures BG1' and BG2' can be self-aligned with the bottom surfaces of the gate structure G2 and the gate structure G5 along the side surfaces of the contact spacer 103 formed on the back-side source / drain contact structures BC1 and BC3, respectively. For example, the side surface of the first back-side gate contact structure BG1' facing the first back-side source / drain contact structure BC1 can contact the contact spacer 103 (103A) formed on the first back-side source / drain contact structure BC1. Similarly, the side surface of the second back-side gate contact structure BG2' facing the third back-side source / drain contact structure BC3 can contact the contact spacer 103 (103A) formed on the third back-side source / drain contact structure BC3. Therefore, the side surfaces of the back-side gate contact structures BG1' and BG2' that contact the contact spacer 103 can have a different profile from their opposite side surfaces, as shown in FIG. 3. Due to the above self-alignment, the back-gate contact structures BG1' and BG2' may not completely contact the bottom surfaces of the gate structures G2 and G5, but some portions of these back-gate contact structures may respectively contact the bottom surface of the lowermost inner spacer 104. For example, only a portion of the top surface of the first back-gate contact structure BG1' may contact the bottom surface of the second gate structure, and another portion of the top surface of the first back-gate contact structure BG1' may contact the bottom surface of the lowermost inner spacer 104. In addition, there may be no back isolation structure 106 between the contact spacer 103 and each of the back-gate contact structures BG1' and BG2'. Therefore, the first back-gate contact structure BG1' may be disposed closer to the second source / drain region SD2 than the first source / drain region SD1, and the second back-gate contact structure BG2' may be disposed closer to the fifth source / drain region SD5 than the fourth source / drain region SD4. However, similar to the semiconductor device 20, the first back-gate contact structure BG1' may be separated from the contact spacer 103 on the first occupancy structure P1 by the back isolation structure 106. Similarly, the second back-gate contact structure BG2' may be separated from the contact spacer 103 on the fourth occupancy structure P4. As will be described later with reference to FIGS. 4A to 4O, the above inaccurate alignment or misalignment of the back-gate contact structures BG1' and BG2' with the second gate structure G2 and the fifth gate structure G5 may be caused by one or more errors in the masking / etching / deposition operations in the backside process of the semiconductor device 30. However, the contact spacers 103 that enable the self-aligned formation of the back-gate contact structures BG1' and BG2' can sufficiently isolate these back-gate contact structures from the back-source / drain contact structures BC1 and BC3, respectively. Hereinafter, a method of manufacturing a semiconductor device corresponding to the semiconductor device 20 shown in FIG. 2 and the semiconductor device 30 shown in FIG. 3 will be described. FIGS. 4A to 4O illustrate intermediate semiconductor devices obtained after corresponding steps of manufacturing a semiconductor device including back-source / drain contact structures and back-gate contact structures according to an embodiment. Since the semiconductor device manufactured through the corresponding steps shown in FIGS. 4A to 4O may be the same as or may correspond to the semiconductor device 20 shown in FIG. 2, its repeated description may be omitted and the same reference numerals may be used in the following description. Referring to FIG. 4A, an intermediate semiconductor device 20' can be provided. The intermediate semiconductor device 20' includes a plurality of semiconductor stacks located on a substrate 101. These semiconductor stacks can include a first dummy gate structure G1' to a sixth dummy gate structure G6' each having corresponding hard mask patterns HM1 to HM6 thereon. Gate spacers 108 can be formed on side surfaces of each of the dummy gate structures G1' to G6' and each of the hard mask patterns HM1 to HM6. In addition, each of the semiconductor stacks can include a plurality of sacrificial layers 109 and channel layers 110 alternately stacked on the substrate 101, with a bottom isolation layer 102 located between the plurality of sacrificial layers 109 and channel layers 110 and the substrate 101. The sacrificial layers 109 in each of the semiconductor stacks and each of the dummy gate structures G1' to G6' will be replaced with gate structures G1 to G6 in a later step. Inner spacers 104 can be formed at side surfaces of the sacrificial layers 109. The dummy gate structures G1' to G6' can each be formed of amorphous silicon or polycrystalline silicon. The semiconductor stacks can be obtained by dividing a single initial semiconductor stack formed on the substrate 101 based on the hard mask patterns HM1 to HM6 through, for example, lithography, masking, and top-down etching operations to form five recesses R1 to R5 between the semiconductor stacks. These recesses R1 to R5 can reach an interior of the substrate 101 at a level lower than a top surface of the substrate 101 from a front side of the intermediate semiconductor device 20'. In subsequent steps, occupancy structures and source / drain regions respectively located above the occupancy structures will be formed in the recesses R1 to R5. Each of the sacrificial layers 109 can contain silicon germanium (SiGe), while each of the channel layers 110 can contain silicon (Si). The hard mask patterns HM1 to HM6 can contain silicon nitride or titanium nitride (such as SiN, Si 3 N 4 or TiN). Referring to FIG. 4B, the lower portions of the recesses R1 to R5 can be filled with occupancy structures P1 to P5 respectively. These occupancy structures can be retained to provide space for forming backside source / drain contact structures in a later step. For example, the dummy structures P1 to P5 can be formed by filling materials (such as SiGe) in the lower portions of the recesses R1 to R5 in the substrate 101 such that the top surfaces of each of the dummy structures P1 to P5 are located at the same horizontal height as the bottom surfaces of each of the inner spacers 104. The formation of the dummy structures P1 to P5 can be performed via, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof, and the dummy structures P1 to P5 are planarized by, for example, chemical mechanical polishing (CMP). Referring to FIG. 4C, the source / drain regions SD1 to SD5 can be respectively formed on the dummy structures P1 to P5 by epitaxially growing silicon included in the channel layer 110 exposed via the recesses R1 to R5. The source / drain regions SD1 to SD5 can be formed such that their bottom surfaces are respectively in contact with the first source / drain region SD1 to the fifth source / drain region SD5. Referring to FIG. 4D, the hard mask patterns HM1 to HM6 can be removed, and the front-side isolation structure 116 can be formed on the semiconductor stack of the intermediate semiconductor device 20' obtained in the previous step. In addition, the dummy gate structures G1' to G6' and the sacrificial layer 109 can be respectively replaced with the gate structures G1 to G6. Thus, the semiconductor stack of the intermediate semiconductor device 20' can form a corresponding nanosheet transistor structure, which is formed on the substrate 101. The hard mask patterns HM1 to HM6 can be removed via, for example, ashing, stripping, and / or etching operations, and the formation of the front-side isolation structure 116 can be performed via, for example, PVD, CVD, PECVD, or a combination thereof followed by CMP. The removal of the dummy gate structures G1' to G6' and the sacrificial layer 109 can be performed via, for example, dry etching, wet etching, reactive ion etching (RIE), and / or chemical oxide removal (COR) processes. The formation of the gate structures G1 to G6 can be performed via at least one of, for example, ALD, CVD, PVD, PECVD, etc. Although a backside process has been performed on the intermediate semiconductor device 20' to form the dummy structures P1 to P5 to reserve space for the formation of the corresponding backside contact structures, the circuit design may have been directed to the first front-side source / drain contact structure CA1 and the fourth front-side source / drain contact structure CA4 that are to be formed on the top surfaces of the first source / drain region SD1 and the fourth source / drain region SD4, respectively. Referring to FIG. 4E, the backside process of the intermediate semiconductor device 20' may continue with the removal of the substrate 101. After inverting the intermediate semiconductor device 20' obtained in the previous step, the substrate 101 may be removed, for example, by dry etching, wet etching, ashing, and / or stripping (but not limited thereto), to facilitate the backside process. Since the substrate 101 is removed, the bottom surface of the bottom isolation layer 102 and the bottom and side surfaces of each of the dummy structures P1 to P5 may be exposed. Referring to FIG. 4F, side spacers 103A may be conformally formed on the bottom surface of the bottom isolation layer 102 and the bottom and side surfaces of each of the dummy structures P1 to P5 that were exposed in the previous step. The formation of the side spacers 103A may be performed, for example, by atomic layer deposition (ALD) (but not limited thereto), such that the side spacers 103A may have the thickness TH1 shown in FIG. 2. Referring to FIG. 4G, the side spacers 103A may be partially patterned such that the side spacers 103A remain only on the side surfaces of the dummy structures P1 to P5. Such partial patterning of the side spacers 103A may be performed, for example, by anisotropic dry etching (such as reactive ion etching (RIE)), but not limited thereto. Referring to FIG. 4H, a backside isolation structure 106 may be formed to isolate the backside contact structures to be formed in a later step from the backside metal lines. The formation of the backside isolation structure 106 may be performed, for example, by PVD, CVD, PECVD, ALD, or a combination thereof, and the backside isolation structure 106 may be planarized, for example, by CMP (not limited thereto), such that the bottom surface of the backside isolation structure 106, the bottom surface of the side spacers 103A, and the bottom surfaces of the dummy structures P1 to P5 may be coplanar with each other. Referring to FIG. 4I, the dummy structures PL1 to PL5 may be partially recessed relative to the side spacers 103A. This may be performed, for example, by dry etching and / or wet etching based on an etchant (e.g., hydrofluoric acid (HF), nitric acid (HNO 3)(or a mixture thereof) selectively etches silicon germanium (SiGe) or silicon oxide (e.g., SiO or SiO 2 ) to perform partial recesses of the dummy structures PL1 to PL5. In this step, each of the dummy structures PL1 to PL5 may be recessed from its bottom surface to form a recess R surrounded by a lower portion of the side spacer 103A. The recess R may have the same depth as the thickness TH2 of the bottom spacer 103B to be formed in the recess R in the next step. Referring to FIG. 4J, the recess R formed under each of the dummy structures PL1 to PL5 in the previous step may be filled with the bottom spacer 103B to finally form the contact spacer 103 together with the previously formed side spacer 103A. A material (e.g., silicon nitride (e.g., SiN, SiBCN, SiOCN, SiOC, etc.)) may be filled into the recess R via, for example, PVD, CVD, PECVD, etc. to form the bottom spacer 103B, and the bottom spacer 103B may be planarized by, for example, CMP, but is not limited thereto. Thus, the bottom spacer 103B may have the same thickness TH2 as the depth of the recess R. When the bottom spacer 103B is formed in the recess R and planarized, the bottom spacer 103B and the side spacer 103A together may form the contact spacer 103 surrounding the side surfaces and the bottom surface of each of the dummy structures PL1 to PL5. In addition, the bottom surface of the backside isolation structure 106 and the bottom surface of the contact spacer 103 may be coplanar with each other again. Referring to FIG. 4K, a photoresist layer or a hard mask structure may be formed on the bottom surface of the backside isolation structure 106, and the photoresist layer or the hard mask structure may be patterned to form a first mask structure 107 having two openings O1 and O2 that expose the bottom surface of the backside isolation structure 106. The openings O1 and O2 may be formed to be vertically aligned or corresponding to the bottom surfaces of the second gate structure G2 and the fifth gate structure G5, such that the subsequent etching operations via the openings O1 and O2 in the next step may expose the bottom surfaces of the second gate structure G2 and the fifth gate structure G5. Referring to FIG. 4L, the backside isolation structure 106 and the bottom isolation layer 102 can be patterned based on the first masking structure 107 to form two holes H1 and H2, and the bottom surfaces of the second gate structure G2 and the fifth gate structure G5 are respectively exposed by the two holes H1 and H2. These two holes H1 and H2 will be filled with the materials for forming the backside gate contact structures BG1 and BG2 in the next step. Etching agents (such as hydrofluoric acid (HF), but not limited thereto) that have etching selectivity for silicon nitride (such as SiN, SiBCN, SiOCN, etc.) for forming the contact spacer 103 can be used via, for example, dry etching or wet etching to perform patterning on the backside isolation structure 106 and the bottom isolation layer 102 that can be formed by silicon oxide (such as SiO, SiO 2 etc.). Since the silicon nitride of the contact spacer 103 can withstand this selective etching, the misalignment masking and etching operations on the backside isolation structure 106 will not damage the adjacent contact spacers 103 and the occupation structures P2 and P5 that are surrounded by the contact spacers 103 and will be replaced with the backside source / drain contact structures BC2 and BC5 respectively. Such possible misalignment masking and etching will be described later with reference to FIGS. 5A to 5C. Referring to FIG. 4M, the holes H1 and H2 in the backside isolation structure 106 can be filled with the materials for forming the first backside gate contact structure BG1 and the second backside gate contact structure BG2 respectively via, for example, PVD, CVD, PECVD or a combination thereof (not limited thereto), and the first masking structure 107 can be removed via, for example, ashing or stripping. In addition, the bottom surface of the intermediate semiconductor device 20' including the backside gate contact structures BG1 and BG2 can be planarized via, for example, CMP. Referring to FIG. 4N, a second masking structure 107 aligned with the second occupation structure P2, the third occupation structure P3 and the fifth occupation structure P5 can be formed on the bottom surface of the intermediate semiconductor device 20' obtained in the previous step, and based on the second masking structure 107, the bottom spacer 103B and the occupation structures P2, P3 and P5 located on the bottom spacer 103B can be removed via dry etching and / or wet etching to form holes H3, H4 and H5, and the bottom surfaces of the second source / drain region SD2, the third source / drain region SD3 and the fifth source / drain region SD5 are respectively exposed by the holes H3, H4 and H5. For example, the bottom spacer 103B can be removed based on the second masking structure 107 via dry etching and / or wet etching, and the occupation structures P2, P3, and P5 formed of silicon germanium (SiGe) or silicon oxide (such as SiO, SiO 2 ), which is not limited thereto) can be used to selectively etch the silicon germanium (SiGe) forming the occupation structures P2 and P5 based on the side spacers 103A via dry etching and / or wet etching relative to the silicon nitride (such as SiN, SiBCN, SiOCN, etc.) forming the side spacers 103A. 3 ). The occupation structures P2 and P5 formed of silicon germanium (SiGe) are removed. Therefore, each of the holes H3, H4, and H5 formed by the selective etching operation can be surrounded by the contact spacer 103 (103A) to expose the bottom surfaces of the second source / drain region SD2, the third source / drain region SD3, and the fifth source / drain region SD5, respectively. Referring to FIG. 4O, the holes H3, H4, and H5 obtained in the previous step can be filled with the materials forming the second back-side source / drain contact structure BC1, the third back-side source / drain contact structure BC2, and the fifth back-side source / drain contact structure BC3, respectively, via, for example, PVD, CVD, PECVD, or a combination thereof (which is not limited thereto), and the second masking structure 107 can be removed via, for example, ashing or stripping. In addition, the bottom surface of the intermediate semiconductor device 20' including the back-side source / drain contact structures BC1, BC2, and BC3 and the back-side gate contact structures BG1 and BG2 can be planarized via, for example, CMP. Subsequently, one or more back-side metal lines can be connected to the back-side gate contact structures BG1 and BG2 to deliver the corresponding gate input signals or a common gate input signal to the gate structures G2 and G5, respectively, via the back-side gate contact structures BG1 and BG2. And, another one or more back-side metal lines can be connected to the back-side source / drain contact structures BC1 to BC3 to connect the source / drain regions SD2, SD3, and SD5 to one or more voltage sources or other circuit elements via the back-side source / drain contact structures BC1 to BC3, thereby obtaining the semiconductor device 20 shown in FIG. 2. Meanwhile, referring back to FIG. 4H, the first masking structure may be inaccurately patterned, and thus, the openings O1 and O2 in the nanoscale device structure may be misaligned with the bottom surfaces of the gate structures G2 and G5, respectively. As a result, subsequent etching and deposition operations in the backside process may also prevent the connection between the backside contact structures to be formed in the backside isolation structure 106. However, the contact spacers 103 surrounding the occupancy structures P1 to P5 can function in the backside process by compensating for the masking / etching / deposition misalignment, as described below. FIGS. 5A to 5C illustrate intermediate semiconductor devices obtained after corresponding steps of manufacturing a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to other embodiments. Referring to FIG. 5A, the intermediate semiconductor device 30' may have the same structural elements as the intermediate semiconductor device 20' of FIG. 4I, but the openings O1' and O2' of the masking structure 107' may be formed to be misaligned or inaccurately aligned with the bottom surfaces of the gate structures G2 and G5 in the vertical direction. Referring to FIG. 5B, since the masking structure 107' has misaligned openings O1' and O2', the etching operation performed on the backside isolation structure 106 based on the masking structure 107' may form corresponding holes H1' and H2' that may also be misaligned or inaccurately aligned with the bottom surfaces of the gate structures G2 and G5, respectively. As a result, the contact spacers 103 can be exposed through the holes H1 and H2. However, when an etchant (e.g., hydrofluoric acid (HF)) for dry etching and / or wet etching is applied to the contact spacers 103 during the formation of the holes H1' and H2', the contact spacers 103 formed of silicon nitride (e.g., SiN, SiBCN, SiOCN, etc.) can withstand the selective etching operation for the backside isolation structure 106 formed of silicon oxide (e.g., SiO, SiO2, etc.). Therefore, the contact spacers 103 can prevent the etchant from reaching the backside source / drain contact structures BC1 and BC3, respectively, which may subsequently disrupt the formation of the backside source / drain contact structures BC1 and BC3 in a later step. Due to this selective etching operation, the holes H1' and H2' can be formed along the side surfaces of the contact spacers 103 to expose the bottom surfaces of the gate structures G2 and G5 and further expose the bottom surface of the lowermost inner spacer 104. Meanwhile, the openings O1' and O2' can be further misaligned with the bottom surfaces of the gate structures G2 and G5 respectively, such that at least a portion of the openings can be aligned with the dummy structures P2 and P5 to expose the bottom surface of the side spacer 103A and even expose the bottom surface of the bottom spacer 103B. However, even in such a case, since the contact spacer 103 has an etching selectivity relative to the backside isolation structure 106, selective etching can form self-aligned holes leading to the bottom surfaces of the gate structures G2 and G5 without damaging the dummy structures P2 and P5. In such a case, the bottom spacer 103B can be exposed to the etchant more or for a longer time than the side spacer 103A. Therefore, the bottom spacer 103B can be formed to have a thickness TH2 greater than the thickness TH1 of the side spacer 103A to better withstand selective etching. Referring to FIG. 5C, backside gate contact structures BG1' and BG2' can be formed in a self-aligned manner in the holes H1' and H2' respectively, for example, by PVD, CVD, PECVD or a combination thereof (not limited thereto), and the backside gate contact structures BG1' and BG2' can be planarized. In addition, backside source / drain contact structures BC1 to BC3 can be formed in the same process as described with reference to FIGS. 4N and 4O to obtain the semiconductor device 30 shown in FIG. 3. FIG. 6 illustrates a flowchart of a method of manufacturing a semiconductor device including a backside source / drain contact structure and a backside gate contact structure with reference to FIGS. 4A to 4O according to an embodiment. In step S10, a plurality of dummy structures can be formed on the bottom surfaces of a plurality of source / drain regions in a substrate of an intermediate semiconductor device. See FIGS. 4A to 4D. Dummy structures can be formed in the substrate to reserve space for forming corresponding backside source / drain contact structures. The dummy structures can be formed of materials such as silicon germanium (SiGe) or silicon oxide (such as SiO, SiO 2 etc.). In step S20, the substrate is removed and replaced with a backside isolation structure, and contact spacers can be formed to surround the side surfaces and bottom surfaces of each of the dummy structures. See FIGS. 4E to 4J. The backside process starts with removing the substrate and forming a backside isolation structure at the place where the substrate has been removed. To perform the backside process, the intermediate semiconductor device can be flipped so that the direction of the bottom surface of the backside source / drain contact structure is in the upward direction. Contact spacers may be formed on the side and bottom surfaces of the dummy structure to protect the dummy structure during subsequent etching operations performed on the backside isolation structure. When the semiconductor device is completed, the contact spacers may also serve as additional or alternative isolation profiles of the semiconductor device. The contact spacers may be formed of one or more materials including silicon nitride (such as SiN, SiBCN, SiOCN, etc.). In step S30, the backside isolation structure may be etched based on the contact spacers to form holes exposing the bottom surface of at least one gate structure. Refer to FIGS. 4K and 4L. For this step, a masking structure (e.g., a photoresist pattern or a hard mask pattern having at least one opening aligned with at least one gate structure in the vertical direction) may be formed on the bottom surface of the backside isolation structure, and the backside isolation structure may be etched based on the masking structure to form holes exposing the bottom surface of the gate structure. At this time, even when the opening is formed to be misaligned with the bottom surface of the gate structure, the holes will still be formed to expose the contact spacers. However, due to the etching selectivity between the backside isolation structure and the contact spacers, the holes may be formed in a self-aligned manner along the contact spacers to expose the bottom surface of the gate structure. In step S40, a backside gate contact structure connected to the bottom surface of the backside gate contact structure may be formed in the holes. Refer to FIG. 4M. Since the backside gate contact structure may be formed based on the contact spacers, the backside gate contact structure may be sufficiently isolated from the dummy structure. In step S50, at least one dummy structure may be removed to form holes surrounded by the contact spacers and exposing the bottom surface of at least one source / drain region, and a backside source / drain contact structure connected to the bottom surface of the source / drain region may be formed in the holes. Refer to FIGS. 4N and 4O. When the dummy structure is removed, the contact spacers surrounding the dummy structure may remain, and thus the backside source / drain contact structure may be formed inside the contact spacers, such that the backside source / drain contact structure is sufficiently isolated from the backside isolation structure and / or the backside gate contact structure. The above embodiments have been described with respect to manufacturing a semiconductor device including multiple nanosheet field-effect transistors. However, the present disclosure is not limited thereto, but may also be applicable to semiconductor devices including different types of field-effect transistors (e.g., finFETs). In addition, the above embodiments may be applicable to a three-dimensional stacked field-effect transistor device (3D-stacked FET device) formed of a lower stacked field-effect transistor and an upper stacked field-effect transistor. For example, at least one selected back-gate contact structure and / or at least one selected back-source / drain contact structure may be formed for the circuit elements of the lower stacked field-effect transistor, while at least one selected front-gate structure and / or at least one selected front-source / drain contact structure may be formed for the circuit elements of the upper stacked field-effect transistor. FIG. 7 is a schematic block diagram of an electronic device according to an embodiment, illustrating at least one of the semiconductor devices shown in FIGS. 2 and 3. Referring to FIG. 7, the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device, such as a smart phone or a tablet computer, but is not limited thereto. The processor 1100 may include a central processing unit (CPU), a graphic processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving an input and at least one of a display, a speaker, etc. for generating an output signal to be processed by the processor 1100. The storage 1400 may be implemented to store user data, output signals, etc. input via the input / output module 1300. The storage 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc. The buffer RAM module 1500 can temporarily store data for the processing operations of the electronic device 1000. For example, the buffer RAM module 1500 can include volatile memory, such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus DRAM (RDRAM), and so on. Although not shown in FIG. 7, the electronic device 1000 can further include at least one sensor, such as an image sensor. According to an embodiment, at least one component in the electronic device 1000 can be formed based on at least one of the semiconductor devices shown in FIGS. 2 and 3. The foregoing is an illustration of exemplary embodiments and should not be construed as limiting the disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the above embodiments without substantially departing from the disclosure. 10, 20, 30: Semiconductor device 20': Intermediate semiconductor device 101: Substrate 102: Bottom isolation layer 103: Contact spacer 103A: Side spacer 103B: Bottom spacer 104: Inner spacer 106: Backside isolation structure 107: Second masking structure 107': Masking structure 108: Gate spacer 109: Sacrificial layer 110: Nanowire channel layer / Channel layer 116: Isolation structure 1000: Electronic device 1100: Processor 1200: Communication module 1300: Input / output module 1400: Memory 1500: Buffer random access memory (RAM) module BC1: Backside contact structure / Backside source / drain contact structure / First backside source / drain contact structure BC2: Backside contact structure / Backside source / drain contact structure / Second backside source / drain contact structure BC3: Backside contact structure / Third backside source / drain contact structure / Backside source / drain contact structure BG1: First backside gate contact structure / Backside contact structure BG1': First backside gate contact structure / Backside gate contact structure BG2: Second backside gate contact structure / Backside contact structure BG2': Second backside gate contact structure / Backside gate contact structure CA1: First source / drain contact structure / Contact structure / Channel structure / Source / drain contact structure / Front side source / drain channel structure CA2: Second source / drain contact structure / Contact structure / Channel structure / Source / drain contact structure CA3: Third source / drain contact structure / Contact structure / Channel structure CA4: Fourth source / drain contact structure / Contact structure / Channel structure / Source / drain contact structure / Front side source / drain channel structure CA5: Fifth source / drain contact structure / Contact structure / Source / drain contact structure / Channel structure CB1: First gate contact structure / Contact structure / Channel structure CB2: Second gate contact structure / Contact structure / Channel structure D1: Channel length direction D2: Channel width direction D3: Vertical direction DT1: Distance G1: First gate structure / Gate structure G1': First dummy gate structure / Dummy gate structure G2: Second gate structure / Gate structure G2': Second dummy gate structure / Dummy gate structure G3: Third gate structure / Gate structure G3': Third dummy gate structure / Dummy gate structure G4: Fourth gate structure / Gate structure G4': Fourth dummy gate structure / Dummy gate structure G5: Fifth gate structure / Gate structure G5': Fifth dummy gate structure / Dummy gate structure G6: Sixth gate structure / Gate structure G6': Sixth dummy gate structure / Dummy gate structure H1, H1', H2, H2', H3, H4, H5: Hole I-I': Line NT1: First nanowire transistor NT2: Second nanowire transistorO1, O1', O2, O2': Openings P1: First Occupancy Structure / Occupancy Structure P2: Second Occupancy Structure / Occupancy Structure P3: Third Occupancy Structure / Occupancy Structure P4: Fourth Occupancy Structure / Occupancy Structure P5: Fifth Occupancy Structure / Occupancy Structure R, R1, R2, R3, R4, R5: Recesses S10, S20, S30, S40, S50: Steps SD1: First Source / Drain Region / Source / Drain Region SD2: Second Source / Drain Region / Source / Drain Region SD3: Third Source / Drain Region / Source / Drain Region SD4: Fourth Source / Drain Region / Source / Drain Region SD5: Fifth Source / Drain Region / Source / Drain Region TH1, TH2: Thickness Referring to the following detailed description in conjunction with the accompanying drawings, the exemplary embodiments of the present disclosure will be more clearly understood. In the drawings: FIG. 1A illustrates a top plan view of a semiconductor device in which a plurality of gate structures and source / drain regions are formed to constitute corresponding field effect transistors. FIG. 1B illustrates a cross-sectional view in the D1 direction along the line I-I' shown in FIG. 1A of the semiconductor device shown in FIG. 1A according to an embodiment. FIG. 2 illustrates a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to an embodiment. FIG. 3 illustrates a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to another embodiment. FIGS. 4A to 4O illustrate intermediate semiconductor devices obtained after corresponding steps of manufacturing a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to an embodiment. FIGS. 5A to 5C illustrate intermediate semiconductor devices obtained after corresponding steps of manufacturing a semiconductor device including a backside source / drain contact structure and a backside gate contact structure according to other embodiments. FIG. 6 illustrates a flowchart of a method for manufacturing a semiconductor device including a backside source / drain contact structure and a backside gate contact structure with reference to FIGS. 4A to 4O according to an embodiment. FIG. 7 is a schematic block diagram of an electronic device including at least one of the semiconductor devices shown in FIGS. 2 and 3 according to an embodiment. 20: Semiconductor device 102: Bottom isolation layer 103: Contact spacer 103A: Side spacer 103B: Bottom spacer 104: Inner spacer 106: Backside isolation structure 108: Gate spacer 110: Nanowire channel layer / Channel layer 116: Isolation structure BC1: Backside contact structure / Backside source / drain contact structure / First backside source / drain contact structure BC2: Back contact structure / Back source / drain contact structure / Second back source / drain contact structure 1 BC3: Back contact structure / Third back source / drain contact structure / Back source / drain contact structure BG1: First back gate contact structure / Back contact structure BG2: Second back gate contact structure / Back contact structure CA1: First source / drain contact structure / Contact structure / Channel structure / Source / drain contact structure / Front side source / drain channel structure CA4: Fourth source / drain contact structure / Contact structure / Channel structure / Source / drain contact structure / Front side source / drain channel structure G1: First gate structure / Gate structure G2: Second gate structure / Gate structure G3: Third gate structure / Gate structure G4: Fourth gate structure / Gate structure G5: Fifth gate structure / Gate structure G6: Sixth gate structure / Gate structure P1: First occupancy structure / Occupancy structure P4: Fourth occupancy structure / Occupancy structure SD1: First source / drain region / Source / drain region SD2: Second source / drain region / Source / drain region SD3: Third source / drain region / Source / drain region SD4: Fourth source / drain region / Source / drain region SD5: Fifth source / drain region / Source / drain region TH1, TH2: Thickness

Claims

1. A semiconductor device, comprising: First source / drain region; Second source / drain region; The channel structure connects the first source / drain region to the second source / drain region; A gate structure configured to control the channel structure; a back-side isolation structure located at the lower portion of the semiconductor device; a back-side source / drain contact structure connected to the bottom surface of the first source / drain region in the back-side isolation structure; a first contact spacer located on the back-side source / drain contact structure; a occupant structure connected to the bottom surface of the second source / drain region; and a second contact spacer located on the occupant structure, the second contact spacer isolating the occupant structure from another circuit element in the back-side isolation structure, wherein the first contact spacer is configured to isolate the back-side source / drain contact structure from another circuit element in the back-side isolation structure, wherein the second contact spacer includes: a side spacer located on the side surface of the occupant structure; And a bottom spacer, located on the bottom surface of the occupant structure, wherein the side spacers and the bottom spacer are formed of different silicon nitride materials.

2. The semiconductor device of claim 1, wherein the first contact spacer is formed on a side surface of the back-side source / drain contact structure, and the first contact spacer comprises an insulating material.

3. The semiconductor device as claimed in claim 1, further comprising: A back-side gate contact structure is connected to the bottom surface of the gate structure.

4. The semiconductor device of claim 3, wherein the back-side isolation structure is formed between the back-side gate contact structure and the first contact spacer.

5. The semiconductor device as claimed in claim 3, wherein the back-side gate contact structure contacts the first contact spacer.

6. The semiconductor device as claimed in claim 1, further comprising a front-side source / drain contact structure connected to the second source / drain region.

7. The semiconductor device of claim 3, wherein the back-side gate contact structure is formed between the first contact spacer and the second contact spacer.

8. A semiconductor device, comprising: First source / drain region; Second source / drain region; The channel structure connects the first source / drain region to the second source / drain region; A gate structure configured to control the channel structure; a back-side isolation structure located at the lower portion of the semiconductor device; a back-side gate contact structure connected to the bottom surface of the gate structure in the back-side isolation structure; a berth structure connected to the bottom surface of the second source / drain region; and a second contact spacer located on the berth structure, the second contact spacer isolating the berth structure from another circuit element in the back-side isolation structure, wherein the second contact spacer includes: a side spacer located on the side surface of the berth structure; and a bottom spacer located on the bottom surface of the occupant structure, wherein the side spacers and the bottom spacers are formed of different silicon nitride materials, wherein the back gate contact structure is not aligned with the bottom surface of the gate structure to be closer to the second source / drain region than the first source / drain region.

9. The semiconductor device of claim 8, wherein a portion of the back-side gate contact structure does not contact the bottom surface of the gate structure.

10. The semiconductor device of claim 9, wherein the portion of the back-side gate contact structure that does not contact the bottom surface of the gate structure is formed on the bottom surface of the inner spacer between the gate structure and the first source / drain region.

11. The semiconductor device of claim 9, wherein the back-side gate contact structure is formed closer to the first source / drain region than the second source / drain region.

12. The semiconductor device as claimed in claim 8, further comprising: A back-side source / drain contact structure is connected to the bottom surface of the first source / drain region; And a first contact spacer located on the back-side source / drain contact structure, the first contact spacer being configured to isolate the back-side source / drain contact structure from another circuit element in the back-side isolation structure.

13. The semiconductor device of claim 12, wherein the back-side gate contact structure contacts the first contact spacer.

14. The semiconductor device as claimed in claim 8, further comprising a front-side source / drain contact structure connected to the second source / drain region.

15. A method of manufacturing a semiconductor device as described in any one of claims 1 to 14, comprising: A spacer structure is formed on the bottom surface of the source / drain region; a contact spacer is formed on the spacer structure; A back-side gate contact structure is formed on the bottom surface of the gate structure; and the occupant structure is replaced with a back-side source / drain contact structure such that the back-side source / drain contact structure is surrounded by the contact spacer.

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