Semiconductor device layout, semiconductor device structure, and method of manufacturing the same

Abstract

A gate layout and / or apparatus for implementing a gate support structure (e.g., a gate bar) in a non-active region (e.g., an isolation region) and a method of manufacturing the same are described. An exemplary gate support structure is connected to at least two gates (e.g., two to six in some embodiments) disposed in the non-active region. The aforementioned at least two gates extend longitudinally along a first direction, and the gate support structure extends longitudinally along a second direction different from the first direction. The gate support structure and the aforementioned at least two gates may be disposed on a substrate isolation structure, such as a shallow trench isolation structure. The composition and / or configuration of the gate support structure may be the same as or different from the composition and / or configuration of the aforementioned at least two gates.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to gate bars located in isolation regions. Prior Art

[0002] The semiconductor integrated circuits (IC) industry has experienced exponential growth. Advancements in modern technology in integrated circuit materials and design have produced several generations of integrated circuits, each of which has smaller and more complex circuits compared to the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnect devices per unit wafer area) generally increases while the geometry size (i.e., the smallest element (or line) that can be produced using the process) decreases. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization also increases the complexity of producing and manufacturing integrated circuits, and similar advancements in integrated circuit production and manufacturing are required to achieve these progressions. Summary of the Invention

[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device structure, including forming an active region in a device region, where the active region extends longitudinally along a first direction and laterally along a second direction; forming isolation structures in the device region and an isolation region, where the isolation structures in the device region are adjacent to the active region; and forming a plurality of first gates above the active region and the isolation structures in the device region, forming a plurality of second gates above the isolation structures in the isolation region, and forming a third gate above the isolation structures in the isolation region, where the first gates and the second gates extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates.

[0004] Embodiments of the present invention provide a semiconductor device structure, including a plurality of first gates extending longitudinally along a first direction in a device region, where the first gates are disposed above isolation structures and an active region, the first gates have a first height above the isolation structures and a second height above the active region, and the first height is greater than the second height; a plurality of second gates extending longitudinally along the first direction in an isolation region, where the second gates are disposed above the isolation structures, the second gates have a third height above the isolation structures, and the third height is greater than the second height; and a gate support bar extending longitudinally along a second direction in the isolation region, where the second direction is different from the first direction, the gate support bar is disposed above the isolation structures, and the gate support bar is connected to at least two of the second gates.

[0005] An embodiment of the present invention provides a semiconductor device layout, including a first active gate wire, a second active gate wire, a first dummy gate wire, and a second dummy gate wire, longitudinally oriented along a first direction; a dummy gate support bar, longitudinally oriented along a second direction different from the first direction, wherein the dummy gate support bar extends from the first dummy gate wire to the second dummy gate wire along the second direction; and an active region, longitudinally oriented along the second direction, wherein the first active gate wire and the second active gate wire are disposed above the active region. Brief Description of the Drawings

[0006] Embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various elements can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. FIG. 1 is a flowchart showing a method of manufacturing a part or the whole of a device having a gate support structure according to various aspects of the present disclosure. FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A are top views showing a part or the whole of a device (e.g., a fully-depleted surround gate transistor or a fin field effect transistor) at various manufacturing stages, such as those related to the method in FIG. 1, according to various aspects of the present disclosure. FIGS. 2B, 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional views showing a part or the whole of the device along the section line B-B of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A, respectively, according to various aspects of the present disclosure. FIGS. 2C, 3C, 4C, 5C, 6C, 7C, and 8C are cross-sectional views showing a part or the whole of the device along the section line C-C of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A, respectively, according to various aspects of the present disclosure. FIGS. 2D, 3D, 4D, 5D, 6D, 7D, and 8D are cross-sectional views showing a part or the whole of the device along the section line D-D of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A, respectively, according to various aspects of the present disclosure. FIGS. 3E, 4E, 5E, 6E, 7E, and 8E are cross-sectional views showing a part or the whole of the device along the section line E-E of FIGS. 3A, 4A, 5A, 6A, 7A, and 8A, respectively, according to various aspects of the present disclosure. The 3F, 4F, 5F, 6F, 7F diagrams and the 8F diagram respectively show schematic cross-sectional views of part or all of the device along the section line F-F of the 3A, 4A, 5A, 6A, 7A diagrams and the 8A diagram, according to various aspects of the present disclosure. The 7G diagram and the 8G diagram respectively show schematic cross-sectional views of part or all of the device along the section line G-G of the 7A diagram and the 8A diagram, according to various aspects of the present disclosure. The 9, 10, 11 diagrams and the 12 diagram show different top views of part or all of the devices of the 2A, 3A, 4A, 5A, 6A, 7A diagrams and the 8A diagram after performing the processes related to the 2A, 2B, 2C, 2D diagrams and the 3A, 3B, 3C, 3D diagrams, according to various aspects of the present disclosure. The 13A diagram shows a top view and a schematic cross-sectional view of part or all of the device without a gate support structure, according to various aspects of the present disclosure. The 13B diagram shows a top view and a schematic cross-sectional view of part or all of the device with a gate support structure, according to various aspects of the present disclosure. The 14A, 14B diagrams and the 14C diagram show various schematic views of part or all of the device with a gate support structure. The device can be manufactured according to the method of the 1st diagram and is configured and arranged according to the design rules. The 15 diagram shows a flowchart of a method for manufacturing part or all of the device with a gate support structure, according to various aspects of the present disclosure. Embodiments

[0007] The present invention relates to the gate layout of a device, such as the gate layout of a gate-all-around (GAA) transistor and the device formed thereby.

[0008] The following disclosure provides numerous examples or embodiments for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is stated that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "higher", etc. and their derivatives such as "horizontally", "downwardly", "upwardly", etc., to facilitate the description of the relationship between one (or more) components or features in a drawing and another (or more) components or features. Spatially relative terms are intended to include different orientations of the device during use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after turning. Even further, when using terms such as "about", "approximately" to describe a number or a range of numbers, such terms are intended to encompass numbers within a reasonable range, which is considered based on the variations that inherently occur during the manufacturing process as understood by those of ordinary skill in the art. For example, based on the known manufacturing tolerances for manufacturing components with features related to that number, the quantity or range of numbers encompasses a reasonable range including the stated number, such as within + / −10% of the stated number. For example, those of ordinary skill in the art know that the manufacturing tolerance related to depositing a material layer is + / −10%, and a material layer with a thickness of "about 5 nanometers" can cover a size range from 4.5 nanometers to 5.5 nanometers. Additionally, embodiments of the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed.

[0009] The present disclosure describes a gate layout and / or device and a method of manufacturing the same that implement a gate support structure (e.g., a gate bar) to reduce peeling, collapsing, bending, etc. of gates in a non-active region (e.g., an isolation region). An exemplary gate support structure is connected to at least two gates (e.g., two to six in some embodiments) disposed in the non-active region. The at least two gates extend longitudinally along a first direction, and the gate support structure extends longitudinally along a second direction different from the first direction. The gate support structure and the at least two gates may be disposed on a substrate isolation structure such as a shallow trench isolation (STI) structure. The gate support structure may be formed simultaneously with the at least two gates. The composition and / or configuration of the gate support structure may be the same as or different from the composition and / or configuration of the at least two gates. In some embodiments, the gate support structure and the at least two gates may be a polysilicon bar and a polysilicon gate, respectively. In some embodiments, the gate support structure and the at least two gates each include a gate dielectric and a gate electrode. In some embodiments, the gate support structure and the at least two gates are formed simultaneously with the gate of a transistor (i.e., the active gate). The active gate may extend longitudinally along the first direction. In some embodiments, the gate support structure and the at least two gates are formed at different times from the active gate. The size of the gate support structure and / or the pitch between the gate support structure and other structures (e.g., source / drain contacts, gate isolation structures, etc.) may be configured to minimize the risk of electrical short circuits and / or minimize residual defects.

[0010] FIG. 1 is a flow diagram of a method 100 of fabricating a partial or entire device having a gate support structure, in accordance with various aspects of the present disclosure. At block 105, method 100 includes forming a plurality of first gates longitudinally extending in a first direction over an active region. The active region includes a plurality of active areas, and the active areas may include and / or be processed to have a plurality of channel structures and a plurality of source / drain regions, where the channel structures are disposed between respective source / drain regions. The first gates may be disposed over the channel structures. In some embodiments, the active region is a device region. At block 110, method 100 includes forming a plurality of second gates longitudinally extending in the first direction over a non-active region. The non-active region does not include active areas, and the non-active region may include and / or be processed to have isolation structures, such as substrate isolation structures. The second gates may be disposed over the isolation structures. In some embodiments, the isolation structures are also in the active region, the isolation structures may bound and / or surround the active areas, and the first gates may be disposed over the isolation structures. In some embodiments, the non-active region is an isolation region. At block 115, method 100 includes forming a gate support bar longitudinally extending in a second direction over the non-active region. The second direction is different from the first direction, and the gate support bar is connected to at least two second gates. The gate support bar may be disposed over the isolation structures. In some embodiments, the active areas longitudinally extend in the second direction. In some embodiments, the gate support bar is a third gate. In some embodiments, the first gates, the second gates, and the third gate are formed simultaneously. The present disclosure contemplates additional processes. Additional steps may be provided before, during, and after method 100, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of method 100. The following discussion illustrates various embodiments of devices that may be fabricated in accordance with method 100.

[0011] Figures 2A, 3A, 4A, 5A, 6A, 7A, and 8A are top schematic views showing part or all of device 200 at various manufacturing stages (such as related to method 100 in FIG. 1) according to various aspects of the present disclosure. Figures 2B, 3B, 4B, 5B, 6B, 7B, and 8B are cross-sectional schematic views (e.g., y-direction cross-section) showing part or all of device 200 along section line B-B of Figures 2A, 3A, 4A, 5A, 6A, 7A, and 8A respectively according to various aspects of the present disclosure. Figures 2C, 3C, 4C, 5C, 6C, 7C, and 8C are cross-sectional schematic views (e.g., x-direction cross-section) showing part or all of device 200 along section line C-C of Figures 2A, 3A, 4A, 5A, 6A, 7A, and 8A respectively according to various aspects of the present disclosure. Figures 2D, 3D, 4D, 5D, 6D, 7D, and 8D are cross-sectional schematic views (e.g., x-direction cross-section) showing part or all of device 200 along section line D-D of Figures 2A, 3A, 4A, 5A, 6A, 7A, and 8A respectively according to various aspects of the present disclosure. Figures 3E, 4E, 5E, 6E, 7E, and 8E are cross-sectional schematic views (e.g., y-direction cross-section) showing part or all of device 200 along section line E-E of Figures 3A, 4A, 5A, 6A, 7A, and 8A respectively according to various aspects of the present disclosure. Figures 3F, 4F, 5F, 6F, 7F, and 8F are cross-sectional schematic views (e.g., x-direction cross-section) showing part or all of device 200 along section line F-F of Figures 3A, 4A, 5A, 6A, 7A, and 8A respectively according to various aspects of the present disclosure. Figures 7G and 8G are cross-sectional schematic views (e.g., x-direction cross-section) showing part or all of device 200 along section line G-G of Figures 7A and 8A respectively according to various aspects of the present disclosure. Figures 9, 10, 11, and 12 are different top schematic views showing part or all of device 200 after performing processes related to Figures 2A, 2B, 2C, 2D, 3A, 3B, 3C, and 3D according to various aspects of the present disclosure. Figure 13A is a top and cross-sectional schematic view showing part or all of device 200 without a gate support structure according to various aspects of the present disclosure. Figure 13B is a top and cross-sectional schematic view showing part or all of device 200 with a gate support structure according to various aspects of the present disclosure. For ease of description and understanding, Figures 2A-8A, 2B-8B, 2C-8C, 2D-8D, 3E-8E, 3F-8F, 7G-8G, 9-12, 13A, and 13B are discussed simultaneously in the present disclosure and are simplified for clarity to better understand the inventive concept of the present disclosure.Additional components may be added to the device 200, and some of the described components may be replaced, modified, or eliminated in other embodiments of the device 200.

[0012] The device 200 may include a device region 202A, a device region 202B, and an isolation region 204 between the device region 202A and the device region 202B. As described herein, the device 200 may be processed to form transistors, such as gate-all-around (GAA) transistors, in the device regions 202A and 202B. In some embodiments, the device region 202A is processed to form n-type GAA transistors therein, and the device region 202B is processed to form p-type GAA transistors therein, or vice versa. In some embodiments, the device region 202A and / or the device region 202B are processed to form n-type GAA transistors and p-type GAA transistors therein. In such embodiments, the device regions 202A and 202B may include complementary metal-oxide semiconductor (CMOS) transistors. The isolation region 204 is configured to electrically isolate the device region 202A and the device region 202B. For example, the isolation region 204 may electrically isolate the transistors in the device region 202A from the transistors in the device region 202B.

[0013] Referring to FIGS. 2A-2D, a fin manufacturing process can be performed to form fins extending from a substrate (wafer) 206, such as fins 208A and 208B (also referred to as fin structures, fin elements, etc.) extending from the substrate 206. Fin 208A is disposed in device region 202A, and fin 208B is disposed in device region 202B. Fins 208A and 208B extend substantially parallel to each other along direction x, having a length in direction x, a width in direction y, and a height in direction z. For example, fin 208A has a width W1, and fin 208B has a width W2. In the illustrated embodiment, fins 208A and 208B have the same width (i.e., width W1 is the same as width W2), and fin 208A is centered-aligned with fin 208B along direction x. Fins 208A and 208B are thus aligned and / or overlapping along direction x. In some embodiments, fins 208A and 208B have different widths (i.e., width W1 is greater than or less than width W2), and fin 208A is centered-aligned, top-aligned, or bottom-aligned with fin 208B along direction x. In some embodiments, referring to FIG. 9, width W2 is less than width W1, some fins 208B are aligned and / or overlapping with fins 208A, and some fins 208B are not aligned and not overlapping with fins 208A. For example, in FIG. 9, the topmost fin 208B and the bottommost fin 208B are not aligned and not overlapping with the corresponding fins 208A, one of the middle fins 208B is centered-aligned and overlapping with the corresponding fin 208A, and one of the middle fins 208B is top-aligned and overlapping with the corresponding fin 208A. In some embodiments, one or more of fins 208B may overlap with the corresponding fins 208A without being centered-aligned, top-aligned, or bottom-aligned therewith. The present disclosure contemplates various alignment and / or width configurations of fins 208A and 208B.

[0014] Referring again to FIGS. 2A-2D, each of fin 208A and fin 208B includes a substrate portion and a semiconductor layer stack portion disposed above the substrate portion. The substrate portion includes a mesa 206' (also referred to as a substrate extension, a fin portion of substrate 206, a substrate fin portion, an etched substrate portion, etc.). In the illustrated embodiment, substrate 206 includes silicon. Substrate 206 may alternatively or additionally include another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination of the above. In some embodiments, substrate 206 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon germanium-on-insulator substrate, or a germanium-on-insulator substrate. Substrate 206 (including mesa 206') may include various doped regions, such as p-type wells and n-type wells. The n-type wells are doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type wells are doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, substrate 206 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly above and / or within substrate 206, for example, to provide a p-type well structure, an n-type well structure, a dual-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions.

[0015] The semiconductor layer stack portion includes a semiconductor layer stack 210 having a semiconductor layer 215 and a semiconductor layer 220. Each semiconductor layer stack 210 is disposed above a corresponding mesa 206' of the substrate 206 and includes a corresponding semiconductor layer 215 and a corresponding semiconductor layer 220. The semiconductor layer 215 and the semiconductor layer 220 are stacked vertically (e.g., along the direction z) in an interleaved or alternating configuration from the top surface of the substrate 206. The compositions of the semiconductor layer 215 and the semiconductor layer 220 are different to achieve etch selectivity and / or different oxidation rates during the process. For example, the semiconductor layer 215 and the semiconductor layer 220 include different materials, atomic percentages of components, weight percentages of components, thicknesses, other characteristics, or combinations of the above to achieve the desired etch selectivity. In the illustrated embodiment, the semiconductor layer 220 includes silicon, and the semiconductor layer 215 includes silicon germanium. With such a composition, the semiconductor layer 215 can have a first etch rate with respect to an etchant, and the semiconductor layer 220 can have a second etch rate with respect to the etchant, where the first etch rate is different from the second etch rate. In some embodiments, the semiconductor layer 220 includes silicon germanium having a germanium atomic percentage different from that of the semiconductor layer 215. In some embodiments, the semiconductor layer 215 and / or the semiconductor layer 220 include n-type dopants and / or p-type dopants. The present disclosure contemplates any combination of semiconductor materials for the semiconductor layer 215 and the semiconductor layer 220 that can provide the desired etch selectivity and / or the desired performance characteristics (e.g., materials that maximize current).

[0016] As further described below, the semiconductor layer 220 or a portion thereof forms the channel region of a transistor in the device 200. In FIGS. 2A-2D, each semiconductor layer stack 210 includes four semiconductor layers 215 and four semiconductor layers 220. The semiconductor layer stack 210 thus includes four pairs of semiconductor layers disposed above the substrate 206, each pair of semiconductor layers having a corresponding semiconductor layer 215 and a corresponding semiconductor layer 220. After the process, this configuration can result in the transistors of the device 200 having four channels. In some embodiments, the semiconductor layer stack 210 includes more or fewer semiconductor layers, depending on, for example, the number of channels required for the transistors of the device 200 and / or design requirements. For example, the semiconductor layer stack 210 can include two to ten semiconductor layers 220. The thicknesses of the semiconductor layer 215 and the semiconductor layer 220 can be selected based on manufacturing and / or device performance considerations. For example, the thickness of the semiconductor layer 215 is configured to provide a desired distance (or pitch) between adjacent channels (e.g., between semiconductor layers 220), and the thickness of the semiconductor layer 220 is configured to provide a desired thickness of the channel.

[0017] The fabrication of fin 208A and fin 208B may include forming a semiconductor layer stack precursor over substrate 206 and performing a lithography process and / or an etching process to pattern the semiconductor layer stack precursor and / or substrate 206. In some embodiments, forming the semiconductor layer stack precursor includes epitaxially growing semiconductor layer 215 and semiconductor layer 220 on substrate 206 in a staggered and alternating configuration. For example, a first one of semiconductor layer 215 is epitaxially grown on substrate 206, a first one of semiconductor layer 220 is epitaxially grown on the first one of semiconductor layer 215, a second one of semiconductor layer 215 is epitaxially grown on the first one of semiconductor layer 220, and so on, until the desired number of semiconductor layer 215 and semiconductor layer 220 are provided for semiconductor layer stack 210. The epitaxial growth can be achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metalorganic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0018] The lithography process may include forming a resist layer (e.g., by spin coating) over a semiconductor layer stack precursor, performing a pre-exposure bake process, performing an exposure process using a photomask, performing a post-exposure bake process, and performing a development process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), wherein according to the mask pattern and / or mask type of the mask (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects radiation onto the resist layer, such that an image is projected onto the resist layer corresponding to the mask pattern. Since the resist layer is sensitive to radiation energy, the exposed portion of the resist layer undergoes a chemical change, and depending on the characteristics of the resist layer and the developer used in the development process, the exposed (or unexposed) portion of the resist layer is dissolved during the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etching mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. In some embodiments, the patterned resist layer is formed over a mask layer disposed over the semiconductor layer stack precursor, a first etching process removes portions of the mask layer to form a patterned layer (e.g., a patterned hard mask layer), and a second etching process uses the patterned layer as an etching mask to remove portions of the semiconductor layer stack precursor and / or substrate 206. The etching process is a dry etching, wet etching, other suitable etching process, or a combination of the above. In some embodiments, the etching process is a reactive ion etching (RIE) process. After etching, the patterned resist layer may be removed, for example, by a resist stripping process or other suitable process.

[0019] In some embodiments, fins 208A and 208B are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. These processes can also provide corresponding semiconductor layer stacks 210 above the corresponding pedestals 206' for each of fins 208A and 208B. In some embodiments, a directed self-assembly (DSA) technique is implemented while patterning the semiconductor layer stack precursor. Additionally, in some embodiments, the exposure process can implement maskless lithography, electron-beam (e-beam) writing, ion-beam writing, or a combination thereof to pattern the impedance layer.

[0020] After fins 208A and 208B are formed, a substrate isolation structure 225 can be formed over substrate 206. The substrate isolation structure 225 can fill multiple lower portions of the trenches between fins 208A, fins 208B, and fins 208A and fins 208B. The substrate isolation structure 225 can surround multiple portions of fins 208A and fins 208B, and the portions of fins 208A and fins 208B that extend beyond the top surface of the substrate isolation structure 225 can be referred to as fin active regions. The substrate isolation structure 225 electrically isolates the active device regions and / or passive device regions. For example, the substrate isolation structure 225 separates and electrically isolates fins 208A, fins 208B, and fins 208A and fins 208B (e.g., fin 208A is isolated from fin 208B by a corresponding one of the substrate isolation structures 225 across isolation region 204). The substrate isolation structure 225 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, or a combination of the foregoing), or a combination of the foregoing. The substrate isolation structure 225 can have a multi-layer structure. For example, the substrate isolation structure 225 can include a bulk dielectric (e.g., an oxide layer) over a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, or a combination of the foregoing). In another example, the substrate isolation structure 225 can include a doped liner, such as a boron silicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner, over a bulk dielectric. The size and / or characteristics of the substrate isolation structure 225 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination of the foregoing. For example, the substrate isolation structure 225 can be an STI.

[0021] The substrate isolation structure 225 can be formed by depositing a liner (e.g., a dielectric layer) that partially fills the trenches between the fins above the device 200, depositing an oxide material that fills the remaining portion of the trenches above the device 200 (e.g., above the liner), and performing a planarization process. The planarization process, such as a chemical mechanical polishing (CMP) process, can be performed until a planarization stop layer, such as the top semiconductor layer 220, is reached and exposed. In some embodiments, the planarization process removes any mask layer above and / or on top of the top surfaces of the fins 208A and 208B, any layer in the liner, any oxide material, or a combination of the foregoing. The remaining portions of the liner and the oxide material form the liner and the bulk dielectric of the substrate isolation structure 225, respectively. The liner can cover the sidewalls of the trenches (formed by the sidewalls of the fins) and the bottom of the trenches (formed by the substrate 206). The liner can be formed by atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), or a combination of the foregoing. The oxide material can be formed by flowable chemical vapor deposition (FCVD), high aspect ratio deposition (HARP) process, high density plasma chemical vapor deposition (HDPCVD), or a combination of the foregoing. In some embodiments, an annealing process is performed when the substrate isolation structure 225 is formed.

[0022] Next, the substrate isolation structure 225 can be etched and / or etched back such that the fins 208A and 208B protrude from the substrate isolation structure 225. In FIGS. 2A-2D, the substrate isolation structure 225 is etched back until it is below the semiconductor layer stack 210. In some embodiments, the height of the substrate isolation structure 225 is less than or equal to the height of the mesa 206' (e.g., relative to the top surface of the substrate 206). In some embodiments, the etching process selectively removes the substrate isolation structure 225 relative to the semiconductor layer stack 210. For example, the etching process etches / removes the substrate isolation structure 225 without etching / removing or negligibly etching / removing the semiconductor layer 220, the semiconductor layer 215, and the mesa 206'. An etchant that etches dielectric material at a higher rate than semiconductor material can be selected for the etching process. The etching process can be dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the etching process removes the mask / patterning layer of the fin 208A and / or the fin 208B. In some embodiments, the mask / patterning layer serves as an etching mask during the etching process.

[0023] Referring to FIGS. 3A-3F, dummy gates 230A are formed over multiple portions of the fin 208A in the device region 202A, dummy gates 230B are formed over multiple portions of the fin 208B in the device region 202B, and a dummy gate 230C is formed over the substrate isolation structure 225 in the isolation region 204. The dummy gates 230A-230C longitudinally extend in a direction different (e.g., orthogonal) from the longitudinal direction of the fins 208A and the fins 208B. For example, the dummy gates 230A-230C extend substantially parallel to each other along the direction y, having a length in the direction y, a width in the direction x, and a height in the direction z. The dummy gate 230A can have a width W3, the dummy gate 230B can have a width W4, and the dummy gate 230C can have a width W5. Each of the width W3, the width W4, and the width W5 can be less than the width of the active region (e.g., less than the width W1 of the fin 208A and / or the width W2 of the fin 208B). In the illustrated embodiment, the width W3, the width W4, and the width W5 are the same as each other. In some embodiments, the width W3, the width W4, the width W5, or a combination thereof are different from each other. For example, the width W5 can be different from (e.g., less than or greater than) the width W3 and / or the width W4 (i.e., the width of the dummy gate in the isolation region is different from the width of the dummy gate in the device region). In another example, the width W3 is different from (e.g., less than or greater than) the width W4 (i.e., different device regions have different dummy gate widths).

[0024] Along the fin width direction (see, for example, FIG. 3B), the dummy gate 230A is disposed on the top and sidewalls of the fin 208A. The dummy gate 230A surrounds the channel region (channel; C) of the fin 208A, and the dummy gate 230A is disposed above the top of the substrate isolation structure 225. In addition, the dummy gate 230B is disposed on the top and sidewalls of the fin 208B. The dummy gate 230B surrounds the channel region of the fin 208B, and the dummy gate 230B is disposed above the top of the substrate isolation structure 225. Along the fin length direction (see, for example, FIG. 3C), the dummy gate 230A is disposed above the top of the corresponding channel region of the fin 208A, and the dummy gate 230A is disposed between the corresponding source / drain regions (source∕drain; S∕D) of the fin 208A. In addition, the dummy gate 230B is disposed above the top of the corresponding channel region of the fin 208B, and the dummy gate 230B is disposed between the corresponding source / drain regions of the fin 208B. Since the dummy gates in the device regions 202A and 202B are formed above both the fins and the substrate isolation structure, the dummy gates in the device regions 202A and 202B can have varying heights. For example, the dummy gate 230A and the dummy gate 230B can have heights h1 above the fins 208A and 208B, respectively, and have a height h2 above the substrate isolation structure 225. The height h1 is between the top surface of the substrate isolation structure 225 and the top surface of the dummy gates 230A, 230B. The height h2 is between the top surface of the fins 208A, 208B and the top surface of the dummy gates 230A, 230B, and the height h2 is less than the height h1.

[0025] The dummy gate 230C is disposed above the top of the substrate isolation structure 225 along the fin width direction and the fin length direction (see, for example, FIG. 3D). To prevent the peeling and / or collapse of the dummy gate 230C in the isolation region 204, the gate support structure is inserted into the isolation region 204 between the dummy gates 230C. For example, the dummy gate is formed above the substrate isolation structure 225 in the isolation region 204 and extends along the fin length direction (e.g., direction x) to connect at least two dummy gates 230C. In the illustrated embodiment, the dummy gate 230D extends longitudinally along the direction x and connects two dummy gates 230C, such that the dummy gate 230D has a length in the direction x, a width in the direction y, and a height in the direction z. The dummy gate 230D may have a width W6, and the dummy gate 230D may have a height h1. In the illustrated embodiment, the width W6 is the same as the width W4, the width W5, and the width W3. In some embodiments, the width W6 is different from the width W5, the width W4, the width W3, or a combination of the foregoing. For example, to increase the structural support of the dummy gate 230C, the width W6 may be greater than the width W5.

[0026] In the illustrated embodiment, the dummy gate 230D is not aligned with and does not overlap the active region of the device region. Thus, the dummy gate 230D can be offset from the active region by a certain distance along the direction y, such as the distance d1 between the dummy gate 230D and the corresponding fin (e.g., the corresponding fin 208A and / or the corresponding fin 208B) along the direction y, and the distance d2 between the dummy gate 230D and another corresponding fin (e.g., the corresponding fin 208A and / or the corresponding fin 208B) along the direction y. In some embodiments, the dummy gate 230D is centered, top-aligned, or bottom-aligned with the fin 208A and / or the fin 208B along the direction x. For example, referring to FIG. 10, the dummy gate 230D can be centered with both the fin 208A and the fin 208B, such as where the fin 208A and the fin 208B are centered, and the dummy gate 230D has an overlap ov1 with the fin 208A and / or the fin 208B. In FIG. 10, where the width W6 is less than the width W1 and / or the width W2, the overlap ov1 is equal to the width W6. In embodiments where the width W6 is greater than the width W1 and / or the width W2, the overlap ov1 is equal to the width W1 and / or the width W2. In another example, referring to FIG. 11, the dummy gate 230D can overlap the corresponding fin 208A and / or the corresponding fin 208B without being centered, top-aligned, or bottom-aligned therewith. In FIG. 11, the dummy gate 230D has an overlap ov2 with the fin 208A and / or the fin 208B, and the overlap ov2 is less than the width W6. In some embodiments, the dummy gate 230D is centered, top-aligned, or bottom-aligned with the fin 208A but not aligned with the fin 208B. In such embodiments, the dummy gate 230D can overlap the fin 208A, and the dummy gate 230D can overlap or not overlap the fin 208B. The present disclosure contemplates various alignment and / or width configurations of the dummy gate 230D.

[0027] In some embodiments, more than one dummy gate 230D connects two dummy gates 230C. In some embodiments, dummy gate 230D connects more than two dummy gates 230C, such as two to six dummy gates 230C. For example, referring to FIG. 12, five dummy gates 230C (instead of two) may extend longitudinally in the isolation region 204 along the direction y, and the dummy gate 230D may extend longitudinally along the direction x to connect the five dummy gates 230C. In such an example, the dummy gate 230D may be composed of dummy gate 230D-1, dummy gate 230D-2, dummy gate 230D-3, dummy gate 230D-4, and multiple portions of the dummy gate 230C merged with each other by the dummy gates 230D-1 to 230D-4. Each of the dummy gates 230D-1 to 230D-4 connects and / or merges two corresponding dummy gates 230C together, and each of the dummy gates 230D-1 to 230D-4 may be referred to as a sub-gate.

[0028] The dummy gates 230A - 230D can also be referred to as a dummy gate stack. In some embodiments, the dummy gates 230A - 230D include a polysilicon layer, and the dummy gates 230A - 230D can be referred to as polysilicon gates. The dummy gates 230A - 230D can be formed by a single layer (e.g., a polysilicon layer) or multiple layers, such as a dummy gate dielectric, a dummy gate electrode, and a hard mask. The dummy gate dielectric includes a dielectric material, such as silicon oxide, a high - dielectric - constant dielectric material, other suitable dielectric materials, or a combination thereof. For example, the dummy gate dielectric is a silicon oxide layer (e.g., a SiO2 layer). The dummy gate electrode includes a suitable dummy gate material, such as polysilicon, and the hard mask includes a suitable hard mask material, such as silicon nitride. In some embodiments, the dummy gates 230A - 230D are formed simultaneously. For example, the dummy gates 230A - 230D can be formed by depositing a dummy gate dielectric layer over the device 200, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing a hard mask layer over the dummy gate electrode layer, and performing a lithography process and an etching process to pattern the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer. The remaining portions of the hard mask layer, the dummy gate electrode layer, and the dummy gate dielectric layer form the dummy gates 230A - 230D. In some embodiments, when patterning the hard mask layer, the dummy gate electrode layer, the dummy gate dielectric layer, or a combination thereof, the substrate isolation structure 225 can be recess - etched, which can result in the substrate isolation structure 225 having an isolation mesa 225' extending therefrom (see, for example, FIGS. 13A and 13B), and the dummy gates 230A - 230D can be disposed on the isolation mesa 225'. In some embodiments, the dummy gates in the device region (e.g., dummy gates 230A and 230B) and the dummy gates in the isolation region (e.g., dummy gates 230C and 230D) are formed at different times (i.e., by separate processes). In some embodiments, the dummy gates 230C and 230D are formed at different times. In some embodiments, the dummy gates 230A and 230B are formed at different times. In some embodiments, the dummy gates 230A - 230D are at least partially formed simultaneously (e.g., using the same deposition process and / or etching process but different lithography processes).

[0029] Referring to FIGS. 4A-4F, the fabrication of the device 200 may include forming gate spacers 232 along the sidewalls of the dummy gates 230A-230D to form gate structures 240A-240D. Each gate structure 240A has a corresponding dummy gate 230A and a gate spacer 232, each gate structure 240B has a corresponding dummy gate 230B and a gate spacer 232, each gate structure 240C has a corresponding dummy gate 230C and a gate spacer 232, and the gate structure 240D has a dummy gate 230D and a gate spacer 232. Fin spacers may be formed along the sidewalls of the source / drain regions of the fins 208A and / or 208B before, during, or after the formation of the gate spacers 232. The gate spacers 232 are disposed adjacent to the dummy gates 230A-230D, and the fin spacers may be disposed adjacent to the semiconductor layer stack 210 in the source / drain regions of the fins 208A and 208B before their removal. The gate spacers 232 and the fin spacers are formed by any suitable process and include a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or a combination thereof). For example, a spacer layer containing silicon and nitrogen (such as a silicon nitride layer) is deposited over the device 200 and etched to form the gate spacers 232 and the fin spacers. In some embodiments, the gate spacers 232 and / or the fin spacers have a multi-layer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon carbide. In some embodiments, the gate spacers 232 and / or the fin spacers include more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or a combination thereof. In such embodiments, each set of spacers may have different compositions and / or dimensions.

[0030] The manufacturing of device 200 may also include partially removing portions of fins 208A and 208B (e.g., source / drain regions not covered by dummy gates 230A and 230B) to form source / drain grooves, such that inner spacers 234 are formed along the sidewalls of semiconductor layer 215 below gate spacers 232, and source / drains 245 are formed in the source / drain grooves. Forming the source / drain grooves may include performing an etching process that removes semiconductor stack 210 in the source / drain regions of fins 208A and 208B, thereby exposing their mesa 206'. The etching process may further remove some but not all of mesa 206', such that the source / drain grooves may extend below the top surface of substrate isolation structure 225. The etching process is dry etching, wet etching, other suitable etching, or a combination of the above. In some embodiments, the etching process is a multi-step etching process. In some embodiments, the parameters of the etching process (e.g., its etchant) are configured to selectively remove semiconductor material (i.e., semiconductor stack 210), while not removing or negligibly removing dielectric material (e.g., hard masks of dummy gates 230A - 230D, gate spacers 232, fin spacers, substrate isolation structure 225, etc.). In some embodiments, the parameters of the etching process (e.g., its etchant) are configured to selectively remove semiconductor material (i.e., semiconductor stack 210), while not removing or negligibly removing polysilicon (e.g., dummy gates 230A - 230D) and dielectric material.

[0031] Forming inner spacers 234 may include a first etching process, a deposition process, and a second etching process. The first etching process may selectively etch semiconductor layer 215, with negligible etching of semiconductor layer 220, mesa 206', substrate isolation structure 225, dummy gates 230A - 230D, gate spacers 232, fin spacers, or a combination of the above. The first etching process is configured to laterally etch (e.g., along direction x and / or direction y) semiconductor layer 215 to form gaps between semiconductor layers 220 and gaps between mesa 206' and semiconductor layer 220. The first etching process is dry etching, wet etching, other suitable etching, or a combination of the above. In some embodiments, the first etching process is an anisotropic etching having a horizontal etching rate greater than the vertical etching rate (e.g., the vertical etching rate is zero), and the anisotropic etching may substantially remove material in the horizontal direction while not removing or negligibly removing material in the vertical direction.

[0032] The deposition process can form an insulating material that fills the gaps between the semiconductor layers 220 and the gaps between the mesa 206' and the semiconductor layer 220, and the second etching process selectively etches the insulating material to form the inner spacer 234 without etching or negligibly etching the semiconductor layer 220, the mesa 206', the substrate isolation structure 225, the dummy gates 230A - 230D, the gate spacer 232, the fin spacer, or a combination of the foregoing. To achieve etching selectivity during the second etching process, the composition of the insulating material (and thus the inner spacer 234) is different from the composition of the semiconductor layer 220, the mesa 206', the substrate isolation structure 225, the dummy gates 230A - 230D, the gate spacer 232, or a combination of the foregoing. The insulating material includes a dielectric material, and the dielectric material includes silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or a combination of the foregoing. For example, the insulating material is silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, other suitable materials, or a combination of the foregoing. The second etching process is a dry etching, a wet etching, other suitable etching, or a combination of the foregoing.

[0033] The source / drain 245 includes semiconductor material, and the source / drain 245 can be doped with n-type dopants and / or p-type dopants. In some embodiments (e.g., when forming portions of an n-type transistor), the source / drain 245 can include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination of the foregoing (e.g., Si:C source / drain, Si:P source / drain, or Si:C:P source / drain). In some embodiments (e.g., when forming portions of a p-type transistor), the source / drain 245 can include silicon germanium or germanium doped with boron, other p-type dopants, or a combination of the foregoing (e.g., Si:Ge:B source / drain). In some embodiments, the source / drain 245 has a multi-layer structure, such as two or more semiconductor layers having different compositions and / or different sizes / configurations. Different compositions can be achieved by using different semiconductor materials, different dopants, different atomic percentages of components, different dopant concentrations, or a combination of the foregoing. In some embodiments, the source / drain 245 includes materials and / or dopants that achieve the desired tensile stress and / or compressive stress in the channel region (e.g., the semiconductor layer 220) of the transistors formed in the device regions 202A and / or 202B. The source / drain 245 has the same or different compositions and / or materials according to the configurations of their respective transistors. In some embodiments, the device regions 202A and / or 202B include some source / drains 245 configured for n-type transistors (e.g., Si:C source / drain) and some source / drains 245 configured for p-type transistors (e.g., Si:Ge:B source / drain).

[0034] The source / drain 245 can be formed by an epitaxial process, which can include epitaxially growing a semiconductor material from the exposed semiconductor layer 220 and / or the mesa 206'. The semiconductor material is formed in the source / drain trench and can fill the source / drain trench. The epitaxial process can use CVD deposition techniques (e.g., remote plasma CVD (RPCVD), low pressure CVD (LPCVD), vapor phase epitaxy (VPE), ultrahigh vacuum CVD (UHV-CVD), or a combination thereof), MBE, other suitable epitaxial processes, or a combination thereof. The epitaxial process can use gaseous precursors and / or liquid precursors that can interact with and / or adsorb on the composition of the semiconductor layer 220 and / or the mesa 206', but do not interact with the composition of the inner spacer 234, the gate spacer 232, the contact etch stop layer (CESL) 252, the interlayer dielectric (ILD) layer 254, or a combination thereof. In some embodiments, the source / drain 245 is doped during deposition (i.e., in-situ), e.g., by adding dopants to the source material of the epitaxial process. In some embodiments, the source / drain 245 is doped after its deposition, e.g., by an ion implantation process. In some embodiments, an annealing process (e.g., rapid thermal annealing and / or laser annealing) is performed to activate the dopants in the source / drain 245. In some embodiments, when the source / drain 245 is configured for different transistors and has different compositions and / or materials, the source / drain 245 can be formed by separate process sequences. For example, when forming the source / drain 245 for an n-type transistor in an n-type transistor region, the p-type transistor region can be masked, and when forming the source / drain 245 for a p-type transistor in a p-type transistor region, the n-type transistor region can be masked.

[0035] The fabrication of device 200 may also include forming a dielectric layer 250 over device 200, such as over substrate isolation structure 225 and epitaxial source / drain 245. The dielectric layer 250 may fill the space between adjacent source / drains 245 and the space between adjacent gate structures 240A - 240D. For example, the dielectric layer 250 may fill the space between the gate spacers 232 of adjacent gate structures 240A - 240D. Forming the dielectric layer 250 may include depositing a contact etch stop layer (CESL) 252, depositing an interlayer dielectric (ILD) layer 254 over the CESL 252, and performing CMP and / or other planarization processes until the dummy gates 230A - 230D are reached (exposed). The planarization process may remove a portion of the dummy gates 230A - 230D, such as their hard masks, to expose the underlying dummy gate electrodes, such as their polysilicon gates. In such an embodiment, the height of the dummy gates 230A - 230D may be reduced by the planarization process. The CESL 252 and the ILD layer 254 are formed by CVD, other suitable methods, or a combination of the above. In some embodiments, the ILD layer 254 is formed by FCVD, HARP, HDPCVD, or a combination of the above.

[0036] The ILD layer 254 comprises a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethyl orthosilicate (TEOS), BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorocarbon, parylene, a benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or a combination of the foregoing. In some embodiments, the ILD layer 254 comprises a low dielectric constant dielectric material having a dielectric constant less than that of silicon oxide (e.g., k value < 3.9). In some embodiments, the ILD layer 254 comprises a dielectric material having a dielectric constant less than about 2.5 (i.e., an extreme low-k (ELK) dielectric material), such as porous silicon oxide, silicon carbide, carbon-doped oxide (e.g., SiCOH-based materials having, for example, Si-CH3 bonds), or a combination of the foregoing, each of which is tuned / configured to exhibit a dielectric constant less than about 2.5. The ILD layer 254 may have a multi-layer structure comprising multiple dielectric materials. The CESL 252 comprises a material different from that of the ILD layer 254, such as a dielectric material different from the dielectric material of the ILD layer 254. For example, when the ILD layer 254 comprises silicon and oxygen containing a low dielectric constant dielectric material, the CESL 252 may comprise silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0037] Turning to FIGS. 5A-5F and FIGS. 6A-6F, a gate replacement process is performed to replace dummy gates 230A-230D with metal gates, and a channel release process is performed to form suspended channel layers in the channel regions of fins 208A and 208B. Referring to FIGS. 5A-5F, gate openings 260A-260D are formed by removing dummy gates 230A-230D, respectively. Gate opening 260A exposes the channel region of fin 208A, and gate opening 260B exposes the channel region of fin 208B. Gate openings 260C and 260D expose substrate isolation structure 225, and gate opening 260D connects at least two gate openings 260C. For example, in FIG. 5D, gate opening 260C (formed by removing dummy gate 230C) and gate opening 260D (formed by removing dummy gate 230D) are combined to form gate opening 260E. The width of gate opening 260E (e.g., the sum of length l and (width W5×2)) is greater than the width of gate opening 260C (e.g., width W5). In some embodiments, gate openings 260A-260C are referred to as vertical gate openings (or trenches), and gate opening 260D and / or gate opening 260E are referred to as horizontal gate openings (or trenches), gate bar openings, gate support structure openings, or combinations thereof.

[0038] In some embodiments, an etching process selectively removes dummy gates 230A-230D relative to semiconductor stack 210, substrate isolation structure 225, gate spacers 232, ILD layer 254, CESL 252, or combinations thereof. In other words, the etching process removes dummy gates 230A-230D without removing or negligibly removing semiconductor stack 210, substrate isolation structure 225, gate spacers 232, ILD layer 254, CESL 252, or combinations thereof. For example, an etchant that removes polysilicon (e.g., dummy gates 230A-230D and / or their dummy gate electrodes) at a higher rate than semiconductor materials (e.g., semiconductor layers 220, 215, and mesa 206') and dielectric materials (e.g., substrate isolation structure 225, gate spacers 232, ILD layer 254, CESL 252, etc.) is selected (i.e., the etchant has a high etch selectivity relative to polysilicon). The etching process is dry etching, wet etching, other suitable etching, or combinations thereof. In some embodiments, a patterned mask layer covers ILD layer 254, CESL 252, gate spacers 232, or combinations thereof, and the patterned mask layer has openings that expose dummy gates 230A-230D.

[0039] After forming the gate openings 260A - 260D, a channel release process can be performed to provide a suspended channel layer. For example, the semiconductor layer 215 exposed by the gate opening 260A and the gate opening 260B can be selectively removed to form a gap between the semiconductor layers 220 and a gap between the semiconductor layer 220 and the mesa 206', thereby suspending the semiconductor layer 220 above the mesa 206'. The gate openings 260A and 260B thus extend between the semiconductor layers 220 and between the semiconductor layer 220 and the mesa 206'. In the illustrated embodiment, four semiconductor layers 220 are vertically stacked along the direction z, and the four semiconductor layers 220 provide a channel through which current can flow between the corresponding source / drain 245. The semiconductor layer 220 can thus be referred to as the channel layer 220' (or the suspended semiconductor layer 220').

[0040] In some embodiments, the etching process selectively removes the semiconductor layer 215 without removing or negligibly removing the mesa 206', the semiconductor layer 220, the substrate isolation structure 225, the gate spacer 232, the inner spacer 234, the dielectric layer 250, or a combination thereof. For example, an etchant that etches / removes silicon germanium (i.e., the semiconductor layer 215) at a higher rate than silicon (i.e., the semiconductor layer 220 and the mesa 206') and dielectric materials (i.e., the substrate isolation structure 225, the gate spacer 232, the inner spacer 234, the CESL 252, the ILD layer 254, or a combination thereof) is selected (i.e., the etchant has a high etching selectivity with respect to silicon germanium). The etching process is a dry etching, a wet etching, other suitable etching, or a combination thereof. In some embodiments, before performing the etching process, an oxidation process converts the semiconductor layer 215 into a silicon germanium oxide component, and the etching process removes the silicon germanium oxide component. In some embodiments, the profile of the channel layer 220' can be modified to provide its target size and / or target shape. For example, the etching process can provide a cylindrical profile (e.g., a nanowire), a rectangular profile (e.g., a nanoribbon), a flake profile (e.g., a nanosheet), or a profile of any other suitable shape for the channel layer 220'. In some embodiments, the channel layer 220' has nanoscale dimensions and can be individually or collectively referred to as a "nanostructure". The present disclosure contemplates that the channel layer 220' has any suitable dimensions, including sub-nanometer dimensions and / or super-nanometer dimensions.

[0041] Referring to FIGS. 6A - 6F, gate stacks 270A - 270D are respectively formed in gate openings 260A - 260D. Gate stack 270A fills gate opening 260A, the gap between channel layers 220' in gate opening 260A, and the gap between channel layer 220' and mesa 206' in gate opening 260A. Gate stack 270B fills gate opening 260B, the gap between channel layers 220' in gate opening 260B, and the gap between channel layer 220' and mesa 206' in gate opening 260B. Gate stack 270C fills gate opening 260C, and gate stack 270D fills gate opening 260D. Along the longitudinal direction of the active region (see, for example, FIG. 6C), gate stacks 270A and 270B are disposed between corresponding gate spacers 232, between corresponding inner spacers 234, between corresponding channel layers 220', and between corresponding channel layer 220' and corresponding mesa 206'. Along the width direction of the active region (e.g., in the Y - Z plane), gate stacks 270A and 270B can surround and / or enclose corresponding channel layers 220' (e.g., nanowires). Additionally, gate stack 270C is disposed along the longitudinal direction of the active region between corresponding gate spacers 232 and above corresponding substrate isolation structure 225 (see, for example, FIG. 6F), and gate stack 270D is disposed along the width direction of the active region between corresponding gate spacers 232 and above corresponding substrate isolation structure 225 (see, for example, FIG. 6E). In the gate support region, gate stacks 270C and 270D can be combined to form gate stack 270E, which includes at least two gate stacks 270C and at least one gate stack 270D. Gate stack 270D and / or gate stack 270E can be referred to as a gate bar, a horizontal gate bar, a gate support structure, or a combination of the above.

[0042] After the gate replacement process, each gate structure 240A includes a corresponding gate stack 270A and a gate spacer 232, each gate structure 240B includes a corresponding gate stack 270B and a gate spacer 232, each gate structure 240C includes a corresponding gate stack 270C and a gate spacer 232, the gate structure 240D includes a corresponding gate stack 270D and a gate spacer 232, and the gate structure 240E includes a gate stack 270E and a gate spacer 232. The gate stack 270A includes a corresponding gate dielectric 272A and a corresponding gate electrode 274A, the gate stack 270B includes a corresponding gate dielectric 272B and a corresponding gate electrode 274B, the gate stack 270C includes a corresponding gate dielectric 272C and a corresponding gate electrode 274C, and the gate stack 270D includes a gate dielectric 272D and a gate electrode 274D.

[0043] The gate dielectrics 272A - 272D are disposed on the channel layer 220’, the mesa 206’, the substrate isolation structure 225, or a combination thereof. The compositions and / or configurations of the gate dielectric 272A, the gate dielectric 272B, the gate dielectric 272C, the gate dielectric 272D, or a combination thereof may be the same or different. Each of the gate dielectrics 272A - 272D includes at least one dielectric gate layer, such as an interfacial layer and / or a high-k dielectric layer. The interfacial layer includes a dielectric material, such as SiO 2, SiGeO x, HfSiO, SiON, other dielectric materials, or a combination thereof. The high-k dielectric layer includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k value ≈ 3.9), such as HfO 2, HfSiO, HfSiO 4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO 2, ZrSiO 2, AlO, AlSiO, Al 2O 3, TiO, TiO 2, LaO, LaSiO, LaO 3, La 2O 3, Ta 2O 3, Ta 2O 5, Y 2O 3, SrTiO 3, BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3N 4, HfO 2 - Al 2O 3, other high-k dielectric materials, or a combination thereof. For example, the gate dielectrics 272A - 272D may each include a hafnium-based oxide (e.g., HfO 2) layer and / or a zirconium-based oxide (e.g., ZrO 2) layer. In some embodiments, the interfacial layer and / or the high-k dielectric layer has a multi-layer structure.

[0044] The gate electrodes 274A - 274D are respectively disposed above the gate dielectrics 272A - 272D. The compositions and / or configurations of the gate electrode 274A, the gate electrode 274B, the gate electrode 274C, the gate electrode 274D, or combinations thereof may be the same or different. The gate electrodes 274A - 274D include at least one electrically conductive gate layer. The electrically conductive gate layer includes an electrically conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other electrically conductive materials, or combinations thereof. In some embodiments, the gate electrodes 274A - 274D include a work function layer. The work function layer is a conductive layer adjusted to have a desired work function (such as an n-type work function or a p-type work function). The work function layer includes (a) work function metal(s) and / or its alloy(s) such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the gate electrodes 274A - 274D include a bulk layer disposed above the gate dielectric and / or the work function layer. The bulk layer includes a suitable conductive material such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable (a) metal(s) and / or its alloy(s), or combinations thereof. In some embodiments, the gate electrodes 274A - 274D include a barrier layer disposed above the work function layer and / or the gate dielectric. The barrier layer includes a material that prevents or eliminates the diffusion and / or reaction of components between adjacent film layers, and / or promotes adhesion between adjacent film layers (such as between the work function layer and the bulk layer). In some embodiments, the barrier layer includes a metal and nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0045] The gate stacks 270A - 270D are configured to implement the required functionality according to the design requirements of the device 200. The gate stacks 270A - 270D can thus have different film layers in the device regions 202A, the device regions 202B, and the isolation region 204 according to their configuration, and depending on their configuration, the gate stacks 270A - 270D can have different film layers within the device region 202A, within the device region 202B, and within the isolation region 204. For example, the number, configuration, material, or combination of the above of the film layers of the gate dielectrics 272A - 272D and / or the gate electrodes 274A - 274D corresponding to a first type of transistor region (e.g., an n-type transistor region) can be different from the number, configuration, material, or combination of the above of the film layers of the gate dielectrics 272A - 272D and / or the gate electrodes 274A - 274D corresponding to a second type of transistor region (e.g., a p-type transistor region). In another example, the number, configuration, material, or combination of the above of the film layers of the gate dielectric 272A and / or the gate electrode 274A in the device region 202A can be different from the number, configuration, material, or combination of the above of the film layers of the gate dielectric 272B and / or the gate electrode 274B in the device region 202B. In yet another example, the number, configuration, material, or combination of the above of the film layers of the gate dielectric and / or the gate electrode in the device regions (e.g., the device region 202A and / or the device region 202B) can be different from the number, configuration, material, or combination of the above of the film layers of the gate dielectric and / or the gate electrode in the isolation region (e.g., the isolation region 204). The gate stacks 270A - 270D can include many other film layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations of the above.

[0046] Forming the gate stacks 270A - 270D may include depositing a gate dielectric material (e.g., an interfacial layer and / or a high-k dielectric layer) that partially fills the gate openings 260A - 260D, depositing a gate electrode material (e.g., a work function layer, a barrier layer, a bulk layer, etc.) that fills the remaining portions of the gate openings 260A - 260D, and performing a planarization process to remove portions of the gate dielectric material and / or portions of the gate electrode material above the dielectric layer 250. In some embodiments, the fabrication of the device 200 may further include etching back the gate stacks 270A - 270D and forming a hard mask (e.g., a self-aligned cap (SAC) structure) over the etched-back gate stacks 270A - 270D. The hard mask includes a material different from the dielectric layer 250 and / or a subsequently formed dielectric layer to achieve etch selectivity. In some embodiments, the hard mask includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, other silicon nitrides, other silicon carbides, or a combination thereof. In some embodiments, the hard mask includes a metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HfO2), zirconium aluminum oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or a combination thereof.

[0047] Referring to FIGS. 7A - 7F, the fabrication of the device 200 may include forming a dielectric layer 280 over the device 200 (e.g., over the dielectric layer 250 and the gate stacks 270A - 270D) and forming a source / drain contact isolation structure 285 over the dielectric layer 280. The dielectric layer 280 may be configured and formed in a manner similar to the dielectric layer 250. For example, the dielectric layer 280 may include an ILD layer over a CESL. The source / drain contact isolation structure 285 extends longitudinally along the fin longitudinal direction (e.g., along the direction x), such that the source / drain contact isolation structure 285 has a length in the direction x, a width in the direction y, and a height in the direction z. Along the width direction of the active region (see, e.g., FIG. 7A), the source / drain contact isolation structure 285 has a width W7, which may be less than the pitch between the fins 208A and / or the pitch between the fins 208B. Along the longitudinal direction of the active region (see, e.g., FIG. 7A), the source / drain contact isolation structure 285 spans the device region 202A, the device region 202B, and the isolation region 204.

[0048] In the gate support region of the isolation region 204 (i.e., the region of the isolation region 204 where the through-gate structure 240D is inserted to enhance the structural integrity of the gate structure 240C), the source / drain contact isolation structure 285 is widened to prevent electrical short circuits, which may be caused by an unexpected electrical connection and / or physical connection between the gate stack 270D and the subsequently formed source / drain contact. For example, the middle source / drain contact isolation structure 285 of the device 200 has a widened portion 285' above the gate structure 240D. The widened portion 285' has a width W8 greater than the width W7 along the width direction of the active region. The width W8 is also greater than the width of the gate stack 270D (e.g., width W6) to ensure that the subsequently formed source / drain contact and the gate stack 270D are sufficiently spaced apart. In the illustrated embodiment (see, for example, FIG. 7E), the widened portion 285' is disposed above the gate stack 270D and covers the gate stack 270D, and the widened portion 285' extends laterally beyond the two sidewalls of the gate stack 270D. For example, the widened portion 285' may extend beyond the first sidewall and the second sidewall of the gate stack 270D by a distance d3 and a distance d4, respectively. The distance d3 may be the same as or different from the distance d4. The length of the widened portion 285' (e.g., along the direction x) may be configured such that the widened portion 285' is disposed above the gate structure 240E and covers the gate structure 240E (i.e., the gate structure 240D and a plurality of portions of the gate structure 240C connected thereto). In some embodiments, the length of the widened portion 285' is greater than or equal to the sum of the lengths of the gate stack 270D and the sum of the widths of at least two gate stacks 270C (e.g., length = length l+(2×width W5)). In some embodiments, the length of the widened portion 285' is greater than or equal to the length of the gate stack 270D.

[0049] The source / drain contact isolation structure 285 includes an electrically insulating material, such as a dielectric material. The composition of the source / drain contact isolation structure 285 is different from the composition of the dielectric layer 280 and / or the composition of the dielectric layer 250, so that selective etching / removal can be performed therebetween. For example, the source / drain contact isolation structure 285 is formed of a dielectric material different from the dielectric material of the dielectric layer 280 and / or the dielectric material of the dielectric layer 250. In some embodiments, the source / drain contact isolation structure 285 is formed of a dielectric material including silicon and oxygen, carbon, nitrogen, or a combination thereof. For example, the source / drain contact isolation structure 285 can be formed of silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the source / drain contact isolation structure 285 is formed of a dielectric material including boron and oxygen, carbon, nitrogen, or a combination thereof. For example, the source / drain contact isolation structure 285 can be formed of boron nitride. In some embodiments, the source / drain contact isolation structure 285 is formed of a dielectric material including a metal and oxygen, carbon, nitrogen, or a combination thereof. In some embodiments, the source / drain contact isolation structure 285 is formed by depositing a source / drain contact isolation material over the dielectric layer 280 and patterning the source / drain contact isolation material (e.g., by forming a patterned mask layer over the source / drain contact isolation material and etching / removing the source / drain contact isolation material exposed by the openings in the patterned mask layer). The present disclosure contemplates source / drain contact isolation layers having various patterns and / or width variations depending on the layout of the active regions (e.g., fins 208A, 208B), the layout of the active gates (e.g., gate structures 240A, 240B and / or gate stacks 270A, 270B), the layout of the dummy gates (e.g., gate structure 240C and / or gate stack 270C), the layout of the gate support structures (e.g., gate structure 240D and / or gate stack 270D), or a combination thereof (collectively referred to as the source / drain contact isolation structure 285). In some embodiments, the dielectric layer 280 is omitted, and the source / drain contact isolation structure 285 is formed directly over and in physical contact with the dielectric layer 250 and / or the gate stacks 270A-270D.

[0050] Referring to FIGS. 8A-8G, the fabrication of device 200 can include forming source / drain contacts 290A-290C, which can be physically and / or electrically isolated from each other by source / drain contact isolation structures 285. The source / drain contacts 290A-290C extend along the gate longitudinal direction (e.g., along the direction y), such that the source / drain contacts 290A-290C have a length in the direction y, a width in the direction x, and a height in the direction z. Along the longitudinal direction of the active region (see, e.g., FIG. 8A), the source / drain contact 290A has a width less than the pitch between the gate structures 240A, the source / drain contact 290B has a width less than the pitch between the gate structures 240B, and the source / drain contact 290C has a width less than the pitch between the gate structures 240C. Along the width direction of the active region (see, e.g., FIG. 8A), the source / drain contacts 290A-290C have a length less than or equal to the pitch between the source / drain contact isolation structures 285. In the illustrated embodiment, each of the source / drain contacts 290A-290C is located between and in physical contact with a first one of the source / drain contact isolation structures 285 and a second one of the source / drain contact isolation structures 285.

[0051] The source / drain contact 290A can extend through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof and reach the corresponding source / drain 245 in the device region 202A (see, for example, FIGS. 8B and 8C). The source / drain contact 290B can extend through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof and reach the corresponding source / drain 245 in the device region 202B. The source / drain contact 290C can extend through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof and reach the substrate isolation structure 225 in the isolation region 204 (see, for example, FIGS. 8E, 8F, and 8G). In the illustrated embodiment, the source / drain contact 290C extends into the substrate isolation structure 225 such that the source / drain contact 290C extends below the bottom of the gate stack 270C and / or the gate stack 270D. In some embodiments, the source / drain contact 290C can stop at the substrate isolation structure 225 and not extend into the substrate isolation structure 225. Because the source / drain contact isolation structure 285 has a (plurality of) widened portions 285' in the gate support region of the isolation region 204, the source / drain contact 290C is separated by a first distance (e.g., width W8) in the gate support region (see, for example, FIG. 8E) and by a second distance (e.g., width W7) in the gate-free support region (see, for example, FIG. 8G). Widening the pitch between the source / drain contacts 290C in the gate support region ensures that there is sufficient pitch (e.g., distance d3 and / or distance d4) between the source / drain contact 290C and the gate stack 270D, thereby reducing the risk that the source / drain contact 290C electrically and / or physically connects to the gate stack 270D and causes a short circuit. In some embodiments, the distance d5 between the gate stack 270C and the source / drain contact 290C (i.e., in the gate-free support region of the isolation region 204) is less than the distance d3 and / or the distance d4 between the gate stack 270D and the source / drain contact 290C (i.e., in the gate support region).

[0052] The source / drain contacts 290A - 290C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal component, an alloy thereof, or a combination thereof. In the illustrated embodiment, the source / drain contacts 290A - 290C include tungsten, ruthenium, cobalt, an alloy thereof, or a combination thereof. For example, the source / drain contacts 290A - 290C can be tungsten contacts, ruthenium contacts, or cobalt contacts. The source / drain contacts 290A - 290C can have the same or different configurations and / or compositions. The source / drain contacts 290A - 290C can be formed by forming a dielectric layer 292 over the source / drain contact isolation structure 285 and the dielectric layer 280; forming source / drain contact openings extending through the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof to expose the source / drain 245 or the substrate isolation structure 225; depositing at least one electrically conductive material filling the source / drain contact openings over the dielectric layer 292; and performing a planarization process to remove any conductive material disposed over the top of the source / drain contact isolation structure 285 and / or the dielectric layer 292. The planarization process can be performed until the source / drain contact isolation structure 285 and / or the dielectric layer 292 is reached and exposed. The remaining portion of the electrically conductive material forms metal plugs, and in some embodiments, forms metal liners for the source / drain contacts 290A - 290C. In some embodiments, a silicidation process is performed to form a silicide layer over the source / drain 245 before depositing at least one electrically conductive material in the source / drain contact openings.

[0053] In some embodiments, forming the source / drain contact openings includes forming a patterned mask layer over a dielectric layer 292 having openings therein overlapping the source / drain 245 in the device region 202A, the source / drain 245 in the device region 202B, and the substrate isolation structure 225 in the isolation region 204, and selectively etching the dielectric material (e.g., the dielectric layer 292, the dielectric layer 280, the dielectric layer 250, or a combination thereof) exposed by the openings of the patterned mask layer without etching or negligibly etching the semiconductor material (e.g., the source / drain 245). In the illustrated embodiment, since the substrate isolation structure 225 is formed of a dielectric material, the etching can remove portions thereof such that the source / drain contact openings in the isolation region 204 extend into the substrate isolation structure 225. In some embodiments, the etching is configured to stop upon reaching and / or exposing the source / drain 245. The etching is dry etching, wet etching, other suitable etching, or a combination thereof. One or more deposition processes can be performed to form the electrically conductive material filling the source / drain contact openings.

[0054] In FIGS. 8A - 8G, device 200 includes transistors in device region 202A and transistors in device region 202B. For example, in device region 202A, a transistor can include a corresponding channel layer 220’, a corresponding source / drain 245, and a corresponding gate structure 240A (e.g., a corresponding gate stack 270A and a corresponding gate spacer 232). The corresponding gate structure 240A is disposed between the corresponding source / drain 245 along direction x, and an inner spacer 234 is disposed between the corresponding gate structure 240A and the corresponding source / drain 245. In addition, the corresponding gate stack 270A engages the corresponding channel layer 220’, and the corresponding channel layer 220’ extends between the corresponding source / drain 245 along direction x. The corresponding gate structure 240A is disposed on at least two sides of the corresponding channel layer 220’. For example, the corresponding gate structure 240A has a corresponding gate dielectric 272A and a corresponding gate electrode 274A that can surround the corresponding channel layer 220’ (e.g., in a Y - Z cross-sectional schematic view). In device region 202B, a transistor can include a corresponding channel layer 220’, a corresponding source / drain 245, and a corresponding gate structure 240B (e.g., a corresponding gate stack 270B and a corresponding gate spacer 232). The corresponding gate structure 240B is disposed between the corresponding source / drain 245 along direction x, and an inner spacer 234 is disposed between the corresponding gate structure 240B and the corresponding source / drain 245. In addition, the corresponding gate stack 270B engages the corresponding channel layer 220’, and the corresponding channel layer 220’ extends between the corresponding source / drain 245 along direction x. The corresponding gate structure 240B is disposed on at least two sides of the corresponding channel layer 220’. For example, the corresponding gate structure 240B has a corresponding gate dielectric 272B and a corresponding gate electrode 274B that can surround the corresponding channel layer 220’ (e.g., in a Y - Z cross-sectional schematic view).

[0055] Applying a voltage to gate stack 270A and / or gate stack 270B enables current to flow through corresponding channel layer 220' between corresponding source / drain 245. Gate structures 240A, 240B forming multiple portions of the transistor can thus be referred to as active gate structures, and gate stacks 270A, 270B forming multiple portions of the transistor can be referred to as active gate stacks and / or active gates. "Active gate structure", "active gate stack", and "active gate" generally refer to charged functional gate structures (and / or gate stacks), while "dummy gate structure" generally refers to non-charged functional gate structures (and / or gate stacks). A dummy gate structure can mimic the physical characteristics of an active gate structure, such as the physical dimensions and / or film layers of the active gate structure, but is electrically inoperable (i.e., applying a voltage to the dummy gate structure cannot cause current to flow through the channel and / or between the source / drain). In the illustrated embodiment, device 200 includes dummy gate structures in isolation region 204, such as gate structure 240C and / or its gate stack 270C. Additionally, since source / drain contact 290C is connected to substrate isolation structure 225 rather than an electrically conductive component, source / drain contact 290C can be referred to as a dummy source / drain contact. Gate structure 240C, its gate stack 270C, source / drain contact 290C, or a combination thereof can achieve a substantially uniform process environment (e.g., by reducing (or preventing) the dishing effect caused by CMP).

[0056] Device 200 further includes a gate support structure, such as gate structure 240D and / or its gate stack 270D, which may also be referred to as a gate support bar and / or a dummy gate support bar (since gate structure 240D and / or its gate stack 270D are dummy gate structures). The gate support structure can improve the reliability and / or structural integrity of device 200 in isolation region 204. Referring to FIGS. 13A and 13B, gate structure 240A (and / or its gate stack 270A) and gate structure 240B (and / or its gate stack 270B) are formed above the active regions of both (e.g., the channel regions of fins 208A and 208B, respectively, which may include corresponding channel layers 220') and substrate isolation structure 225. Since gate structure 240A and gate structure 240B can adhere well to the active regions, gate structure 240A and gate structure 240B are anchored and structurally supported by the active regions, which prevents the collapse and / or bending of gate structure 240A and gate structure 240B, even though the gate height may increase as the IC technology node is scaled down. This anchoring also provides gate structure 240A and gate structure 240B with heights that vary along their lengths (e.g., height h1 and height h2), further reducing collapse and / or bending. In contrast, gate structure 240C is formed above substrate isolation structure 225. Since gate structure 240C may not adhere well to substrate isolation structure 225 (e.g., dielectric material to semiconductor material), and gate structure 240C has a greater overall height (i.e., gate structure 240C has height h1 along its length since gate structure 240C is also not disposed above an active region), gate structure 240C may undesirably peel off, bend, collapse, or a combination of the above from substrate isolation structure 225, as depicted in FIG. 13A. This reduces device performance, device reliability, device yield, or a combination of the above. This problem may be exacerbated by (intentionally or unintentionally) etching substrate isolation structure 225, resulting in gate structure 240C being supported by isolation mesa 225', which is narrower than substrate isolation structure 225 and provides even worse structural stability for gate structure 240C. By interposing a gate support structure (e.g., gate structure 240D and / or its gate stack 270D) into isolation region 204, additional support and / or anchoring is provided for gate structure 240C, which can reduce and / or prevent its collapse and / or bending, as depicted in FIG. 13B. The gate support structure can be easily integrated into existing device manufacturing processes. Different embodiments may have different advantages, and not every embodiment needs to have a particular advantage.

[0057] Gate support structures such as those described in this disclosure can be integrated into a device and / or device layout according to a set of design rules. Referring to FIGS. 14A-14C, a device 300 having a gate support structure is configured and arranged according to a set of design rules, as further described below. FIG. 14A is a top schematic view, in accordance with various aspects of the present disclosure, of a portion or entirety of device 300. FIG. 14B is a sectional schematic view, in accordance with various aspects of the present disclosure, of a portion or entirety of device 300 along section line B-B of FIG. 14A. FIG. 14C is a sectional schematic view, in accordance with various aspects of the present disclosure, of a portion or entirety of device 300 along section line C-C of FIG. 14A. Device 300 is similar to device 200 in many aspects. Thus, for clarity and simplicity, like components in device 300 and device 200 are identified by the same reference numerals. For ease of description and understanding, FIGS. 14A-14C are discussed simultaneously in this disclosure. For clarity, FIGS. 14A-14C have been simplified to better understand the inventive concept of this disclosure. Additional components may be added to device 300, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 300.

[0058] Device 300 includes a region containing active regions (e.g., device regions 302A, 302B, and 302C) and a region without active regions (i.e., non-active regions such as isolation regions 304A, 304B, and 304C). Device regions 302A-302C each include a corresponding active region (OD), a gate (G), and a source / drain contact (MD). The active regions extend longitudinally along a first direction (e.g., direction x), the gates extend longitudinally along a second direction different from the first direction (e.g., direction y), and the source / drain contacts extend longitudinally along the second direction. The active region may include a channel structure (e.g., a stack of channel layers 220') disposed between the source / drain (e.g., source / drain 245), and the gate may be disposed above and engage the channel structure (e.g., the gate may surround and / or enclose channel layer 220'). The gate and the active region may be combined to form transistors in device regions 302A-302C.

[0059] Device 300 may include one or more gate isolation structures (CPO or CMG). In the illustrated embodiment, the gate isolation structure physically and / or electrically isolates the gates of different device regions, such as the gate of device region 302A and the gate of device region 302C. The gate isolation structure extends longitudinally along a first direction (i.e., the longitudinal direction of the active region). In some embodiments, the gate of device region 302A and the gate of device region 302C may be formed by a gate wire that is cut into two gates, for example, by replacing a portion of the gate wire with an electrically insulating material (such as a dielectric material). In FIG. 14C, the gate isolation structure may include a dielectric material 310 disposed between the gate of device region 302A (e.g., gate stack 270A-1 having a gate dielectric 272A-1 and a gate electrode 274A-1) and the gate of device region 302C (e.g., gate stack 270A-2 having a gate dielectric 272A-2 and a gate electrode 274A-2), which may be formed by replacing a portion of the corresponding gate (e.g., the corresponding gate stack 270A) with the dielectric material 310. The gate isolation structure may extend into the substrate isolation structure 225 such that the gate isolation structure extends below the bottom of the gate (e.g., beyond gate stack 270A-1 and gate stack 270A-2). The dielectric material 310 may be a single layer or a multi-layer film.

[0060] Device 300 may further include one or more active region isolation structures (CPODE), which may replace multiple portions of the gate. In the illustrated embodiment, the active region isolation structure physically and / or electrically isolates the active regions of different devices, such as the first active region of the first device in device region 302A and the second active region of the second device in device region 302A. The active region isolation structure extends longitudinally along a second direction (i.e., the longitudinal direction of the gate). In such an embodiment, the active regions of the devices within a device region (such as device region 302A) may be formed by an active region wire that is cut into two active regions, for example, by replacing a portion of the active region wire with an electrically insulating material (such as a dielectric material) and / or a gate wire passing through the active region wire. In FIG. 14B, the active region isolation structure may include a dielectric material 315 disposed between the first active region of the first device (e.g., its corresponding source / drain 245) and the second active region of the second device (e.g., its corresponding source / drain 245). The active region isolation structure (e.g., the dielectric material 315) may extend into the substrate isolation structure 225 such that the active region isolation structure extends below the bottom of the source / drain 245 and / or the channel layer 220'. The dielectric material 315 may be a single layer or a multi-layer film.

[0061] The isolation region 304A is disposed between the device region 302A and the device region 302B, the isolation region 304B is disposed adjacent to the device region 302A and the device region 302C, and the isolation region 304C is disposed adjacent to the device region 302C, such that the device region 302A is disposed between the isolation region 304A and the isolation region 304B, and the device region 302C is disposed between the isolation region 304B and the isolation region 304C. The isolation region 304A includes corresponding gates, corresponding source / drain contact members, source / drain contact member isolation structures (CMD), and corresponding gate support structures (HG1). The isolation region 304B includes corresponding gates and corresponding gate support structures (HG2), but does not include source / drain contact members and / or source / drain contact member isolation structures. The gate support structures extend longitudinally along a first direction (i.e., the longitudinal direction of the active region).

[0062] Depending on whether the gate support structure is formed in a region with or without source / drain contact members, the dimensions and / or pitches corresponding to the gate support structure can be configured differently. For example, the dimensions and / or pitches corresponding to the gate support structures (e.g., HG2) in the isolation regions 304B and 304C without source / drain contact members can be relaxed relative to the dimensions and / or pitches corresponding to the gate support structures (e.g., HG1) in the isolation region 304A with source / drain contact members. In some embodiments, the length of the gate support structure in the isolation region 304B and / or the isolation region 304C can be configured to be greater than the length of the gate support structure in the isolation region 304A. For example, the gate support structure in the isolation region 304A can be connected to two gates, while the gate support structure in the isolation region 304B and / or the isolation region 304C can be connected to two to six gates. In such an example, the length of the gate support structure in the isolation region 304B and / or the isolation region 304C (e.g., along the direction x) can be approximately five times greater than the length of the gate support structure in the isolation region 304A (e.g., along the direction x). In some embodiments, the gate support structures in the isolation regions 304A - 304C have a width (e.g., along the direction y) in the range of about 8 nm to about 12 nm (e.g., 10 nm), the length of the gate support structure in the isolation region 304A is less than or equal to about 54 nm, and the length of the gate support structure in the isolation region 304B and / or the isolation region 304C is less than or equal to about 270 nm.

[0063] In some embodiments, within the region including the gate support structure, the pitch y1 between the gate support structures along the direction y (e.g., along the gate longitudinal direction) is greater than the pitch between the gate support structures along the direction x (e.g., along the active region longitudinal direction). For example, the pitch y1 is about 4 to about 5 times greater than the pitch between the gate support structures along the direction x. In some embodiments, the pitch y1 is greater than or equal to about 224 nm, and the pitch between the gate support structures along the direction x is greater than about 48 nm.

[0064] In some embodiments, the pitch y2 between the gate support structure and the active region (e.g., its sidewall) along the direction y is configured to reduce the risk of forming a short circuit between the gate support structure and the active region. For example, the pitch y2 can be greater than or equal to about 130 nm. In some embodiments, the pitch y3 between the gate support structure and the end of the source / drain contact along the direction y is configured to reduce the risk of forming a short circuit between the gate support structure and the source / drain contact. For example, the pitch y3 can be greater than or equal to about 100 nm. In some embodiments, the width W of the source / drain contact isolation structure (e.g., along the direction y) is configured to be about six to about nine times greater than the width of the gate support structure in the isolation region 304A to reduce the risk of forming a short circuit between the gate support structure and the source / drain contact. For example, the gate support structure in the isolation region 304A can have a width (e.g., along the direction y) in the range of about 8 nm to about 12 nm (e.g., 10 nm), and the width W can be about 68 nm to about 72 nm.

[0065] In some embodiments, the pitch y4 along the direction y between the gate support structure and the end of the active region isolation structure is configured to reduce the risk of forming a short circuit between the gate support structure and the active region. For example, the pitch y4 can be greater than or equal to about 135 nm. In some embodiments, the pitch x1 along the direction x between the gate support structure and the active region isolation structure (e.g., its sidewall) is configured to reduce the risk of forming a short circuit between the gate support structure and the active region. For example, the pitch x1 can be greater than or equal to about 94.5 nm. In some embodiments, the pitch y4 is about 1.25 to about 1.5 times greater than the pitch x1. In some embodiments, the pitch y5 along the direction y between the gate support structure and the gate isolation structure (e.g., its sidewall) is configured to reduce the risk of forming a short circuit between the gate support structure and the active region. For example, the pitch y5 can be greater than or equal to about 48 nm. In some embodiments, the pitch y6 along the direction y between the gate support structure and the end of the gate is configured to optimize the position of the gate support structure and thus optimize the structural integrity of the gate. For example, the pitch y6 can be greater than or equal to about 100 nm.

[0066] FIG. 15 is a flow diagram showing in part or in whole a method 400 for improving device reliability and the structural integrity of a device, according to various aspects of the present disclosure. At block 410, the method 400 includes receiving a device layout having an active region wire longitudinally extending in a first direction in an active region, a first gate wire extending above the active region wire in the active region and longitudinally extending in a second direction different from the first direction, and a second gate wire longitudinally extending in the second direction in a non-active region. The first gate wire can be an active gate wire and represent an active gate, and the second gate wire can be a dummy gate wire and represent a dummy gate. The active region wire can represent a channel region and / or a source / drain region. At block 415, the method 400 includes modifying the device layout by interposing gate support bars in the non-active region, the gate support bars longitudinally extending in the first direction and connecting at least two second gate wires. The gate support bars can be dummy gate wires and / or represent dummy gates. At block 420, the method 400 includes fabricating a device based on the modified device layout. The present disclosure contemplates additional processes. Additional steps can be provided before, during, and after the method 400, and for additional embodiments of the method 400, some of the described steps can be moved, replaced, or eliminated.

[0067] The present disclosure provides many different embodiments. An exemplary method includes forming an active region in a device region. The active region extends longitudinally along a first direction and laterally along a second direction. The method further includes forming isolation structures in the device region and an isolation region. The isolation structures in the device region are adjacent to the active region. In some embodiments, the active region includes a lower portion and an upper portion, the isolation structures are adjacent to the lower portion of the active region, and the upper portion of the active region is disposed above and / or extends from the isolation structures. The method further includes forming a plurality of first gates above the active region and the isolation structures in the device region, forming a plurality of second gates above the isolation structures in the isolation region, and forming a third gate above the isolation structures in the isolation region. The first gates and the second gates extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates. In some embodiments, the first gates, the second gates, and the third gate are formed simultaneously. In some embodiments, there is a first pitch between the first gates, there is a first pitch between the second gates, the first gates have a first height above the active region, and the second gates have a second height above the isolation structures. The second height is greater than the first height.

[0068] In some embodiments, the method further includes forming a contact isolation structure above the first gates, the second gates, and the third gate. The contact isolation structure extends longitudinally along the first direction. The contact isolation structure has a first width along the second direction above the first gates and a second width extending along the second direction above the third gate. The first width is less than the second width. In some embodiments, the contact isolation structure has the second width above the second gates. In some embodiments, the contact isolation structure is a first contact isolation structure, and the method further includes forming a second contact isolation structure above the first gates and the second gates. The second contact isolation structure extends longitudinally along the first direction, and the second contact isolation structure has a first width along the second direction above the first gates. The second contact isolation structure may have the first width above the second gates.

[0069] In some embodiments, the method further includes forming a first source / drain contact in the device region and forming a second source / drain contact in the isolation region. The first source / drain contact and the second source / drain contact extend longitudinally along a second direction. The first source / drain contact is disposed on the active region and the second source / drain contact is disposed on the isolation structure. The first source / drain contact is disposed between a first one of the first gates and a second one of the first gates, and the second source / drain contact is disposed between a first one of the second gates and a second one of the second gates. In some embodiments, a first pitch is located between the second source / drain contact and the first one of the second gates along a first direction, and a second pitch is located between the second source / drain contact and the third gate along the second direction. The second pitch is greater than the first pitch.

[0070] In some embodiments, the steps of forming a first gate over the active region and the isolation structure in the device region, forming a second gate over the isolation structure in the isolation region, and forming a third gate over the isolation structure in the isolation region include forming a plurality of first dummy gate stacks extending longitudinally along the second direction over the active region and the isolation structure in the device region, forming a plurality of second dummy gate stacks extending longitudinally along the second direction over the isolation structure in the isolation region, and forming a third dummy gate stack extending longitudinally along the second direction over the isolation structure in the isolation region. The third dummy gate stack is connected to at least two of the second dummy gate stacks. The method further includes removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack to form a plurality of first gate openings, a plurality of second gate openings, and a third gate opening, respectively. The first gate opening exposes the active region, the second gate opening exposes the isolation structure, and the third gate opening exposes the isolation structure. The third gate opening is connected to at least two of the second gate openings. The method further includes forming a plurality of first gate stacks over the active region in the first gate openings, forming a plurality of second gate stacks over the isolation structure in the second gate openings, and forming a third gate stack over the isolation structure in the third gate openings. In some embodiments, the method further includes forming a plurality of source / drain grooves in a plurality of source / drain regions of the active region and forming a plurality of source / drains in the source / drain grooves before removing the first dummy gate stack, the second dummy gate stack, and the third dummy gate stack. The first gate opening exposes a plurality of channel regions of the active region.

[0071] The exemplary semiconductor device structure includes a plurality of first gates longitudinally extending along a first direction in a device region, a plurality of second gates longitudinally extending along the first direction in an isolation region, and a gate support bar longitudinally extending along a second direction in the isolation region. The second direction is different from the first direction. The first gates are disposed above an isolation structure and an active region, the second gates are disposed above the isolation structure, and the gate support bar is disposed above the isolation structure. The first gates have a first height above the isolation structure and a second height above the active region, and the first height is greater than the second height. The second gates have a third height above the isolation structure, and the third height is greater than the second height. The gate support bar is connected to at least two of the second gates.

[0072] In some embodiments, the gate support bar has a third height above the isolation structure. In some embodiments, the device region does not include a gate support bar longitudinally extending along the second direction. In some embodiments, the isolation region does not include an active region. In some embodiments, the active region includes a channel structure disposed between a first source / drain and a second source / drain, and at least one of the first gates is disposed above the channel structure and between the first source / drain and the second source / drain. The channel structure longitudinally extends along the second direction.

[0073] In some embodiments, the semiconductor device structure further includes a source / drain contact isolation structure longitudinally extending along the second direction. The source / drain contact isolation structure is disposed above the first gates, the second gates, and the gate support bar. The source / drain contact isolation structure has a first width along the first direction above the gate support bar and a second width along the first direction above the first gates. The first width is greater than the second width.

[0074] In some embodiments, the device region is a first device region, the active region is a first active region, and the semiconductor device structure further includes a plurality of fourth gates longitudinally extending along the first direction in a second device region. The fourth gates are disposed above the isolation structure and a second active region, the fourth gates have a fourth height above the isolation structure and a fifth height above the second active region, and the fourth height is greater than the fifth height. The isolation region is disposed between the first device region and the second device region along the second direction, and the third height is greater than the fifth height.

[0075] In some embodiments, the semiconductor device structure further includes a source / drain contact isolation structure that extends longitudinally along a second direction. The source / drain contact isolation structure is disposed above the first gate, the second gate, and the gate support bar. The source / drain contact isolation structure has a first width along a first direction above the gate support bar and a second width along the first direction above the first gate. The first width is greater than the second width. In some embodiments, the source / drain contact isolation structure has the second width along the first direction above the second gate.

[0076] In some embodiments, the semiconductor device structure further includes a plurality of first source / drain contacts disposed in a device region and a plurality of second source / drain contacts disposed in an isolation region. At least one of the first source / drain contacts is disposed on an active region and connected to the active region, and at least one of the second source / drain contacts is disposed on an isolation structure and extends into the isolation structure. In some embodiments, a first spacing along the first direction between the gate support bar and the second source / drain contact is greater than a second spacing along the second direction between the second gate and the second source / drain contact.

[0077] In some embodiments, the gate support bar is disposed in a gate support region of the isolation region, and the gate support bar includes a plurality of first gate spacers disposed along a plurality of first sidewalls of the first gate stack. The first gate stack includes a first gate dielectric and a first gate electrode. The gate support bar is connected to a first one of the second gates and a second one of the second gates. The first one of the second gates includes a plurality of second gate spacers disposed along a plurality of second sidewalls of the second gate stack, and the second gate stack includes a second gate dielectric and a second gate electrode. The second one of the second gates includes a third gate stack having a plurality of third gate spacers, and the third gate spacers are disposed along a plurality of third sidewalls of the third gate stack, and the third gate stack includes a third gate dielectric and a third gate electrode. In the gate support region, along the first direction, the first gate dielectric surrounds the first gate electrode, and the first gate dielectric forms a first sidewall of the first gate stack. In the gate support region, along the second direction, the first gate electrode is disposed between the second gate electrode and the third gate electrode, the second gate dielectric is disposed between the second gate electrode and one of the second gate spacers, and the third gate dielectric is disposed between the third gate electrode and one of the third gate spacers.

[0078] An exemplary semiconductor device layout includes a first active gate wire, a second active gate wire, a first dummy gate wire, and a second dummy gate wire, longitudinally oriented along a first direction. The semiconductor device layout further includes a dummy gate support bar, longitudinally oriented along a second direction different from the first direction. The dummy gate support bar extends from the first dummy gate wire to the second dummy gate wire along the second direction. The semiconductor device layout further includes an active region, longitudinally oriented along the second direction. The first active gate wire and the second active gate wire are disposed above the active region. In some embodiments, the active region includes a first active region and a second active region, the first active gate wire is disposed above the first active region, the second active gate wire is disposed above the second active region, and the first dummy gate wire and the second dummy gate wire are disposed between the first active gate wire and the second active gate wire.

[0079] In some embodiments, the semiconductor device layout further includes a first source / drain contact isolation wire and a second source / drain contact isolation wire, longitudinally oriented along the second direction. The first source / drain contact isolation wire is disposed above the first active gate wire, the second active gate wire, the first dummy gate wire, and the second dummy gate wire. The second source / drain contact isolation wire is disposed above the first active gate wire, the second active gate wire, the first dummy gate wire, the second dummy gate wire, and the dummy gate support bar. The first source / drain contact isolation wire has a first width along the second direction above the first active gate wire, the second active gate wire, the first dummy gate wire, and the second dummy gate wire. The second source / drain contact isolation wire has the first width above the first active gate wire and the second active gate wire, and has a second width along the second direction on the dummy gate support bar. The second width is greater than the first width. In some embodiments, the second source / drain contact isolation wire has the second width above the first dummy gate wire and the second dummy gate wire.

[0080] The above outlines the features of several embodiments to enable those of ordinary skill in the art to which the present invention pertains to better understand the viewpoints of the embodiments of the present invention. Those of ordinary skill in the art to which the present invention pertains should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

[0081] 100: Method 105: Square 110: Square 115: Square 200: Device 202A: Device area 202B: Device area 204: Isolation area 206: Substrate 206’: Tabletop 208A: Fin 208B: Fin 210: Semiconductor layer stack 215: Semiconductor layer 220: Semiconductor layer 220’: Channel layer 225: Substrate isolation structure 225’: Isolation tabletop 230A: dummy gate 230B: dummy gate 230C: dummy gate 230D: dummy gate 230D-1: dummy gate 230D-2: dummy gate 230D-3: dummy gate 230D-4: dummy gate 232: Gate spacer 234: Inner spacer 240A: Gate structure 240B: Gate structure 240C: Gate structure 240D: Gate structure 245: Source / drain 250: Dielectric layer 252: Contact etch stop layer 254: Interlayer dielectric layer 260A: Gate opening 260B: Gate opening 260C: Gate opening 260D: Gate opening 260E: Gate opening 270A: Gate stack 270A-1: Gate stack 270A-2: Gate stack 270B: Gate Stack 270C: Gate Stack 270D: Gate Stack 270E: Gate Stack 272A: Gate Dielectric 272A-1: Gate Dielectric 272A-2: Gate Dielectric 272B: Gate Dielectric 272C: Gate Dielectric 272D: Gate Dielectric 274A: Gate Electrode 274A-1: Gate Electrode 274A-2: Gate Electrode 274B: Gate Electrode 274C: Gate Electrode 274D: Gate Electrode 280: Dielectric Layer 285: Source / Drain Contact Isolation Structure 285’: Widened Portion 290A: Source / Drain Contact 290B: Source / Drain Contact 290C: Source / Drain Contact 292: Dielectric Layer 300: Device 302A: Device Region 302B: Device Region 302C: Device Region 304A: Isolation Region 304B: Isolation Region 304C: Isolation Region 310: Dielectric Material 315: Dielectric Material 400: Method 410: Block 415: Block 420: Block B-B: Section Line C-C: Section Line C: Channel Region CPO: Gate Isolation Structure CPODE: Active Region Isolation Structure CMD: Source / Drain Contact Isolation Structure CMG: Gate Isolation Structure D-D: Section line d1: Distance d2: Distance d3: Distance d4: Distance d5: Distance E-E: Section line F-F: Section line G: Gate G-G: Section line h1: Height h2: Height HG1: Gate support structure HG2: Gate support structure l: Length MD: Source / drain contact OD: Active region ov1: Overlap ov2: Overlap S∕D: Source / drain region W: Width W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width W7: Width W8: Width x: Direction x1: Pitch y: Direction y1: Pitch y2: Pitch y3: Pitch y4: Pitch y5: Pitch y6: Pitch z: Direction

Claims

1. A method for manufacturing a semiconductor device structure, comprising: An active region is formed in a device region, wherein the active region extends longitudinally along a first direction and laterally along a second direction; an isolation structure is formed in the device region and an isolation region, wherein the isolation structure in the device region is adjacent to the active region; and a plurality of first gates are formed above the active region and the isolation structure in the device region, a plurality of second gates are formed above the isolation structure in the isolation region, and a third gate is formed above the isolation structure in the isolation region, wherein the first gates and the second gates extend longitudinally along the second direction, the third gate extends longitudinally along the first direction, and the third gate is connected to at least two of the second gates, wherein the third gate is orthogonal to the second gates in a top view.

2. The method of manufacturing the semiconductor device structure as described in claim 1 further includes forming a contact isolation structure above the first gates, the second gates, and the third gate, wherein: The contact isolation structure extends longitudinally along the first direction; and the contact isolation structure has a first width above the first gates along the second direction and a second width above the third gate extending along the second direction, wherein the first width is smaller than the second width.

3. A method for manufacturing a semiconductor device structure as described in claim 1 or 2, wherein the contact isolation structure is a first contact isolation structure, and the manufacturing method further includes forming a second contact isolation structure above the first gates and the second gates, wherein: The second contact isolation structure extends longitudinally along the first direction; and the second contact isolation structure has the first width along the second direction above the first gates.

4. The method of manufacturing a semiconductor device structure as described in claim 1, further comprising forming a first source / drain contact in the device region and forming a second source / drain contact in the isolation region, wherein: The first source / drain contact and the second source / drain contact extend longitudinally along the second direction; the first source / drain contact is disposed on the active region and the second source / drain contact is disposed on the isolation structure; the first source / drain contact is disposed between a first of the first gates and a second of the first gates; and the second source / drain contact is disposed between a first of the second gates and a second of the second gates, wherein a first spacing is located along the first direction between the second source / drain contact and the first of the second gates, and a second spacing is located along the second direction between the second source / drain contact and the third gate, and wherein the second spacing is greater than the first spacing.

5. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the steps of forming the first gates over the active region and the isolation structure in the device region, forming the second gates over the isolation structure in the isolation region, and forming the third gate over the isolation structure in the isolation region include: Multiple first dummy gate stacks are formed, extending longitudinally along the second direction above the active region and the isolation structure in the device area; multiple second dummy gate stacks are formed, extending longitudinally along the second direction above the isolation structure in the isolation region; and a third dummy gate stack is formed, extending longitudinally along the second direction above the isolation structure in the isolation region, wherein the third dummy gate stack is connected to at least two of the second dummy gate stacks; the first dummy gate stacks, the second dummy gate stacks, and the third dummy gate stack are removed to form multiple first gate openings, multiple second gate openings, and a third gate opening, wherein the first gate openings expose the active region, the second gate openings expose the isolation structure, the third gate opening exposes the isolation structure, and the third gate opening is connected to at least two of the second gate openings; A plurality of first gates are stacked above the active region in the openings of the first gates; a plurality of second gates are stacked above the isolation structure in the openings of the second gates; and a third gate is stacked above the isolation structure in the openings of the third gate. Before removing the stacks of first dummy gates, the stacks of second dummy gates, and the stack of third dummy gates, a plurality of source / drain grooves are formed in the plurality of source / drain regions of the active region and a plurality of source / drains are formed in the source / drain grooves, wherein the openings of the first gates expose the plurality of channel regions of the active region.

6. A method of manufacturing a semiconductor device structure as claimed in claim 1, wherein the first gates have a first spacing between them, the second gates have the first spacing between them, the first gates have a first height above the active region, and the second gates have a second height above the isolation structure, wherein the second height is greater than the first height.

7. A semiconductor device structure, comprising: A plurality of first gates extend longitudinally along a first direction in a device region, wherein the first gates are disposed above an isolation structure and an active region, the first gates having a first height above the isolation structure and a second height above the active region, and the first height being greater than the second height; a plurality of second gates extend longitudinally along the first direction in an isolation region, wherein the second gates are disposed above the isolation structure, the second gates having a third height above the isolation structure, and the third height being greater than the second height; and a gate support strip extends longitudinally along a second direction in the isolation region, wherein the second direction is different from the first direction, the gate support strip is disposed above the isolation structure, and the gate support strip is connected to at least two of the second gates, wherein the gate support strip is orthogonal to the second gates in a top view.

8. The semiconductor device structure as claimed in claim 7, wherein the active region includes a channel structure disposed between a first source / drain and a second source / drain, wherein at least one of the first gates is disposed above the channel structure and between the first source / drain and the second source / drain, and the channel structure extends longitudinally along the second direction.

9. The semiconductor device structure as described in claim 7 further includes a source / drain contact isolation structure extending longitudinally along the second direction, wherein: The source / drain contact isolation structure is disposed above the first gates, the second gates, and the gate support bar; and the source / drain contact isolation structure has a first width along the first direction above the gate support bar, and the source / drain contact isolation structure has a second width along the first direction above the first gates, and the first width is greater than the second width.

10. The semiconductor device structure as described in claim 7, wherein the device region is a first device region, the active region is a first active region, and the semiconductor device structure further includes: A plurality of fourth gates extend longitudinally along the first direction in a second device region, wherein the fourth gates are disposed above the isolation structure and a second active region, the fourth gates have a fourth height above the isolation structure, the fourth gates have a fifth height above the second active region, and the fourth height is greater than the fifth height; and the isolation region is disposed between the first device region and the second device region along the second direction, and the third height is greater than the fifth height.

11. The semiconductor device structure as described in claim 7, further comprising: A plurality of first source / drain contacts are disposed in the device region, wherein at least one of the first source / drain contacts is disposed on and connected to the active region; and a plurality of second source / drain contacts are disposed in the isolation region, wherein at least one of the second source / drain contacts is disposed on and extends into the isolation structure.

12. The semiconductor device structure as described in claim 7, wherein: The gate support bar is disposed in a gate support region of the isolation region; the gate support bar includes a plurality of first gate spacers disposed along a plurality of first sidewalls of a first gate stack, wherein the first gate stack includes a first gate dielectric and a first gate electrode; the gate support bar is connected to a first of the second gates and a second of the second gates, wherein the first of the second gates includes a plurality of second gate spacers disposed along a plurality of second sidewalls of a second gate stack, wherein the second gate stack includes a second gate dielectric and a second gate electrode, and the second of the second gates includes a third gate stack having a plurality of third gate spacers disposed along a plurality of third sidewalls of the third gate stack, wherein the third gate stack includes a third gate dielectric and a third gate electrode; In the gate support region, along the first direction, the first gate dielectric surrounds the first gate electrode, and the first gate dielectric forms the first sidewalls of the first gate stack; and in the gate support region, along the second direction, the first gate electrode is disposed between the second gate electrode and the third gate electrode, the second gate dielectric is disposed between the second gate electrode and one of the second gate spacers, and the third gate dielectric is disposed between the third gate electrode and one of the third gate spacers.

13. The semiconductor device structure as claimed in claim 7, wherein the device region does not include the gate support strip extending longitudinally along the second direction.

14. A semiconductor device layout, comprising: A first active gate conductor, a second active gate conductor, a first dummy gate conductor, and a second dummy gate conductor are longitudinally oriented along a first direction; a dummy gate support bar is longitudinally oriented along a second direction different from the first direction, wherein the dummy gate support bar extends from the first dummy gate conductor to the second dummy gate conductor along the second direction. And an active region, oriented longitudinally along the second direction, wherein the first active gate conductor and the second active gate conductor are disposed above the active region, wherein the dummy gate support bar is orthogonal to the second dummy gate conductor in a top view.

15. The semiconductor device layout as described in claim 14 further includes a first source / drain contact isolation wire and a second source / drain contact isolation wire, longitudinally oriented along the second direction, wherein: The first source / drain contact isolation wire is disposed above the first active gate wire, the second active gate wire, the first dummy gate wire, and the second dummy gate wire; the second source / drain contact isolation wire is disposed above the first active gate wire, the second active gate wire, the first dummy gate wire, the second dummy gate wire, and the dummy gate support bar; The first source / drain contact isolation wire has a first width along the second direction above the first active gate wire, the second active gate wire, the first dummy gate wire, and the second dummy gate wire; and the second source / drain contact isolation wire has the first width above the first active gate wire and the second active gate wire, and has a second width along the second direction on the dummy gate support bar, wherein the second width is greater than the first width, and the second source / drain contact isolation wire has the second width above the first dummy gate wire and the second dummy gate wire.

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