Memory apparatus, method for reading a selected memory cell, and memory system

Abstract

This invention discloses a technique for reading memory cells with threshold switching selectors. A sense amplifier may have a set of capacitors that can exchange charge with a sense node connected to a selected word line. The capacitors can be used to pull excess charge from the sense node or to supply charge to the sense node. Control circuitry drives current to the selected word line to charge it, thereby activating the threshold switching selector of the selected memory cell. When the threshold switching selector is activated (or shortly thereafter), the capacitors can be connected to the selected word line. The capacitors can draw away excess charge to prevent backflow current from flowing through the memory cell, thereby preventing false reads. The capacitors can reduce read latency by increasing the rate of voltage change on the word line.

Description

Technical Field

[0001] None Prior Art

[0002] Memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows storage and retention of information even when the non-volatile memory is not connected to a power source (e.g., a battery pack). Non-volatile memory can be made to exhibit non-volatility at least for a limited time by adding a battery pack back to the power supply outside the memory chip.

[0003] Memory cells can be resident in a cross-point memory array. In a memory array having a cross-point architecture, a set of conductive lines travels across the surface of a substrate, and another set of conductive lines is formed above the set of conductive lines and travels in an orthogonal direction with respect to the initial layer. Memory cells are located at the cross-point junctions of the two sets of conductive lines.

[0004] Programmable resistive memory cells are formed of a material having a programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed into one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states can be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. Compared to some other memory technologies that use electronic charge (DRAM) or voltage (SRAM) to store data, MRAM cells use magnetization to represent stored data. Data bits are written into an MRAM cell by changing the magnetization direction of a magnetic element (the "free layer") within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell, which varies with the magnetization direction.

[0005] In a cross-point memory array, each memory cell may include a threshold switching selector in series with a material having a programmable resistance. The threshold switching selector has a high resistance (in an off or non-conductive state) until it is biased to a voltage above its threshold voltage (Vt), or a current above its threshold current (It), and until its voltage bias drops below Vhold (「Voffset」) or its current drops below a holding current Ihold. While the threshold switching selector is above Vt and above Vhold, the threshold switching selector has a relatively low resistance (in an on or conductive state). The threshold switching selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by turning it on before determining the resistance state of the memory. An example of a threshold switching selector is a bidirectional threshold switch (ovonic threshold switch, OTS). Other examples of threshold switching selectors include, but are not limited to, a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly non-linear dependence of current on a selected voltage.

[0006] In a forced current technique, to read a programmable resistance memory cell in a cross-point array, a current is driven through a memory cell selected by address in one direction (the 「selected memory cell」). The address selected wire in the Y direction is actively driven to a reverse power supply; for example, a forced voltage. This current will charge the voltage across the selected memory cell until the threshold switching selector turns on. Then, while driving a read current through the programmable resistance memory element of the selected memory cell, the voltage across the selected cell is sensed.

[0007] A technique for reading programmable resistive memory cells can be referred to as global reference reading. Global reference reading is sometimes called midpoint reading or midpoint reference reading. Global reference reading can use a reference voltage between a lower resistance state (LRS) and a higher resistance state (HRS). Here, LRS and HRS refer to the voltages presented across the cell in response to a read current. For example, the midpoint reference can be a reference voltage midway between two voltages corresponding to sensing a cell with LRS or HRS. In the forced current method, the state of the memory cell is determined based on whether the sensed voltage Vsense is higher or lower than the midpoint reference voltage VREF.

[0008] Another technique for reading programmable resistive memory cells is commonly referred to as destructive self-referenced read (SRR). In SRR, rather than using a midpoint reference independent of the state of the cell, a reference is generated based on the sensed cell itself. In destructive SRR, the state of the memory cell can be changed (e.g., destroyed) by the write operation of SRR. One SRR technique includes a first read (Read1), a destructive write to a known state (e.g., high resistance state HRS), and a second read (Read2). The results of the two reads are compared to determine the original state of the cell. One technique for the first read is to apply a read current through the memory cell, resulting in a voltage across the cell having a magnitude representative of the resistance of the memory cell. The voltage is stored and adjustable (e.g., adjusted up or down by 150 mv) for comparison with a voltage sample from the second read. For each state, the voltage adjustment can be approximately half of the signal difference across the MRAM. For example, if the MRAM low resistance state (LRS) is 25 Kohm, the high resistance state is 50 Kohm, and the read current is 15 ua, then the difference from the state change is 375 mV, so the voltage can be stored from Read1 of SRR and adjusted by approximately 180 mV. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage from Read1 of SRR is adjusted upward and written to HRS, then if the cell was originally HRS, the second sampled voltage from Read2 should be approximately the same as Read1 and thus lower than the first upward adjusted voltage. Then, if the cell was originally LRS, the second sampled voltage from Read2 should be higher than the upward adjusted voltage from Read1 because of the higher Read2 voltage resulting from writing a bit from the low resistance LRS to HRS.

[0009] For two midpoint reads during the SRR period, signals, voltages, and currents are applied to conductive lines such as word lines and / or bit lines. The time to complete the read will depend on the time for the voltage on the word line and / or bit line to reach a stable voltage.

[0010] Memory elements such as, but not limited to, MRAM and OTS elements may inadvertently change their states due to the current flowing through the memory elements during a read operation. The turning on of the threshold switching selector can result in a snapback current through the memory element, which can potentially change the state of the MRAM memory element before sensing the memory element. Summary of the Invention

[0011] None Brief Description of the Drawings

[0012] Elements with similar numbers refer to common components in different drawings. [FIG. 1] is a block diagram of an embodiment of a non-volatile memory system connected to a host. [FIG. 2] is a block diagram of an embodiment of a memory die. [FIG. 3] is a block diagram of an embodiment of an integrated memory assembly including a control die and a memory structure die. [FIG. 4A] depicts in perspective view an embodiment of a portion of a memory array forming a cross-point architecture. [FIG. 4B] and [FIG. 4C] respectively present side and top views of the cross-point structure in FIG. 4A. [FIG. 4D] depicts in perspective view an embodiment of a portion of a second-order memory array forming a cross-point architecture. [FIG. 5] illustrates an embodiment of the structure of an MRAM memory cell, for example, where the selected cell here is driven by a current source for reading or writing. [FIG. 6A] and [FIG. 6B] illustrate embodiments of incorporating a threshold switching selector into an MRAM memory array with a cross-point architecture. [FIG. 7] depicts an embodiment of a memory array with a cross-point architecture accessed using a forced current method. [FIG. 8] is a diagram of an embodiment of a system for reading a memory cell with a threshold switching selector. [FIG. 9] is a flowchart of an embodiment of a procedure for reading a programmable resistance memory cell in a cross-point array. [FIG. 10] shows the voltages on the bit line and word line during the read of a memory cell with a threshold switching selector. [FIG. 11] is a schematic diagram of an embodiment of a read path connected to a sense amplifier. [FIG. 12] is a schematic diagram of an embodiment of a sense amplifier. [FIG. 13] is a table indicating signal timings in a sense amplifier for an embodiment of global reference reading, where capacitor C1 is used as a snap-back discharge capacitor. [FIG. 14A] and [FIG. 14B] depict further details of timing signals during an embodiment of global reference reading. [FIG. 15] is a table indicating signal timings in a sense amplifier for an embodiment of SRR, where capacitor C1 is used as a snap-back discharge capacitor. [FIG. 16] is a table indicating signal timings in a sense amplifier for an embodiment of SRR, where capacitor C4 is used as a write reset charge capacitor. [FIG. 17A] and [FIG. 17B] depict further details of timing signals during an embodiment of SRR. [FIG. 18] is a flowchart of an embodiment of a procedure for controlling a capacitor to accelerate the charging of a word line during a destructive write phase during SRR. [FIG. 19] is a flowchart of an embodiment of a procedure for controlling a capacitor to accelerate the discharge of a word line after a destructive write phase during SRR. [FIG. 20] is a table indicating signal timings in a sense amplifier for an embodiment of the write-back phase of SRR. [FIG. 21] is a flowchart of an embodiment of a procedure for controlling a capacitor to accelerate the charging of a word line during the write-back phase of SRR. Embodiments

[0013] Techniques for a memory system and method for reading memory cells having threshold switching selectors are disclosed. In one embodiment, a capacitor is used to exchange charge with a sense node connected to a selected conductive line, which in turn is connected to a selected memory cell. For example, the capacitor can be used to pull excess charge from the sense node to accelerate the rate of voltage drop on the selected word line to reduce read latency. In one embodiment, the capacitor can be used to provide charge to accelerate the rate of voltage rise on the selected word line to reduce read latency. In one embodiment, after the snap-back of the threshold switching selector, the capacitor draws away the charge that would otherwise flow through the selected memory cell, thereby preventing the state of the memory cell from flipping. Thus, misreading is prevented.

[0014] In some embodiments, a sense amplifier has a set of capacitors that can be used to exchange charge with a sense node connected to a selected word line. A control circuit drives a current to the selected word line to charge the selected word line to turn on a threshold switching selector of the selected memory cell. In one embodiment, when (or shortly after) the threshold switching selector is turned on, the capacitor is connected to the selected word line. Turning on the threshold switching selector may potentially cause a snapback current to undesirably flow through the memory cell. If a significant snapback current flows through the memory cell, the state of the memory cell may change, resulting in a misread. The capacitor can draw away the excess charge to thereby prevent such a snapback current from flowing through the memory cell, thereby preventing a misread. In addition, the capacitor can reduce the time it takes for the word line voltage to settle to a stable voltage (Vfinal) for sensing the state of the memory cell. Thus, the read latency is reduced. In one embodiment, the capacitor is used to exchange charge with a sense node connected to a selected word line in a global reference read. In one embodiment, the capacitor is used to exchange charge with a sense node connected to a selected word line in an SRR.

[0015] The set of capacitors can be used at different times in an SRR. The capacitor can be used to accelerate the rate of voltage increase on the selected word line for a destructive write of the SRR. The capacitor can be used to accelerate the rate of voltage decrease on the selected word line after a destructive write of the SRR. The capacitor can be used to accelerate the rate of voltage increase and / or decrease on the selected word line during a write-back phase in which the original state of the memory cell is restored in the SRR.

[0016] In one embodiment, a memory system is configured to read programmable resistive memory cells residing in a cross-point memory array. In a memory array having a cross-point architecture, a set of conductive lines travel across the surface of a substrate, and another set of conductive lines is formed above the set of conductive lines and travels over the substrate in a direction perpendicular to the set of conductive lines. Memory cells are located at the cross-point junctions of the two sets of conductive lines. A cross-point memory array is sometimes referred to as a cross-bar memory array. In one embodiment, each memory cell has a magnetoresistive memory element in series with an OTS, which can be referred to as an MRAM memory cell. However, a cross-point memory array can have other types of memory cells. For example, a cross-point memory array can have memory cells of other technologies, such as ReRam, PCM (phase change memory), FeRam. Additionally, the threshold switching selector does not need to be an OTS.

[0017] In some embodiments, the programmable resistive memory cell has a magnetoresistive random access memory (MRAM) element. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction set by another element (the "reference layer") of the MRAM. In some embodiments, the low resistance is referred to as parallel or P-state or LRS, and the high resistance is referred to as anti-parallel or AP-state or HRS. The MRAM can use the spin-transfer torque effect to change the magnetization direction from the P-state to the AP-state and vice versa, which generally requires a bipolar (bidirectional write) operation for writing. However, the SRR of the programmable resistive memory cell disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0018] FIG. 1 is a block diagram of an embodiment of a non-volatile memory system (or more simply referred to as a "memory system") 100 connected to a host system 120. The memory system 100 can implement the techniques presented herein for a system to read memory cells having a threshold switching selector. In one embodiment, the memory cell has a programmable resistive memory element (e.g., an MRAM element) in series with a threshold switching selector, such as an OTS. Many types of memory systems can be used with the techniques presented herein. Example memory systems include dual in-line memory modules (DIMMs), solid state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems can also be used.

[0019] The memory system 100 of FIG. 1 includes a memory controller 102, a memory 104 for storing data, and a local memory 140 (e.g., MRAM, ReRAM, DRAM). The local memory 140 can be non-volatile and retain data after power is turned off. The local memory 140 can be volatile and not expected to retain data after power is turned off. In one embodiment, the local memory 140 is MRAM. In one embodiment, the local memory MRAM does not need to retain data after power is turned off. However, the local memory MRAM can retain data after power is turned off. In one embodiment, the memory controller 102 and / or the local memory controller 164 provides access to programmable resistance memory cells in the local memory 140. For example, the memory controller 102 can provide access to a cross-point array of MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126 or both are removed, and the memory package is directly connected to the host 120 through a bus such as DDRn. Alternatively, they are connected to a host memory management unit (MMU). In another case, the memory controller 102 or part of it is moved onto the memory 104 for directly connecting the memory 104 to the host, such as by providing a parity bit, ECC, and wear leveling on the memory 104, as well as a DDRn interface to / from the host or MMU. As used throughout this document, the term memory system is not limited to the memory system 100. For example, the local memory 140, or the combination of the local memory 140 and the local memory controller 164, can be regarded as a memory system. Similarly, the host memory 124, or the combination of the host processor 122 and the host memory 124, is regarded as a memory system.

[0020] The components of the memory system 100 depicted in FIG. 1 are circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, a rejuvenation logic 172, and a wear leveling 174. The host interface 152 is connected to the host 120 and communicates with the host. The host interface 152 is also connected to a network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use clockless asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements over conventional buses and crossbar interconnects. Compared to other designs, the NOC improves the scalability of systems on a chip (SoCs) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystems continues to grow, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, rejuvenation logic 172, and wear leveling 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate the local high-speed memory 140 (e.g., MRAM) and communicate with the local high-speed memory. In other embodiments, the local high-speed memory 140 can be DRAM, SRAM, or another type of volatile memory.

[0021] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs encoding to provide data encoding and decoding of parity bits either on the memory or not on the memory, as part of a code word for error correction of data retrieved from the memory 140 or 104. In one embodiment, the ECC engine 158 is a circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit that does not require any software. In one embodiment, the function of the ECC engine 158 is implemented by the processor 156. In one embodiment, the local memory 140 has an ECC engine with or without a wear leveling engine. In one embodiment, the memory 104 has an ECC engine with or without a wear leveling engine.

[0022] Processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management procedures including wear leveling. A separate wear leveling 174 is depicted, but wear leveling 174 can be implemented by processor 156. Additionally, refresh logic 172 is depicted, but refresh logic can also be implemented by processor 156. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is custom dedicated hardware circuitry without any software. Processor 156 also implements a translation module as a software / firmware procedure or as dedicated hardware circuitry. In many systems, the non-volatile memory is internally addressed to the storage system using physical addresses associated with the one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to contiguous logical addresses while the storage system is free to store the data among the locations of the one or more memory dies as it desires. To implement such a system, memory controller 102 (e.g., the translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One example implementation scheme is to maintain a table (i.e., the L2P table mentioned above) that identifies the current translation between logical addresses and physical addresses. Entries in the L2P table can include the identification of the logical address and the corresponding physical address. Although the logical address to physical address table (or L2P table) includes the word "table", it does not need to be a table literally. Instead, the logical address to physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in memory 104 and a subset of the L2P tables (L2P cache) is cached in the local cache memory 140.

[0023] Memory interface 160 communicates with non-volatile memory 104. In one embodiment, non-volatile memory 104 contains programmable resistive memory cells in a cross-point array. In one embodiment, the memory interface provides a Toggle Mode interface. Other interfaces can also be used. In some example implementations, memory interface 160 (or another part of controller 102) implements a scheduler and buffer for transferring data to and receiving data from the one or more memory dies.

[0024] In one embodiment, the local memory 140 has an ECC engine. The local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window", and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window", both of which are incorporated herein by reference in their entireties. In one embodiment, the local memory 140 is synchronous. In one embodiment, the local memory 140 is asynchronous.

[0025] In one embodiment, the memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Accordingly, the memory controller 102 is connected to one or more memory dies. In one embodiment, the memory package may include other types of memory, such as storage class memory (SCM) based on programmable resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in the cross-point array in the memory package 104.

[0026] The memory controller 102 communicates with the host system 120 via an interface 152 implementing a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be removed, and the memory package can be placed directly on the host bus, such as DDRn or CXL. To work with the memory system 100, the host system 120 includes a host processor 122, a host memory 124, and an interface 126 connected along a bus 128. The host memory 124 is the physical memory of the host and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In one embodiment, the host memory 124 contains a cross-point array of programmable resistive memory cells, where each memory cell includes a programmable resistive memory element and a threshold switching selector in series with the programmable resistive memory element.

[0027] The host system 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded in the host system 120. The host memory 124 may be referred to herein as the memory system. Herein, the combination of the host processor 122 and the host memory 124 may be referred to as the memory system. In one embodiment, such host memory may be cross-point memory using MRAM.

[0028] FIG. 2 is a block diagram depicting an example of a memory die 292 in which the techniques described herein may be implemented. In one embodiment, the memory die 292 is included in the local memory 140, and in an embodiment, the memory die 292 is included in the memory 104. In one embodiment, the memory die 292 is included in the host system 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various (multiple) layers of word lines organized into columns, and various (multiple) layers of bit lines organized into rows. However, other orientations may also be implemented, including, for example, diagonal patterns to save space. The memory die 292 includes column control circuitry 220, the output 208 of which is connected to the respective word lines of the memory structure 202. The column control circuitry 220 receives a set of M column address signals and one or more various control signals from the system control logic circuitry 260, and generally may include circuitry such as a column decoder 222, a column driver 224, and block selection circuitry 226 for both read and write operations. The column control circuitry 220 may also include read / write circuitry. In one embodiment, the column decoding and control circuitry 220 has sense amplifiers 228, each of which contains circuitry for sensing the condition (e.g., voltage) of the word lines of the memory structure 202. In one embodiment, the condition or bit state of a memory cell in the cross-point array is determined by sensing the word line voltage, directly by comparing the accessed memory cell voltage with a reference voltage by a sense amplifier. Alternatively, a less direct way is to first access the memory cell and store the read voltage generated by forcing a read current through the cell and adjusting it up or down by 150 mv (or half of the voltage difference generated by changing the bit state), then write the cell to the AP state, access the memory cell again with the read current, and compare the resulting voltage with the stored voltage adjusted, for example, by 150 mV (or half of the voltage difference obtained from two different bit states). The memory die 292 also includes row decoding and control circuitry 210, the input / output 206 of which is connected to the respective bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays or "tiles" that can be accessed individually. The row control circuitry 210 receives a group of N row address signals and one or more various control signals from the system control logic 260, and generally may include circuitry such as a row decoder 212, a row decoder and driver 214, block selection circuitry 216, and read / write circuitry, and an I / O multiplexer.

[0029] The system control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, the system control logic 260 receives data and commands from a separate controller circuit and provides output data to the controller circuit, where the controller circuit communicates with the host system. Such controller systems can implement interfaces such as DDR, DIMM, CXL, PCIe, and others. In another embodiment, the data and commands are sent and received directly from the memory package to the host without a separate controller, and any required controllers are within each die or within the die added to the multi-die memory package. In some embodiments, the system control logic 260 may include a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, the state machine 262 is replaced by a microcontroller or a microprocessor. The system control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the columns and rows of the memory structure 202 during memory operations, and may include a charge pump and regulator circuitry for generating regulated voltages, and on / off control for each of the word line and bit line selections of the memory cells. In some embodiments, the power control section 264 includes one or more current sources. The (multiple) current sources can be used to provide read and / or write currents. The system control logic 260 includes a register 266 that can be used to store parameters for operating the memory structure 202. The system control logic 260 also includes refresh logic 272 and wear-leveling logic 274. Such system control logic can be commanded by the host 120 or the memory controller 102 as the refresh logic 272, which can load on-chip stored column and row addresses (pointers) that can be incremented after refresh. Only such (multiple) address bits may be selected (to refresh OTS). Alternatively, such addresses can be read, corrected by being directed through the ECC engine 269, and then stored in a "spare" location, which is also incremented (so that under the control of the wear-leveling logic 274, all codewords are periodically read, corrected, and relocated across the die) to achieve wear leveling, so that each bit on the die is used more evenly. Such operations can be more directly controlled by the host of an external controller, e.g., a PCIe or CXL or DDRn controller located separately from the memory die or on the memory die.

[0030] Commands and data are transferred between the memory controller 102 and the memory die 292 via the memory controller interface 268 (also referred to as the "communication interface"). Such interfaces can be, for example, PCIe, CXL, DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a bistable thixotropic mode interface. Other I / O interfaces can also be used. For example, the memory controller interface 268 can implement a bistable thixotropic mode interface of the memory interfaces 228 / 258 connected to the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn (such as DDR5 or LPDDR5) or a subset thereof with smaller pages and / or relaxed timing.

[0031] The system control logic 260 in the controller on the memory die located in the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 can be referred to as an on-die ECC engine because it is on the same semiconductor die as the memory cells. That is, the on-die ECC engine 269 can be used to encode the data and parity bits to be stored in the memory structure 202, and to decode and correct errors in the decoded data. The encoded data can be referred to herein as a codeword or an ECC codeword. The ECC engine 269 can be used to execute a decoding algorithm and perform error correction. Therefore, the ECC engine 269 can decode the ECC codeword. In one embodiment, the ECC engine 269 is capable of decoding the decoded data more quickly by direct decoding without iteration. Having the ECC engine 269 on the same die as the memory cells can make the decoding faster. The ECC engine 269 can use various decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC).

[0032] In some embodiments, all components of the memory die 292, including the system control logic 260, can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on different dies (such as an external controller chip).

[0033] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile or volatile memory cells, where multiple memory levels are formed over a single substrate (such as a wafer). The memory structure can include any type of non-volatile or volatile memory formed monolithically in one or more physical levels of the memory cells, and such memories have an active region disposed over a silicon or silicon-on-insulator (or other type) substrate. In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells.

[0034] The exact type of memory array architecture or memory cells included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. For the purposes of the novel claim embodiments presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memories (resistive random access memories), magnetoresistive memories (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memories (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architectures of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit-line arrays, and the like.

[0035] An example of ReRAM or MRAM cross-point memory includes a programmable resistance switching element in series with an OTS selector disposed in a cross-point array accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment of the cross-point, it is PCM in series with an OTS selector. In another embodiment, the memory cell can include a conductive bridge memory element. The conductive bridge memory element can also be referred to as a programmable metallization cell. The conductive bridge memory element can be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element can include two solid metal electrodes (one is relatively inert (e.g., tungsten) and the other is electrochemically active (e.g., silver or copper)) with a solid electrolyte film between the two electrodes. As the temperature increases, the mobility of the ions also increases, resulting in a reduction in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element has a wide range of programming thresholds with respect to temperature.

[0036] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. The element is formed by two ferromagnetic layers separated by a thin insulating layer, and each of these ferromagnetic layers can maintain magnetization. For field-controlled MRAM, one of the two layers is set as a permanent magnet with a specific polarity; the magnetization of the other layer can be changed by applying an external field to store memory. Other types of MRAM cells are feasible. The memory device can be constructed from a grid of MRAM cells or as a SOT magnetoresistive memory. Memory device embodiments based on MRAM will be discussed in more detail below.

[0037] Phase change memory (PCM) utilizes the unique behavior of chalcogenide glass. One embodiment uses a GeTe - Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms using a laser pulse (or an optical pulse from another source). The memory cell is programmed or switched between the amorphous and crystalline states by a current pulse that can change the common coordination of the PCM material. Note that the use of "pulse" in this document does not need to be a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. Also, the current forced for writing can be quickly driven to a peak, and then linearly ramped down at an edge rate of, for example, 500 ns. Such peak current forces can be limited by a zoned voltage compliance that varies depending on the position of the memory cell along the word line or bit line. In one embodiment, the phase change memory cell has a phase change memory element in series with a threshold switching selector such as OTS.

[0038] Those of ordinary skill in the art will recognize that the technologies described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather encompass many related memory structures within the spirit and scope of the technologies as described herein and as understood by those of ordinary skill in the art.

[0039] The components of FIG. 2 can be grouped into two parts: the memory structure 202 and the peripheral circuitry, including all other components. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of the memory die 292 allocated to the memory structure 202; however, this reduces the area available on the memory die for the peripheral circuitry or increases the cost associated with the die area. This can place rather severe limitations on such peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation in the sense amplifier design architecture. With respect to the system control logic 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Thus, a fundamental tradeoff in the design of the memory die 292 is the tradeoff between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry. Such a tradeoff can result in a larger IR drop due to the use of a larger x-y memory array between the drive circuits on the word lines and bit lines, which in turn can benefit more from the use of voltage limiting and partitioning of the constant current output voltage according to the memory cell positions along the word lines and bit lines.

[0040] Another aspect in which the memory structure 202 and the peripheral circuitry are often inconsistent is in the processing involved in forming these regions, because these regions often involve different processing techniques and the tradeoffs of having different technologies on a single die. For example, the components in the system control logic 260, such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry, typically employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations for fabricating a CMOS die will differ in many aspects from the processing operations optimized for only NMOS technology.

[0041] To address these limitations, the embodiments described below may separate the components of FIG. 2 onto separately formed dies that are later bonded together. FIG. 3 depicts an integrated memory assembly 270 having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuit system components, including one or more control circuits, are formed on the control die 290. For example, the memory structure die 280 may be formed solely of memory elements, such as an array of memory cells of MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuit system, even including components such as decoders, current sources, and sense amplifiers, may then be moved onto the control die. This allows each semiconductor die to be individually optimized according to its technology. This permits more space for peripheral components, which can now incorporate additional capabilities that were previously restricted by the margin required to maintain the same die as the memory cell array and could not be easily incorporated. The two dies may then be bonded together in a multi-die integrated memory assembly, where the array on one die is connected to the peripheral components on the other die. Although the following will focus on one integrated memory assembly of one memory die and one control die, other embodiments may use additional dies, such as two memory dies and one control die.

[0042] Similar to the memory die 292 of FIG. 2, the memory structure die 280 of FIG. 3 includes a memory structure 202, which may include multiple independently addressable arrays or "tiles". System control logic 260, column control circuitry 220, and row control circuitry 210 are located in the control die 290. In some embodiments, all or part of the row control circuitry 210, and all or part of the column control circuitry 220, are located on the memory structure die 280. In some embodiments, some circuitry in the system control logic 260 is located on the memory structure die 280.

[0043] FIG. 3 shows a row control circuit system 210 on a control die 290, coupled to a memory structure 202 on a memory structure die 280 via a circuit path 293. For example, the circuit path 293 can provide an electrical connection between a row decoder 212, a row driver circuit system 214, and a block selection section 216 and bit lines of the memory structure 202. The circuit path can extend from the row control circuit system 210 in the control die 290 through pads on the control die 290, which are bonded to corresponding pads of the memory structure die 280, and the corresponding pads are connected to the bit lines of the memory structure 202. Each of the bit lines of the memory structure 202 can have a corresponding circuit path connected to the row control circuit system 210 in the circuit path 293 (including a pair of bonding pads). Similarly, a column control circuit system 220 including a column decoder 222, a column driver 224, a block selection section 226, and sense amplifiers 228 is coupled to the memory structure 202 via a circuit path 294. Each of the circuit paths 294 can correspond to, for example, a word line. Additional circuit paths can also be provided between the control die 290 and the memory structure die 280.

[0044] For purposes of this document, the phrase "a control circuit" can include one or more of the following: a memory controller 102, a local memory controller 164, a processor 156, system control logic 260, a row control circuit system 210, a column control circuit system 220, a host processor 122, a microcontroller, a state machine, and / or other control circuit systems, or other similar circuits for controlling non-volatile memory. The control circuit can include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit can include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuits. Such control circuit systems can include drivers driven to a fixed voltage (such as a power supply), such as via a connection (gate to power supply) through a node of a fully-conducting transistor. Such control circuit systems can include current source drivers.

[0045] For purposes of this document, the term "apparatus" can include, but is not limited to, one or more of the following: a memory system 100, a local memory 140, a local memory controller 164 and / or a combination of a memory controller 102 and a local memory 140, a memory package 104, a memory die 292, an integrated memory assembly 270, and / or a control die 290.

[0046] In the following discussion, the memory structure 202 of FIGS. 2 and 3 will be discussed in the context of a cross-point architecture. In a cross-point architecture, a first set of conductive lines or wires (such as word lines) travels in a first direction relative to a underlying substrate; and a second set of conductive lines or wires (such as bit lines) travels in a second direction relative to the underlying substrate. Memory cells are located at the intersections of the word lines and the bit lines. The memory cells at these intersections can be formed according to any of a variety of techniques, including those described above. The following discussion will primarily focus on embodiments of a cross-point architecture based on the use of MRAM memory cells, each MRAM memory cell being in series with a threshold switching selector (such as a bidirectional threshold switch (OTS)) to form an addressable memory bit. However, the embodiments are not limited to providing current to a cross-point architecture having MRAM cells that each have a magnetic memory element in series with an OTS selector.

[0047] FIG. 4A depicts in perspective view an embodiment forming a portion of a memory array 402 of a cross-point architecture. The memory array 402 of FIG. 4A is an example of an implementation of the memory structure 202 of FIG. 2 or FIG. 3, where a memory die 292 or a memory structure die 280 can include multiple such memory arrays 402. The memory array 402 can be included in a local memory 140 or a host memory 124. Bit lines BL1 to BL5 are arranged (and shown as traveling into the page) in a first direction relative to a die's underlying substrate (not shown), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction, or diagonally to provide intersections where memory cells are interconnected between the WLs and the BLs. FIG. 4A is an example of a horizontal cross-point structure where both the word lines WL1 to WL5 and the BL1 to BL5 travel in a horizontal direction relative to the substrate, and the memory cells (two of which are indicated at 401) are oriented such that current passes through the memory cells (such as shown as Icell) in a vertical direction. In a memory array having additional memory cell layers, such as, as discussed below with respect to FIG. 4D, there will be corresponding layers of additional bit lines and word lines. For example, one pattern starting from the bottom layer would be: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0048] As depicted in FIG. 4A, memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as may be implemented using ReRAM, MRAM, PCM, or other materials with programmable resistance. Memory cells 401 may be referred to herein as programmable resistance memory cells. One type of programmable resistance memory cell is called an MRAM cell, which is a memory cell including an MRAM memory element. Memory cells 401 may also include a threshold switching selector as an additional series element within memory cell 401, such as may be implemented using: a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials providing a highly non-linear dependence of current or resistance on a switching voltage. The following discussion will focus on memory cells composed of MRAM memory elements in series combination with a bidirectional threshold switch element, but most of the discussion may apply more generally. The current in the memory cells of the first memory stage is shown flowing upward, as indicated by arrow I cell, but the current may flow in either direction to read or write the memory cell bit state, as discussed in more detail below.

[0049] Figures 4B and 4C respectively present a side view and a top view of the cross-point structure in Figure 4A. The side view of Figure 4B shows a bottom conductor (or word line) WL1, and top conductors (or bit lines) BL1 to BLn. The MRAM memory cells 401 at the intersections between each top conductor and the bottom conductor, however, PCM, ReRAM, FeRAM, or other technologies can also be used as memory elements. Figure 4C is a top view of the cross-point structure of M bottom conductors WL1 to WL M and N top conductors BL1 to BL N. In a binary embodiment, the MRAM cells at each intersection can be programmed into one of the following two resistance states: high and low. More details of the MRAM memory cell design and its read technology embodiments are given below. In some embodiments, this set of wires is arranged in a continuous array into "blocks", and such blocks can be paired adjacent to each other in the word line (WL) direction and orthogonally paired in the bit line direction to form modules. Such modules can be composed of 2 x 2 blocks to form a four-block combination, where the WL drivers between these blocks are "center driven" between these blocks, and the WL continuously travels above the transistor drivers at approximately the center of the line. Similarly, the BL drivers can be located between pairs of blocks paired in the BL direction to be center driven, whereby the transistor drivers and their area are shared between a pair of blocks. Copper or other types of low-resistance vias can decode and connect the transistor drivers / selectors to the WL or BL. In addition to the memory element, a series selection element such as an OTS can also be included between the WL and the BL in the memory cell.

[0050] The cross-point array of Figure 4A shows an embodiment with one layer of word lines and bit lines, where the MRAM or other memory technology for the memory cells is located at the intersections of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. An example of two layers is shown in Figure 4D.

[0051] FIG. 4D depicts an example of a portion of a two - level memory array forming an intersection architecture in a perspective view. Similar to FIG. 4A, FIG. 4D shows a first level 418 of memory cells 401 of the memory array 403, which are connected at the intersections of the first level word lines WL1,1 to WL1,4 and the bit lines BL1 to BL5 above. The memory array 403 may be included in the memory structure 202 of FIG. 2 or FIG. 3. A second level 420 of the memory cells is formed above the bit lines BL1 to BL5 and between these bit lines and a second set of word lines WL2,1 to WL2,4. In fact, the BLs are shared. In an alternative, the second level may include another stack of BLs located above the BLs shown and below a second stack of WLs. Although FIG. 4D shows two levels 418 and 420 of memory cells, the structure may extend upward with additional alternating levels of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array in FIG. 4D may be biased for read or program operations such that the current in each level flows from the word line level to the bit line level, or vice versa. The two levels may be structured to have current flow in the same direction in each level for a given operation, or to have current flow in opposite directions by selection of a driver in the positive or negative direction. The memory cells may be placed in the first and second levels in the same orientation, while implementing the use of opposite - direction currents layer - by - layer for reading or writing. Alternatively, the memory cells are placed in the opposite or flipped direction when placed between the BLs and WLs in the second level (while implementing the use of the same direction of current as that used for reading or writing in the memory cells in the first level).

[0052] The use of a cross-point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be resistive memory cells, where data values are encoded as different resistance levels, such as encoded as two levels in MRAM, or encoded as two or more levels for other memory element technologies (such as PCM). Depending on the embodiment, the memory cells can be binary-valued with a low resistance state or a high resistance state, or can be multi-level cells (MLCs) that can have additional resistance levels intermediate between the low and high resistance states. The cross-point arrays described herein can be used in the memory die 292 of FIG. 2, the local memory 140 of FIG. 1, and / or the host memory 124 of FIG. 1, or in any other configuration where additional memory is applicable. The resistive type memory cells can be formed according to many of the techniques mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented primarily in the context of a memory array using a cross-point architecture with binary-valued MRAM memory cells, but most of the discussion can be more generally applied to memory cells within a cross-point array or other configurations that would be apparent to one of ordinary skill in the art for other memory elements.

[0053] FIG. 5 illustrates the structure of an embodiment of an MRAM cell. The MRAM cell can be used as, for example, the programmable resistive memory cell 401 in FIGS. 4A through 4D. The MRAM memory cell includes a bottom electrode 501, a spacer 512, a threshold switching selector 502, a spacer 514, a pair of magnetic layers (a reference layer 503 and a free layer 507) separated in this example by a separating layer or tunneling layer of magnesium oxide (MgO) 505, and a top electrode 511 separated from the free layer 507 by a spacer 509. The spacer 509 can be composed of a MgO capping layer in contact with the free layer 507. The spacer 509 can also contain additional metal layers. In another embodiment, the positions of the reference layer 503 and the free layer 507 are swapped with each other, where the reference layer 503 is on top of the MgO 505 and the free layer 507 is below the MgO 505. In another embodiment, the position of the threshold switching selector 502 is between the free layer 507 and the top electrode 511.

[0054] In some embodiments, the bottom electrode 501 is a word line, and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line, and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 503 and the free layer 507: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 503 is fixed, and in the example of FIG. 5, the orientation is upward. The reference layer 503 is also referred to as the fixed layer or the pinned layer. The reference layer 503 may be composed of multiple ferromagnetic layers that are antiferromagnetically coupled in a structure commonly referred to as a synthetic antiferromagnet or simply SAF.

[0055] Data is written to the MRAM memory cell by programming the free layer 507 to have the same or opposite direction as the reference layer 503. An array of MRAM memory cells can be placed in an initial (or erased) state by setting all MRAM memory cells to the low resistance state, where all of their free layers have the same magnetic field orientation as their reference layers. Then, each memory cell is selectively programmed (also referred to as "written") by placing its free layer 507 in the high resistance state (by reversing the magnetic field to be opposite to the reference layer 503). The reference layer 503 is formed such that it will maintain its orientation when programming the free layer 507. The reference layer 503 can have a more complex design, including synthetic antiferromagnetic layers and additional reference layers. For simplicity, the figures and discussion omit these additional layers and focus only on the fixed magnetic layer that is primarily responsible for the tunneling magnetoresistance in the cell.

[0056] The threshold switching selector 502 has a high resistance (in an open or non-conductive state) until it is biased to a voltage higher than its threshold voltage, or a current higher than its threshold current, and until its voltage bias drops below Vhold (“Voffset”) or its current drops below Ihold. While the voltage across the switching selector exceeds Vt and exceeds Vhold, the switching selector has a low resistance (in a conducting or conductive state). The threshold switching selector remains conducting until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the open (higher) resistance state. Accordingly, to program a memory cell at a cross point, a voltage sufficient to turn on the associated threshold switching selector and set or reset the memory cell is applied; and to read a memory cell, the threshold switching selector is similarly activated by turning it on prior to determining the resistance state of the memory cell. A set of examples of threshold switching selectors are two-way threshold switching materials of two-way threshold switches (OTS). Example threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe 6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te, and Ge-Se-a-Te, where the atomic percentages range from a few percentages to more than 90%. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also contain additional conductive layers at the interface with the reference layer 503. For example, the spacer 514 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 514 at the interface with the reference layer 503 may consist of a single conductive layer or multiple conductive layers. The threshold switching selector 502 may also contain additional conductive layers at the interface with the bottom electrode 501. For example, the spacer 512 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 512 at the interface with the bottom electrode 501 may consist of a single conductive layer or multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, silicon carbide, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. The threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device substantially changes from insulating or quasi-insulating to conductive.

[0057] In one embodiment, a current forcing method is used to access an MRAM cell. The current forcing method can be used to read or write to the MRAM cell. In the current forcing method, an access current (e.g., Iread or Iwrite) is driven through the bottom electrode 501 by a current driver. The current will be provided by a current source based on a transistor or a resistor. In one embodiment, the current driver can be part of a column driver circuit system (e.g., array driver 224) for the electrode 501 that is address selected. However, alternatively, the current driver can be part of a row driver circuit system (e.g., driver circuit system 214) for the electrode 501 that is address selected. A voltage (e.g., Vselect) is provided to the top electrode 511. Herein, the terms "read current" (Iread) and "write current" (Iwrite) will be used in conjunction with the access current driven through the MRAM cell (or other programmable resistance cell). The write current can change the state of the MRAM cell. As an example, for an MRAM cell having a critical dimension (CD) of approximately 20 nm and an RA of 10 Ωµm2, a write current of approximately 30 uA for approximately 50 ns can be used to switch the MRAM state from the P state to the AP state. If the application time is limited (such as < 20 ns), the read current can be approximately half of the write current. A write current flowing through the MRAM cell in one direction will cause the MRAM cell in the AP state to change from the AP state to the P state. A write current flowing through the MRAM cell in the other direction (such as in the read direction) will cause the MRAM cell in the P state to change from the P state to the AP state. Generally, before determining the cell state, or capturing and storing the voltage level related to the memory cell state, the read current will preferably be set low enough and the read duration short enough so that the state of the MRAM cell is not changed from the P state to the AP state or from the AP state to the P state during the read. Generally, the write current required to switch the MRAM state from the P state to the AP state is greater in absolute magnitude than the write current required to switch the MRAM state from the AP state to the P state. The current magnitude can be adjusted accordingly by the write direction, or in the case of using a single magnitude, by the current for P to AP.

[0058] In some embodiments, a read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some embodiments, the MRAM cell reads by performing SRR (self - reference read). In one embodiment, SRR has a first read (Read1 in the P2AP direction), a first write (Write 1 to the AP state), and a second read (Read2 in the P2AP direction). The original state of the cell can then be restored by a second write (Write_Back to the P state for a bit initially in the P state). Alternatively, in another embodiment, for example, when addressing a second layer with memory cells having the same orientation as in the first layer, the SRR read current and write current are reversed.

[0059] In one embodiment, sense the voltage level of the memory cell due to Read1 in the P2AP direction and store it on a capacitor, for example; or convert it into a digital bit by an analog - to - digital converter and store these in a memory (e.g., SRAM) until after being used in Read2. The state stored on the capacitor can be adjusted by imposing a voltage on one terminal of the capacitor connected to the storage capacitor, for example, plus or minus 150 mv. Alternatively, the digitally stored level can be adjusted by adding or subtracting 150 mV digitally to the stored bit. The 150 mV can be adjusted according to the typical bit resistance. For example, if the low - resistance state of the bit is 25 K ohms and the high - resistance is 50 K, the difference is 25 K. If the read current is 15 ua, the differential voltage between the states is 25 K x 15 ua = 375 mV, making the choice of 150 mv acceptable, but perhaps indicating that 187 mV might be more optimal, for example.

[0060] Although the foregoing describes reading in the P2AP direction and a destructive write to the AP state (where it is written back to the P state after SRR), in an alternative embodiment, the first SRR has a first read (Read1 in the AP2P direction), a destructive write to the P state (Write 1), and a second read (Read2 in the AP2P direction).

[0061] In one embodiment, while driving a current, such as 15 microamperes (µA), through the bottom electrode 501, the MRAM cell is read by turning on a transistor conductively connected between 511 and a power supply, by applying, for example, approximately 0 V to the top electrode 511. This read current can flow from the bottom electrode 501 to the top electrode 511. Note that the read can be Read1 or Read2 in the P2AP direction. P2AP means the current flows along the direction that would write a bit from P to AP, or from AP to AP. In some embodiments, a bipolar write operation is used to write data to the MRAM cell. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3 V to the top electrode 511 while driving a write current, such as -30 µA, through the bottom electrode 501. This write current will flow from the top electrode 511 to the bottom electrode 501. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0 V to the top electrode 511 while driving a current, such as 30 µA, through the bottom electrode 501. This write current will flow from the electrode 501 to the electrode 511.

[0062] As an alternative to the method in FIG. 5, a select voltage can be applied to the bottom electrode 501 as the applied access current passes through the top electrode 511. In one embodiment, the MRAM cell is read by applying, for example, 3 V to the bottom electrode 501 while driving a read current, such as -15 µA, through the top electrode 511. This read current can flow from the bottom electrode 501 to the top electrode 511.

[0063] In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, -3 V to the bottom electrode 501 while driving a write current, such as 30 µA, through the top electrode 511. The electron flow will flow from the bottom electrode 501 to the top electrode 511. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0 V to the bottom electrode 501 while driving a current, such as -30 µA, through the top electrode 511. The electron flow will flow from the top electrode 511 to the bottom electrode 501. It should also be understood in this discussion that the direction of the current polarity for switching the magnetization direction of the bit to the P or AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0064] Some biasing techniques may cause voltages to be generated in unselected memory cells in the array, which may induce currents in the unselected memory cells. Although this power consumption waste can be alleviated to some extent by designing the memory cells to have a relatively high resistance level to both the high-resistance state and the low-resistance state when the WL or BL is not selected by an address, this leakage burden will still result in increased current and power consumption and impose additional design constraints on the design of the memory cells and the array. One way to address this unwanted current leakage is to place selector elements in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a select transistor can be placed in series with each resistive memory cell element in FIGS. 4A-4D, such that the memory cell 401 is now a composite of the select transistor and the programmable resistor. Such an architecture can be referred to as 1T1R. However, the use of a select transistor requires the introduction of additional control lines and cell area to be able to turn on the corresponding transistor of the selected memory cell. Additionally, transistors often cannot scale in the same way as the write current of the resistive memory element, such that when the memory array is scaled down in size, the use of a transistor-based selector may become a limiting factor, e.g., in terms of reducing cost. An alternative to a select transistor is to use a threshold-switching selector (e.g., threshold-switching selector 502) in series with the programmable resistive element. The two-terminal threshold-switching selector does not require the aforementioned additional control lines and additional cell area to be able to turn on the corresponding select transistor of the selected memory cell. In some embodiments, a memory system as described herein performs a read of a memory cell having a two-terminal threshold-switching selector in series with a programmable resistive memory element.

[0065] Figures 6A and 6B illustrate an embodiment of incorporating a threshold switching selector into an MRAM memory array having a cross-point architecture. The examples of Figures 6A and 6B show two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer cross-point array, such as shown in Figure 4D, but are shown in a side view. As depicted in Figure 6A, the direction of the MRAM layers is kept the same as that of the layer 1 cell and the layer 2 cell, allowing the same manufacturing process for each layer. While Figure 6B has inverted memory cells, which allows the drive circuitry to work in the same way; for example, for each layer, the BL is lowered to Read P2AP. Figures 6A and 6B show a first lower conductive line of word line 1 600, a first upper conductive line of word line 2 620, and a second intermediate conductive line of bit line 610. In these figures, for ease of presentation, all these lines are shown as traveling from left to right across the drawing, but in the cross-point array, they would be represented more accurately as in the perspective view of Figure 4D, where the word lines (or first conductive lines or wires) travel in one direction parallel to the surface of the underlying substrate, and the bit lines (or second conductive lines or wires) travel in a second direction parallel to the substrate surface that is mainly orthogonal to the first direction. The MRAM memory cells are also represented in a simplified form, showing only the reference layer, the free layer, and the intermediate tunneling barrier, but in an actual implementation, generally additional structures related to Figure 5 in the above description would be included.

[0066] An MRAM element 602 including a free layer 601, a tunneling barrier 603, and a reference layer 605 is formed above a threshold switching selector 609, where this series combination of the MRAM element 602 and the threshold switching selector 609 together forms a layer 1 cell between the bit line 610 and the word line 1 600. The series combination of the MRAM element 602 and the threshold switching selector 609 operates mostly as described above when the threshold switching selector 609 is turned on. Although, the threshold switching selector 609 initially needs to be turned on by applying a voltage higher than the threshold voltage Vth of the threshold switching selector 609, and the bias current or voltage then needs to be kept high enough to be higher than the holding current or holding voltage of the threshold switching selector 609 to keep it on during subsequent read or write operations.

[0067] On the second layer, an MRAM element 612 including a free layer 611, a tunneling barrier 613, and a reference layer 615 is formed above a threshold switching selector 619, wherein the series combination of the MRAM element 612 and the threshold switching selector 619 together forms a layer 2 cell between a bit line 610 and a word line 2 620. The layer 2 cell operates in the same manner as the layer 1 cell, although the lower conductor now corresponds to the bit line 610 and the upper conductor now is the word line (word line 2 620). Additional paired layers can similarly share another bit line between them, having the following patterns: WL1, BL1, WL2; WL3, BL2, WL4; or having separate bit lines in the pattern, such as WL1, BL1, WL2, BL2. Or having separate bit lines in the pattern of WL1, BL1, BL2, WL2.

[0068] In the embodiment of FIG. 6A, the threshold switching selector 609 / 619 is formed below the MRAM element 602 / 612, but in an alternative embodiment, the threshold switching selector can be formed above one or two layers of MRAM elements. The MRAM memory cell is directional. In FIG. 6A, the MRAM elements 602 and 612 have the same direction, wherein the free layer 601 / 611 is above the reference layer 605 / 615 (relative to a substrate not shown). Since each of the two layers and subsequent layers in embodiments with more layers can be formed according to the same process sequence, forming these layers with the same structure between conductive lines can have several advantages, especially regarding the process.

[0069] FIG. 6B shows an alternative embodiment configured similarly to the embodiment of FIG. 6A, except that in the layer 2 cell, the positions of the reference layer and the free layer are reversed. More specifically, as in FIG. 6A, between a word line 1 650 and a bit line 660, the layer 1 cell includes an MRAM element having a free layer 651 formed above a tunneling barrier 653, which in turn is formed above a reference layer 655, wherein the MRAM element 652 is formed above a threshold switching selector 659. The second layer of the embodiment of FIG. 6B again has an MRAM element 662 above a threshold switching selector 669 formed between the bit line 660 and a word line 2 670, but relative to FIG. 6A, in a reversed state of the MRAM element 662, such that the reference layer 661 is now formed above the tunneling barrier 663 and the free layer 665 is now below the tunneling barrier 663. Alternatively, the configuration of the MRAM element 662 can be used for the layer 1 cell and the configuration of the MRAM cell 652 can be used for the layer 2 cell.

[0070] Although the embodiments of FIG. 6B require different program sequences to form the layers, in some embodiments, it may have advantages. Specifically, the directionality of the MRAM structure may make the embodiments of FIG. 6B attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit line biases both the lower and upper layers equally, and the biases of the two word lines are also the same. For example, if the sense layer 1 and layer 2 memory cells are sensed in the P2AP direction (relative to the reference layer and the free layer), the bit line layer 660 will be biased in a direction such as P2AP. For both the upper and lower cells, when both the word line 1 650 and the word line 2 670 are biased to a higher voltage level, the bit line 660 is biased to a lower voltage level (e.g., 0V). Regarding writing, the situation is similar when writing into the high-resistance AP state. When both the word line 1 650 and the word line 2 670 are biased to a higher voltage level, the bit line 660 biases both the upper and lower cells to a lower voltage level (e.g., 0V).

[0071] Reading data from or writing data into an MRAM memory cell involves passing a current through the memory cell. In embodiments where the threshold switch selector is placed in series with the MRAM element, the threshold switch selector can be turned on by applying a sufficient voltage across and passing a sufficient current through the series combination of the threshold switch selector and the MRAM element before the current can pass through the MRAM element.

[0072] FIG. 7 depicts an embodiment of a memory array 700 having a cross-point architecture. The memory array 700 can be included in the memory structure 202 of FIG. 2 or FIG. 3. The array 700 has a set of first conductive lines 706a to 706h and a set of second conductive lines 708a to 708d. In one embodiment, the set of first conductive lines 706a to 706h are word lines, and the set of second conductive lines 708a to 708b are bit lines. For ease of discussion, the set of first conductive lines 706a to 706h can be referred to as word lines, and the set of second conductive lines 708a to 708b can be referred to as bit lines. However, the set of first conductive lines 706a to 706h can be bit lines, and the set of second conductive lines 708a to 708b can be word lines.

[0073] The memory array 700 has a plurality of programmable resistive memory cells 401. Each memory cell 401 is connected between one of the first conductive lines 706 and one of the second conductive lines 708. In one embodiment, each memory cell 401 has a magnetoresistive random access memory (MRAM) element in series with a threshold switching selector. The threshold switching selector 502 is configured to conduct with a lower resistance in response to a voltage level that exceeds the threshold voltage of the threshold switching selector 502, and to maintain conduction with the lower resistance until the current through the switching selector 502 drops below the selector holding current (Ihold). The threshold switching selector 502 can be a two-terminal device. In one embodiment, the threshold switching selector 502 includes an OTS.

[0074] For purposes of discussion, memory cell 401a is selected for access. This can be read or write access. The selected memory cell 401a is at the intersection of the selected word line 706g and the selected bit line 708b. A selected memory cell means a memory cell that is selected for a memory operation such as read or write. The selected memory cell is connected between the selected word line and the selected bit line. To select the memory cell 401, a select voltage (Vselect_BL) such as near ground is provided to the selected bit line (e.g., bit line 708b), and an access current (Iaccess) is driven (or forced) through the selected word line (e.g., word line 706g). A selected word line means the word line that is connected to at least one selected memory cell. The selected word line will generally be connected to one or more unselected memory cells. A selected bit line means the bit line that is connected to at least one selected memory cell. The selected bit line will generally be connected to one or more unselected memory cells.

[0075] In one embodiment, assuming that I access is applied to a selected word line with a constant current output voltage sufficient relative to the BL voltage, V select_BL has a sufficient magnitude such that the threshold switching selector 502 in the selected memory cell will conduct. For example, V select_BL can be approximately 0V. On the other hand, the magnitude of V unsel_BL is such that the threshold switching selector 502 in the unselected memory cell will not conduct. For example, if the positive supply is 3.3V, then V select_BL can be approximately 1.65V. The access current (I access) is driven through at least a portion of the selected word line 706g. This access current can also flow through the selected memory cell 401a and a portion of the selected bit line 708b after the OTS conducts. Such a selected WL can be driven up to, for example, 15 µa to read or up to, for example, 30 µa to write by a current source having a constant current output (compliance) voltage, such as 3.3V. To write the opposite polarity, the selected word line is forced with, for example, -30 µa, and the selected bit line is forced to be close to 3.3V.

[0076] Other memory cells are not selected for access (i.e., are unselected memory cells). An unselected memory cell means that the memory cell is not currently selected for access (e.g., read or write). Unselected word lines are only connected to unselected memory cells. Unselected bit lines are only connected to unselected memory cells. The unselected word lines and bit lines are respectively referred to as unselected word lines or unselected bit lines. In one embodiment, the word lines and bit lines can be deselected by forcing them to an unselected voltage, such as Vmid, for example 1.65V, which is approximately half of the constant current output voltage (e.g., 3.3V) being driven. The unselected voltage (V unsel_BL) is provided to the unselected bit lines (e.g., bit lines 708a, 708c, 708d). The unselected voltage (V unsel_WL), such as Vmid, is provided to the unselected word lines (e.g., word lines 710a, 710b, 710c, 710d, 710e, 710f, and 710h). I access can flow through the selected word line (and the selected bit line) in either direction. In one embodiment, except for leakage current, no current is forced through the unselected word lines (e.g., 706a, 706b, 706c, 706d, 706e, 706f, and 706h).

[0077] In the example of FIG. 7, there are more word lines than bit lines in the cross-point array. In one embodiment, there are more bit lines than word lines in the cross-point array. In one embodiment, the number of bit lines in the cross-point array is equal to the number of word lines. In the example of FIG. 7, the number of word lines in the cross-point array is up to twice the number of bit lines; however, different ratios can be used. Thus, different block sizes can be achieved. For example, a block can have 1024 BL x 2048 Wl, which can be configured as a module of 2048 x 4096 cells by centrally driving the WL and BL between four blocks. In one embodiment, a set of memories is read by, for example, selecting one memory cell from each of a number of blocks. In some embodiments, more than one memory cell from a block can be selected for reading.

[0078] In some embodiments, a current forcing method is used to access memory cells in a cross-point memory array. A threshold switching selector can be used in series with the memory cell. The threshold switching selector can be connected in series with the memory element between the word line and the bit line. Thus, any voltage across the switching selector will reduce the voltage across the memory element. Generally, there will be some variation in the offset or holding voltage between the switching selectors. The current forcing method can help mitigate the offset voltage variation between the threshold switching selectors to help minimize the selected cell current variation between cells.

[0079] FIG. 8 is a diagram of an embodiment of a system for reading memory cells with threshold switching selectors. The system has a current source 802, control circuitry 804, and a sense amplifier 806. Each memory cell 401 has a programmable resistive memory element 702 in series with a threshold switching selector 502. In one embodiment, the memory cell 401 is an MRAM cell, where the programmable resistive memory element 702 is a magnetoresistive memory element and the threshold switching selector 502 is an OTS. However, the memory cell can be a PCM cell, a ReRaM cell, etc. The threshold switching selector 502 does not need to be an OTS. The threshold switching selector 502 can instead be a volatile conductive bridge (VCB), metal-insulator-metal (MIM), or other materials that provide a highly non-linear dependence of current on the selected voltage. The voltage Vselect on the bit line (BL) is a voltage having a magnitude suitable for selecting the memory cell, such as 0V. Vselect to the bit line is close to 3.3V in one embodiment and close to 0V in another embodiment.

[0080] The output of current source 802 is connected to a node called VXSP. The node VXSP can be connected to the word line via an address decoding transistor, where the source-drain connection is between VXSP and the word line, and the gate is connected to the binary address signal. Such a transistor can be a p-channel or an n-channel one. The system can have a WL decoder for selecting which word line is connected to the current source 802. Such a WL decoder is not depicted in FIG. 8. The node VXSP can be connected to the input of the sense amplifier 806 and can thus be called a sense node. The current source 802 supplies a current (Isource) to the selected word line. Note that the current source 802 can use different magnitude current generators for the read current and the write current. In one embodiment, the current source 802 provides a first write current to "set" the memory cell and a second write current to "reset" the memory cell, where the two write currents have opposite polarities. During a read, the current can charge the selected word line until the threshold switching selector 502 turns on. After the threshold switching selector 502 turns on, Isource is driven through the memory cell 401 in a direction and magnitude designed for reading and / or writing.

[0081] The sense amplifier 806 (more simply referred to as "sense amp") can be connected to node VXSP and can sense the memory cell 401 while driving Isource through the memory cell 401. The sense amplifier 806 has a set of capacitors 810. In one embodiment, the sense amplifier includes a differential amplifier that is capable of comparing the voltage on VXSP with a reference voltage (e.g., Vref). In one embodiment, one of the capacitors in the sense amplifier 806 can be connected to node VXSP to sense and store the voltage on VXSP to sense the memory cell. In one embodiment, the capacitor 810 includes one or more additional capacitors that can be connected to node VXSP (and thus to the selected word line) during a read operation. As will be explained in more detail below, these one or more additional capacitors can be used to add or remove charge from node VXSP (and thus from the selected word line). In one embodiment, the capacitor can be connected to node VXSP (and thus to the selected word line) immediately after the threshold switching selector 502 is turned on. If BL is close to 0, the disconnect OTS occurs at the Vth on WL. Before conduction, only the leakage current to the unselected bits flows when the WL and BL are selected, and the read current charges the WL to turn on the OTS, and then through the selected memory cell. Then, the voltage between WL and BL drops suddenly from Vth to Voffset plus Iread times the path resistance from VXSP to ground (as described later, such as the select transistors T1+T3 to WL and T1+T3 to BL and the memory cell resistance and voltage (mram+ots) and the drive transistors T1+T3 driving from ground to the bit line. Any voltage difference is discharged through the memory cell and other loads. This capacitor can be precharged to a lower voltage and thus serves as a load that removes charge from node VXSP (and thus from the selected word line) when the transistor is connected to VXSP. Removing charge from node VXSP (and thus from the selected word line) can prevent unwanted current exceeding Iread from flowing in the memory element 702, thereby helping to avoid the memory element 702 changing its state before sensing the voltage after the voltage on the memory element 702 has stabilized after address selection and OTS conduction. Another benefit of removing charge from node VXSP (and thus from the selected word line) immediately after the threshold switching selector 502 is turned on is to accelerate the rate at which the selected word line drops to a stable voltage, thereby reducing the read latency during a sense read operation or reducing the time to establish the write voltage during a write.

[0082] The capacitor 810 can be used for global reference reading (also known as midpoint reading) or in SRR. In one embodiment of SRR, one of the capacitors is used to provide charge to node VXSP (and thus to the selected word line) to accelerate the rate of charging the word line to the write voltage. This write can be a destructive write between Read1 and Read2, or (if needed) a write-back used to restore the original state of the memory element 702. In one embodiment of SRR, one of the capacitors is used to discharge node VXSP (and thus the selected word line) after the current from current source 802 is reduced from the write current to the read current. Thus, such capacitors can be used to accelerate the rate of discharging the selected word line, such that Read2 can be performed more quickly, thereby reducing the read latency.

[0083] FIG. 9 is a flowchart of an embodiment of a procedure 900 for reading programmable resistive memory cells in a read cross-point array. The procedure can be used to read memory cells having a threshold switching selector 502 (such as but not limited to OTS). Procedure 900 can reduce the read latency. Procedure 900 can improve the read accuracy (bit error rate) by preventing the memory cells from inadvertently flipping their states before sensing the memory cells. In one embodiment, procedure 900 is used for midpoint reading. In one embodiment, procedure 900 is used in SRR.

[0084] Step 902 includes applying a select voltage to a first conductive line. For example, control circuit 804 provides the select voltage to the bit line. As an example, the bit line can be grounded to select the bit line; however, other voltages can be used. Step 902 can include applying a voltage to the global and / or local bit line decoder based on the address of the selected memory cell.

[0085] Step 904 includes providing a signal (e.g., current) to a second conductive line to turn on the threshold switching selector 502. For example, control circuit 804 controls current source 802 to apply Isource to the word line. Control circuit 804 can control the magnitude of the current by selecting which current to apply from current source 802. Step 902 can include applying a voltage to the global and / or local word line decoder based on the address of the selected memory cell.

[0086] Step 906 includes connecting a first capacitor of the sense amplifier 806 to a second conductive line after the threshold switching selector 502 has been turned on. Step 906 may include connecting the first capacitor to a sense node VXSP connected to a word line, thereby connecting the first capacitor to the word line. The threshold switching selector 502 may have a high resistance before being turned on; however, when the threshold switching selector 502 is turned on, the resistance may drop rapidly. The rapid drop in resistance may result in what may be referred to as "excess charge" at the node VXSP and / or the word line. The excess charge may potentially flow in the memory element 702, which may potentially change the state of the memory element 702, thereby causing a read error. In one embodiment, the excess charge is transferred from the node VXSP and / or the word line to the first capacitor, which may reduce the flow of unwanted current in the memory element 702 (above the desired Iread current), thereby preventing a change in the state of the memory element 702. Additionally, by removing charge from the node VXSP and / or the word line, the first capacitor may help reduce the voltage stabilization on the second word line to the time it takes to sense the memory cell.

[0087] Step 908 includes disconnecting the first capacitor from the second conductive line. The first capacitor may be disconnected after the voltage on the second conductive line has stabilized, but the memory system does not need to wait until the voltage has stabilized to disconnect the first capacitor from the second conductive line. In one embodiment, the memory system connects more than one capacitor to the second conductive line to quickly reduce the voltage on the second conductive line. Then, after the voltage has dropped appreciably, the memory system disconnects one of the capacitors, while the other capacitor remains connected to the second conductive line. The two capacitors may include a larger capacitor and a smaller capacitor. The purpose of the larger capacitor is to be large enough to quickly discharge VXSP. However, a large capacitance may result in a longer settling time for Vfinal required to distinguish between the two states of the memory cell. Thus, attaching two capacitors can quickly discharge VXSP. Then, disconnecting the larger capacitor and leaving the smaller capacitor can speed up the settling time, so VXSP reaches Vfinal more quickly. This technique of using two capacitors can be used to reduce the time it takes for the voltage on the second conductive line to stabilize.

[0088] Step 910 includes sensing the memory cell while driving current through the memory cell and while both capacitors are connected to, or the first capacitor or the second capacitor is disconnected from, the second conductive line, or neither is disconnected. In one embodiment, the sensing is a Read1 for the SRR. In one embodiment, the second capacitor is connected to VXSP to sense the memory cell. The second capacitor can be used in the Read1 of the SRR to sense and store the voltage at VXSP. In one embodiment, the sensing is for a midpoint read. In one embodiment of the midpoint read, the sense amplifier 806 can compare the voltage at VXSP with a reference voltage (Vref) after VXSP has settled sufficiently near Vfinal (such that the difference is less than the available margin in the sensed bit state).

[0089] FIG. 10 shows the voltages on the bit line and the word line during the read operation of a memory cell with a threshold switching selector. Initially, the voltages on the bit line and the word line are each set to Vmid (e.g., about 1.65V). At t1, the bit line is connected to ground, where the voltage on the bit line decreases from Vmid to ground before t2. In this example, the select voltage for the bit line is close to ground. Also at t1, the voltage on the word line (WL) starts to increase as current source 802 begins to supply current to the word line. This current can be equal to the read current used when sensing and using the voltage. At t3, the threshold switching selector 502 turns on. The resistance of the threshold switching selector 502 can rapidly decrease when it turns on, which can be referred to herein as a "snapback", which is the difference between the voltage on the word line in the OTS on condition, and the voltage after the voltage on the word line stabilizes in the condition where the read current flows through the selected memory element. At t3, the voltage on the word line starts to drop (see trace 1010). At t4, the first capacitor is connected to the word line, which rapidly discharges the word line (see trace 1012). The word line can reach a stable voltage relatively quickly (see trace 1016). The memory cell can be sensed while the word line is at the stable voltage, such as at t5, rather than having to wait until t6 if the first capacitor was not connected to the word line. In one embodiment, the first capacitor is disconnected from the word line before sensing the memory cell. In one embodiment, a second (sensing) capacitor can be connected to the word line to sense and store the voltage from the memory cell for later adjustment to the midpoint of the possible signal difference from the memory cell. This second (sensing) capacitor can also be connected to the word line while the first capacitor is connected to the word line. The first capacitor can also be used instead of the second capacitor for sensing and storing. The size of the first capacitor can be adjusted for an optimal voltage drop for VXSP, as the first capacitor is mainly responsible for discharging the word line. If the first capacitor was not connected to the word line, the voltage on the word line may take much longer to decrease and stabilize (see trace 1014). Thus, sensing of the memory cell would need to wait until after t6. Therefore, connecting the first capacitor to the word line after the threshold switching selector 502 turns on can reduce the read latency. Additionally, the snapback can potentially cause an unwanted current in the memory element 702, which can potentially flip the state of the memory element 702, resulting in a read error. However, connecting the first capacitor to the word line after the threshold switching selector 502 turns on can divert such unwanted current from flowing in the memory element 702 and instead flow into the first capacitor, thereby preventing the aforementioned flip of the memory element state.

[0090] FIG. 11 is a schematic diagram of an embodiment of a read path and a sense amplifier. The read path includes a current source, a word line decoding transistor, a selected word line, a memory cell, a selected bit line, and a bit line decoding transistor. The read path has a Vp positive power supply, such as 4V. The read current source 1102 is connected to the power supply (Vp) and supplies Iread to the memory cell. The read current can be enabled by pulling Read* low to turn on transistor T1. The output of T1, which is node VXSP, also drives the non-inverting input (+) of the differential sense amplifier 806. The P-channel transistor T3P acts as a global WL decoder and can be selected when the gate of T3P is low (such as when driven by a binary decoder address signal from the host). The P-channel transistor T1P acts as a local WL decoder and can be selected when the gate of T1P is low (such as when driven by a binary decoder address signal from the host). The P-channel transistor T3P can act as a driver to the selected WL. The memory cell 401 is connected between the selected WL and the selected BL. The memory cell (or bit) has a threshold switching selector 502 and a memory element 702. The selected WL can be one of the N WLs in the array. The selected BL can be one of the M BLs in the array. The memory cell 401 can be located at the intersection of the selected WL and the selected BL on a chip having one or more arrays. The N-channel transistor T1N can act as a local decoding driver to the selected BL. The BL can be selected when the T1N gate is high (such as when driven by a binary decoder address signal from the host). The N-channel transistor T3N acts as a global decoder and is selected when the T3N gate is high (such as when driven by a binary decoder address signal from the host). The output of T3N is VYS. A driver (YEN) is located between VYS and the negative power supply (GND). For reverse writing, there can be a separate driver connected to VYS and a positive power supply Vp to which VYS drives, and a parallel p-channel transistor decoding path (n-channel T1 and T3) parallel to the n-channel driver path described here can be provided. Then, the n-channel path is disconnected, and the p-channel path is enabled to Vp together with the driver transistor, with the gate grounded. Similarly, the n-channel path can be provided together with a current source to ground, which is provided in parallel with the above p-channel path to the word line, where the current source of the word line is to Vp or some other suitable voltage. Then, the p-channel path is disconnected, and the n-channel path is enabled by turning on the n-channel driver transistor in series with the current source to ground. The sense amplifier 806 has a non-inverting input (+) and an inverting input (-). The inverting input (-) is provided with a reference voltage (Vref). The non-inverting input (+) is connected to VXSP.

[0091] In one embodiment, the operation of reading a path may be as follows. Nodes VXSP, selected WL, selected BL, and VYS may be transistors precharged to Vmid during the standby phase. The desired WL line (one out of N) may be selected by disconnecting the precharge and applying a low voltage (gate voltage is called the decoded address signal) to the gates of transistors T3P and T1P. The BL line may be selected by disconnecting the precharge and applying a high voltage (gate voltage is called the decoded address signal) to the gates of transistors T1N and T3N. The gate of transistor YEN may be pulled high to connect node VYS to GND. Then, Iread may be turned on and connected to VXSP by pulling the gate of T1 low (e.g., Read* goes low). Thus, when turned on by YEN becoming H, BL may be quickly pulled to GND by its main driver. The selected WL and VXSP ramp down towards Vp at a rate of Time = Ctotal x V / Iread through Iread. When the voltage on WL reaches approximately the voltage Vth(OTS), the threshold switching selector 502 turns on because the IxR voltage drop due to leakage current is relatively low. Here, Vth(OTS) refers to the threshold switching voltage of the threshold switching selector 502, which may be but does not need to be OTS. Then, the voltage on VXSP in the sense amplifier 806 settles back to Vfinal = Vread(final) = Voff(OTS) + Rpath x Iread. Here, Rpath includes the WL and BL wire resistances, the address transistors (T3P, T1P, T1N, T3N), and the driver to GND (YEN), as well as the resistance of the memory element itself 702. Here, Voff(OTS) refers to the voltage across the threshold switching selector 502. The sense amplifier 806 compares the input Vfinal on the sense amplifier (+) with Vref on the sense amplifier (-).

[0092] FIG. 12 is a schematic diagram of an embodiment of the sense amplifier 806. For each of the n-channel transistor or the p-channel transistor, except for the cross-coupled and time-controlled transistors T16, T17, T21, complementary transistors (p-channel or n-channel) can be added in parallel and driven by complementary signals. The sense amplifier 806 has several capacitors C1, C2, C3, and C4. In one embodiment, C1 is a discharge capacitor for discharging VXSP when the threshold switching selector 502 is turned on or immediately after that. In one embodiment, C2 is a Read1 storage capacitor for sensing VXSP (e.g., sensing a memory cell). Note that C2 can also store the voltage sensed at VXSP for later comparison with the voltage sensed at VXSP during Read2 (where the voltage stored on C2 is appropriately adjusted by disconnecting T28 and then pulsing a positive Vbump (e.g., 150 mv) sufficient to raise the voltage). Transistors T19 and T20 provide the ability to bistable thixotropy between Vbump and ground using the Bump and Bump_Bar signals. Here, Bump bar is the logical complement of Bump. In one embodiment, C3 is a reset discharge capacitor written to discharge VXSP (e.g., discharge the selected WL) after a destructive write of SRR. Capacitor C3 can be used to accelerate the discharge of the selected WL when the current decreases from Iwrite to Iread. In one embodiment, C4 is a write reset charge capacitor for charging VXSP (e.g., charging the selected WL) at the start of a destructive write of SRR. Capacitor C4 can be used to accelerate the charging of the selected WL when the current increases from the read current to the write current. In one embodiment, the sense amplifier 806 has a fifth capacitor C5 (not depicted in FIG. 12) that can be used as a charge capacitor set for writing. The optional fifth capacitor C5 can be used to charge VXSP (e.g., charge the selected WL) during the second write of SRR, and the second write is used to restore the original state of the memory cell 401 if needed. Further details of the sense amplifier 806 will be discussed below.

[0093] In some embodiments, capacitors in the sense amplifier are used during global reference reads to discharge the selected word line when the threshold switching selector is turned on (or shortly after that). In one embodiment, C1 is a discharge capacitor for discharging VXSP when the threshold switching selector 502 is turned on or immediately after that. In one embodiment, the procedure 900 of FIG. 9 is used for global reference reads, where C1 is used as the discharge capacitor for discharging VXSP when the threshold switching selector 502 is turned on or immediately after that.

[0094] Table 1300 indicates the signal timing in sense amplifier 806 for an embodiment for global reference reading, where C1 is used as the step - discharge capacitor. Table 13 lists the signals applied at the gates of various transistors in sense amplifier 806 in FIG. 12. The Read signal refers to the signal that initiates the read current (see Read* at the gate of T1 in FIG. 11). Table 1300 provides descriptions of the various signals. Each time box represents the time interval during which the signal is enabled (black) or disabled (white). The time boxes are sorted from earlier time to later time, but each time box does not necessarily have the same duration. This table is used to illustrate the synchronization relationship between the signals. The best transition between the enabled signal state and the disabled signal state does not need to occur at the start of the time interval and can be time - shifted relative to other signals within the same time box. At box 0, one or more capacitors in sense amplifier 806 are pre - charged. In one embodiment, C1 is pre - charged to a voltage, such as close to ground, which is tuned to provide a rapid discharge of VXSP to near its ReadVfinal during Read1. C1 is pre - charged to near GND in one embodiment and to near Vmid in another embodiment. The size of C1 can be selected based on other capacitances in the circuit. For example, the size of C1 can be selected based on the capacitance along the read path. These read - path capacitances can be segmented into two separate capacitances C_CMOS and C_array. For example, C_CMOS is the combined capacitance of transistors, wires, and circuitry in the read path between the current mirror and the cross - point array. That is, C_CMOS represents all the capacitances outside the cross - point array, and the stored charge in the cross - point array will discharge through the selected memory cell after the selector turns on. C_array is the combined capacitance of the selected WL or BL, vias, and other wiring located between the select transistor and the selected memory element. As an example, C1 can be between about 10% and 50% of the combined CMOS and array capacitances. The CMOS and array capacitances can range from 50 fF to 200 fF or more. Example ranges for C1 are between 10 femtofarads (fF) and 100 fF (i.e., between 10 x 10^ - 15 farads and 100 x 10^ - 15 farads), where the actual range and size are adjusted by the process selection of CMOS transistors and their sizes, array wire lengths, widths, and pitches (spacing), as well as the memory cell diameter (CD) and height, and the side - tilt angles along the memory and selector elements. At box 0, Trap, Precharge, S1, and S3 are high. At box 1, Trap, Precharge, S1, and S3 are low.

[0095] At block 1 (time t1 in FIG. 10) in FIG. 13, the Read signal is used to enable the read current (e.g., T1 in FIG. 11 is turned on). As previously discussed, the read current will charge the selected WL. The duration of block 1 is long enough to provide sufficient voltage for turning on the threshold switching selector 502 (time t3 in FIG. 10). Trap is low in block 1 and high at blocks 2 and 3. When Trap is low, the sense amplifier is isolated from the data input. Trap being high enables signals to enter the sense amplifier. At blocks 2 to 4, S1 is high. At block 2, S3 is high. Referring to FIG. 12, “Trap” is applied to T12 and T13 at blocks 2 and 3. At block 2, the VXSP and VREF connections are enabled. Referring to FIG. 12, S1 is applied to T11 to connect the sense amplifier 806 to VXSP. At block 2 (time t4 in FIG. 10), the signal S3 is used to enable the snap-back discharge capacitor C1, and this snap-back discharge capacitor is disconnected at block 3. Referring to FIG. 12, S3 is applied to the gate of T26 to connect C1 to VXSP. Thus, the snap-back discharge capacitor C1 can discharge VXSP (and thus will discharge the voltage on WL). After block 3, the snap-back discharge capacitor C1 is disconnected from VXSP. Note that when T11, T12, T13, and T14 are all turned on, T16 and T17 are connected to VXSP and Vref. Additionally, S2 is high at blocks 3 and 4 to enable the Vref connection. Referring to FIG. 12, S2 is applied to T14 to enable Vref. Note that when T13 and T14 are both turned on, the cross-coupled T16 and T17 are connected to Vref and VXSP. Thus, the voltage of VXSP at the non-inverting input (+) can be compared with Vref at the inverting input (−) by asserting Clock. At block 4, the sense amplifier output is turned on by timing. Referring to FIG. 12, Clock is applied to T21.

[0096] Figures 14A and 14B depict further details of the timing signals during an embodiment of global reference read. Figure 14A depicts the read current 1410 provided to the selected WL between t1 and t4. Figure 14B depicts the voltage on the selected WL. From t1 to ts, the voltage across the memory cell increases. Between t1 and ts, the threshold switch selector disconnects. Between t1 and ts, the current causes the word line voltage to increase. The current also supports any leakage in the path. Once the voltage across the threshold switch selector reaches the threshold voltage Vth of the threshold switch selector 502, the threshold switch selector will turn on and switch to the low resistance state (at ts). Once the threshold switch selector 502 is in the on state (at ts), current can flow through the selected memory cell 401. The WL voltage will drop to a level that depends on the series resistance of the memory element 702, the on-state resistance of the threshold switch selector 502, and the address selection transistors and metal resistances in the read path. At t2, the snap-back discharge capacitor C1 is connected to VXSP, which can accelerate the rate at which the word line drops to its stable voltage. If the memory cell is in the HRS state, the voltage drops to line 1430. If the memory cell is in the LRS state, the voltage drops to line 1440. The sense amplifier 806 can then sense VXSP and compare it with Vref to determine whether the memory cell is in the HRS or LRS. Note that after connecting the snap-back discharge capacitor C1 to VXSP at t2, the word line voltage drops and stabilizes very quickly to reduce the read latency. In addition, the snap-back discharge capacitor C1 can prevent the state of the memory cell from flipping before sensing the memory cell by diverting the current that would otherwise flow through the memory element 702 to the capacitor.

[0097] In some embodiments, a capacitor in the sense amplifier 806 is used during SRR read to discharge the selected word line when (or shortly after) the threshold switch selector turns on. In one embodiment, C1 is used as a snap-back discharge capacitor that discharges VXSP when the threshold switch selector 502 turns on in SRR or shortly after that. In one embodiment, the procedure 900 of FIG. 9 is used during SRR read, where C1 is used as a snap-back discharge capacitor that discharges VXSP when the threshold switch selector 502 turns on or shortly after that. In another embodiment, the snap-back discharge capacitor remains connected throughout the first read in SRR. In some embodiments, a capacitor in the sense amplifier is used during SRR read to discharge the selected word line after the write phase of SRR to prepare for the second read after a bit has been destructively written to the AP. In one embodiment, C3 is used as a write reset discharge capacitor by asserting S5 during SRR.

[0098] FIG. 15 is a table 1500 indicating signal timing in sense amplifier 806 for an embodiment of SRR, where C1 is used as a step - down discharge capacitor. C2 is used as a read reference capacitor. Additionally, C3 is used as a write reset discharge capacitor. Table 1500 lists the signals applied at the gates of various transistors in sense amplifier 806 in FIG. 12. The Read signal refers to the signal that initiates the read current (see Read* at the gate of T1 in FIG. 11). At box 0, one or more capacitors in sense amplifier 806 are pre - charged. The pre - charge voltages of C1, C2, and C3 can be different. In one embodiment, C1 is pre - charged to a voltage that is tuned to provide a rapid discharge of VXSP after the threshold switching selector 502 turns on. In another embodiment, C1 is pre - charged to GND. In another embodiment, C1 is pre - charged to Vmid (VPC), for example if Vth is closer to Read Vfinal. The sizes of capacitors C1 and C3 can be selected based on other capacitances in the circuit. For example, the sizes of capacitors C1 and C3 can be selected based on the capacitance along the read path. The example range of C1 is between 10 femto - farads (fF) and 100 fF. In one embodiment, C2 is pre - charged to a voltage suitable for sensing. C2 is pre - charged to GND in one embodiment and to Vmid (VPC) in another embodiment. The example range of C2 is between 1 fF and 10 fF. In one embodiment, C3 is pre - charged to a voltage that is tuned to provide a rapid discharge of VXSP after a destructive write in SRR. In one embodiment, C3 is pre - charged from GND to Vmid (VPC). As an example, C3 can be between approximately 10% and 50% of C_CMOS + C_array. The example range of C3 is between 10 fF and 100 fF. Referring to FIG. 12, the signal "Precharge" applied to the gate of T23 can be used to pre - charge C1 and C3 to VPC. The signal "Precharge" applied to the gate of T25 can be used to pre - charge C2 to VPC or GND. During pre - charge, S1 and S2 are open / low. At box 0, Trap, S1, S3, S4, and S5 are set to high during pre - charge. During pre - charge, Vbump is set to 0V.

[0099] At block 1 in FIG. 15, the Read signal is used to enable a read current (e.g., turn on T1 in FIG. 11). As previously discussed, the read current will charge the selected WL and turn on the threshold switching selector 502. At block 2, before block 4, trap is high. At block 2, before block 4, the signal S1 to transistor T11 connects the sense amplifier 806 to VXSP until after Sample is deasserted before block 4. At block 2, before block 3, S3 is used to enable the snap-back discharge capacitor C1. Referring to FIG. 12, S3 is applied to the gate of T26 to connect C1 to VXSP. Thus, the snap-back discharge capacitor C1 can discharge VXSP (and thus can discharge the voltage on the WL). In one embodiment, S3 can stay high during block 3 to achieve a longer settling time before locking the VXSP voltage on C2 for later use.

[0100] At the start of block 3, the read reference capacitor C2 is enabled by asserting Sample and S4 until the end of block 3. At the start of block 3, the snap-back discharge capacitor C1 is disconnected from VXSP. During block 3, sample is pulled high to connect C2 to VXSP. Referring to FIG. 12, S4 is applied to T28 to enable the read reference capacitor C2. Additionally, "sample" at the gate of T24 is high to connect C2 to VXSP. Thus, the read reference capacitor C2 can be used to sense and store the voltage on VXSP obtained by reading during the first Read1 of the memory cell 401. The read reference capacitor C2 will store the Read1 result and allow its level to be adjusted using Vbump. Additionally, after Sample L at block 4, the VXSP connection is disabled by pulling S1 low. In one embodiment, the read reference capacitor C2 is enabled together with the snap-back discharge capacitor C1 during block 2, where C1 is disabled at the end of block 2 and C1 is disabled at the end of block 3.

[0101] At block 4, the read current, Sample, and Trap are disabled before enabling the write current, preferably as a transition of increasing the read current to become the write current, and the current does not drop below the read current. The read current can be disabled by disconnecting T1 (see FIG. 11). Between block 4 and block 6, Trap is low, which can avoid precharge interference during writing. In one embodiment, there is a separate write current source similar to the read current source 1102. However, the write current can have a magnitude larger than the read current. At block 4, the write current source can be connected to VXSP to provide Iwrite, similar to how the read current source 1102 can be connected to VXSP to supply Iread, or increasing the read current to become Iwrite, or turning on a parallel current source into VXSP to add to the Iread current source. At block 5, Vbump driven into C2 is used to bump the sampled read voltage. The bump in voltage can be about half of the expected voltage difference between LRS and HRS (e.g., about 150 mV). FIG. 12 shows how T19 can be used to provide the voltage bump Vbump.

[0102] At block 7, the write current is disabled and the read current is enabled. The read current can be enabled by turning on T1 again (see FIG. 11). At block 7, the VXSP connection is enabled again. Referring to FIG. 12, S1 is applied to T11 to connect the sense amplifier 806 to VXSP (note that Trap is high at t7 and t8). At block 7, after reducing the write current to the read current, the write reset discharge capacitor C3 is enabled. Referring to FIG. 12, S5 at the gate of T27 is pulled high to connect C3 to VXSP. Thus, C3 can accelerate the discharge rate to VXSP to accelerate the rate of WL voltage drop after the current decreases from Iwrite to Iread.

[0103] Trap is high at block 7 and block 8, and then low at block 9, and then Clock is asserted at block 9. Referring to FIG. 12, "Trap" is applied to T12 and T13 to turn on the sense amplifier again to the signal. Thus, T16 and T17 are connected to VXSP to sample the cell voltage. Additionally, T16 and T17 are connected through T13 to the bumped voltage from Read1. In one embodiment, Vref is removed since it is not used for SRR. Thus, the voltage at the inverting input (+) can be compared with the bumped voltage provided by T19. At block 9, the sense amplifier outputs on a time control. Referring to FIG. 12, Clock is applied to T21.

[0104] In some embodiments, a capacitor in a sense amplifier is used during SRR read to charge the selected word line at the start of a destructive write. In one embodiment, C4 is used as a write reset charge capacitor. FIG. 16 is a table 1600 indicating signal timing in sense amplifier 806 for an embodiment of SRR, where C4 is used as a write reset charge capacitor. Additionally, C1 is used as a snap-back discharge capacitor and C3 is used as a write reset discharge capacitor, similar to the example in table 1500. Thus, many of the signals in table 1600 are similar to those in table 1500 and will not be discussed further. At box 4, the read current is disabled and the write current is enabled, similar to the discussion of table 1500. Between box 4 and box 6, Trap is low, which can avoid precharge interference during write. Table 1600 shows that the capacitor can be precharged at t0. Referring to FIG. 12, the signal “Precharge” applied to the gate of T22 can be used to precharge C4 to Vpcw. The precharging of C1, C2, and C3 has been described in conjunction with table 1500. The size of capacitor C4 can be selected based on other capacitances in the circuit. For example, the size of capacitor C4 can be selected based on the capacitance along the read path. As an example, C4 can be between approximately 10% and 50% of C_CMOS + C_array. An example range for C4 is between 100 femtofarads (fF) and 200 fF. Table 1600 shows that at box 4, the write reset charge capacitor C4 is enabled. Referring to FIG. 12, the signal S6 at the gate of T15 goes high to connect the write reset charge capacitor C4 to VXSP. Note that at box 7 to box 10, S1 is applied to T11 again to connect the sense amplifier to VXSP. Also note that Trap is high in box 7 and box 8.

[0105] Figures 17A and 17B depict further details of the timing signals during an embodiment of the SRR. Figure 17A depicts a read current 1702 provided to the selected WL between t1 and t4, a write current 1704 provided to the selected WL between t4 and t7, and a read current 1706 provided to the selected WL between t7 and t10. Figure 17B depicts the voltage on the selected WL. From t1 to ts, the voltage across the memory cell increases. Between t1 and ts, the threshold switching selector disconnects. Between t1 and ts, the current increases the word line voltage. The current also supports any leakage in the path. Once the voltage across the threshold switching selector reaches the threshold voltage Vth of the threshold switching selector 502, the threshold switching selector will turn on and switch to the low resistance state (at ts). Once the threshold switching selector 502 is in the on state (at ts), the discharge current induced by the OTS turn-on and the read current (minus the leakage to the unselected cells) can flow through the selected memory cell 401. The WL voltage will drop to a level that depends on the series resistance of the memory element 702, the on-state resistance of the threshold switching selector 502, and the Voffset voltage, as well as the address selection transistors and metal resistances in the read path. At t2, the snap-back discharge capacitor C1 is connected to VXSP, which can accelerate the rate at which the word line drops to its stable value. If the memory cell is in the HRS state, the voltage drops to line 1710. If the memory cell is in the LRS state, the voltage drops to line 1712. Note that after connecting the snap-back discharge capacitor C1 to VXSP at t2, the word line voltage drops very quickly and stabilizes to reduce the read latency. In addition, the snap-back discharge capacitor C1 can prevent the state of the memory cell from flipping before sensing the memory cell by diverting some of the discharge current that would otherwise flow through the memory element 702.

[0106] At t4, the current increases from Iread to Iwrite. To help accelerate the rate at which the WL voltage increases in response to the increased current passing through the memory cell 401, the write reset charge capacitor C4 is connected to the WL at t4 (and S2 remains on during t4, using C4 to act on VXSP1, and). If the memory cell is already in the HRS, the WL voltage can be increased to level 1720. If the memory cell is initially in the LRS, the WL voltage can be increased to level 1722. The write current resets the memory cell to the HRS, such that after writing the LRS to the HRS during this write, the memory cell will end the write phase at level 1720. And if initially in the HRS state, it remains in the HRS.

[0107] At t7, the current decreases from Iwrite to Iread. To help accelerate the rate at which the WL voltage decreases in response to the decreasing current passing through memory cell 401, the write reset discharge capacitor C3 is connected to the WL at t7. The WL voltage rapidly decreases to level 1730.

[0108] FIG. 18 is a flowchart of an embodiment of a procedure 1800 for controlling a capacitor during SRR to accelerate the charging of a word line during a destructive write phase. Step 1802 includes precharging the write reset charge capacitor C4. In one embodiment, the write reset charge capacitor C4 is precharged to a charge assist voltage. As used throughout this document, the term "charge assist voltage" means the voltage on a capacitor that will enable the capacitor to transfer charge to a node (e.g., VXSP) to increase the voltage at that node. In one embodiment, the write reset charge capacitor C4 is precharged to Vp (see Vp in FIG. 11). As an example, Vp may be about 4V. Step 1804 includes increasing the current from Iread to Iwrite. Step 1806 includes connecting the write reset charge capacitor C4 to the selected WL to accelerate the rate of charging the selected WL. Step 1808 includes disconnecting the write reset charge capacitor C4 from the selected WL, thus accelerating the decay of the WL to the read voltage level after the write is complete.

[0109] FIG. 19 is a flowchart of an embodiment of a procedure 1900 for controlling a capacitor during SRR to accelerate the discharge of a word line after a destructive write phase. Step 1902 includes precharging the write reset discharge capacitor C3. In one embodiment, the write reset discharge capacitor C3 is precharged to Vmid (or VPC). In another embodiment, the write reset discharge capacitor C3 is precharged to a voltage at or near GND. The capacitor and the precharge voltage are adjusted to ensure that the coupling voltage is not lower than Read Vfinal, because this may disconnect the OTS and require the WL to be recharged to Vth before sensing the Read2 voltage and comparing it to the adjusted Read1 voltage. Step 1904 includes decreasing the current from Iwrite to Iread. Step 1906 includes connecting the write reset discharge capacitor C3 to the selected WL to accelerate the rate of discharging the selected WL. Step 1908 includes disconnecting the write reset discharge capacitor C3 from the selected WL. Step 1910 includes sensing the memory cell while driving a read current through the memory cell.

[0110] The last stage of the SRR may include writing to a memory cell to restore its original state in the event that a destructive write changes its original state. This last stage may be referred to as write setup or writeback. The writeback stage may include increasing the current to a write current. In one embodiment, a capacitor in the sense amplifier 806 may be used to accelerate the rate at which the word line is charged towards GND during the writeback stage. In one embodiment, a capacitor in the sense amplifier 806 may be used to accelerate the rate at which the word line is discharged at the end of the writeback stage. FIG. 20 is a table 2000 indicating the signal timing in the sense amplifier 806 for an embodiment of the writeback stage for the SRR. Table 2000 refers to writing to set up charge the capacitor (C5), which may be in one embodiment of the sense amplifier 806. The size of the capacitor C5 may be selected based on other capacitances in the circuit. For example, the size of the capacitor C5 may be selected based on the capacitance along the read path. As an example, C5 may be between approximately 10% and 50% of C_CMOS + C_array. An example range for C5 is between 5 femtofarads (fF) and 50 fF. At t0, C5 is precharged. In one embodiment, C5 is precharged to GND (since the write of the mram is in the opposite direction of the WL and BL directions for the destructive write reset). At block 11, Trap is high. Between block 12 and block 14, Trap is low, which may avoid precharge interference during the write. At t12, the write setup current is enabled. The write setup current may have a polarity opposite to the write current in the destructive write. At t12, as previously discussed, the VXSP connection is enabled by applying S1 to T11. At t12, the write setup charge capacitor C5 is enabled. In one embodiment, the write setup charge capacitor C5, along with the transistor that may be used to select the write setup charge capacitor C5, is added to the sense amplifier 806 of FIG. 12. A signal S7 may be applied at the gate of this transistor to connect the write setup charge capacitor to VXSN (using the n-channel path for the write setup). Thus, the write setup discharge capacitor C5 may be used to accelerate the rate at which the WL is charged at the start of the writeback stage. Another option is to add a write setup discharge capacitor to accelerate the rate at which the word line is discharged at the end of the writeback stage.

[0111] FIG. 21 is a flowchart of an embodiment of a procedure 2100 for controlling a capacitor to speed up the charging of a word line during the write-back phase of an SRR. Step 2102 includes precharging a write-set charge capacitor C5. In one embodiment, the write-set charge capacitor C5 is precharged to Gnd. Step 2104 includes increasing the current to Iwrite. Step 2106 includes connecting a write-set discharge capacitor C5 to a selected WL to speed up the rate of charging the selected WL. Step 2108 includes disconnecting the write-set discharge capacitor C5 from the selected WL. Step 2110 includes reducing the current after write-back, such as to 0A. In other embodiments, these steps 2108 and 2110 are reversed or approximately simultaneous. Another option is to connect the write-set discharge capacitor to speed up the rate of discharging the word line at the end of the write-back phase. In another embodiment, the transistor is turned on, and (precharging) connects the WL and BL (along with all other WLs and BLs if the cycle has ended) to Vmid.

[0112] The cross-point memory array can have multiple levels (or stacks). For the upper and lower stacks, the WL voltage and the BL voltage can be different. Accordingly, the various circuits (e.g., sense amplifier 806) depicted herein can be modified accordingly.

[0113] In view of the foregoing, it can be seen that, according to one embodiment, an apparatus includes a sense amplifier having a plurality of capacitors. The apparatus includes a control circuit in communication with the array and the plurality of capacitors. The control circuit is configured to connect to an array that includes a plurality of first conductive lines, a plurality of second conductive lines, and memory cells. Each memory cell resides at an intersection of a first conductive line and a second conductive line. Each memory cell includes a threshold switching selector in series with a memory element. The control circuit is configured to provide a signal during a read operation to turn on the threshold switching selector of a selected memory cell. The selected memory cell resides between a selected first conductive line and a selected second conductive line. The control circuit is configured to, after the threshold switching selector has been turned on, connect a first capacitor of the plurality of capacitors to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor as a voltage on the selected first conductive line changes. The control circuit is configured to control the sense amplifier to sense the selected memory cell during the read operation while the first capacitor is disconnected from the selected first conductive line.

[0114] In a further embodiment, the control circuit is configured to connect the first capacitor to the selected first conductive line after the threshold switching selector has been turned on, to accelerate the discharge of the selected first conductive line to a stable voltage. The control circuit is configured to control the sense amplifier to sense the selected memory cell while the selected first conductive line is at the stable voltage.

[0115] In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a pre-charge voltage after the threshold switching selector has been turned on, and a magnitude of the pre-charge voltage is tuned to accelerate the discharge of the selected first conductive line to the stable voltage.

[0116] In a further embodiment, the control circuit is configured to disconnect the first capacitor from the selected first conductive line. The control circuit is configured to connect a second capacitor among the plurality of capacitors to the selected first conductive line. The first capacitor has a capacitance different from that of the second capacitor. The control circuit is configured to sense the selected memory cell using the second capacitor while the selected first conductive line is at a stable voltage and the first capacitor is disconnected from the selected first conductive line.

[0117] In a further embodiment, the control circuit is configured to connect the second capacitor to the first conductive line while the first capacitor is connected to the selected first conductive line. The control circuit is configured to disconnect the first capacitor from the first conductive line while keeping the second capacitor connected to the selected first conductive line.

[0118] In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line. The control circuit is configured to drive a write current to the selected first conductive line to write the selected memory cell after a first read of a self-reference read of the selected memory cell during the read operation after the threshold switching selector is turned on. The control circuit is configured to connect the first capacitor to the selected first conductive line in response to the write current to accelerate the charging of the selected first conductive line.

[0119] In a further embodiment, the control circuit is configured to drive a current having a write magnitude to the selected first conductive line to charge the selected first conductive line after a first read of a self-reference read of the selected memory cell during the read operation, to write the selected memory cell. The control circuit is configured to reduce the current driven to the selected first conductive line to a read magnitude after writing the selected memory cell. The control circuit is configured to connect the first capacitor after reducing the current to the read magnitude to accelerate the discharge of the selected first conductive line.

[0120] In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a voltage after the current is reduced to the read magnitude, the voltage being tuned to accelerate the discharge of the selected first conductive line.

[0121] In a further embodiment, the control circuit is configured to pre-charge the first capacitor to a charge assist voltage before connecting the first capacitor to the selected first conductive line. The control circuit is configured to drive a write current to the selected first conductive line to write the selected memory cell during a write-back phase of a self-reference read of the read operation. The control circuit is configured to connect the first capacitor to the selected first conductive line during the write-back phase to accelerate the charging of the selected first conductive line.

[0122] In a further embodiment, the device includes the array. The threshold switching selector includes a bidirectional threshold switch (OTS). The memory element includes a magnetoresistive random access memory (MRAM) element.

[0123] One embodiment includes a method for reading a selected memory cell in a cross-point array. The method includes applying a select voltage to a selected bit line in the cross-point array. The method includes driving a current to a selected word line in the cross-point array to charge a voltage on the selected word line. The selected memory cell resides between the selected bit line and the selected word line. The selected memory cell includes a threshold switching selector in series with a memory element. The method includes, while driving the current through a path including the selected word line, the selected memory cell, and the selected bit line, after the threshold switching selector has turned on, connecting a first capacitor in a sense amplifier to the selected word line to accelerate the discharge of the selected word line toward a stable voltage. The method includes disconnecting the first capacitor from the selected word line. The method includes, with the first capacitor disconnected from the selected word line, while continuing to drive the current through the path, sensing the selected memory cell using the sense amplifier while the selected word line is at the stable voltage.

[0124] One embodiment includes a memory system that includes a cross-point array including word lines, bit lines, and programmable resistance memory cells. Each memory cell resides at an intersection of a word line and a bit line. Each memory cell includes a threshold switching selector in series with a programmable resistance memory element. The threshold switching selector has a high resistance when in an off state and a low resistance when in an on state. The memory system includes one or more sense amplifiers coupled to the cross-point array. Each sense amplifier includes one or more capacitors. The memory system includes a control circuit that communicates with the array and the sense amplifiers. The control circuit is configured to apply a select voltage to a selected bit line in the cross-point array. A selected memory cell resides between the selected bit line and a selected word line on a read path that includes a sense node, the selected word line, the selected memory cell, and the selected bit line. The control circuit is configured to drive a current to the selected word line to charge a voltage on the sense node to turn on the threshold switching selector of the selected memory cell. The control circuit is configured to, after the threshold switching selector has been turned on, connect a first capacitor in a first sense amplifier of the one or more sense amplifiers to the sense node to accelerate discharge of the sense node toward a stable voltage. The control circuit is configured to disconnect the first capacitor from the sense node. The control circuit is configured to, with the first capacitor disconnected from the sense node, control the first sense amplifier to sense a voltage on the sense node while the sense node is at the stable voltage and while driving a read current through the read path. Such a control circuit can be configured to connect the first capacitor to the sense node and then, after the voltage of the first capacitor is almost equal to the sense node, disconnect the capacitor. The voltage of the disconnected capacitor can be adjusted upward by a voltage and used as a reference to compare with another read voltage on the sense node by the sense amplifier after a destructive write.

[0125] For the purposes of this document, references in this specification to "an embodiment", "one embodiment", "some embodiments", or "another embodiment" can be used to describe different embodiments or the same embodiment.

[0126] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is said to be connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is said to be directly connected to another element, there is no intervening element between the element and the other element. Two devices are "in communication" if they are directly or indirectly connected such that they can convey an electronic signal between them.

[0127] For the purposes of this document, the term "based on" may be construed as "based at least in part on".

[0128] For the purposes of this document, without additional context, the use of numerical terms such as "first" object, "second" object, and "third" object may not imply an order of the objects, and may instead be used for identification purposes to identify different objects.

[0129] The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" and their forms used herein are for illustrative and descriptive purposes only, and are not intended to limit the description of the technology since the items referred to may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "about" represent that the specified dimension or parameter may vary within an acceptable tolerance for a given application.

[0130] The above embodiments have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical applications, thereby enabling one of ordinary skill in the art to best utilize them in various embodiments and to contemplate various modifications suitable for a particular use. The scope is intended to be defined by the appended claims.

[0131] 100: Memory system 102: Memory controller 104: Memory; Memory package 120: Host system; Host 122: Host processor 124: Host memory 126: Interface 128: Bus 140: Local memory; Local cache memory 152: Host interface 154: Network-on-chip (NOC) 156: Processor 158: ECC engine 160: Memory interface 164: Local memory controller 172: Refresh logic 174: Wear leveling 202: Memory structure 206: Input / output 208: Output 210: Row decoding and control circuitry; Row control circuitry 212: Row decoder 214: Row decoder and driver; Row driver circuitry 216: Block selection circuitry; Block selection section 220: Column control circuitry; Column decoding and control circuitry 222: Column decoder 224: Column driver 226: Block selection circuitry; Block selection section 228: Sense amplifier; Memory interface 260: System control logic circuitry; System control logic 262: State machine 264: Power control module / power control section 266: Register 268: Memory controller interface 269: ECC engine 270: Integrated memory assembly 272: Refresh logic 274: Wear leveling logic 280: Memory structure die 290: Control die 292: Memory die 293: Circuit path 294: Circuit path 401: Memory cell 402: Memory array 403: Memory array 418: First layer 420: Second layer 501: Bottom electrode 502: Threshold switching selector 503: Reference layer 505: MgO 507: Free layer 509: Spacer 511: Top electrode 512: Spacer 514: Spacer 600: Word line 1 601: Free layer 602: MRAM element 603: Tunneling barrier 605: Reference layer 609: Threshold switching selector 610: Bit line 611: Free layer 612: MRAM element 613: Tunneling barrier 615: Reference layer 619: Threshold switching selector 620: Word line 2 650: Word line 1 651: Free layer 652: MRAM element 653: Bit line 655: Reference layer 659: Threshold switching selector 660: Bit line / bit line layer 661: Reference layer 662: MRAM element 663: Tunneling barrier 665: Free layer 669: Threshold switching selector 670: Word line 2 700: Memory array 706a~706h: First conductive wire 708a~708d: Second conductive wire 802: Current source 804: Control circuit 806: Sense amplifier 810: Capacitor 900: Program 902~910: Steps 1010~1016: Graph lines 1102: Read current source 1300: Table 1410: Read current 1430, 1440: Lines 1500: Table 1600: Table 1702: Read current 1704: Write current 1706: Read current 1710, 1712: Lines 1720, 1722, 1730: Levels 1800: Program 1802, 1804, 1806, 1808: Steps 1900: Program 1902, 1904, 1906, 1908, 1910: Steps 2000: Table 2100: Program 2102, 2104, 2106, 2108, 2110: Steps BL, BL 1~BL N: Bit lines C1~C4: Capacitors C_CMOS, C_array: Capacitance I access: Access current Icell: Current Ihold: Holding current I read: Read current Isource: Current I write: Write current Read1: First read Read2: Second read T1, T3: Transistors; Channels T11: Transistor T16, T17, T21: Timing transistors T19, T20: Transistors T1N, T3N: N-channel transistors; Address transistors T1P, T3P: P-channel transistor; address transistor t1~t10: Time Vfinal: Stable voltage Vhold: Holding voltage Vref: Reference voltage Vselect: Voltage V select_BL: Selection voltage Vsense: Sensing voltage V unsel_BL: Unselected voltage V unsel_WL: Unselected voltage VXSP: Node VYS: Output WL, WL 1~WL M: Word line WL 1,1~WL 1,4: Word line WL 2,1~WL 2,4: Word line YEN: Driver

Claims

1. A memory device comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of a first conductive line and a second conductive line, wherein each memory cell includes a threshold switching selector connected in series with a memory element, the control circuit communicating with the array and the plurality of capacitors, the control circuit being configured to: provide a signal during a read operation to activate the threshold switching selector of a selected memory cell, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; and, after the threshold switching selector is activated, connect one of the plurality of capacitors, a first capacitor, to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor in response to a voltage change on the selected first conductive line; While the first capacitor is disconnected from the selected first conductive line, the sensing amplifier is controlled to sense the selected memory cell during the read operation; after the threshold switching selector is turned on, the first capacitor is connected to the selected first conductive line to accelerate the discharge of the selected first conductive line to a stable voltage; while the selected first conductive line is at the stable voltage, the sensing amplifier is controlled to sense the selected memory cell; and after the threshold switching selector is turned on, the first capacitor is pre-charged to a pre-charge voltage, the value of which is tuned to accelerate the discharge of the selected first conductive line to the stable voltage.

2. A memory device comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of a first conductive line and a second conductive line, wherein each memory cell includes a threshold switching selector connected in series with a memory element, the control circuit communicating with the array and the plurality of capacitors, the control circuit being configured to: provide a signal during a read operation to activate the threshold switching selector of a selected memory cell, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; and, after the threshold switching selector is activated, connect one of the plurality of capacitors, a first capacitor, to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor in response to a voltage change on the selected first conductive line; While disconnecting the first capacitor from the selected first conductive line, the sensing amplifier is controlled to sense the selected memory cell during the read operation; before connecting the first capacitor to the selected first conductive line, the first capacitor is pre-charged to a charging auxiliary voltage; after the threshold switching selector is turned on and after a first read of a self-reference read of the selected memory cell during the read operation, a write current is driven to the selected first conductive line to write to the selected memory cell; and in response to the write current, the first capacitor is connected to the selected first conductive line to accelerate the charging of the selected first conductive line.

3. A memory device comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of a first conductive line and a second conductive line, wherein each memory cell includes a threshold switching selector connected in series with a memory element, the control circuit communicating with the array and the plurality of capacitors, the control circuit being configured to: provide a signal during a read operation to activate the threshold switching selector of a selected memory cell, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; and, after the threshold switching selector is activated, connect one of the plurality of capacitors, a first capacitor, to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor in response to a voltage change on the selected first conductive line; While the first capacitor is disconnected from the selected first conductive line, the sensing amplifier is controlled to sense the selected memory cell during the read operation; after a first read of the selected memory cell by a self-reference read during the read operation, a current having a write value is driven to the selected first conductive line to charge the selected first conductive line for writing to the selected memory cell; after writing to the selected memory cell, the current driven to the selected first conductive line is reduced to a read value; and after the current is reduced to the read value, the first capacitor is connected to accelerate the discharge of the selected first conductive line.

4. The memory device of claim 3, wherein the control circuit is configured to: after the current decreases to the read value, precharge the first capacitor to a voltage that is tuned to accelerate the discharge of the selected first conductor.

5. A memory device comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of a first conductive line and a second conductive line, wherein each memory cell includes a threshold switching selector connected in series with a memory element, the control circuit communicating with the array and the plurality of capacitors, the control circuit being configured to: provide a signal during a read operation to activate the threshold switching selector of a selected memory cell, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; and, after the threshold switching selector is activated, connect one of the plurality of capacitors, a first capacitor, to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor in response to a voltage change on the selected first conductive line; While disconnecting the first capacitor from the selected first conductor, the sensing amplifier is controlled to sense the selected memory cell during the read operation; before connecting the first capacitor to the selected first conductor, the first capacitor is pre-charged to a charging auxiliary voltage; during a write-back phase of a self-reference read in the read operation, a write current is driven to the selected first conductor to write to the selected memory cell; and during the write-back phase, the first capacitor is connected to the selected first conductor to accelerate the charging of the selected first conductor.

6. A memory device comprising: a sense amplifier having a plurality of capacitors; and a control circuit configured to be connected to an array including a plurality of first conductive lines, a plurality of second conductive lines, and memory cells, wherein each memory cell resides at an intersection of a first conductive line and a second conductive line, wherein each memory cell includes a threshold switching selector connected in series with a memory element, the control circuit communicating with the array and the plurality of capacitors, the control circuit being configured to: provide a signal during a read operation to activate the threshold switching selector of a selected memory cell, wherein the selected memory cell resides between a selected first conductive line and a selected second conductive line; After the threshold switching selector is turned on, one of the plurality of capacitors, a first capacitor, is connected to the selected first conductive line to transfer charge between the selected first conductive line and the first capacitor as a voltage change occurs on the selected first conductive line; and simultaneously, when the first capacitor is disconnected from the selected first conductive line, the sensing amplifier is controlled to sense the selected memory cell during the read operation, wherein: The device includes the array; the threshold switching selector includes a bidirectional threshold switch (OTS); and the memory element includes a magnetoresistive random access memory (MRAM) element.

7. A method for reading a selected memory cell in a crosspoint array, the method comprising: applying a selection voltage to a selected bit line in the crosspoint array; driving a current to a selected word line in the crosspoint array to charge a voltage on the selected word line, wherein the selected memory cell resides between the selected bit line and the selected word line, wherein the selected memory cell includes a threshold switching selector connected in series with a memory element; while driving the current through a path including the selected word line, the selected memory cell, and the selected bit line, after the threshold switching selector has been turned on, connecting a first capacitor in a sense amplifier to the selected word line to accelerate the discharge of the selected word line toward a stable voltage; disconnecting the first capacitor from the selected word line; and while the first capacitor is disconnected from the selected word line, sensing the selected memory cell using the sense amplifier while continuing to drive the current through the path, and while the selected word line is at the stable voltage.

8. The method of claim 7, further comprising: after the threshold switching selector has been turned on, precharging the first capacitor to a precharge voltage, a value of which is tuned to accelerate the discharge via the select word line to the stable voltage.

9. The method of claim 7, further comprising: after sensing the selected memory cell, performing a destructive write to the selected memory cell, including driving a write current through the path; after performing the destructive write, reducing the current through the path from the write current to a read current; and in response to the reduction of the current through the path, while the current through the path is at the read current, connecting a second capacitor to the selected word line to accelerate the discharge of the voltage on the selected word line.

10. The method of claim 9, further comprising: disconnecting the second capacitor from the selected word line; and sensing the selected memory cell using a third capacitor while continuing to drive the read current through the path and while the second capacitor is disconnected from the selected word line.

11. A memory system comprising: a crosspoint array including word lines, bit lines, and programmable resistive memory cells, wherein each memory cell resides at a crosspoint of a word line and a bit line, wherein each memory cell includes a threshold selector connected in series with a programmable resistive memory element, wherein the threshold selector has a high resistance when in an off state and a low resistance when in an on state; one or more sense amplifiers coupled to the crosspoint array, wherein each sense amplifier includes one or more capacitors; and a control circuit communicating with the array and the one or more sense amplifiers, the control circuit being configured to: A selection voltage is applied to a selected bit line in the crosspoint array, wherein a selected memory cell resides between the selected bit line and a selected word line on a read path, the read path including a sensing node, the selected word line, the selected memory cell, and the selected bit line; a current is driven to the selected word line to charge a voltage on the sensing node to turn on the threshold switching selector of the selected memory cell; after the threshold switching selector is turned on, a first capacitor of one or more first sensing amplifiers is connected to the sensing node to accelerate the discharge of the sensing node toward a stable voltage; the first capacitor is disconnected from the sensing node; and when the first capacitor is disconnected from the sensing node, while the sensing node is at the stable voltage and while a read current is driven through the read path, the first sensing amplifier is controlled to sense a voltage on the sensing node.

12. The memory system of claim 11, wherein the control circuit is further configured to: after the threshold switching selector has been turned on, precharge the first capacitor to a precharge voltage, a value of which is tuned to accelerate the discharge of the sensing node.

13. The memory system of claim 11, wherein the control circuitry is further configured to: sense the selected memory cell using a second capacitor in the first sensing amplifier while the sensing node is at the stable voltage; after sensing the selected memory cell using the second capacitor, perform a destructive write to the selected memory cell, including driving a write current through the read path; after performing the destructive write, reduce the current to the read path to a read current; and in response to the reduction of the current, connect a third capacitor of the first sensing amplifier to the sensing node while the current is at the read current to accelerate the discharge of the voltage on the sensing node.

14. The memory system of claim 13, wherein the control circuit is further configured to: in response to the decrease in current, precharge the third capacitor to a precharge voltage, a value of which is tuned to accelerate the discharge of the sensing node.

15. The memory system of claim 13, wherein the control circuitry is further configured to: precharge a fourth capacitor of the first sense amplifier to a charging auxiliary voltage; after sensing the selected memory cell using the second capacitor, increase the current to the read path from a read current to a write current; and while the current is at the write current, connect the fourth capacitor to the sense node to accelerate the charging of the voltage on the sense node.

16. The memory system of claim 11, wherein the control circuitry is further configured to: disconnect the first capacitor from the sensing node after the voltage on the first capacitor is nearly equal to the voltage at the sensing node; adjust the voltage on the first capacitor by a bump voltage; and, after a destructive write to the selected memory cell, use the bump voltage on the first capacitor as a reference voltage for comparison with another read voltage of the selected memory cell at the sensing node.

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