Semiconductor device, integrated circuit including the same and method for forming the same

Abstract

The various embodiments disclosed herein pertain to a thin-film transistor (TFT) with a hydrogen absorption layer and a method for forming the same. The TFT includes a stacked semiconductor channel, a gate, and a gate dielectric layer, with the gate dielectric layer separating the gate from the semiconductor channel. A first source / drain and a second source / drain are located in different portions of the semiconductor channel. Furthermore, the hydrogen absorption layer is adjacent to the gate, the first source / drain, the second source / drain, or a combination thereof. The hydrogen absorption layer traps hydrogen and other undetermined particles, preventing them from interacting with the semiconductor material of the TFT, thereby preventing performance and reliability degradation.

Description

Prior Art

[0001] A thin-film transistor (TFT) is a type of field-effect transistor (FET) in which the semiconductor channel is formed by depositing a thin film onto a non-conductive substrate. One type of TFT is the oxide semiconductor TFT. Oxide semiconductor TFTs are compatible with back-end-of-line (BEOL) processing, making them promising candidates for next-generation memory and similar applications. Simple diagram description

[0002] The various aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of a thin film transistor (TFT) including a hydrogen absorbing layer. FIG. 2 illustrates a top-down layout diagram of some embodiments of the TFT of FIG. 1 . FIG. 3 shows a cross-sectional view of some embodiments of an integrated circuit (IC) including a plurality of TFTs as shown in FIG. 1 . FIG. 4 shows cross-sectional views of some alternative embodiments of the TFT of FIG. 1 , in which the conductive barrier is omitted. 5A to 5C illustrate cross-sectional views of some alternative embodiments of the TFT of FIG. 4 . FIG. 6 shows cross-sectional views of some alternative embodiments of the TFT of FIG. 1 , wherein a plurality of hydrogen absorbing layers and a plurality of conductive layers are alternately stacked to form the gate of the TFT. FIG. 7 illustrates cross-sectional views of some alternative embodiments of the TFT of FIG. 1 , wherein the gate of the TFT is located above the semiconductor channel of the TFT. 8A and 8B illustrate cross-sectional views of some alternative embodiments of the TFT of FIG. 7 . 9 illustrates cross-sectional views of some alternative embodiments of the TFT of FIG. 1 , wherein the TFT includes additional hydrogen absorbing layers located at the source / drain of the TFT, respectively. 10A to 10C illustrate cross-sectional views of some alternative embodiments of the TFT of FIG. 9 . 11 to 22 illustrate a series of cross-sectional views of some embodiments of a method for forming a TFT having a hydrogen absorbing layer. FIG. 23 shows a block diagram of some embodiments of the methods of FIG. 11 to FIG. 22 . 24 to 27 show a series of cross-sectional views of some first alternative embodiments of the method of FIGS. 11 to 22 . 28 to 30 show a series of cross-sectional views of some second alternative embodiments of the method of FIGS. 11 to 22 . 31 to 33 show a series of cross-sectional views of some third alternative embodiments of the method of Figs. 11 to 22. 34 to 36 show a series of cross-sectional views of some fourth alternative embodiments of the method of Figs. 11 to 22. 37 to 42 show a series of cross-sectional views of some fifth alternative embodiments of the method of Figs. 11 to 22. 43 and 44 show a series of cross-sectional views of some sixth alternative embodiments of the method of FIGS. 11-22 . 45 to 48 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC including a TFT having a hydrogen absorbing layer. Implementation Method

[0003] This disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby preventing the first and second features from directly contacting each other. Furthermore, this disclosure may reuse reference numbers and / or letters across various examples. This repetition is for the sake of brevity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0005] Oxide semiconductor thin-film transistors (TFTs) can be formed in back-end-of-line (BEOL) interconnect structures, and therefore, the oxide semiconductor TFTs may be exposed to hydrogen. For example, hydrogen from BEOL layers formed before the oxide semiconductor TFTs are formed may migrate into the oxide semiconductor TFTs. Such BEOL layers may include high-k dielectric layers and interlayer dielectric (ILD) layers. As another example, hydrogen from BEOL processes performed after the oxide semiconductor TFTs are formed may migrate into the oxide semiconductor TFTs.

[0006] The oxide semiconductor material of an oxide semiconductor TFT may be sensitive to hydrogen, and therefore exposure to hydrogen may degrade the performance and reliability of the oxide semiconductor TFT. For example, the on-current (I ON) of the oxide semiconductor TFT may decrease and / or the threshold voltage variation (TVV) may increase when the oxide semiconductor TFT is subjected to stress (e.g., thermal stress). Because the formation of the oxide semiconductor TFT in the BEOL interconnect structure may result in exposure to hydrogen, the performance and reliability of the oxide semiconductor TFT may degrade. Furthermore, this degradation may become increasingly severe as the size of the oxide semiconductor TFT decreases.

[0007] Various embodiments of the present disclosure are directed to oxide semiconductor TFTs having a hydrogen absorption layer and methods for forming the same. The hydrogen absorption layer captures hydrogen and other adventitious particles, preventing them from interacting with the oxide semiconductor material of the oxide semiconductor TFT, thereby preventing degradation of the performance and reliability of the oxide semiconductor TFT.

[0008] In some embodiments, an oxide semiconductor TFT includes a stacked semiconductor channel, a gate, and a gate dielectric layer, wherein the gate dielectric layer separates the gate from the semiconductor channel. A first source / drain and a second source / drain are located in different portions of the semiconductor channel. Furthermore, a hydrogen absorption layer is adjacent to the gate, the first source / drain, the second source / drain, or a combination thereof.

[0009] 1 , a cross-sectional view 100 of some embodiments of a TFT 102 including a hydrogen absorbing layer 104 is provided. TFT 102 may be, for example, an oxide semiconductor TFT or some other suitable type of TFT. Furthermore, as will be seen below, TFT 102 may be formed, for example, in a BEOL interconnect structure.

[0010] The hydrogen absorption layer 104 is embedded in the gate 106, which is located below the semiconductor channel 108. The gate dielectric layer 110 separates the gate 106 from the semiconductor channel 108. In addition, a first source / drain 112a and a second source / drain 112b are located above the semiconductor channel 108 and are electrically coupled to opposite ends of the semiconductor channel 108. The term "source / drain" may refer to the source or drain individually, or collectively, the source and the drain, depending on the context.

[0011] Semiconductor channel 108 is sensitive to hydrogen, and hydrogen absorbing layer 104 tends to absorb hydrogen. This sensitivity to hydrogen exposure of semiconductor channel 108 may cause degradation in the performance and / or reliability of TFT 102. For example, exposure may reduce the on-state current (e.g., I ON) of TFT 102. As another example, when TFT 102 is subjected to thermal stress and / or some other suitable type of stress, exposure may increase the variation in threshold voltage.

[0012] In some embodiments, when TFT 102 is formed in a BEOL interconnect structure, hydrogen may migrate toward semiconductor channel 108. For example, hydrogen from BEOL layers formed before forming TFT 102 may migrate toward semiconductor channel 108. As another example, hydrogen from BEOL processing performed after forming TFT 102 may migrate toward semiconductor channel 108.

[0013] Because the hydrogen absorbing layer 104 is embedded in the gate 106, the hydrogen absorbing layer 104 is close to the semiconductor channel 108. This proximity and the propensity to absorb hydrogen enable the hydrogen absorbing layer 104 to absorb hydrogen and prevent hydrogen from migrating to the semiconductor channel 108 and interacting with the semiconductor channel 108, thereby enhancing the performance of the TFT 102 (e.g., increasing the on-state current) and enhancing the reliability of the TFT 102 (e.g., reducing variations in the threshold voltage).

[0014] In some embodiments, hydrogen absorbing layer 104 is a material that combines with hydrogen at room temperature and / or at the operating temperature of TFT 102. Furthermore, in some embodiments, hydrogen absorbing layer 104 is or includes a noble metal, indium gallium zinc oxide (e.g., InGaZnO), an n-type metal oxide, or other suitable material that has a tendency to absorb hydrogen. The noble metal may, for example, have a nanocrystalline structure that facilitates hydrogen absorption and capture. The noble metal may, for example, be or include platinum (e.g., Pt), silver (e.g., Ag), palladium (e.g., Pd), gold (e.g., Au), or any combination thereof.

[0015] In some embodiments, the n-type metal oxide is or includes an indium-oxide-based semiconductor doped with an n-type dopant. The indium-oxide-based semiconductor may, for example, be or include InxMyO, where M is an element and x and y are numerical values. In some embodiments, the element is tungsten (e.g., W), titanium (e.g., Ti), gallium (e.g., Ga), zinc (e.g., Zn), calcium (e.g., Ca), magnesium (e.g., Mg), tin (e.g., Sn), a rare earth element, or the like. In some embodiments, the ratio of x to y (e.g., x / y) is greater than zero and less than 1. However, other suitable values are also applicable to the ratio.

[0016] In some embodiments, an n-type metal oxide (e.g., the aforementioned indium oxide-based semiconductor) is doped with an n-type dopant to a high carrier concentration greater than 1E19 atoms / cm³ (e.g., atoms / cm³) to avoid significantly increasing the resistance of gate 106. Furthermore, in some embodiments, the n-type metal oxide has a carrier concentration of approximately 1E19 atoms / cm³ to 1E21 atoms / cm³. However, other suitable carrier concentrations are also possible in alternative embodiments.

[0017] In some embodiments, the thickness Tha of the hydrogen absorbing layer 104 is approximately 5-20 nm, approximately 5-10 nm, approximately 10-15 nm, approximately 15-20 nm, or some other suitable value or range of values. In some embodiments in which the hydrogen absorbing layer 104 is or includes an n-type metal oxide, the thickness Tha of the hydrogen absorbing layer 104 is approximately 0.5-10 nm, approximately 0.5-5 nm, approximately 5-10 nm, or some other suitable value or range of values. If the thickness Tha is too large (e.g., greater than 10 nm), the resistance of the gate 106 may significantly degrade, thereby degrading the performance of the TFT 102. If the thickness Tha is too small (e.g., less than 0.5 nm), the hydrogen absorbing layer 104 may not effectively absorb hydrogen and prevent hydrogen from migrating to and interacting with the semiconductor channel 108.

[0018] In some embodiments, the hydrogen absorbing layer 104 includes hydrogen absorbed from BEOL layers and / or BEOL processing. Furthermore, in some embodiments, the hydrogen absorbing layer 104 has a hydrogen concentration greater than the hydrogen concentration in the semiconductor channel 108. The hydrogen concentration in the hydrogen absorbing layer 104 can be, for example, greater than approximately 1E15 atoms / cm 3 , 1E19 atoms / cm 3 , or some other suitable value. In some embodiments, the semiconductor channel 108 is free of or substantially free of hydrogen. For example, the semiconductor channel 108 can have a hydrogen concentration less than approximately 1E15 atoms / cm 3 , 1E10 atoms / cm 3 , or some other suitable value.

[0019] In some embodiments, semiconductor channel 108 is or includes indium zinc oxide (e.g., IZO), indium tin oxide (e.g., ITO), indium oxide (e.g., In 2 O 3), gallium oxide (e.g., Ga 2 O 3), indium gallium zinc oxide (e.g., InGaZnO), zinc oxide (e.g., ZnO), aluminum zinc oxide (e.g., Al 2 O 5 Zn 2), aluminum-doped zinc oxide (e.g., AZO), indium tungsten oxide (e.g., IWO), titanium oxide (e.g., TiO x ), or any combination thereof. In some embodiments, semiconductor channel 108 may also be considered a semiconductor body.

[0020] Continuing with FIG. 1 , gate 106 is located above dielectric substrate 114, which can also be considered a dielectric layer. Gate 106 includes a conductive body 116 and a conductive liner 118. The conductive liner 118 extends along the bottom surface and sidewalls of the conductive body 116. Furthermore, the conductive liner 118 is separated from the conductive body 116 by the hydrogen absorbing layer 104. In some embodiments, the conductive liner 118 acts as a diffusion barrier for the material of the conductive body 116, thereby preventing outward diffusion. Therefore, in such embodiments, the conductive liner 118 can also be referred to as a barrier layer.

[0021] During use of the TFT 102, the semiconductor channel 108 selectively conducts the first source / drain 112a and the second source / drain 112b based on a bias voltage applied to the gate 106. For example, the semiconductor channel 108 may be conductive when the bias voltage is greater than a threshold voltage, and may be non-conductive when the bias voltage is less than the threshold voltage, and vice versa.

[0022] In some embodiments, the conductive body 116 is or includes a metal. For example, the conductive body 116 can be or include copper, aluminum copper, tungsten, some other suitable metal or metal-containing material, or any combination thereof. The conductive liner 118 is or includes titanium nitride, tantalum nitride, some other suitable barrier material for the conductive body 116, or any combination thereof.

[0023] In some embodiments where the hydrogen absorbing layer 104 is or includes an n-type metal oxide and the conductive body 116 is or includes a metal, the hydrogen absorbing layer 104 and the conductive body 116 form a heterojunction. Furthermore, an energy gap and shallow trap states are formed at the heterojunction. The energy gap corresponds to the energy difference between the Fermi level of the conductive body 116 and the band gap of the hydrogen absorbing layer 104. In some embodiments, the band gap is depressed relative to the Fermi level, resulting in a step-like decrease in energy from the Fermi level to the band gap. Shallow trap states exist within the band gap and serve as reservoirs for capturing and storing hydrogen.

[0024] In some embodiments, the energy gap is formed due to the energy difference between the Fermi level of the conductive body 116 and the conduction band edge of the n-type metal oxide. The Fermi level of the conductive body 116 can, for example, be demarcated by the work function of the conductive body 116, which can be, for example, approximately 4-5 electron volts (eV), approximately 4-4.5 eV, approximately 4.5-5 eV, or some other suitable value. The conduction band edge of the n-type metal oxide can, for example, be less than the Fermi level of the conductive body 116 and can be, for example, approximately 0.2-3 eV, approximately 0.2-1.6 eV, approximately 1.6-3 eV, or some other suitable value. In other embodiments, the energy gap is formed due to Fermi-level pinning resulting from the energy difference between the conduction band edge of the n-type metal oxide and the valence band edge of the n-type metal oxide. Furthermore, in some embodiments, the band gap of the n-type metal oxide can be approximately 1-3 eV or some other suitable value or range of energy values.

[0025] In some embodiments where the hydrogen absorbing layer 104 is or includes the aforementioned n-type metal oxide and the conductive liner 118 is or includes a metal, the hydrogen absorbing layer 104 forms a heterojunction with the conductive liner 118. Furthermore, an energy gap is formed in the hydrogen absorbing layer 104 at the heterojunction, and the formation of the energy gap enables hydrogen to be captured and used as a reservoir for the captured hydrogen.

[0026] Multiple dielectric layers 120 and a hydrogen barrier layer 122 are stacked on the dielectric substrate 114 and surround the TFT 102. The lower dielectric layer 120 surrounds the gate 106 and is located between the dielectric substrate 114 and the gate dielectric layer 110. The middle dielectric layer 120 surrounds the semiconductor channel 108 and is located between the gate dielectric layer 110 and the hydrogen barrier layer 122. In some embodiments, the gate dielectric layer 110 is a high-k dielectric material and / or some other suitable dielectric material, or the gate dielectric layer 110 includes a high-k dielectric material and / or some other suitable dielectric material, and / or the dielectric layer 120 is a low-k dielectric material and / or some other suitable dielectric material, or the dielectric layer 120 includes a low-k dielectric material and / or some other suitable dielectric material.

[0027] The hydrogen barrier layer 122 and the dielectric layer 120 above it are located above the semiconductor channel 108 and the intermediate dielectric layer 120. Furthermore, the hydrogen barrier layer 122 and the dielectric layer 120 above it surround the first source / drain 112a and the second source / drain 112b. The hydrogen barrier layer 122 is used to prevent hydrogen from migrating into the semiconductor channel 108, thereby further preventing degradation of the performance and / or reliability of the TFT 102.

[0028] In some embodiments, the hydrogen barrier layer 122 does not combine with and / or absorb hydrogen to trap it. This is in contrast to the hydrogen absorbing layer 104. Thus, even though the hydrogen barrier layer 122 initially blocks hydrogen, hydrogen may still migrate around the hydrogen barrier layer 122. For example, hydrogen may migrate around the hydrogen barrier layer 122 along the sidewall interface between the first source / drain 112a and the hydrogen barrier layer 122.

[0029] Although hydrogen absorbing layer 104 is described as absorbing hydrogen, hydrogen absorbing layer 104 may additionally or alternatively absorb other errant particles that are harmful to TFT 102. Therefore, in some embodiments, hydrogen absorbing layer 104 may also be referred to as an absorbing layer, an errant particle absorbing layer, etc. Similarly, although hydrogen barrier layer 122 is described as blocking hydrogen, hydrogen barrier layer 122 may additionally or alternatively block other errant particles that are harmful to TFT 102. Therefore, in some embodiments, hydrogen barrier layer 122 may also be referred to as a blocking layer, an errant particle blocking layer, etc.

[0030] Referring to FIG. 2 , a top-down layout diagram 200 of some embodiments of the TFT 102 of FIG. The cross-sectional view 100 of FIG. 1 can be taken, for example, along line AA′ in FIG. 2 , and / or the top-down layout diagram 200 can be taken, for example, along line AA′ in FIG. Furthermore, the semiconductor channel 108, the first source / drain 112 a, and the second source / drain 112 b are shown with dashed lines.

[0031] The conductive liner 118 extends along the sidewalls of the hydrogen absorbing layer 104 in a closed path to surround the hydrogen absorbing layer 104. The hydrogen absorbing layer 104 separates the conductive liner 118 from the conductive body 116. Furthermore, the hydrogen absorbing layer 104 extends along the sidewalls of the conductive body 116 in a closed path to surround the conductive body 116. The semiconductor channel 108 overlaps with the conductive body 116 and is confined to the area of the conductive body 116. Similarly, the first source / drain 112a and the second source / drain 112b overlap with the semiconductor channel 108. Furthermore, the first source / drain 112a and the second source / drain 112b are respectively confined to areas located at opposite ends of the semiconductor channel 108.

[0032] Referring to FIG. 3 , a cross-sectional view 300 of some embodiments of an integrated circuit (IC) including a plurality of TFTs 102, each of which is shown in FIG. The plurality of TFTs 102 are located above a semiconductor substrate 302 and include a first TFT 102a, a second TFT 102b, and a third TFT 102c, each located at different heights above the semiconductor substrate 302. In alternative embodiments, any one or two of the plurality of TFTs 102 may be omitted and / or any one or more of the plurality of TFTs 102 may be located at different heights. In some embodiments, the semiconductor substrate 302 is or includes silicon, germanium, some other suitable material, or any combination thereof.

[0033] Device layer 304 is located above semiconductor substrate 302 and between semiconductor substrate 302 and the plurality of TFTs 102. Device layer 304 also includes a plurality of logic elements 306. In some embodiments, device layer 304 includes additional device types and / or may be referred to as a front-end-of-line (FEOL) layer.

[0034] A plurality of logic elements 306 are formed in part from the semiconductor substrate 302 and separated from each other by isolation structures 308. The isolation structure 308 may be, for example, or include, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) isolation structure, some other suitable isolation structure, or any combination thereof. Furthermore, the plurality of logic elements 306 may be, for example, planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), gate-all-around (GAA) field-effect transistors (GAA FETs), some other suitable type of logic element and / or transistor, or any combination thereof.

[0035] Multiple logic elements 306 include individual gates 310, individual gate dielectric layers 312, and individual pairs of source / drain regions 314. The source / drain regions may be referred to individually as source regions or drain regions, or collectively as source and drain regions, depending on the context. The pairs of source / drain regions 314 are inserted into the top of the semiconductor substrate 302. The gates 310 are each located above the gate dielectric layers 312 and between the pairs of source / drain regions 314.

[0036] BEOL interconnect structure 316 is located above and electrically coupled to the components of component layer 304 (e.g., plurality of logic components 306). Furthermore, BEOL interconnect structure 316 surrounds and electrically couples to plurality of TFTs 102. BEOL interconnect structure 316 includes a plurality of metal lines 318 and a plurality of vias 320. The plurality of metal lines 318 are grouped into a plurality of metal line levels, and the plurality of vias 320 are grouped into a plurality of via levels. Furthermore, the plurality of metal line levels and the plurality of via levels are vertically stacked alternately from the bottom to the top of BEOL interconnect structure 316.

[0037] The plurality of metal line levels are labeled M1, M2, and so on, through M6, from the bottom of the BEOL interconnect structure 316 to the top of the BEOL interconnect structure 316. Similarly, the plurality of via levels are labeled V0, V1, and so on, through V5, from the bottom of the BEOL interconnect structure 316 to the top of the BEOL interconnect structure 316. In some embodiments, the heights of the plurality of metal line levels increase from the bottom of the BEOL interconnect structure 316 to the top of the BEOL interconnect structure 316. In some embodiments, the heights and / or widths of the plurality of via levels increase from the bottom of the BEOL interconnect structure 316 to the top of the BEOL interconnect structure 316.

[0038] The first TFT 102a is located between metal line level M1 and metal line level M2, but in other embodiments, it can be located between any two adjacent metal line levels. The second TFT 102b is located between metal line level M3 and metal line level M4, but in other embodiments, it can be located between any two adjacent metal line levels. The third TFT 102c is located between metal line level M5 and metal line level M6, but in other embodiments, it can be located between any two adjacent metal line levels.

[0039] The dielectric stack surrounds the BEOL interconnect structure 316 and includes a plurality of interconnect dielectric layers 322 and a plurality of etch stop layers 324. The plurality of interconnect dielectric layers 322 may correspond to, for example, the dielectric layers 120 of FIG. 1 , and / or the plurality of etch stop layers 324 may correspond to, for example, the dielectric substrate 114 of FIG. The plurality of interconnect dielectric layers 322 and the plurality of etch stop layers 324 are alternately stacked from the bottom of the BEOL interconnect structure 316 to the top of the BEOL interconnect structure 316.

[0040] The dielectric stack further includes a plurality of gate dielectric layers 110 and a plurality of hydrogen barrier layers 122. The plurality of gate dielectric layers 110 correspond to the plurality of TFTs 102 and are as described with respect to their corresponding portions of FIG1 . Similarly, the plurality of hydrogen barrier layers 122 correspond to the plurality of TFTs 102 and are as described with respect to their corresponding portions of FIG1 .

[0041] 4, a cross-sectional view 400 of some alternative embodiments of the TFT 102 of FIG1 is provided, wherein the conductive liner 118 is omitted. As such, the hydrogen absorbing layer 104 directly contacts the dielectric substrate 114 and also directly contacts the underlying dielectric layer 120.

[0042] 5A-5C , cross-sectional views 500A- 500C of some alternative embodiments of the TFT 102 of FIG. 4 are provided, wherein the hydrogen absorbing layer 104 has a different layout and / or positioning relative to the conductive body 116 .

[0043] 5A , the hydrogen absorbing layer 104 is located on the top surface of the conductive body 116 and separates the conductive body 116 from the gate dielectric layer 110. Furthermore, the hydrogen absorbing layer 104 and the conductive body 116 have the same width and form common sidewalls on opposite sides of the conductive body 116.

[0044] 5B , the hydrogen absorbing layer 104 is located above the top surface of the conductive body 116. Furthermore, the hydrogen absorbing layer 104 extends laterally beyond the conductive body 116, and the width of the hydrogen absorbing layer 104 is greater than the width of the conductive body 116. In some embodiments, the hydrogen absorbing layer 104 shares a common width with the gate dielectric layer 110 and / or the hydrogen barrier layer 122.

[0045] 5C , the hydrogen absorbing layer 104 covers the conductive body 116 and extends along the sidewalls of the conductive body 116. In addition, the hydrogen absorbing layer 104 separates the conductive body 116 from the gate dielectric layer 110.

[0046] 6 , a cross-sectional view 600 of some alternative embodiments of the TFT 102 of FIG. 1 is provided, wherein a plurality of conductive layers 602 form the gate 106 and are alternately stacked with a plurality of hydrogen absorbing layers 104. Thus, the conductive body 116 and the conductive liner 118 are omitted.

[0047] The plurality of conductive layers 602 has N=3 layers, while the plurality of hydrogen absorbing layers 104 has N-1 layers. Although N is 3, in alternative embodiments, N can be 4, 5, 6, or some other suitable integer value. Furthermore, the plurality of conductive layers 602 and the plurality of hydrogen absorbing layers 104 have a common width and form common sidewalls on opposite sides of the gate 106. The plurality of conductive layers 602 can be, for example, or include, metal and / or some other suitable conductive material. For example, each of the plurality of hydrogen absorbing layers 104 can be as described with respect to its corresponding portion of FIG. 1 .

[0048] 7 , a cross-sectional view 700 of some alternative embodiments of the TFT 102 of FIG. 1 is provided, wherein the gate 106 is located above the semiconductor channel 108. Thus, the TFT 102 of FIG. 1 can be considered a bottom-gate TFT, while the TFT 102 of FIG. 7 can be considered a top-gate TFT.

[0049] A hydrogen barrier layer 122 is located below the semiconductor channel 108 and, unlike in FIG1 , is separated from the semiconductor channel 108. In alternative embodiments, the hydrogen barrier layer 122 contacts the semiconductor channel 108. Additionally, the first source / drain 112 a and the second source / drain 112 b extend through the dielectric substrate 114. For example, the first source / drain 112 a may extend through the dielectric substrate 114 to a metal line of a BEOL interconnect structure (not shown) below the TFT 102.

[0050] Although the top view layout 200 of FIG2 is described with respect to the cross-sectional view 100 of FIG1 , it should be understood that the top view layout 200 is applicable to the cross-sectional view 700 of FIG7 . For example, the cross-sectional view 700 of FIG7 can be taken along the line AA′ in FIG2 , and / or the top view layout 200 can be taken along the line AA′ in FIG7 .

[0051] 8A and 8B , cross-sectional views 800A and 800B of alternative embodiments of the TFT 102 of FIG. 7 are provided. In the cross-sectional view 800A of FIG. 8A , the conductive liner 118 is omitted, resulting in the gate 106 as shown in FIG. 4 . In the cross-sectional view 800B of FIG. 8B , the gate 106 is as shown in FIG. 6 . Thus, the gate 106 is formed by alternating stacks of multiple conductive layers 602 and multiple hydrogen absorbing layers 104. In yet another additional alternative embodiment of the TFT 102 of FIG. 7 , the gate 106 is as shown in any one of FIG. 5A to FIG. 5C , or a combination thereof.

[0052] 9 , a cross-sectional view 900 of some alternative embodiments of the TFT 102 of FIG. 1 is provided, wherein the TFT 102 includes a pair of additional hydrogen absorbing layers 902 at the first source / drain 112 a and the second source / drain 112 b, respectively. The pair of additional hydrogen absorbing layers 902 are each similar to the hydrogen absorbing layer 104 described with respect to FIG. Furthermore, the pair of additional hydrogen absorbing layers 902 extend along the bottom surface and sidewalls of the first source / drain 112 a and the second source / drain 112 b, respectively.

[0053] The pair of additional hydrogen absorbing layers 902 absorb and capture hydrogen that migrates toward the semiconductor channel 108. Therefore, the pair of additional hydrogen absorbing layers 902 can prevent hydrogen from reaching and interacting with the semiconductor channel 108. As described with respect to FIG. 1 , this can reduce hydrogen-induced performance degradation and / or reliability degradation of the TFT 102.

[0054] Referring to Figures 10A to 10C , cross-sectional views 1000A-1000C of some alternative embodiments of the TFT 102 of Figure 9 are provided. In the cross-sectional view 1000A of Figure 10A , the gate 106 is as shown in Figure 4 . In the cross-sectional view 1000B of Figure 10B , the gate 106 is as shown in Figure 6 . In the cross-sectional view 1000C of Figure 10C , the gate 106 is located above the semiconductor channel 108, as shown in Figure 7 . In another additional alternative embodiment of the TFT 102 of Figure 9 , the gate 106 is as shown in any one of Figures 5A to 5C , or a combination thereof, and / or any one of Figures 8A and 8B , or a combination thereof.

[0055] Although the plurality of TFTs 102 in FIG3 are each individually configured according to the TFT embodiment of FIG1 , any one, two, or more of the plurality of TFTs 102 may alternatively be configured according to the TFT embodiments of FIG4 , 5A-5C , 6 , 7 , 8A, 8B, 9 , and 10A-10C , or any combination thereof. For example, the first TFT 102a in FIG3 may be configured according to the TFT embodiment of FIG1 , the second TFT 102b in FIG3 may be configured according to the TFT embodiment of FIG6 , and the third TFT 102c in FIG3 may be configured according to the TFT embodiment of FIG9 .

[0056] 11 to 22, a series of cross-sectional views 1100-2200 of some embodiments of a method for forming a TFT having a hydrogen absorbing layer are provided. For example, this method can be used to form the TFT 102 of FIG. 1.

[0057] 11, a first dielectric layer 120a is deposited on the dielectric substrate 114. The first dielectric layer 120a may be or include, for example, a low-k dielectric layer and / or other suitable dielectric materials.

[0058] 12, the first dielectric layer 120a is patterned to form a gate opening 1202 exposing the dielectric substrate 114. The patterning can be performed, for example, by photolithography / etching processes.

[0059] As shown in cross-sectional view 1300 of FIG13 , a first conductive layer 1181, a hydrogen absorbing layer 104, and a second conductive layer 1161 are stacked and deposited over the first dielectric layer 120a and lining the gate opening 1202. In alternative embodiments, the first conductive layer 1181 is omitted to form a TFT as shown in FIG4 . Furthermore, in some embodiments, the first conductive layer 1181 is configured to prevent outdiffusion of material from the second conductive layer 1161. The hydrogen absorbing layer 104 covers the first conductive layer 1181. Furthermore, the hydrogen absorbing layer 104 is electrically conductive and configured to absorb hydrogen and, in some embodiments, other adventitious particles. The second conductive layer 1161 covers the hydrogen absorbing layer 104.

[0060] In some embodiments, the hydrogen absorbing layer 104 is or includes a noble metal, indium gallium zinc oxide (e.g., InGaZnO), an n-type metal oxide, or the like that has a tendency to absorb hydrogen. The noble metal may, for example, have a nanocrystalline structure that facilitates hydrogen absorption and capture. The noble metal may, for example, be or include platinum (e.g., Pt), silver (e.g., Ag), palladium (e.g., Pd), gold (e.g., Au), or any combination thereof.

[0061] In some embodiments, the n-type metal oxide is or includes an indium oxide-based semiconductor doped with an n-type dopant. The indium oxide-based semiconductor may, for example, be or include InxMyO, where M is an element and x and y are numerical values. In some embodiments, the element is tungsten (e.g., W), titanium (e.g., Ti), gallium (e.g., Ga), zinc (e.g., Zn), calcium (e.g., Ca), magnesium (e.g., Mg), tin (e.g., Sn), a rare earth element, or the like. In some embodiments, the ratio of x to y (e.g., x / y) is greater than zero and less than 1. However, other suitable values are also applicable to the ratio.

[0062] In some embodiments, an n-type metal oxide (e.g., the aforementioned indium oxide-based semiconductor) is doped with an n-type dopant to a high concentration of greater than 1E19 atoms per cubic centimeter (e.g., atoms / cm 3 ) to avoid significantly increasing the resistance of the gate being formed. Furthermore, in some embodiments, the n-type metal oxide has a carrier concentration of approximately 1E19 atoms / cm 3 to 1E21 atoms / cm 3 . However, other suitable carrier concentrations are possible in alternative embodiments.

[0063] In some embodiments, the thickness T ha of the hydrogen absorbing layer 104 is approximately 5-20 nm, approximately 5-10 nm, approximately 10-15 nm, approximately 15-20 nm, or some other suitable value or range of values. In some embodiments, the thickness T cl of the first conductive layer 1181 is 1-5 nm, or some other suitable value or range of values.

[0064] As shown in cross-sectional view 1400 of FIG14 , first conductive layer 1181, hydrogen absorber layer 104, and second conductive layer 1161 are planarized to remove these layers from the top of first dielectric layer 120a. Planarization further forms gate 106 within gate opening 1202 (see, for example, FIG12 ). Planarization can be performed, for example, by chemical mechanical polishing (CMP).

[0065] The gate 106 includes a portion of the second conductive layer 116l, hereinafter referred to as the conductive body 116. Furthermore, the gate 106 includes a portion of the first conductive layer 118l, hereinafter referred to as the conductive liner 118. The conductive liner 118 surrounds the bottom of the conductive body 116 and is separated from the conductive body 116 by a portion of the hydrogen absorbing layer 104. In some embodiments, the top view layout of the gate 106 is shown in FIG2.

[0066] As shown in cross-sectional view 1500 of FIG15 , a gate dielectric layer 110 and a semiconductor layer 1081 are stacked and deposited above the gate 106 and the first dielectric layer 120a. The gate dielectric layer 110 is deposited first and is therefore positioned below the semiconductor layer 1081. The gate dielectric layer 110 may be, for example, or include, a high-k dielectric material and / or other suitable dielectric materials.

[0067] Semiconductor layer 1081 is sensitive to hydrogen. This sensitivity may result in degradation of the performance and / or reliability of the resulting TFT in response to exposure of semiconductor layer 1081 to hydrogen. For example, exposure may reduce the on-current (e.g., ION) of the TFT. As another example, exposure may increase the variation in threshold voltage when the TFT is subjected to thermal stress and / or some other suitable type of stress. Semiconductor layer 1081 may be, for example, or include, indium zinc oxide (e.g., IZO), indium tin oxide (e.g., ITO), indium oxide (e.g., In2O3), gallium oxide (e.g., Ga2O3), indium gallium zinc oxide (e.g., InGaZnO), zinc oxide (e.g., ZnO), aluminum zinc oxide (e.g., Al2O5Zn2), aluminum-doped zinc oxide (e.g., AZO), indium tungsten oxide (e.g., IWO), titanium oxide (e.g., TiOx), or any combination thereof.

[0068] As shown in cross-sectional view 1600 of FIG16 , semiconductor layer 108l is patterned to form a semiconductor channel 108 located above gate 106. Semiconductor channel 108 corresponds to a portion of semiconductor layer 108l. Furthermore, the width of semiconductor channel 108 is smaller than the width of conductive body 116. In some embodiments, semiconductor channel 108 can be considered a semiconductor island, a semiconductor body, or the like. In some embodiments, semiconductor channel 108 and gate 106 have a top-down layout as shown in FIG2 . Furthermore, in some embodiments, when viewed from above, semiconductor channel 108 is confined within the region of gate 106. Patterning can be performed, for example, through photolithography / etching processes.

[0069] As described above, semiconductor layer 1081 is sensitive to hydrogen. Therefore, semiconductor channel 108 is also sensitive to hydrogen. Since hydrogen absorbing layer 104 is embedded in gate 106, it is close to semiconductor channel 108. This proximity and its propensity to absorb hydrogen enable hydrogen absorbing layer 104 to absorb hydrogen and prevent it from migrating to and interacting with semiconductor channel 108. This, in turn, enhances the performance and reliability of the resulting TFT.

[0070] 17, a second dielectric layer 120b is deposited over the gate dielectric layer 110 and the semiconductor channel 108. The second dielectric layer 120b may be or include, for example, the same dielectric material as the first dielectric layer 120a and / or some other suitable dielectric material.

[0071] 18 , the second dielectric layer 120 b is planarized to remove the second dielectric layer 120 b from the top of the semiconductor channel 108 and expose the semiconductor channel 108. The planarization may be performed, for example, by CMP.

[0072] As shown in cross-sectional view 1900 of FIG. 19 , a hydrogen barrier layer 122 and a third dielectric layer 120c are deposited over the second dielectric layer 120b and the semiconductor channel 108. The hydrogen barrier layer 122 is a dielectric and is located below the third dielectric layer 120c. Furthermore, the hydrogen barrier layer 122 is configured to prevent hydrogen above the hydrogen barrier layer 122 from reaching the semiconductor channel 108. The third dielectric layer 120c may, for example, be or include the same dielectric material as the first dielectric layer 120a and / or the second dielectric layer 120b. Alternatively, the third dielectric layer 120c may be or include some other suitable dielectric material.

[0073] As shown in cross-sectional view 2000 of FIG. 20 , the third dielectric layer 120 c and the hydrogen barrier layer 122 are patterned to form a pair of source / drain openings 2002 extending into the semiconductor channel 108 and located on opposite sides of the semiconductor channel 108. In some embodiments, the semiconductor channel 108 has a top-down layout as shown in FIG. 2 , and the top-down layouts of the pair of source / drain openings 2002 are similar to the top-down layouts of the first source / drain 112 a and the second source / drain 112 b in FIG. 2 . Furthermore, in some embodiments, when viewed from above, the pair of source / drain openings 2002 are confined to the region of the semiconductor channel 108. Patterning can be performed, for example, through photolithography / etching processes.

[0074] 21 , a conductive layer 2102 is deposited over the third dielectric layer 120c and fills the pair of source / drain openings 2002. In some embodiments, the top of the conductive layer 2102 is recessed directly above each of the pair of source / drain openings 2002.

[0075] As shown in cross-sectional view 2200 of FIG. 22 , the conductive layer 2102 is planarized to remove the conductive layer 2102 from the top of the third dielectric layer 120c and expose the third dielectric layer 120c. This in turn forms a first source / drain 112a and a second source / drain 112b, respectively, within a pair of source / drain openings 2002 (see, for example, FIG. 20 ). The term "source / drain" may be referred to individually as a source or a drain, or collectively as a source and a drain, depending on the context. The first source / drain 112a, the second source / drain 112b, the semiconductor channel 108, the gate dielectric layer 110, the gate 106, and the hydrogen absorption layer 104 collectively form the TFT 102. Planarization can be performed, for example, by CMP.

[0076] While Figures 11-22 are described with reference to a method, it should be understood that the structures shown in these figures are not limited to the method and can be independent of the method. While Figures 11-22 are described as a series of actions, it should be understood that the order of the actions can be changed in other embodiments. While Figures 11-22 illustrate and describe a specific set of actions, some of the actions shown and / or described may be omitted in other embodiments. Furthermore, other embodiments may include actions that are not shown and / or described.

[0077] 23 , a block diagram 2300 of some embodiments of the methods of FIGS. 11-22 is provided.

[0078] In action 2302, a first dielectric layer is deposited over the substrate. For example, see FIG. 11 .

[0079] In action 2304, the first dielectric layer is patterned to form a gate opening. For example, see FIG. 12 .

[0080] In action 2306, a barrier layer, a hydrogen absorber layer, and a conductive layer are deposited as a stack over the first dielectric layer and lining the gate opening. For example, see FIG. 13 .

[0081] At act 2308, the barrier layer, hydrogen absorber layer, and conductive layer are planarized to remove these layers from above the top of the first dielectric layer and form a gate in the gate opening. For example, see FIG. 14.

[0082] In action 2310, a gate dielectric layer and a semiconductor layer are deposited as a stack over the top of the gate. For example, see FIG. 15 .

[0083] In action 2312, the semiconductor layer is patterned to form a semiconductor channel located above the gate dielectric layer and the gate. For example, see FIG. 16 .

[0084] In action 2314, a second dielectric layer is formed around the semiconductor channel. For example, see Figures 17 and 18. In some embodiments, forming the second dielectric layer includes depositing the second dielectric layer and then planarizing the second dielectric layer.

[0085] In action 2316, a hydrogen barrier layer and a third dielectric layer are deposited over the semiconductor channel and the second dielectric layer. For example, see FIG. 19 .

[0086] In action 2318, a pair of source / drain electrodes are formed that extend through the hydrogen barrier layer and the third dielectric layer to the semiconductor channel. For example, see Figures 20 to 22.

[0087] Although the block diagram 2300 of FIG. 23 is illustrated and described herein as a series of actions or events, it should be understood that the order in which these actions or events are illustrated should not be construed as limiting. For example, some actions may occur in a different order and / or concurrently with other actions or events than those illustrated and / or described herein. Furthermore, not all illustrated actions are required to implement one or more aspects or embodiments described herein, and one or more of the actions described herein may be performed in one or more separate actions and / or phases.

[0088] 24 to 27, a series of cross-sectional views 2400-2700 are provided of some first alternative embodiments of the method of FIG11 to FIG22. For example, the first alternative embodiment can be used to form the TFT 102 of FIG5A.

[0089] As shown in cross-sectional view 2400 of FIG. 24 , a conductive layer 1161 and a hydrogen absorbing layer 104 are deposited and stacked above dielectric substrate 114. Hydrogen absorbing layer 104 covers conductive layer 1161. Furthermore, hydrogen absorbing layer 104 is conductive and configured to absorb hydrogen. For example, hydrogen absorbing layer 104 may be as described with respect to FIG. 13 .

[0090] As shown in cross-sectional view 2500 of FIG. 25 , the conductive layer 1161 and the hydrogen absorbing layer 104 are patterned to form the gate 106. The gate 106 includes a portion of the conductive layer 1161 (hereinafter referred to as the conductive body 116) and also includes a portion of the hydrogen absorbing layer 104 that covers the conductive body 116. Patterning can be performed, for example, through a photolithography / etching process.

[0091] As shown in the cross-sectional view 2600 of FIG. 26 , the first dielectric layer 120 a is deposited on the gate 106 .

[0092] As shown in cross-sectional view 2700 of FIG. 27 , the first dielectric layer 120 a is planarized to remove the first dielectric layer 120 a above the top of the gate 106 and expose the hydrogen absorbing layer 104. Planarization can be performed, for example, by CMP. After planarization, the steps described with respect to FIG. 15 to FIG. 22 can be performed to form the TFT shown in FIG. 5A .

[0093] 28 to 30, a series of cross-sectional views 2800-3000 are provided of some second alternative embodiments of the method of Figures 11 to 22. For example, the second alternative embodiment can be used to form the TFT 102 of Figure 5B.

[0094] 28, a conductive layer 1161 is deposited over the dielectric substrate 114 and then patterned into a conductive body 116, thereby forming the gate 106. The patterning can be performed, for example, by a photolithography / etching process.

[0095] As shown in cross-sectional view 2900 of FIG29 , a first dielectric layer 120 a is deposited over gate 106 and then planarized. For example, first dielectric layer 120 a can be deposited as shown in FIG26 . Planarization removes the first dielectric layer 120 a above the top of gate 106 and exposes gate 106. Planarization can be performed, for example, by CMP.

[0096] As shown in cross-sectional view 3000 of FIG30 , a hydrogen absorbing layer 104 is deposited over the gate 106 and the first dielectric layer 120a. For example, the hydrogen absorbing layer 104 can be as described with respect to FIG13 . After the hydrogen absorbing layer 104 is deposited, the steps described with respect to FIG15 to FIG22 can be performed to form a TFT as shown in FIG5B .

[0097] 31 to 33, a series of cross-sectional views 3100-3300 are provided of some third alternative embodiments of the method of Figures 11 to 22. For example, the third alternative embodiment can be used to form the TFT 102 of Figure 5C.

[0098] 31 , a conductive layer 1161 is deposited over the dielectric substrate 114 and then patterned into a conductive body 116, thereby forming the gate 106. The patterning may be performed, for example, by a photolithography / etching process.

[0099] As also shown in cross-sectional view 3100 of FIG31 , a hydrogen absorbing layer 104 is deposited on the gate 106. The hydrogen absorbing layer 104 extends along the top surface of the gate 106 and the top surface of the dielectric substrate 114. Furthermore, the hydrogen absorbing layer 104 extends along the sidewalls of the gate 106. For example, the hydrogen absorbing layer 104 can be as described with respect to FIG13 .

[0100] 32 , the hydrogen absorbing layer 104 is patterned to remove the hydrogen absorbing layer 104 on the top surface of the dielectric substrate 114. The patterning may be performed, for example, by a photolithography / etching process.

[0101] As shown in cross-sectional view 3300 of FIG. 33 , a first dielectric layer 120 a is deposited over the hydrogen absorbing layer 104 and subsequently planarized. For example, the first dielectric layer 120 a can be deposited as shown in FIG. 26 . Planarization removes the first dielectric layer 120 a from above the top of the hydrogen absorbing layer 104 and can be performed, for example, by CMP or the like. After planarization, the actions described with respect to FIG. 15 to FIG. 22 can be performed to form a TFT as shown in FIG. 5C .

[0102] 34 to 36, a series of cross-sectional views 3400-3600 are provided of some fourth alternative embodiments of the method of Figures 11 to 22. For example, the fourth alternative embodiment can be used to form the TFT 102 of Figure 6.

[0103] As shown in cross-sectional view 3400 of FIG. 34 , multiple hydrogen absorbing layers 104 and multiple conductive layers 602 are deposited in an alternating stack. The multiple conductive layers 602 have N=3 layers, and the multiple hydrogen absorbing layers 104 have N-1 layers. However, in alternative embodiments, N can be 4, 5, 6, or some other suitable integer value. Furthermore, the multiple hydrogen absorbing layers 104 are conductive and configured to absorb hydrogen. For example, each of the multiple hydrogen absorbing layers 104 can be similar to its counterpart described with respect to FIG. 13 .

[0104] As shown in cross-sectional view 3500 of FIG35 , the plurality of hydrogen absorbing layers 104 and the plurality of conductive layers 602 are patterned to form a gate 106. The gate 106 includes portions of the plurality of conductive layers 602, which are alternately stacked with portions of the plurality of hydrogen absorbing layers 104. Patterning can be performed, for example, through a photolithography / etching process.

[0105] As shown in cross-sectional view 3600 of FIG. 36 , a first dielectric layer 120 a is deposited over gate 106 and subsequently planarized. For example, first dielectric layer 120 a can be deposited as shown in FIG. 26 . Planarization removes first dielectric layer 120 a from the top of gate 106 and can be performed, for example, by CMP. After planarization, the actions described with respect to FIG. 15 to FIG. 22 can be performed to form a TFT as shown in FIG. 6 .

[0106] 37 to 42, a series of cross-sectional views 3700-4200 are provided of some fifth alternative embodiments of the method of Figures 11 to 22. For example, the fifth alternative embodiment can be used to form the TFT 102 of Figure 7.

[0107] As shown in cross-sectional view 3700 of FIG37 , a first dielectric layer 120a, a hydrogen barrier layer 122, and a second dielectric layer 120b are deposited and stacked above dielectric substrate 114. Hydrogen barrier layer 122 is located above first dielectric layer 120a and is configured to block hydrogen. Furthermore, second dielectric layer 120b covers hydrogen barrier layer 122.

[0108] As shown in cross-sectional view 3800 of FIG38 , a first source / drain 112 a and a second source / drain 112 b are formed, extending through the first dielectric layer 120 a, the hydrogen barrier layer 122, the second dielectric layer 120 b, and the dielectric substrate 114. The first source / drain 112 a and the second source / drain 112 b may, for example, extend to corresponding metal lines of a BEOL interconnect structure (not shown) beneath the dielectric substrate 114.

[0109] In some embodiments, the formation of the first source / drain 112a and the second source / drain 112b is performed according to the processes described in Figures 20 to 22. For example, the first dielectric layer 120a, the hydrogen barrier layer 122, the second dielectric layer 120b, and the dielectric substrate 114 may be patterned to form a pair of source / drain openings 2002 (see, for example, Figure 20). A conductive layer 2102 may then be deposited to fill the pair of source / drain openings 2002 (see, for example, Figure 21). Furthermore, the conductive layer 2102 may be planarized to remove the conductive layer 2102 above the top of the second dielectric layer 120b and expose the second dielectric layer 120b (see, for example, Figure 22).

[0110] As shown in cross-sectional view 3900 of FIG39 , semiconductor channel 108 is formed on top of second dielectric layer 120 b, first source / drain 112 a, and second source / drain 112 b. In some embodiments, this formation is performed according to the actions described in FIG15 and FIG16 . For example, semiconductor layer 108 l can be deposited and then patterned into semiconductor channel 108.

[0111] As shown in cross-sectional view 4000 of FIG40 , a dielectric material is deposited to extend the second dielectric layer 120 b over the semiconductor channel 108, and then planarization is performed to remove the second dielectric layer 120 b over the top of the semiconductor channel 108. For example, this can be similar to the deposition and subsequent planarization of the first dielectric layer 120 a in FIG26 and FIG27 .

[0112] As shown in the cross-sectional view 4100 of FIG. 41 , the gate dielectric layer 110 is deposited on the semiconductor channel 108 and the second dielectric layer 120 b.

[0113] As shown in cross-sectional view 4200 of FIG42 , gate 106 and third dielectric layer 120c are formed over gate dielectric layer 110 according to the processes described in FIG11 to FIG14 , except that third dielectric layer 120c is used instead of first dielectric layer 120a. In alternative embodiments, gate 106 and third dielectric layer 120c are formed according to the processes described in FIG24 to FIG27 , the processes described in FIG28 to FIG30 , the processes described in FIG31 to FIG33 , or the processes described in FIG34 to FIG36 .

[0114] 43 and 44, a series of cross-sectional views 4300, 4400 of some sixth alternative embodiments of the method of Figures 11 to 22 are provided. For example, the sixth alternative embodiment can be used to form the TFT 102 of Figure 9.

[0115] As shown in cross-sectional view 4300 of FIG. 43 , the operations according to FIG. 11 to FIG. 20 are performed to form the structure of FIG. Furthermore, an additional hydrogen absorbing layer 902 and a conductive layer 2102 are deposited, stacked over the third dielectric layer 120 c and filling the pair of source / drain openings 2002. The additional hydrogen absorbing layer 902 is located below the conductive layer 2102 and can be, for example, the hydrogen absorbing layer 104 described with respect to FIG. 13 .

[0116] As shown in cross-sectional view 4400 of FIG. 44 , the additional hydrogen absorbing layer 902 and the conductive layer 2102 are planarized to remove these layers above the top of the third dielectric layer 120 c and expose the third dielectric layer 120 c. This, in turn, forms the first source / drain 112 a and the second source / drain 112 b lined by respective sections of the additional hydrogen absorbing layer 902. These sections themselves can be referred to as the additional hydrogen absorbing layer. The first source / drain 112 a, the second source / drain 112 b, the semiconductor channel 108, the gate dielectric layer 110, the gate 106, and the hydrogen absorbing layer 104 collectively form the TFT 102. Planarization can be performed, for example, by CMP.

[0117] While Figures 24 through 44 are described with reference to a method, it should be understood that the structures shown in these figures are not limited to the method and can be independent of the method. While Figures 24 through 44 are described as a series of actions, it should be understood that the order of the actions can be varied in other embodiments. While Figures 24 through 44 illustrate and describe a specific set of actions, some of the actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0118] 45 to 48, a series of cross-sectional views 4500-4800 of some embodiments of a method for forming an IC including a TFT having a hydrogen absorbing layer are provided. The TFT may be, for example, as shown in FIG.

[0119] As shown in cross-sectional view 4500 of FIG45 , device layer 304 is formed on semiconductor substrate 302. Device layer 304 includes a plurality of logic devices 306, which are partially formed from semiconductor substrate 302 and separated from each other by isolation structures 308. In some embodiments, device layer 304 includes additional device types and / or may also be referred to as a FEOL layer.

[0120] Multiple logic elements 306 include respective gates 310, respective gate dielectric layers 312, and respective pairs of source / drain regions 314. The source / drain regions may be referred to individually as source regions or drain regions, or collectively as source and drain regions, depending on the context. The pairs of source / drain regions 314 are inserted into the top of the semiconductor substrate 302. The gates 310 are each located above the gate dielectric layers 312 and between the pairs of source / drain regions 314.

[0121] As shown in cross-sectional view 4600 of FIG46 , BEOL interconnect structure 316 is partially formed above and electrically coupled to multiple logic elements 306. Furthermore, a dielectric structure is partially formed around BEOL interconnect structure 316. The dielectric structure includes a plurality of interconnect dielectric layers 322 and a plurality of etch stop layers 324, which are alternately stacked. The plurality of etch stop layers 324 include a TFT support etch stop layer 324a located on top of the dielectric structure. BEOL interconnect structure 316 includes a plurality of metal lines 318 and a plurality of vias 320.

[0122] The plurality of metal lines 318 are grouped into a plurality of metal line levels, and the plurality of vias 320 are grouped into a plurality of via levels stacked alternately with the plurality of metal line levels. The plurality of metal line levels are labeled M1, M2, and M3 in a direction away from the semiconductor substrate 302. Similarly, the plurality of via levels are labeled V0, V1, and V2 in a direction away from the semiconductor substrate 302.

[0123] As shown in cross-sectional view 4700 of FIG. 47 , TFT 102 is formed on TFT support etch stop layer 324 a according to the method of FIG. 11 to FIG. 22 . Dielectric substrate 114 in the method of FIG. 11 to FIG. 22 corresponds to TFT support etch stop layer 324 a, and first dielectric layer 120 a, second dielectric layer 120 b, and third dielectric layer 120 c correspond to interconnect dielectric layer 322. In alternative embodiments, TFT 102 is formed according to the method of FIG. 24 to FIG. 27 , the method of FIG. 28 to FIG. 30 , the method of FIG. 31 to FIG. 33 , the method of FIG. 34 to FIG. 36 , the method of FIG. 37 to FIG. 42 , or the method of FIG. 43 and FIG. 44 .

[0124] 48 , the BEOL interconnect structure 316 is completed over the TFT 102. Additionally, a dielectric structure extends around the BEOL interconnect structure 316.

[0125] To extend the dielectric structure, a plurality of additional interconnect dielectric layers 322 and a plurality of additional etch stop layers 324 are formed in alternating stacks. To complete the BEOL interconnect structure 316, a plurality of additional metal lines 318 and a plurality of additional vias 320 are formed. The plurality of additional metal lines 318 are grouped into a plurality of additional metal line levels, and the plurality of additional vias 320 are grouped into a plurality of additional via levels that are stacked alternately with the plurality of additional metal line levels. The plurality of additional metal line levels are labeled M4, M5, and M6 in a direction away from the semiconductor substrate 302. Similarly, the plurality of additional via levels are labeled V3, V4, and V5 in a direction away from the semiconductor substrate 302.

[0126] While Figures 45-48 are described with reference to a method, it should be understood that the structures shown in these figures are not limited to the method and can be independent of the method. While Figures 45-48 are described as a series of actions, it should be understood that the order of the actions can be changed in other embodiments. While Figures 45-48 illustrate and describe a specific set of actions, some of the actions shown and / or described may be omitted in other embodiments. Furthermore, other embodiments may include actions that are not shown and / or described.

[0127] In view of the foregoing, the present disclosure is directed to a TFT including a hydrogen absorbing layer.

[0128] In some embodiments, the present disclosure provides a semiconductor device comprising: a semiconductor channel; a first source / drain and a second source / drain located on a first side of the semiconductor channel and electrically coupled to different portions of the semiconductor channel; a gate located on a second side of the semiconductor channel, the second side opposite the first side of the semiconductor channel; a gate dielectric layer located between the gate and the semiconductor channel; and a hydrogen absorbing layer adjacent to the gate, the first source / drain, the second source / drain, or a combination thereof. In some embodiments, the hydrogen absorbing layer is embedded in the gate. In some embodiments, the hydrogen absorbing layer is in direct contact with the gate dielectric layer. In some embodiments, the hydrogen absorbing layer is located between the gate and the gate dielectric layer and has the same width as the gate. In some embodiments, the hydrogen absorbing layer is located between the gate and the gate dielectric layer and also extends along the sidewalls of the gate. In some embodiments, the semiconductor device further comprises: an additional hydrogen absorbing layer; and a plurality of conductive layers stacked alternately with the hydrogen absorbing layer and the additional hydrogen absorbing layer, wherein the plurality of conductive layers form the gate. In some embodiments, the hydrogen absorbing layer is located between the semiconductor channel and one of the first source / drain and the second source / drain, and further extends along a sidewall of one of the first source / drain and the second source / drain.

[0129] In some embodiments, the present disclosure provides an integrated circuit comprising a semiconductor device, wherein the semiconductor device includes: a stacked semiconductor channel, a gate, and a gate dielectric layer, wherein the gate dielectric layer separates the gate from the semiconductor channel; a first source / drain and a second source / drain, respectively, located in different portions of the semiconductor channel; and a hydrogen absorption layer adjacent to the gate and the gate dielectric layer. In some embodiments, the gate includes a conductive body and a barrier layer, wherein the barrier layer lines the sidewalls of the conductive body and a surface of the conductive body facing away from the gate dielectric layer, wherein the hydrogen absorption layer separates the conductive body from the barrier layer. In some embodiments, the integrated circuit further includes an interconnect structure located above a semiconductor substrate and comprising a plurality of metal line levels and a plurality of via levels alternately stacked away from the semiconductor substrate, wherein at least one of the plurality of metal line levels separates the semiconductor substrate from the semiconductor device. In some embodiments, the semiconductor channel comprises a metal oxide semiconductor material, and wherein the hydrogen absorption layer comprises an n-type metal oxide containing indium. In some embodiments, the semiconductor channel comprises a metal oxide semiconductor material, and wherein the hydrogen absorption layer comprises a noble metal. In some embodiments, a semiconductor channel is located above a semiconductor substrate, wherein the semiconductor channel, gate, and gate dielectric layer are vertically stacked, and the gate is vertically located between the gate dielectric layer and the semiconductor substrate. In some embodiments, a semiconductor channel is located above a semiconductor substrate, wherein the semiconductor channel, gate, and gate dielectric layer are vertically stacked, and the semiconductor channel is vertically located between the gate and the semiconductor substrate.

[0130] In some embodiments, the present disclosure provides a method for forming a semiconductor device, comprising: forming a gate and a hydrogen absorbing layer adjacent to each other; depositing a gate dielectric layer over the gate and the hydrogen absorbing layer; depositing a semiconductor layer over the gate dielectric layer; patterning the semiconductor layer to form a semiconductor channel over the gate and the hydrogen absorbing layer; and forming a first source / drain and a second source / drain laterally separated from each other over a top portion of the semiconductor channel. In some embodiments, the method further comprises patterning the dielectric layer to form a gate opening, wherein the gate is formed to fill the gate opening, and wherein the hydrogen absorbing layer is formed over the gate and the dielectric layer. In some embodiments, forming the gate and the hydrogen absorbing layer comprises: patterning the dielectric layer to form a gate opening; depositing a barrier layer over the dielectric layer and lining the gate opening; depositing a hydrogen absorbing layer over the barrier layer and lining the gate opening; depositing a conductive layer over the hydrogen absorbing layer and filling the gate opening; and planarizing the barrier layer, the hydrogen absorbing layer, and the conductive layer to expose a top surface of the dielectric layer. In some embodiments, forming a gate and a hydrogen absorbing layer includes: patterning a dielectric layer to form a gate opening; depositing a hydrogen absorbing layer over the dielectric layer, directly contacting the dielectric layer, and lining the gate opening; depositing a conductive layer over the hydrogen absorbing layer and filling the gate opening; and planarizing the hydrogen absorbing layer and the conductive layer to expose a top surface of the dielectric layer. In some embodiments, forming a gate and a hydrogen absorbing layer includes: depositing a conductive layer over the dielectric layer; patterning the conductive layer into a gate; and depositing a hydrogen absorbing layer over the gate, with the hydrogen absorbing layer extending along the sidewalls of the gate. In some embodiments, forming a gate and a hydrogen absorbing layer includes: depositing a thin film including a plurality of conductive layers, a hydrogen absorbing layer, and an additional hydrogen absorbing layer, wherein the plurality of conductive layers are deposited to alternate with the hydrogen absorbing layer and the additional hydrogen absorbing layer; and patterning the thin film into a gate.

[0131] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0132] 100, 300, 400, 500A-500C, 600, 700, 800A, 800B, 900, 1000A-1000C, 1100-2200, 2400-4800: Cross-sectional view 102:TFT 104: Hydrogen absorption layer 106, 310: Gate 108:Semiconductor Channel 1081: semiconductor layer 110, 312: Gate dielectric layer 112a: first source / drain 112b: second source / drain 114: Dielectric substrate 116: conductive body 1161: second conductive layer 118: Conductive lining 1181: first conductive layer 120: dielectric layer 120a: first dielectric layer 120b: second dielectric layer 120c: third dielectric layer 122: Hydrogen barrier layer 200: Top view layout 302: semiconductor substrate 304: Component layer 306:Logical Elements 308: Isolation Structure 314: Source / Drain Region 316:BEOL interconnect structure 318: Metal wire 320:Through hole 322: Interconnect dielectric layer 324: Etching stop layer 324a: TFT support etch stop layer 602, 2102: conductive layer 902: Additional hydrogen absorption layer 1202: Gate opening 2002: Source / Drain Opening 2300: Block Diagram 2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316, 2318: Action V 0, V 1, V 2, V 3, V 4, V 5: Via levels M1, M2, M3, M4, M5, M6: Metal line levels T cl, T ha: thickness

Claims

1. A semiconductor device, comprising: Semiconductor channel; The first source / drain and the second source / drain are located on the first side of the semiconductor channel and are electrically coupled to different parts of the semiconductor channel, respectively. A gate is located on the second side of the semiconductor channel, the second side being opposite to the first side of the semiconductor channel; A gate dielectric layer is located between the gate and the semiconductor channel; and a hydrogen absorption layer is adjacent to the gate, the first source / drain, the second source / drain, or a combination thereof, wherein the hydrogen absorption layer comprises a noble metal or an n-type metal oxide, and the hydrogen absorption layer is embedded in the gate.

2. The semiconductor device of claim 1, wherein the hydrogen absorption layer has the same width as the gate.

3. The semiconductor device of claim 1, wherein the hydrogen absorption layer is in direct contact with the gate dielectric layer.

4. The semiconductor device of claim 1, wherein the hydrogen absorption layer is located between the semiconductor channel and one of the first source / drain electrode and the second source / drain electrode, and extends along the sidewall of said one of the first source / drain electrode and the second source / drain electrode.

5. An integrated circuit comprising a semiconductor device, wherein the semiconductor device comprises: A stacked semiconductor channel, gate, and gate dielectric layer, wherein the gate dielectric layer separates the gate from the semiconductor channel; The first source / drain and the second source / drain are located in different portions of the semiconductor channel, respectively; and a hydrogen absorption layer is adjacent to the gate and the gate dielectric layer, wherein the hydrogen absorption layer comprises a noble metal or an n-type metal oxide, and the hydrogen absorption layer is embedded in the gate.

6. The integrated circuit of claim 5, wherein the gate includes a conductive body and a barrier layer, the barrier layer lining the sidewalls of the conductive body and the surface of the conductive body facing away from the gate dielectric layer, and wherein the hydrogen absorption layer separates the conductive body from the barrier layer.

7. The integrated circuit of claim 5, wherein the semiconductor channel comprises a metal oxide semiconductor material, and wherein the hydrogen absorption layer comprises an indium-containing n-type metal oxide.

8. The integrated circuit of claim 5, wherein the semiconductor channel comprises a metal oxide semiconductor material, and wherein the hydrogen absorption layer comprises a noble metal.

9. A method of forming a semiconductor device, comprising: Forming adjacent gates and hydrogen absorption layers, wherein the hydrogen absorption layer comprises a noble metal or an n-type metal oxide, the hydrogen absorption layer being embedded in the gate; depositing a gate dielectric layer above the gate and the hydrogen absorption layer; depositing a semiconductor layer above the gate dielectric layer; patterning the semiconductor layer to form a semiconductor channel above the gate and the hydrogen absorption layer; and forming a first source / drain and a second source / drain laterally separated from each other above the top of the semiconductor channel.

10. The method as described in claim 9, further comprising: A patterned dielectric layer is used to form a gate opening, wherein the gate is formed to fill the gate opening, and wherein the hydrogen absorption layer is formed above the gate and the dielectric layer.

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