Integrated dry processing systems for patterning radiation photoresist patterning

Abstract

A method for fabricating a thin film on a semiconductor substrate, which can be patterned using EUV, includes: depositing an organometallic polymeric material on the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for subsequent transfer to an underlying layer. The deposition operation can be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with CVD elements (e.g., discontinuous ALD processes where the metal precursor and reactant are separated in time or space).

Description

Integrated Dry Processing System for Patterning Radiation Resist The background description provided herein is to generally present the background of the technology. The work of the currently named inventors, to the extent described in this technical field and aspects that may not conform to the description of the prior art at the time of filing, are not expressly or impliedly admitted to be the prior art relative to this technology. The manufacture of semiconductor devices (such as integrated circuits) is a multi-step process involving lithography. Generally, the process includes depositing materials on a wafer and patterning the materials by lithography to form the structural features (such as transistors and circuits) of the semiconductor device. The steps of a typical lithography process known in the art include: preparing a substrate; applying a photoresist, for example, by spin coating; exposing the photoresist to a desired pattern so that the exposed portion of the photoresist is more or less soluble in a developer; applying the developer for development to remove the exposed or unexposed portion of the photoresist; and performing subsequent processes, such as by etching or material deposition, to create features on the substrate area where the photoresist has been removed. The development of semiconductor design has created a need to create smaller features on semiconductor substrate materials and has been driven by this ability. This technological progress is described in "Moore's Law" as the transistor density in dense integrated circuits doubling approximately every two years. In fact, chip design and manufacturing have advanced to the point where modern microprocessors may contain billions of transistors and other circuit features on a single chip. Individual features on such chips may be on the order of about 22 nanometers (nm) or smaller, and in some cases less than 10 nm. One challenge in fabricating devices with such small features is being able to reliably and reproducibly produce a photomask with sufficient resolution. Current lithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the wavelength of the light is significantly larger than the desired size of the features to be created on a semiconductor substrate creates an inherent problem. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multiple patterning. Thus, there is significant interest and research effort in the aspect of developing lithography techniques using shorter wavelength light such as extreme ultraviolet radiation (EUV), e.g., having a wavelength of 10 nm to 15 nm, such as 13.5 nm. However, EUV lithography processing can present challenges, including low power output and issues with lack of light during patterning. Conventional chemically amplified resist (CAR) materials similar to those used in 193 nm UV lithography have potential drawbacks when used for EUV lithography, particularly because they have a low absorption coefficient in the EUV region and diffusion of the photoactivated chemicals can result in blurring or line edge roughness. Additionally, to provide the etch resistance required to pattern the underlying device layer, small features patterned in conventional CAR materials can result in high aspect ratios and thus a risk of pattern collapse. Accordingly, there is still a need for improved EUV resist materials having properties such as a thinner thickness, greater light absorbency, and greater etch resistance. Methods and systems for an integrated process for forming a patterned resist are disclosed herein. In one aspect of the embodiments disclosed herein, an integrated lithography system is provided that includes: a plurality of reaction chambers within a cluster, the plurality of reaction chambers including: a photoresist (PR) deposition chamber, a post-application bake (PAB) chamber, a post-exposure bake (PEB) chamber, and a development chamber, and a controller including one or more processors and one or more memory devices, wherein the one or more memory devices store computer-executable instructions for controlling the one or more processors to perform the following: receive a substrate in the PR deposition chamber, deposit PR on a surface of the substrate in the PR deposition chamber, receive the substrate having PR in the PAB chamber, process the PR in the PAB chamber to modify material properties of the PR, after processing the PR, receive the substrate in the PEB chamber, wherein a portion of the PR has been chemically altered by exposure to radiation to produce a patterned PR; process the patterned PR in the PEB chamber to modify material properties of the patterned PR, and dry-develop the patterned PR in the development chamber by removing an exposed or unexposed portion of the patterned PR by a dry development process that includes exposure to a compound to form a PR mask. In some embodiments, the PR can be a metal-containing PR. In some embodiments, the PR can be EUV PR. In some embodiments, the plurality of reaction chambers further includes a substrate cleaning chamber, and before the computer-executable instructions for receiving the substrate with the PR in the PAB chamber, the computer-executable instructions further include instructions for controlling one or more processors to perform the following: receiving the substrate with the PR in the cleaning chamber, and performing a dry cleaning process to remove the PR from the bevel edge portion and / or the back side of the substrate. In some embodiments, the plurality of reaction chambers further includes a lower layer deposition chamber, and before the computer-executable instructions for depositing the PR, the computer-executable instructions further include instructions for controlling one or more processors to perform the following: depositing a lower layer on the substrate surface by a dry process, where the lower layer increases the adhesion of the PR to the substrate. In some embodiments, the lower layer deposition chamber can be a PR deposition chamber. In some embodiments, the plurality of reaction chambers further includes a pretreatment chamber, and before the computer-executable instructions for depositing the metal-containing PR, the computer-executable instructions further include instructions for controlling the one or more processors to perform the following: treating the surface of the substrate by a dry process to cause more exposed hydroxyl groups on the surface of the substrate. In some embodiments, each of the plurality of reaction chambers is at a pressure lower than atmospheric pressure, and the PR is at a pressure lower than atmospheric pressure until after the dry development process. In some embodiments, the ambient environment of the substrate can be controlled to reduce the chance of photoresist exposure to moisture before dry developing the patterned PR. In some embodiments, the computer-executable instructions further include computer-executable instructions for depositing the PR by a dry process, and the dry process includes mixing a vapor stream of an organometallic precursor with a vapor stream of a reactant. In some embodiments, all the processes performed by the plurality of reaction chambers are dry processes. In some embodiments, the processes performed by the plurality of reaction chambers include wet processes and dry processes. In some embodiments, the cluster includes multiple PR deposition chambers. In some embodiments, the PAB chamber and the PEB chamber are the same chamber. In some embodiments, the computer-executable instructions further include instructions for controlling one or more processors to perform a dry cleaning process to remove PR from the bevel edge and / or the back side of the substrate within the PAB chamber. In some embodiments, the plurality of reaction chambers further includes a lithography scanner, and prior to the computer-executable instructions for receiving the substrate in the PEB chamber, the computer-executable instructions further include instructions for controlling one or more processors to perform the following: receiving the substrate in the lithography scanner and exposing a portion of the PR to radiation to produce patterned PR. In some embodiments, the plurality of substrate processing environments further includes a heat treatment process environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: heat-treating the metal-containing PR in the heat treatment process environment before and / or after a portion of the metal-containing PR has been chemically altered by exposure to radiation to produce patterned PR. In another aspect of the embodiments disclosed herein, an integrated substrate processing system is provided, the system including: a plurality of substrate processing environments, the plurality of substrate processing environments including a metal-containing photoresist (PR) deposition environment and one or more other different integrated processing environments selected from the group consisting of: an additional metal-containing photoresist (PR) deposition environment; a metal-containing PR development environment, and a heat treatment process environment; and a controller including one or more processors and one or more memory devices, wherein the one or more memory devices store computer-executable instructions for controlling the one or more processors to perform the following: receiving a substrate in the metal-containing PR deposition environment; depositing metal-containing PR on the surface of the substrate in the metal-containing PR deposition environment; and performing additional PR processing operations in one or more other different integrated processing environments. In some embodiments, the plurality of substrate processing environments further includes a PR dry development processing environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: after a portion of the metal-containing PR has been chemically altered by exposure to radiation to produce patterned PR, removing the exposed or unexposed portion of the patterned PR by a dry development process and dry-developing the patterned PR in the development environment, the dry development process including exposure to a compound to form a PR mask. In some embodiments, the plurality of substrate processing environments further includes a scanner environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: exposing a portion of the metal-containing PR to radiation in the scanner environment to chemically alter the exposed portion. In some embodiments, the plurality of substrate processing environments are different processing chambers within a cluster. In some embodiments, the plurality of substrate processing environments are different stations within a chamber. In some embodiments, the plurality of substrate processing environments include three metal-containing PR deposition environments. In some embodiments, the plurality of substrate processing environments include two metal-containing PR deposition environments and one metal-containing PR development environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: after chemically altering a portion of the metal-containing PR by exposure to radiation to produce patterned PR, developing the patterned PR by a dry process. In some embodiments, the plurality of substrate processing environments include a metal-containing PR deposition environment, a heat treatment process environment, and a metal-containing PR development environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: before and / or after chemically altering a portion of the metal-containing PR by exposure to radiation to produce patterned PR, heat-treating the metal-containing PR in the heat treatment process environment, and after heat-treating the metal-containing PR in the heat treatment process environment, developing the patterned PR by a dry process. In some embodiments, the plurality of substrate processing environments include a metal-containing PR deposition environment, a first heat treatment process environment, a second heat treatment process environment, and a metal-containing PR development environment, and one or more memory devices store further computer-executable instructions for controlling one or more processors to perform the following: before chemically altering a portion of the metal-containing PR by exposure to radiation to produce patterned PR, heat-treating the metal-containing PR in the first heat treatment process environment, after chemically altering a portion of the metal-containing PR by exposure to radiation to produce patterned PR, heat-treating the metal-containing PR in the second heat treatment process environment, and after heat-treating the metal-containing PR in the second heat treatment process environment, developing the patterned PR by a dry process. These and other features of the disclosed embodiments will be described in detail below with reference to the related drawings. The present disclosure generally relates to the field of semiconductor processing. In a particular aspect, the present disclosure is directed to methods and apparatuses for processing EUV photoresist (e.g., EUV-sensitive metal and / or metal-oxide-containing resist films) in the context of EUV patterning and EUV patterned film development to form a patterned mask. Reference is now made in detail to specific embodiments of the disclosure. Examples of specific embodiments are illustrated by the accompanying drawings. While the disclosure will be described in connection with these specific embodiments, it is to be understood that it is not intended to limit the disclosure to these specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented disclosure. The disclosure may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosure. Patterning of thin films in semiconductor processing is typically an important step in semiconductor manufacturing. Patterning involves lithography. In traditional lithography techniques such as 193 nm lithography, a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist and removing certain portions of the photoresist after development to form the pattern. Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes of 22 nm, 16 nm, and above. For example, in a 16 nm node, the width of a typical via or line in an embedded structure is generally no greater than about 30 nm. Feature scaling on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography technology to improve resolution. Extreme ultraviolet (EUV) lithography can extend lithography technology by using an imaging source wavelength that is smaller than that of traditional lithography methods. EUV light sources with wavelengths of approximately 10 - 20 nm or 11 - 14 nm (e.g., a 13.5 nm wavelength) can be used in state-of-the-art lithography tools, also known as scanners. EUV radiation is strongly absorbed in a wide range of solid and fluid materials including quartz and water vapor, and thus operates in a vacuum. EUV lithography utilizes EUV resists, which are patterned to form masks for etching underlying layers. EUV resists can be polymer-based chemically amplified resists (CARs) produced by liquid-based spin coating techniques. Alternatives to CARs are directly photopatternable metal oxide-containing films, such as those available from Inpria Corporation of Corvallis, Oregon, and described, for example, in U.S. Patent Publication Nos. US 2017 / 0102612, US 2016 / 021660, and US 2016 / 0116839, the disclosures of which are incorporated herein by reference at least for their teachings regarding photopatternable metal oxide-containing films. Such films can be produced by spin coating techniques or dry vapor deposition. The metal oxide-containing film can be directly patterned (i.e., without using an additional photoresist) by EUV exposure in a vacuum environment, providing a patterning resolution of less than 30 nm, as described, for example, in U.S. Patent No. 9,996,004, entitled "EUV Photopatterning of Vapor-Deposited Metal Oxide-Containing Hardmasks," issued on June 12, 2018, and / or in Patent Application No. PCT / US19 / 31618, entitled "Methods for Making EUV Patternable Hard Masks," filed on May 9, 2019, the disclosures of which are incorporated herein by reference at least for their teachings regarding the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks. Generally, patterning involves exposing the EUV resist to EUV radiation to form a photopattern in the resist, followed by developing it to remove a portion of the resist according to the photopattern to form a mask. We should also understand that although this disclosure is about lithography patterning techniques and materials exemplified by EUV lithography, it is also applicable to other next-generation lithography techniques. In addition to EUV, which includes the currently used and developed standard 13.5 nm EUV wavelength, the radiation sources most relevant to such lithography are DUV (deep ultraviolet light), which generally refers to the use of 248 nm or 193 nm excimer laser light sources, X-rays, which formally include EUV in the lower energy range within the X-ray spectrum, and electron beams, which can cover a relatively wide energy range. The specific method may depend on the semiconductor substrate and the specific materials and applications used in the final semiconductor device. Therefore, the methods described in this application are merely illustrative of the methods and materials available for this technology. A directly photopatternable EUV resist can be composed of or contain a metal and / or a metal oxide mixed in an organic component. This metal / metal oxide is very promising because they can enhance EUV photon absorption and generate secondary electrons and / or show an increased etching selectivity to the underlying thin film stack and device layer. So far, these resists are developed using a wet (solvent) method, which requires moving the wafer to a track where it is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity but also may cause line collapse due to surface tension effects during solvent evaporation between fine features. Dry development techniques have been proposed to overcome these problems by eliminating substrate delamination and interface failures. Dry development has its own challenges, including the etching selectivity between unexposed and EUV-exposed resist materials, which may lead to a higher dose for the size requirement of effective resist exposure compared to wet development. Due to the longer exposure time under the etching gas, the suboptimal selectivity also causes the rounding of the PR angle, which may increase the variation of the line critical dimension (CD) in subsequent transfer etching steps. Figure 1 presents a flowchart of an exemplary method for performing dry chamber cleaning when depositing and developing a photoresist according to some embodiments. The operations of process 100 can be performed in a different order and / or with different, fewer, or additional operations. One or more operations of process 100 can be performed using many devices described herein. In some embodiments, the operations of process 100 can be implemented at least partially according to software stored in one or more non-transitory computer-readable media. In block 102 of process 100, a layer of photoresist is deposited. This can be a dry deposition process such as a vapor deposition process or a wet process such as a spin coating deposition process. The photoresist can be an EUV resist or a metal-containing EUV residue. Figure 2 shows an exemplary process by which a polymeric organometallic material can be formed to deposit a metal-containing EUV resist. Returning to Figure 1, in block 102 of process 100, in addition to depositing a metal-containing EUV resist film on a semiconductor substrate, a metal-containing EUV resist material can also be formed on the inner surface of the processing chamber. The inner surface can include the chamber walls, floor, and ceiling of the processing chamber. Other inner surfaces can include showerheads, nozzles, and substrate support surfaces. The result of a dry deposition process such as a CVD or ALD process can form a metal-containing EUV resist material. Due to performing additional processing (such as deposition) operations in the processing chamber, the thickness of the metal-containing EUV resist material formed on the inner surface increases over time. The metal-containing EUV resist material is prone to flaking off in sheets, shaking off particles, or peeling from the inner surface of the processing chamber, contaminating subsequent semiconductor substrates during processing. In block 150 of process 100, after depositing a metal-containing EUV resist film on a semiconductor substrate in block 102 of process 100, the dry chamber cleaning operation of the present disclosure can be performed. This allows deposition and dry cleaning to be carried out in the same processing chamber. However, it should be understood that in embodiments, the dry chamber cleaning can be performed in a processing chamber different from the deposition operation. In fact, the dry chamber cleaning can be performed after angled and / or backside cleaning, baking, developing, or etching operations. The dry-deposited metal-containing EUV photoresist film to be removed typically consists of Sn, O, and C, but the same cleaning method can be extended to films of other metal oxide resists and materials. In addition, this method can also be used for film removal and PR secondary processing. At block 104 of process 100, an optional cleaning process is performed to clean the backside and / or angled edges of the semiconductor substrate. The backside and / or angled edge cleaning can non-selectively etch the EUV resist film to equally remove films with various degrees of oxidation or cross-linking on the backside and angled edges of the substrate. During the process of applying an EUV-patternable film by wet deposition processing or dry deposition processing, some resist materials may be inadvertently deposited on the angled edges and / or backside of the substrate. Such unexpected deposition may cause unwanted particles to subsequently move to the top surface of the semiconductor substrate and become particle defects. In addition, such angled edge and backside deposition can cause downstream processing problems, including contamination of patterning (scanner) and developing tools. Conventionally, the removal of such angled edge and backside deposits is accomplished by wet cleaning techniques. For spin-coated photoresist materials, this process is called edge bead removal (EBR), which is performed by guiding solvent flows above and below the angled edges while the substrate is rotating. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques. The angled edges and / or backside cleaning of the substrate can also be a dry cleaning process. At block 150 of process 100, the dry chamber cleaning operation of the present disclosure can be performed after the angled edge and / or backside cleaning operation. This allows angled and / or backside cleaning and dry chamber cleaning to be carried out in the same processing chamber. However, it should be understood that in some embodiments, the dry chamber cleaning can be performed in a processing chamber different from the angled edge and / or backside cleaning operation. At block 106 of process 100, an optional post-application bake (PAB) is performed after depositing the EUV-patternable film and before EUV exposure. The PAB process may involve a combination of heat treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-patternable film and reduce the EUV dose to form a pattern in the EUV-patternable film. At block 150 of process 100, the dry chamber cleaning operation of the present disclosure can be performed after the PAB process. This allows baking and dry chamber cleaning to be performed in the same processing chamber. However, it should be understood that in some embodiments, the dry chamber cleaning can be performed in a processing chamber different from the PAB processing operation. In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally, EUV exposure causes changes in the chemical composition and cross-linking in the metal-containing EUV resist film, thereby forming a contrast that can be used for subsequent development in terms of etch selectivity. After exposing the metal-containing EUV resist film to EUV light, a photo-patterned metal-containing EUV resist is provided. The photo-patterned metal-containing EUV resist includes EUV-exposed regions and unexposed regions. At block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast of the etch selectivity of the photo-patterned metal-containing EUV resist. The photo-patterned metal-containing EUV resist can be heat-treated in the presence of various chemicals to promote cross-linking in the EUV-exposed regions of the photo-patterned metal-containing EUV resist, or simply baked on a hot plate in ambient air. At block 150 of process 100, the dry chamber cleaning operation of the present disclosure can be performed after the PEB process. This allows baking and dry chamber cleaning to be performed in the same processing chamber. However, it should be understood that in some embodiments, the dry chamber cleaning can be performed in a processing chamber different from the PEB processing operation. At block 112 of process 100, the photo-patterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed regions are removed (positive type) or the unexposed regions are removed (negative type). In some embodiments, development can include selective deposition on the exposed or unexposed regions of the photo-patterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes can be dry processes or wet processes. Examples of the development process include an EUV-sensitive photoresist film containing organotin oxide (e.g., 10 - 30 nm thick, e.g., 20 nm), subjected to an EUV exposure dose and a post-exposure bake, followed by development. The photoresist film can be deposited, for example, by a gas-phase reaction based on an organotin precursor (e.g., isopropyl(tris)(dimethylamino)tin) and water vapor, or can be a spin-coated film containing tin clusters in an organic matrix. The photo-patterned metal-containing EUV resist is developed by exposure to a developing chemical. In some embodiments, the developing chemical includes a halide-containing chemical. At block 150 of process 100, the dry chamber cleaning operation of the present disclosure can be performed after development. This allows development and dry chamber cleaning to be performed in the same processing chamber. However, it should be understood that in some embodiments, the dry chamber cleaning can be performed in a processing chamber different from the development operation. Additionally, it should be understood that in some embodiments, the dry chamber cleaning can be performed in the same or a different processing chamber as the etching operation. The etching operation can be applied to etch the underlying layer of the semiconductor substrate. Each of operations 102 - 112 is further elucidated below. In various embodiments, the method of the present technology combines the dry steps of all film depositions by vapor deposition, (EUV) lithographic patterning, and dry development. In other embodiments, the method of the present technology includes wet deposition and dry development, or dry deposition and wet development. In some processes, after photolithographic patterning in an EUV scanner, the substrate can directly enter a dry development / etching chamber. Such a process can avoid the material and production costs associated with wet development. Alternatively, the post-exposure bake step can be performed in a development chamber or another chamber, during which the exposed areas undergo further crosslinking to form a denser SnO-like network. In some embodiments, substrates can be provided to multiple processing environments to perform each of operations 102 - 112. For example, there may be a PR deposition environment, one or more heat treatment environments for PAB and / or PEB, a wafer cleaning environment, a scanning environment, and a PR development environment. As will be described below, in some embodiments, one or more of these environments can be in-chamber stations / bases, chambers with one or more bases, and / or multi-chamber cluster tools with one or more chambers. In some embodiments, multiple operations can be performed in a single processing environment. For example, the heat treatment environment and the wafer cleaning environment can be the same processing environment, in which these two operations can be sequentially performed without moving the wafer to a different base, chamber, or tool. In some embodiments, multiple processing environments can be within the same chamber or tool. For example, the heat treatment environment and the wafer cleaning environment can be at different stations in a four-station modular chamber. In some embodiments, multiple identical types of processing environments can be provided in the same tool, for example, to increase or optimize throughput in a multi-operation wafer process when one processing operation is much slower than another. Other combinations of the environments defined above should be understood to be within the scope of the present disclosure. Without limiting the mechanisms, functions, or utilities of the present technology, the dry processes of the present technology can provide a variety of benefits known in the art relative to wet development processes. For example, the dry vapor deposition techniques described herein can be used to deposit thinner and more defect-free films than can be applied using wet spin coating techniques, and the exact thickness of the deposited film can be modulated and controlled by simply increasing or decreasing the length or sequence of deposition steps. Thus, dry processes can provide more tunability and provide further critical dimension (CD) control and scum removal. Dry development can improve performance (e.g., prevent line collapse due to surface tension in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion problems, avoiding the need to apply and remove wet resist formulations (e.g., avoiding scum and pattern deformation), improving line edge roughness, patterning directly on the device surface, providing hard mask chemistries that can be tailored for specific substrate and semiconductor device designs, and having no other solubility-based limitations. In some cases, a combination of wet and dry may be appropriate or optimal, such as in cases where a large capital investment has been made in wet wafer processing equipment, the performance of which can be improved by using integrated dry processing and associated equipment in some operations of a multi-operation process. Accordingly, the present disclosure provides processes and equipment for dry development of EUV light-patterned metal and / or metal oxide-containing resists configured for use as part of an EUV resist mask formation process. Various embodiments include all dry operations for film formation in combination with vapor deposition, (EUV) lithographic light patterning, and dry development. Various other embodiments include the dry processing operations described herein being advantageously combined with wet processing operations, such as spin-on EUV photoresist (wet process) available from Inpria Corp. can be combined with dry development or other wet or dry processes described herein. In various embodiments, wafer cleaning can be a wet process as described herein while other processes are dry processes. In further embodiments, a wet development process can be used in combination with (dry) vapor deposition of a PR film. Lithography process Figures 3A-E show another representative process flow of a metal photoresist hard mask formation process. Generally, a metal-containing film sensitive to a patterning agent such as photons, electrons, protons, ions, or neutral substances is deposited on a semiconductor substrate such that the film can be patterned by exposure to one of these substances. The metal-containing film is then patterned by exposure to the patterning agent in a vacuum environment to form a metal mask. This description mainly refers to patterning of a metal-containing film, especially in the case where the metal is Sn, by extreme ultraviolet lithography (EUV lithography (EUVL)), especially EUVL with an EUV source using excited Sn droplets. Such a film is referred to herein as an EUV-sensitive film. However, it should be understood that other embodiments are also possible, including different metal-containing films and patterning agents / techniques. Referring to FIG. 3A, a semiconductor substrate 300 to be patterned is shown. In a typical example, the semiconductor substrate 300 is a silicon wafer containing a partially formed integrated circuit. FIG. 3B illustrates a metal-containing film 302 sensitive to a patterning agent deposited on the semiconductor substrate 300. The metal-containing film can be a metal salt (such as a metal halide) or an organometallic compound sensitive to exposure to the patterning agent such that the metal-containing film becomes decomposed into the base metal or becomes sensitive to subsequent development processing. Suitable patterning agents can be photons, electrons, protons, ions, or neutral substances such that the metal-containing film 302 can be patterned by exposure to one of these substances to be decomposed into the base metal or become sensitive to subsequent development processing. Generally, the semiconductor substrate 300 is placed in a reaction chamber for depositing the metal-containing film under vacuum before deposition. A blanket metal-containing film 302 can be formed by condensation from a suitable precursor (such as in a non-plasma CVD reactor, for example, an Altus® CVD tool or an Aether® GP CVD tool available from Lam Research Corporation, Fremont, Calif.). Suitable process conditions for such deposition by condensation include a deposition temperature between about 0 and 250°C, such as from ambient temperature (such as 23°C) to 150°C, and a reactor pressure of less than 20 Torr, such as between 0.5 and 2 Torr when maintained at 60˚C. Maintaining the precursor flow rate between approximately 100 and 1000 sccm can control the deposition rate. To prevent degradation due to water vapor, the formation and transfer of the Sn-containing film are performed in a vacuum environment. The formed thin film is then transferred to an EUV patterning tool and patterned by direct exposure without using a photoresist, as shown in FIGS. 3C-D. We should note that EUVL tools typically operate at a higher vacuum than deposition tools. If this is the case, we would like to increase the vacuum environment of the substrate during the transfer from the deposition to the patterning tool to allow the substrate and the deposited metal-containing film to outgas before entering the patterning tool. This is to prevent the optical elements of the patterning tool from being contaminated by the outgassing of the substrate. As shown in FIG. 3C, patterning results in the formation of an exposed area 302a of the metal-containing film that forms the metal mask and an unexposed area 302b of the material to be removed by pattern development. Referring to FIG. 3D, the pattern can then be developed. Development is further discussed elsewhere in this document. In some embodiments, pattern development can occur simply by heating the substrate to volatilize the unexposed area 302b of the metal-containing film, such that only the exposed area 302a remains as the fully formed metal mask. It should be noted that this pattern development operation may not require vacuum integration, as a thermally and environmentally stable patterned metal mask may already have been formed. We may also need to perform pattern development outside of the patterning tool to avoid contaminating the tool optics with any incompatible by-products decomposed from the metal-containing film. Referring to FIG. 3E, as an optional step, pattern amplification can be performed. For example, after the operations depicted in FIGS. 3C and / or 3D, selective ALD or electroless deposition (ELD) can be performed on the patterned substrate to increase the thickness of the metal mask with additional selectively deposited metal 306. This may help reduce the light transmission of the mask or make it mechanically more robust. Such amplification can be achieved, for example, by employing electroless deposition processes such as those described in U.S. Patent Nos. 6,911,067, 6,794,288, 6,902,605, and 4,935,312, the disclosures of which in this regard are incorporated herein by reference. For example, an initial 1 nm seed can be amplified to 10 nm in this manner. Similar to the pattern development discussed with reference to FIG. 3D, this operation may not require vacuum integration, as a thermally and environmentally stable patterned metal mask has already been formed prior to amplification. One of the advantages of fully dry or partially dry film formation operations is that dry operations can be a tunable process for single-pass processing. By varying numerous process conditions (described below), the operation can be optimized. For example, the dry processes for the underlying layer and PR deposition can be performed in two operations, while wet processes may require cleaning and baking operations prior to depositing the PR film. In contrast, wet processes may require the use of pre-formulated solutions to limit process parameters, as well as additional multi-pass processing for heat treatment, cooling, and spin-drying. Dry processes can avoid any liquid solution drying steps and reduce PR delamination or line tilt / collapse. Another advantage of fully dry or partially dry film-forming operations is enhanced control over the process environment. Wet spin coating processes can use pre-formulated solutions and be carried out at ambient pressure. Dry processes can be carried out under vacuum, and parameters such as pressure, humidity, oxygen, and temperature can be controlled. In embodiments of an integrated process carried out on the same tool, chamber, or station, the vacuum can be maintained between dry processes, which is beneficial for controlling the environment of the wafer during and between process operations. Additionally, the integrated process can reduce queue time because the processes are all carried out within the same tool, chamber, or station. Photoresist ( PR ) Deposition As described above, the present disclosure provides methods for fabricating an imaging layer on a semiconductor substrate, which can be patterned using EUV or other next-generation lithography techniques. The methods include methods for producing a polymeric organometallic material in a vapor and depositing it on the substrate. In other embodiments, a spin coating formulation can be used. The present technology provides methods for depositing EUV-sensitive thin films on a substrate, which can be used as resists for subsequent EUV lithography and processing. The materials included in such EUV-sensitive thin films change upon exposure to EUV, such as the loss of large pendant substituents bonded to metal atoms in low-density M-OH-rich materials, allowing them to crosslink to a denser M-O-M-bonded metal oxide material. By EUV patterning, the resulting film regions have altered physical or chemical properties relative to the unexposed regions. These properties can be used for subsequent processing, such as dissolving the unexposed or exposed regions, or selectively depositing materials on the exposed or unexposed regions. In some embodiments, under the conditions for such subsequent processing, the unexposed film has a hydrophobic surface and the exposed film has a hydrophilic surface (we should recognize that the hydrophilicity of the exposed and unexposed regions is related to each other). For example, the removal of materials can be carried out by taking advantage of differences in the chemical composition, density, and crosslinking of the film. The removal can be carried out by wet processing or dry processing, as further described below. The thickness of the EUV-patternable film formed on the substrate surface may vary depending on the surface characteristics, the materials used, and the process conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm, and preferably has a sufficient thickness to absorb most of the EUV light under EUV patterning conditions. For example, the total absorption of the resist film can be 30% or less (e.g., 10% or less, or 5% or less), such that the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is 10 to 20 nm. Without limiting the mechanisms, functions, or utilities of the present disclosure, it is believed that, unlike wet spin-coating processes in the art, the processes of the present disclosure have fewer restrictions on the surface adhesion properties of the substrate and can thus be applied to a variety of substrates. Additionally, as described above, the deposited film can closely conform to the surface features, thereby providing an advantage in forming a mask (e.g., a substrate with underlying features) on the substrate without the need to "fill" or otherwise planarize these features. substrate Substrates useful in the methods of the present technology can include any material structure suitable for lithography processing, particularly suitable for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate can be a silicon wafer on which features ("underlying surface topography features") have already been formed and has an irregular surface topography. (As used herein, "surface" is the surface on which the film of the present disclosure will be deposited or will be exposed to EUV during processing). The underlying surface topography features can include regions where material has been removed (e.g., by etching) or material has been added (e.g., by deposition) during processing prior to performing the methods of the present technology. Such prior processing can include the methods of the present technology or other processing methods, and two or more layers of features are formed on the substrate by iterative processing. Without limiting the mechanisms, functions, or utilities of the present technology, it is believed that in some embodiments, the methods of the present technology provide advantages over methods known in the art, where a photolithography film is deposited on the surface of a substrate using a spin-casting method. Such advantages can stem from the ability of the film of the present technology to conform to the underlying features without the need to "fill" or otherwise planarize such features, and the ability to deposit the film on a variety of material surfaces. In some embodiments, an incoming wafer can be prepared using a substrate surface with a desired material, the topmost material of which is the layer to which the resist pattern is to be transferred. Although the material selection can vary depending on the degree of integration, it is generally desirable to select a material that can be etched with high selectivity to the EUV resist or imaging layer (i.e., much faster than it). Suitable substrate materials can include a variety of carbon-based thin films (e.g., ashing hard mask (AHM)), silicon-based thin films (e.g., SiO x 、SiO x N y , SiO x C y Nz), a-Si:H, poly-Si or SiN), or apply any other (usually sacrificial) thin film for promoting the patterning process. In some embodiments, the substrate is a hard mask for lithographic etching of the underlying semiconductor material. The hard mask can comprise any of a variety of materials, including amorphous carbon (aC), SnO x , SiO 2 , SiO x N y , SiO x C, Si 3 N 4 , TiO 2 , TiN, W, W-doped C, WO x , HfO 2 , ZrO 2 and Al 2 O 3 . For example, the substrate can preferably comprise SnO x , such as SnO 2 . In various embodiments, the layer can be 1 nm to 100 nm thick, or 2 nm to 10 nm thick. In some embodiments, the substrate includes a lower layer. The lower layer may be deposited on a hard mask or other layer and is generally beneath the imaging layer as described herein. The lower layer can be used to improve the sensitivity of the PR, increase EUV absorption, and / or increase the patterning performance of the PR. If there are device features to be patterned on the substrate that create significant topography, another important function of the lower layer can be to cover the existing topography and planarize it so that subsequent patterning steps can be performed on a flat surface in all areas with significant patterns. For such applications, spin coating techniques can be used to apply the lower layer (or at least one of the multiple lower layers). When the photoresist material used has a significant inorganic component, e.g., it mainly exhibits a metal oxide framework, the lower layer can advantageously be a carbon-based film and is applied by spin coating or a dry vacuum-based deposition process. The layer can include various ashing hard mask (AHM) films having carbon and hydrogen-based components, and it can be doped with additional elements such as tungsten, boron, nitrogen, or fluorine. Methods and apparatuses useful in these processes are described in U.S. Patent Application No. 62,909,430, filed Oct. 2, 2019, the methods and apparatuses of which are incorporated herein by reference. Thin film deposition In many embodiments, the EUV-patternable films are fabricated and deposited on the substrate using those vapor deposition apparatuses and processes known in the art. In such processes, polymeric organometallic materials are formed in the vapor phase or in situ on the substrate surface. Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a reactant to form a polymeric organometallic material and depositing the organometallic material onto the surface of a semiconductor substrate. Those skilled in the art will understand that the mixing and deposition aspects of the process can be carried out simultaneously in a substantially continuous process. Methods and apparatuses useful in these processes are described in Application No. PCT / US2019 / 031618, filed May 9, 2019, and Application No. PCT / US2019 / 060742, filed Nov. 11, 2019, the methods and apparatuses of which are incorporated herein by reference, particularly the respective organometallic precursors. An EUV-sensitive film can be deposited on a semiconductor substrate, and such a film can be manipulated to serve as a resist in subsequent EUV lithography and processing. Such an EUV-sensitive film contains materials that change upon exposure to EUV. For example, large pendant substituents bonded to metal atoms are lost in a low-density M-OH-rich material, allowing them to crosslink to a denser M-O-M-bonded metal oxide material. By EUV patterning, the resulting film regions have altered physical or chemical properties relative to the unexposed regions. These properties can be used for subsequent processing, such as dissolving the unexposed or exposed regions, or selectively depositing materials on the exposed or unexposed regions. In some embodiments, under the conditions for such subsequent processing, the unexposed film has a more hydrophobic surface than the exposed film. For example, the removal of the material can be carried out by taking advantage of the differences in the chemical composition, density, and crosslinking of the film. The removal can be by wet processing or dry processing, as further described below. In various embodiments, the film is an organometallic material, such as an organotin material containing tin oxide, or other metal oxide materials / functional groups. The organometallic compound can be prepared in a gas-phase reaction of an organometallic precursor with a reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of organometallic precursors having large alkyl or fluoroalkyl groups with a reactant and polymerizing the mixture in the gas phase to produce a low-density, EUV-sensitive material deposited on the surface of the semiconductor substrate. In various embodiments, the organometallic precursor contains at least one alkyl group on each metal atom that can undergo a gas-phase reaction, and other ligands or ions coordinated to the metal atom can be replaced by the reactant. The organometallic precursors include those of the following chemical formula: M a R b L c (Formula 1) where: M is an element with a high EUV absorption cross-section; R is an alkyl group, such as C n H 2n+1 , where preferably n≥2; L is a ligand, ion, or other functional group that reacts with the reactant; a≥1; b≥1; and c≥1. In various embodiments, M has an atomic absorption cross-section equal to or greater than 1x10 7 cm 2 / mol. M can be selected, for example, from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R can be fluorinated, such as having the chemical formula C n F x H （ 2n+1 ） 。In each embodiment, R has at least one β-hydrogen or β-fluorine. For example, R can be selected from the group consisting of ethyl, isopropyl, n-propyl, tert-butyl, isobutyl, n-butyl, sec-butyl, n-pentyl, isopentyl, tert-pentyl, sec-pentyl, and mixtures thereof. L can be any functional group that is easily replaced by a counter-reactant to produce an M-OH functional group, such as a functional group selected from the group consisting of amines (such as dialkylamino, monoalkylamino), alkoxy, carboxylate, halide, and mixtures thereof. The counter-reactant is capable of replacing a reactive functional group, ligand, or ion (such as L in Chemical Formula 1 above) to connect at least two metal atoms by chemical bonding. The counter-reactant can include water, peroxides (such as hydrogen peroxide), dihydroxy or polyhydroxy alcohols, fluorinated dihydroxy or polyhydroxy alcohols, fluorinated diols, and other hydroxyl functional group sources. In each embodiment, the counter-reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other potential counter-reactants include hydrogen sulfide and disulfide, which can crosslink metal atoms through sulfur bridges. Other potential counter-reactants include hydrogen sulfide and disulfide, which can crosslink metal atoms through sulfur bridges. In other cases, for example, a Te precursor can be used with water or in place of water as a counter-reactant to form Te-Sn-Te-Sn crosslinks. Suitable tellurium co-reactants for use with Sn(NMe 2 )x type precursors are RTeH or RTeD (D = deuterium) and R 2 Te precursors, where R = alkyl, especially tert-butyl or isopropyl, such as tert-butyl TeD. For example, when used with an M(OR)x type precursor, bis(trimethylsilyl)Te can be used. In addition to the organometallic precursor and the counter-reactant, the thin film can also include optional materials to change the chemical or physical properties of the film, such as changing the film's sensitivity to EUV or enhancing the etching resistance. Such optional materials can be introduced, for example, by doping during the vapor phase formation before deposition on a semiconductor substrate, after thin film deposition, or both. In some embodiments, a mild remote H 2 plasma can be introduced to replace some Sn-L bonds with Sn-H, which can increase the reactivity of the resist under EUV. In various embodiments, vapor deposition equipment and processes known in the art are used to fabricate and deposit an EUV-patternable film on a semiconductor substrate. In such processes, a polymeric organometallic material is formed in the gas phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with CVD components, such as a discontinuous, ALD-like process where the metal precursor and the reactant are separated in time or space. Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a reactant to form a polymeric organometallic material and depositing the organometallic material onto the surface of the semiconductor substrate. In some embodiments, the vapor stream includes more than one organometallic precursor. In some embodiments, the vapor stream includes more than one reactant. Those skilled in the art will understand that the mixing and deposition aspects of this process can be carried out simultaneously in a substantially continuous process. In an exemplary continuous CVD process, in separate inlet paths, two or more gas streams of an organometallic precursor and a reactant source are introduced into the deposition chamber of a CVD apparatus where they mix and react in the gas phase to form a coalesced polymeric material (e.g., through the formation of metal-oxygen-metal bonds). The streams can be introduced, for example, using separate injection ports or a dual-inlet chamber showerhead. The apparatus is configured to mix the streams of the organometallic precursor and the reactant in the chamber and allow the organometallic precursor and the reactant to react to form a polymeric organometallic material. Without limiting the mechanism, function, or utility of the technology, it is believed that the molecular weight of the product from such a gas-phase reaction becomes heavier as the metal atoms are cross-linked by the reactant and then condenses or otherwise deposits onto the semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of a dense network and produces a smoothed, amorphous, low-density film. The CVD process is typically carried out under reduced pressure, such as from 10 milliTorr to 10 Torr. In some embodiments, the process is carried out at 0.5 to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is equal to or lower than the temperature of the reactant stream. For example, the substrate temperature can be from 0°C to 250°C, or from ambient temperature (e.g., 23°C) to 150°C. In each process, the deposition rate of the polymeric organometallic material on the substrate is inversely proportional to the surface temperature. The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate can vary depending on the surface characteristics, the materials used, and the processing conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm and can be a thickness sufficient to absorb most of the EUV light under EUV patterning conditions. The EUV-patternable film may be capable of an absorption equal to or greater than 30%, resulting in significantly fewer EUV photons available for reaching the bottom of the EUV-patternable film. Higher EUV absorption near the top of the film exposed to EUV results in more cross-linking and densification compared to the bottom of the film exposed to EUV. Although efficient utilization of EUV photons can occur with an EUV-patternable film having a higher overall absorption, it should be understood that in some cases, the EUV-patternable film may be less than about 30%. For comparison, the maximum total absorption of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), such that the resist material at the bottom of the resist film is fully exposed. In some embodiments, the film thickness is from 10 nm to 40 nm or from 10 nm to 20 nm. Without limiting the mechanisms, functions, or utilities of the present disclosure, it is believed that, unlike wet spin-coating processes in the art, the processes of the present disclosure have fewer restrictions on the surface adhesion properties of the substrate and can thus be applied to a variety of substrates. Additionally, as described above, the deposited film can closely conform to the surface features, providing an advantage in forming a mask (e.g., a substrate having underlying features) on the substrate without the need to "fill" or otherwise planarize these features. In some embodiments of the techniques discussed herein, another strategy for further increasing the EUV sensitivity in the PR film is to produce a film with a vertical gradient in the film composition, resulting in an EUV sensitivity that depends on depth. In a homogeneous PR with a high absorption coefficient, a higher EUV dose is required for the light intensity to decrease throughout the film depth to ensure sufficient exposure at the bottom. By increasing the atomic density with a high EUV absorption rate at the bottom of the film relative to the top of the film (i.e., by producing a gradient with an increasing EUV absorption rate), it may become possible to more efficiently utilize the available EUV photons while having a more uniform distribution of the absorption rate (and the effect of secondary electrons) towards the bottom of the higher absorption film. The strategy of designing a vertical composition gradient in a PR film is particularly applicable to dry deposition methods such as CVD and ALD, and can be achieved by adjusting the flow ratio between different reactants during the deposition process. The types of composition gradients that can be designed include: the ratio between different highly absorbent metals, the percentage of metal atoms with EUV-cleavable bulky groups, the percentage of bulky groups or counter-reactants containing highly absorbent elements (such as Te and I), and combinations of the above. Further discussion of the vertically graded film can be found in the patent application PCT / US20 / 70172 filed on June 24, 2020, the methods and apparatuses disclosed therein are incorporated herein by reference. Backside and bevel edge cleaning During the process of applying an EUV photoresist film to a substrate, whether by traditional wet processing (such as spin coating) or dry deposition as described herein, there may be some unwanted resist material deposition on the bevel edges and / or the backside of the wafer. Such bevel edge and backside depositions can lead to downstream processing problems, including contamination of the pattern (scanner) and development tools. Traditionally, the removal of such bevel edge and backside depositions is accomplished by wet cleaning techniques. The state-of-the-art technology currently used for cleaning spin-coated metal-organic photoresists is by wet cleaning processes. Edge bead removal (EBR) is performed on the wet tracks on both the front and back sides of the wafer. The nozzles are located above the wafer edges on both the front and back sides of the wafer and dispense solvents while the wafer is rotating. Organic solvents (such as PGME, PGMEA, 2-heptanone) dissolve the photoresist on the edges and clean the bevel edge regions. If the backside is contaminated, the wafer needs to go to another wet cleaning station for backside cleaning of the wafer. For spin coating, the wafer area in contact with the chuck is usually kept clean, and additional backside cleaning is not always used. To reduce metal contamination, additional cleaning may be required, such as dilute hydrofluoric acid (dHF), dilute hydrochloric acid (dHCl), dilute sulfuric acid, or standard clean 1 (SC-1). A backside scrub is usually performed before entering the EUV scanner. The solvents used in wet cleaning processes inherently have problems of high acquisition and disposal costs. Such solvents may be harmful to the environment and pose health problems. Wet cleaning processes may be limited by the uniformity of the removal of EUV resist materials on the bevel edge regions. Due to surface tension and vapor problems, the removal is usually wavy and does not result in a brittle removal of the EUV resist materials in the bevel edge regions. In addition, backsputtering using organic solvents can create defects on the front side of the wafer. Wet cleaning processes are usually performed in separate tools / chambers, so the wafer needs to be transferred between tools / chambers after deposition. This can lead to contamination of the tools / chambers used for backside and / or bevel edge cleaning. Described herein is a cleaning process for cleaning the backside and bevel edge portions of a semiconductor substrate. Backside and bevel edge cleaning can non-selectively etch the EUV resist film to equally remove films with various degrees of oxidation or cross-linking on the backside and bevel edge portions of the substrate. In the process of applying an EUV-patternable film by wet deposition or dry deposition, some resist materials may inadvertently deposit on the bevel edge portions and / or the backside of the substrate. Such unintentional deposition may cause unwanted particles to move to the top surface of the semiconductor substrate later and become particle defects. In addition, such bevel edge and backside deposition can lead to downstream processing problems, including contamination of patterning (scanner) and development tools and metrology tools. Conventionally, the removal of such bevel edge and backside deposits is accomplished by wet cleaning techniques. For spin-coated photoresist materials, this process is called edge bead removal (EBR), which is performed by guiding solvent flows above and below the bevel edge while the substrate is rotating. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques. Bevel edge and backside cleaning can also be a dry cleaning process. In some embodiments, the dry cleaning process involves a vapor and / or plasma having one or more of the following gases: HBr, HCl, HI, BCl 3 、SOCl 2 、Cl 2 、BBr 3 、H 2 、O 2 、PCl 3 、CH 4 、methanol, ammonia, formic acid, NF 3 、HF. In some embodiments, the dry cleaning process can use the same chemicals as the dry development process described herein. For example, backside and bevel edge cleaning can use hydrohalide development chemicals. For the backside and bevel edge cleaning process, the vapor and / or plasma must be restricted to a specific area of the substrate to ensure that only the backside and bevel edge deposits are removed without any film degradation on the front side of the substrate. The processing conditions can be optimized for bevel edge and backside cleaning. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rates can result in increased etching rates. Depending on the photoresist film and composition and properties, suitable processing conditions for dry bevel edge and backside cleaning may be: a reactant flow rate of 100–10,000 sccm (such as 500 sccm of HCl, HBr, HI, or H 2 and Cl 2 or Br 2 、BCl 3 or H 2 ), a temperature of 20°C to 140°C (such as 80°C), a pressure of 20–1000 mTorr (such as 100 mTorr), or a plasma power of 0 W to 500 W at high frequency (such as 13.56 MHz), and for a duration of about 10 to 20 seconds. It should be understood that while these conditions are suitable for certain processing reactors, such as the Kiyo etch tool available from Lam Research Corporation of Fremont, California, a wider range of processing conditions can be used depending on the capabilities of the processing reactor. Further discussion of bevel edge and backside cleaning can be found in patent application PCT / US20 / 70187 filed on June 25, 2020, and / or patent application PCT / US20 / 39615 filed on June 25, 2020, which are hereby incorporated by reference for all purposes. PR Second processing Alternatively, the dry cleaning operation can be extended to completely remove the photoresist or perform photoresist "second processing", such as when the original photoresist is damaged or has other defects, in which the applied EUV photoresist is removed and the semiconductor substrate is prepared for reapplication of the photoresist. The photoresist second processing should be done without damaging the underlying semiconductor substrate, so oxygen-based etching should be avoided. Instead, variants of the halide-containing chemicals described herein can be used. It should be understood that the photoresist second processing operation can be performed at any stage during the process. Thus, the photoresist second processing operation can be applied after photoresist deposition, after bevel edge and / or backside cleaning, after PAB processing, after EUV exposure, after PEB processing, and after development. In some embodiments, the photoresist second processing can be performed to non-selectively remove the exposed and unexposed regions of the photoresist but is selective to the underlying layer. In some embodiments, the photoresist post-processing involves vapors and / or plasmas of one or more of the following gases: HBr, HCl, HI, BCl 3 、Cl 2 、BBr 3 、H 2 、PCl 3 、CH 4 、methanol, ammonia, formic acid, NF 3 、HF. In some embodiments, the photoresist post-processing can use the same chemicals as the dry development process described herein. For example, the photoresist post-processing can use hydrohalide development chemicals. The processing conditions can be optimized for the photoresist post-processing. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rates can result in increased etching rates. Depending on the photoresist film and composition and properties, suitable processing conditions for the photoresist post-processing may be: a reactant flow rate of 100–500 sccm (e.g., 500 sccm of HCl, HBr, HI, BCl 3 or H 2 and Cl 2 or Br 2 ), a temperature of 20°C to 140°C (e.g., 80°C), a pressure of 20-1000 mTorr (e.g., 300 mTorr), a plasma power of 300 W to 800 W (e.g., 500 W) at high frequency (e.g., 13.56 MHz), a wafer bias of 0 to 200 V b (higher bias can be used with harder underlying substrate materials), and a duration of about 20 seconds to 3 minutes, which is sufficient to completely remove the EUV photoresist. It should be understood that although these conditions apply to some processing reactors, such as the Kiyo etch tool available from Lam Research Corporation of Fremont, California, a wider range of processing conditions can be used depending on the capabilities of the processing reactor. Further discussion of the bevel edge and backside cleaning or PR post-processing can be found in the patent application PCT / US20 / 39615 filed on June 25, 2020, which is incorporated herein by reference for all purposes. PAB / Soft bake Photolithography processing typically includes one or more baking steps to facilitate the chemical reactions required to create a chemical contrast between the exposed and unexposed regions of the photoresist. For high-volume manufacturing (HVM), such baking steps are typically performed on a track where the wafer is baked on a hot plate at a preset temperature in ambient air or in some cases in N 2 flowing down. During these baking steps, more careful control of the baking environment and the introduction of additional reactive gas components into the environment can help further reduce the dose requirements and / or improve pattern fidelity. According to various aspects of the present disclosure, one or more post-treatments on metal and / or metal oxide-based photoresists after deposition (e.g., post-application bake (PAB)) and / or exposure (e.g., post-exposure bake (PEB)) are capable of increasing the difference in material properties between the exposed and unexposed photoresists, thereby reducing the dimension dose (DtS), improving the PR profile, and improving the line edge and width roughness (LER / LWR) after subsequent dry development. The PAB treatment may involve a combination of heat treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-patternable film and reduce the EUV dose of the developed pattern in the EUV-patternable film. The PAB treatment temperature can be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the treatment temperature can be between about 90°C and about 200°C, or between about 150°C and about 190°C. In some embodiments, the PAB treatment can be performed at a pressure between atmospheric pressure and vacuum for a treatment duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB treatment is performed at a temperature between about 100°C and 200°C for about 1 minute to 2 minutes. In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally, EUV exposure causes changes in the chemical composition and cross-linking in the metal-containing EUV resist film, thereby creating a contrast in etch selectivity for subsequent development. Next, a metal-containing EUV resist film can be patterned by exposing a region of the film to EUV light (usually under relatively high vacuum). The EUV devices and imaging methods useful herein include methods known in the art. In particular, the exposed region of the thin film as described above is generated by EUV patterning, which has altered physical or chemical properties relative to the unexposed region. For example, in the exposed region, metal-carbon bond cleavage may occur, such as by β-hydride elimination, leaving reactive and accessible metal hydride functional groups. In this process, these functional groups can be converted to hydroxides and cross-linked metal oxide functional groups by metal-oxygen bridges in a subsequent post-exposure bake (PEB) step. This process can be used to create a development chemical contrast as a negative resist. Generally, the more β-H in the alkyl group, the more sensitive the film. This can also be explained by the weaker Sn-C bonding with more branches. After exposure, the metal-containing EUV resist film can be baked to cause additional cross-linking of the metal oxide film. The property differences between the exposed and unexposed regions can be used for subsequent processing, such as dissolving the unexposed region or depositing materials on the exposed region. For example, dry methods can be used to develop the pattern to form a mask containing metal oxide. Specifically, in various embodiments, the hydrocarbon-capped tin oxide present on the surface is converted to hydrogen-capped tin oxide in the exposed region of the imaging layer, especially when exposed using EUV in a vacuum. However, removing the exposed imaging layer from the vacuum to air, or controlling the introduction of oxygen, ozone, H 2 O 2 or water, causes the surface Sn-H to oxidize to Sn-OH. The property differences between the exposed and unexposed regions can be exploited in subsequent processing, such as by reacting the irradiated region, the non-irradiated region, or both with one or more reagents to selectively add materials to or remove materials from the imaging layer. Without limiting the mechanism, function, or utility of the present technology, for example, EUV exposure at doses from 10 mJ / cm 2 to 100 mJ / cm 2 causes Sn-C bond cleavage, resulting in the loss of alkyl substituents, reducing steric hindrance and causing the low-density film to collapse. In addition, the reactive metal-H bonds generated in the β-hydride elimination reaction can react with adjacent active groups, such as hydroxyl groups in the film, resulting in further cross-linking and densification, and creating a chemical contrast between the exposed and unexposed regions. After exposing the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided. The photopatterned metal-containing EUV resist includes an EUV exposed region and an unexposed region. At block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast of the etch selectivity of the metal-containing EUV resist after photolithography. The metal-containing EUV resist after photolithography can be heat-treated in the presence of various chemicals to promote cross-linking in the EUV-exposed areas, or simply baked on a hot plate in ambient air for 1 to 5 minutes (e.g., 2 minutes at 190°C) between, for example, 150°C and 250°C. In various embodiments, the bake strategy involves careful control of the bake environment, introduction of reactive gases, and / or careful control of the rate of increase of the bake temperature. Examples of useful reactive gases include, for example, air, H 2 O, H 2 O 2 vapor, CO 2 2, CO, O 2 3, O 3 2, CH 4 4, CH 3 3OH, N 2 2, H 2 2, NH 3 3, N 2 2O, NO, alcohol, acetylacetone, formic acid, Ar, He, or a mixture thereof. The PEB process is designed to (1) drive the complete evaporation of the organic fragments generated during EUV exposure, and (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure into metal hydroxides, and (3) promote cross-linking between adjacent Sn-OH groups to form a denser cross-linked SnO 2Class network. The baking temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature will result in insufficient cross-linking, leading to a lower chemical contrast developed at a given dose. Too high a PEB temperature will also have an adverse effect, including severe oxidation of the unexposed area and film shrinkage (in this case, the area is removed by developing the patterned film to form a mask), as well as unwanted interdiffusion at the interface between the metal-containing EUV resist and the underlying layer, both of which will result in a loss of chemical contrast and an increase in defect density due to insoluble scum. The PEB treatment temperature can be between about 100°C and about 300°C, between about 170°C and about 290°C, or between about 200°C and about 240°C. In some embodiments, the PEB treatment can be carried out for a treatment duration of about 1 to 15 minutes (e.g., about 2 minutes) at a pressure between atmospheric pressure and vacuum. In some embodiments, the PEB heat treatment can be repeated to further increase the etch selectivity. In addition, the ramp rate of the baking temperature in the PAB or PEB treatment is another useful process parameter, and the cross-linking / etch selectivity results can be fine-tuned by manipulating this process parameter. Alternatively, the PAB and PEB heat treatments can be completed in a single operation or multiple operations, using different process conditions for each operation, such as ambient gas or mixture, temperature, pressure, etc., to adjust the PR characteristics and thus adjust different etch selectivities. In alternative embodiments, either or both of the post-application and post-exposure treatments can involve a remote plasma process, along with or in place of the heat treatment, to generate radicals to react with the metal-containing photoresist to change its material properties. In such an embodiment, the radicals can be generated from the same or different gas species. In various embodiments, the metal-containing photoresist is treated before and after exposure to EUV lithography (e.g., PAB and PEB) to modify the material properties of the metal-containing photoresist. Further discussion of the PAB and PEB operations can be found in U.S. Patent Application No. 62 / 970,020, filed on February 4, 2020, and Patent Application PCT / US20 / 70171, filed on June 24, 2020, which are incorporated herein by reference for all purposes. EUV Scanner Extreme ultraviolet (EUV) lithography can extend lithography beyond its optical limits by using a smaller imaging source wavelength achievable with current optical lithography methods to pattern small critical dimension features. An EUV light source with a wavelength of about 13.5 nm can be used as a state-of-the-art lithography tool, also known as a scanner. EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, and thus operates in a vacuum. The present technology also provides a method of patterning an imaging layer by exposing regions of the imaging layer to radiation such as EUV, DUV, or an electron beam. In such patterning, the radiation is focused on one or more regions of the imaging layer. A typical exposure is performed such that the imaging layer film contains one or more regions not exposed to the radiation. The resulting imaging layer can contain plural exposed and unexposed regions, thereby generating a pattern consistent with the formation of transistors or other features of a semiconductor device by adding or removing material from the substrate in subsequent processing of the substrate. EUV, DUV, and electron beam radiation methods and apparatuses useful herein include those known in the art. Disclosed herein is a vacuum integrated metal hard mask process and related vacuum integrated hardware that combines film formation (deposition / condensation) and optical lithography, resulting in a significant improvement in EUV lithography (EUVL) performance - such as reducing line edge roughness. In various embodiments described herein, a deposition (e.g., condensation) process (e.g., ALD or MOCVD performed in a PECVD tool, e.g., Lam Vector®) can be used to form a thin film containing a metal-containing film, such as a photosensitive metal salt or an organometallic compound (organometallic compound) containing a metal, e.g., having strong absorption in EUV at the wavelength of the EUVL light source (e.g., 13.5 nm = 91.8 eV), e.g., at wavelengths on the order of 10 - 20 nm. The thin film undergoes photolysis upon EUV exposure and forms a metal mask, which serves as a pattern transfer layer during subsequent etching (e.g., in a conductor etching tool, e.g., Lam 2300® Kiyo®). After deposition, the EUV-patternable thin film is patterned by exposure to an EUV beam (usually under a relatively high vacuum). For EUV exposure, the metal-containing film can then be deposited in a chamber integrated with a lithography platform (e.g., a wafer stepper, e.g., the TWINSCAN NXE:3300B® platform provided by ASML of Veldhoven, Netherlands) and transferred under vacuum so as not to react prior to exposure. Considering that incident photons are, for example, H 2 O, O 2The strong light absorption of ambient gases and the fact that EUVL also requires a much-reduced pressure have facilitated its integration with lithography tools. In other embodiments, photosensitive metal film deposition and EUV exposure can be performed in the same chamber. We should also note that although this disclosure mainly refers to EUVL as a patterning technique, alternative embodiments can directly write patterns onto a blanket mask using a focused beam of electrons, ions, or neutral species, where these steps are also performed in a vacuum. If by-products condense on the reflective optics of the EUVL system, in-situ chamber cleaning can be used. Specifically, as discussed above, thin film regions are created by EUV patterning, and these regions have altered physical or chemical properties relative to the unexposed regions. For example, in the exposed regions, metal-carbon bond cleavage may occur by elimination of β-hydrides, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxides and cross-linked metal oxide functional groups via metal-oxygen bridges, which can be used to create chemical contrast as a negative resist or as a template for a hard mask. Overall, the greater the number of β-Hs in the alkyl group, the more sensitive the film. After exposure, the film can be baked to cause additional cross-linking of the metal oxide film. Without limiting the mechanism, function, or utility of the technology, for example, EUV exposure at doses of 2 10 mJ / cm 2 to 100 mJ / cm can relieve steric hindrance and provide collapse space for low-density films. In addition, the reactive metal-H bonds generated in the β-hydride elimination reaction can react with adjacent active groups such as hydroxyl groups in the film, resulting in further cross-linking and densification and creating a chemical contrast between the exposed and unexposed regions. The vacuum integration of the thin film deposition and lithography processes and equipment described herein provides for the deposition of EUV-sensitive metal thin films and subsequent direct patterning by direct EUV exposure in a vacuum environment to prevent their decomposition or degradation. EUVL is performed in a vacuum to avoid degradation of the incident 13.5 nm light flux due to light absorption by ambient gases. Advantages of the vacuum integrated hard mask process include: vacuum operation of the EUV system opens the possibility of using compounds sensitive to oxygen and moisture; vacuum integration of the deposition system and the EUV system in the equipment enables the use of these materials. Photodissociation of metal precursors results in non-linear reactions where the photodissociation is enhanced by increased adsorption of the metal film. Metals are better at thermalizing high energy secondary electrons than photoresists, thus improving contrast or LER. Direct use of the metal thin film as a mask or in combination with pattern magnification can make the film thinner and reduce the exposure time required. From the mask perspective, the metal thin film can make a better etch hard mask and reduce the thickness required. In addition, materials compatible with EUV vacuum and optics, organometallic precursors with appropriate metal deposition dose thresholds, and nucleation films with multiple photodissociation events to eliminate nucleation sites in a given space can be further developed and optimized according to the processes described herein. Further discussion of photoresist radiation operation can be found in U.S. Patent Application No. 14 / 610,038, filed January 30, 2015, which is incorporated herein by reference for all purposes. Post-exposure bake As described above, photolithography processes typically involve one or more bake steps to facilitate chemical reactions required to create chemical contrast between the exposed and unexposed regions of the photoresist. The bake can be performed after deposition of the imaging layer / before EUV exposure (e.g., post-application bake (PAB)) and / or before exposure to EUV (e.g., post-exposure bake (PEB)). In various embodiments, the bake strategy involves careful control of the bake environment, introduction of reactive gases, and / or careful control of the rate of increase of the bake temperature. In some embodiments, the PEB strategy discussed above can be used. This strategy is particularly useful for metal oxides based on EUV photoresist (PR). In a typical EUV lithography workflow, spin-coated metal oxide resist materials typically undergo two baking steps: one after the resist is applied to evaporate any residual solvent absorbed in the film, and another after EUV exposure. The second bake, commonly referred to as PEB, is designed for multiple purposes: 1) to drive the complete evaporation of organic fragments generated during EUV exposure; 2) to oxidize metal hydrides (another product of the β-H elimination reaction during EUV exposure) to metal hydroxides; 3) to promote crosslinking between adjacent -OH groups to form a crosslinked metal oxide network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature results in incomplete removal of organic fragments and insufficient crosslinking, leading to a reduced chemical contrast developed at a given dose. Too high a PEB temperature also has adverse effects, including severe oxidation of the unexposed regions and film shrinkage (in this case, the regions are removed by developing the patterned film to form a mask), as well as unwanted interdiffusion at the interface between the PR and the underlying layer, both of which result in a loss of chemical contrast and an increase in defect density. With bake temperature and bake time as the only tuning knobs, tunability and process window are very limited. As described above, carefully controlling the bake environment during PEB treatment and introducing reactive gas species as described herein provides an additional chemical tuning knob to fine-tune the crosslinking process. The ability to tune the crosslinking behavior kinetics in the PR material will provide a wider process window, which allows for further optimization of lithography performance by minimizing interdiffusion and other related defect formation mechanisms. In addition, the ramp rate of the bake temperature and pressure control (atmospheric pressure and below) are another useful process parameter that can be manipulated to fine-tune the crosslinking process. Further discussion of PAB and PEB operations can be found in U.S. Patent Application No. 62 / 970,020, filed on February 4, 2020, and Patent Application PCT / US20 / 70171, filed on June 24, 2020, which are incorporated herein by reference for all purposes. EUV Pattern development after exposure After EUV exposure and potential PEB, the selectivity between the exposed and unexposed regions of the imaging layer is exploited by dry development, wet development, or area-selective ALD. For example, a dry or wet development process can remove the unexposed regions leaving the exposed regions. The subsequent processing of the imaging layer after EUV exposure will depend on the substrate material and the desired features of the semiconductor device fabricated using the substrate. For example, features can be created on the substrate by a variety of lithography techniques, such as films that become selectively soluble in a dry or liquid developer in the exposed (positive) or unexposed (negative) regions defined by a patterned exposure tool. Dry development can improve performance (e.g., prevent line collapse due to surface tension in wet development) and increase throughput (e.g., by avoiding the need for wet development tracks). Other advantages of dry development and / or all-dry processing may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion problems, increasing EUV absorption to improve dose efficiency, and having no solubility-based limitations. EUV Dry photoresist development As described above, the exposed regions of the film are created by EUV patterning, which results in regions with altered physical or chemical properties relative to the unexposed regions. For example, in the exposed regions, metal-carbon bond cleavage may occur by elimination of β-hydrides, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxides and cross-linked metal oxide functional groups by metal-oxygen bridges, which can be used to create chemical contrast for use as a negative resist or as a template for a hard mask. Overall, the greater the number of β-Hs in the alkyl group, the more sensitive the film. After exposure, the film can be baked to cause additional cross-linking of the metal oxide film. The property differences between the exposed and unexposed regions can be used for subsequent processing, such as dissolving the unexposed regions or depositing materials on the exposed regions. For example, dry methods can be used to develop the pattern to form a mask containing metal oxide. Methods and apparatuses useful in these processes are described in Patent Application PCT / US2019 / 067540, filed December 19, 2019, Patent Application PCT / US20 / 39615, filed June 25, 2020, and U.S. Patent Application No. 62 / 912,330, filed October 8, 2019, the methods and apparatuses of which are incorporated herein by reference. In a thermal development process, a photopatterned metal-containing EUV resist is exposed to a developing chemical at an optimized temperature for the etch selectivity between the exposed and unexposed regions. Lower temperatures may increase the contrast of the etch selectivity, while higher temperatures may decrease the contrast of the etch selectivity. In some embodiments, the temperature can be between about -60°C and about 120°C, between about -20°C and about 60°C, or between about -20°C and about 20°C, such as about -10°C. The chamber pressure can be adjusted, where the chamber pressure may affect the etch selectivity between the exposed and unexposed regions during the development process. In some embodiments, the chamber pressure can be relatively low and without dilution, where the chamber pressure can be between about 0.1 mTorr and about 300 mTorr, between about 0.2 mTorr and about 100 mTorr, or between about 0.5 mTorr and about 50 mTorr. In some embodiments, the chamber pressure can be between about 20 mTorr and about 800 mTorr, or between about 20 mTorr and about 500 mTorr, such as about 300 mTorr. In some embodiments, the chamber pressure can be relatively high at high flow rates and with dilution, where the chamber pressure can be between about 100 Torr and about 760 Torr or between about 200 Torr and about 760 Torr. The reactant flow rate can be adjusted, where the reactant flow can affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the reactant flow can be between about 50 sccm and about 2000 sccm, between about 100 sccm and about 2000 sccm, or between about 100 sccm and about 1000 sccm, such as about 500 sccm. In the case of high flow rates, the reactant flow can be between about 1 L and about 10 L. The duration of the exposure can be adjusted in the thermal development process. The duration of the exposure may depend on factors such as how much resist needs to be removed, the developing chemical, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of the exposure can be between about 5 seconds and about 5 minutes, between about 10 seconds and about 3 minutes, or between about 10 seconds and about 1 minute. The thermal development process may expose the photopatterned metal-containing EUV resist to certain halide-containing chemicals in the gas phase or liquid phase. In some embodiments, the developing chemical includes a hydrogen halide, hydrogen and a halogen gas, boron trichloride, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a mixture thereof. The hydrogen halide can include, but is not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide can be HCl or HBr. The hydrogen and halogen gas can include, but is not limited to, those with F 2 、Cl 2 , Br 2 or I 2 mixed hydrogen gas (H 2 ). Boron trichloride (BCl 3 ) can be used in combination with any of the above hydrogen halides or hydrogen gas and halogen gas. The organic halide can include but is not limited to C x H y F z , C x H y Cl z , C x H y Br z and C x H y I z , where the values of x, y, and z are equal to or greater than 0. The acyl halide can include but is not limited to CH 3 COF, CH 3 COCl, CH 3 COBr, and CH 3 COI. The carbonyl halide can include but is not limited to COF 2 , COCl 2 , COBr 2 and COI 2 . The thionyl halide can include but is not limited to SOF 2 , SOCl 2 , SoBr 2 and SOI 2. In some embodiments, the halogen-containing chemical substance can flow with or without an inert gas / carrier gas (such as He, Ne, Ar, Xe, and N 2 ). The thermal development process can be completed without plasma. By applying a non-plasma thermal method, the productivity can be significantly increased because multiple wafers can be developed simultaneously in a low-cost thermal vacuum chamber / oven. However, in some embodiments, the thermal development process may be followed by exposure to plasma. Desorption, slag removal, smoothing, or other processing operations may occur after exposure to plasma. In the plasma development process, the photopatterned metal-containing EUV resist is exposed to a development chemical substance containing free radicals / ions of one or more gases. The processing chamber for processing the semiconductor substrate can be a plasma generation chamber or coupled to a plasma generation chamber remote from the processing chamber. In some embodiments, dry development can be achieved by remote plasma generation. The plasma generation chamber can be an inductively coupled plasma (ICP) reactor, a transformer-coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor, and those devices and techniques known in the art can be employed. An electromagnetic field acts on one or more gases to generate plasma in the plasma generation chamber. Ions and / or free radicals from the remote plasma can interact with the photopatterned metal-containing EUV resist. In some embodiments, a vacuum pipeline is coupled to the processing chamber for pressure control, and the development chemical substance pipeline can be coupled to the plasma generation chamber to deliver one or more gases into the plasma generation chamber. The processing chamber may include one or more heaters for temperature control, such as a heater coupled to the substrate support in the processing chamber for substrate temperature control. In some embodiments, the interior of the processing chamber can be coated with an anti-corrosion film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1M. Such materials can be used for the heat treatment of the present disclosure without the risk of being removed by plasma exposure. In a plasma development process, a photo-patterned metal-containing EUV resist is exposed to a remote plasma under conditions optimized for etch selectivity between exposed and unexposed regions. The conditions can be optimized to produce a mild plasma, where the mild plasma can be characterized by high pressure and low power. The chamber pressure can be adjusted, where the chamber pressure can affect the etch selectivity between exposed and unexposed regions in the development process. In some embodiments, the chamber pressure can be equal to or greater than about 5 mTorr, or equal to or greater than about 15 mTorr. In some embodiments, the chamber pressure can be relatively high at high flow rates and accompanied by dilution, where the chamber pressure can be between about 100 Torr and about 760 Torr or between about 200 Torr and about 760 Torr. The RF power level can be adjusted, where the RF power can affect etch selectivity, roughness, slag removal, and other development characteristics. In some embodiments, the RF power can be equal to or less than about 1000 W, equal to or less than about 800 W, or equal to or less than about 500 W. The temperature can be adjusted, where the temperature can affect various aspects of development such as etch selectivity. In some embodiments, the temperature can be between about -60 °C and about 300 °C, between about 0 °C and about 300 °C, or between about 30 °C and about 120 °C. The gas flow rate can be adjusted, where the gas flow rate can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the gas flow rate is between about 50 sccm and about 2000 sccm, between about 100 sccm and about 2000 sccm, or between about 200 sccm and about 1000 sccm, such as about 500 sccm. The exposure duration can be adjusted in the plasma development process. The exposure duration may depend on factors such as how much resist needs to be removed, the development chemistry, the amount of cross-linking in the resist, and the composition and properties of the resist. In some embodiments, the exposure duration can be between about 1 second and about 50 minutes, between about 3 seconds and about 20 minutes, or between about 10 seconds and about 6 minutes. The plasma development process may expose the photo-patterned metal-containing EUV resist to radicals of certain halide-containing gases. In some embodiments, the radicals are generated from a remote plasma source. For example, plasma development can expose the photo-patterned metal-containing EUV resist to radicals of hydrogen gas and a halide gas generated from a remote plasma source. In some embodiments, the halide-containing gas includes a hydrogen halide, hydrogen gas and a halogen gas, boron trichloride, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a mixture thereof. The hydrogen halide can include but is not limited to hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide can be HCl or HBr. The hydrogen gas and the halogen gas can include but are not limited to those with fluorine gas (F 2), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 ), mixed with hydrogen gas (H 2 ). Organic halides may include but are not limited to C x H y F z , C x H y Cl z , C x H y Br z and C x H y I z , where the values of x, y, and z are equal to or greater than 0. Acyl halides may include but are not limited to CH 3 COF, CH 3 COCl, CH 3 COBr, and CH 3 COI. Carbonyl halides may include but are not limited to COF 2 , COCl 2 , COBr 2 and COI 2 . Sulfuryl halides may include but are not limited to SOF 2 , SOCl 2 , SoBr 2 and SOI 2. In some embodiments, the halide-containing gas may flow with or without an inert gas / carrier gas (such as He, Ne, Ar, Xe, and N 2 ). Dross removal / Smoothing / Solidification In some cases, there may be dross (the material in the unexposed portion (e.g., the area of the EUV resist after development) is likely to have a high metal concentration, such as clusters) or roughness (the same composition, but on the sidewalls of the etched features in the developed pattern). These two challenges can be largely attributed to randomness and the non-optimal Gaussian distribution of light, resulting in partial or complete exposure of the material in areas where the resist should remain unexposed, and vice versa. The process conditions for dross removal and smoothing operations can be controlled during or after development. In some embodiments, the reaction gas flow can be between about 50 sccm and about 1000 sccm, or between about 100 sccm and about 500 sccm, such as about 500 sccm He. In some embodiments, the temperature can be between about -60°C and about 120°C, between about -20°C and about 60°C, or between about 20°C and about 40°C, such as about 20°C. In some embodiments, the chamber pressure can be between about 1 mTorr and about 300 mTorr, between about 5 mTorr and about 100 mTorr, between about 5 mTorr and about 20 mTorr, such as about 10 mTorr. In the case of high ion energy, the plasma power may be relatively low. In some embodiments, the plasma power can be between about 50 W and about 1000 W, between about 100 W and about 500 W, or between about 100 W and about 300 W, such as about 300 W. In some embodiments, the wafer bias is between about 10 V and about 500 V, between about 50 V and about 300 V, such as about 200 V. A high RF frequency can be used to generate the plasma. In some embodiments, the RF frequency is 13.56 MHz. The duration of exposure to the inert gas plasma can be relatively short to avoid excessive exposure to UV radiation during plasma exposure. In some embodiments, the duration of exposure is between about 0.5 seconds and about 5 seconds, between about 1 second and about 3 seconds, such as about 2 seconds. He deslagging and cleaning of unexposed resist residues can have the added benefit of curing the exposed resist to harden it, thereby enhancing its hard mask function in subsequent operations to etch the underlying substrate. This resist hardening is achieved by exposing the resist exposed to EUV to UV radiation generated by He plasma, which can continue after deslagging / smoothing is completed and the bias is turned off. If deslagging / smoothing is not needed or not performed, He plasma curing can be alternatively performed. In some embodiments, He plasma deslagging / smoothing can be carried out in conjunction with a dry development cycle as described above to obtain enhanced results. In this way, most of the organic components in the unexposed areas of the pattern, such as the pattern, are removed by dry development. Next, a short He plasma operation can remove some of the concentrated metal on the surface, thereby opening a channel to the remaining underlying organic material, which can then be removed in subsequent dry development operations / cycles. Another cycle of He plasma can be used to remove any remaining metal to leave a clean and smooth feature surface. The cycles can be continued until all or substantially all of the scum and rough residues are removed, leaving a clean and smooth feature surface. In some embodiments, He deslagging and smoothing can be used in conjunction with a wet development process. Wet development has very high selectivity and has shown significant on / off behavior, resulting in the inability of the wet development process to remove areas that are partially or completely misexposed. After the wet development process, residual materials remain, resulting in scum and high line edge and width roughness. Interestingly, due to the tunability of the dry development process, where the etching rate and selectivity can be adjusted based on multiple knobs (such as time, temperature, pressure, gas / flow rate), it can be further applied to remove scum and smooth metal-containing photoresist lines by removing these partially exposed residues. Equipment Current EUV resist coating techniques typically use spin-on resist applied in the atmosphere. This technique does not allow for atmosphere control or influence and only allows a single chemical mixture to be applied to the entire film stack. The chamber shown in FIGS. 4 and 6 below contains many components to enable dry deposition of EUV resist. The chamber includes a four-zone electrostatic chuck for controlling the temperature of the wafer substrate within + / -0.5 C, and a four-precursor vapor delivery system connected to a dual-chamber gas distribution plate. In various embodiments, the chamber, gas distribution plate, and associated delivery pipes are heated to prevent any precursor condensation. In various embodiments, a gas box is also incorporated to deliver the required gas components to the chamber. In various embodiments, the ESC is RF-powered to enhance the chamber cleaning ability. In various embodiments, the gate valve and all internal chamber components are heated to prevent or minimize deposition outside the wafer surface. In various embodiments, a gas exclusion ring is used around the periphery of the wafer to prevent deposition on the backside and top edge chamfers. One of the innovations of these designs is to couple different technical elements into a chamber to achieve the desired deposition performance. Wafer temperature uniformity, chemical composition, through the gradual distribution of the gas distribution plate, deposition exclusion ring, and heated chamber surfaces work together in various embodiments to achieve excellent thin film characteristics. In some embodiments, a dual plenum fractal (DPF) showerhead can be used during the operations described herein. The dual plenum fractal showerhead discussed herein can be configured to uniformly distribute a process gas to a processing volume above a semiconductor wafer located in a semiconductor processing chamber. This may help to promote more uniform wafer processing, as the entire wafer surface is generally simultaneously exposed to such process gas, rather than, for example, being exposed to process gas that first exits from the center of the showerhead for a period of time before exiting around the showerhead. More details of the DPF showerhead are described in U.S. Patent Application No. 62 / 914,616, entitled DUAL PLENUM SHOWERHEAD, the disclosure of which is incorporated herein by reference at least as it pertains to the configuration of the processing chamber. FIG. 4 depicts a schematic diagram of an embodiment of a processing station 400 having a processing chamber body 402 for maintaining a low pressure environment suitable for implementing the dry development, cleaning, secondary processing, slag removal, and planarization embodiments described herein. A plurality of processing stations 400 can be included in a common low pressure processing tool environment. For example, FIG. 5 depicts an embodiment of a multi-station processing tool 500, such as the VECTOR® processing tool available from Lam Research Corporation of Fremont, California. In some embodiments, one or more hardware parameters of those processing stations 400 discussed in detail below can be programmatically adjusted by one or more computer controllers. The processing station can be configured as a module in a cluster tool. FIG. 7 depicts a semiconductor processing cluster tool architecture suitable for implementing the embodiments described herein with vacuum integrated deposition and patterning modules. Such a cluster processing tool architecture can include resist deposition, resist exposure (EUV scanner), resist dry development, and etching modules, as described above and further described below with reference to FIGS. 6 and 7. In some embodiments, certain processing functions can be performed continuously in the same module, such as dry development and etching. Embodiments of the present disclosure are directed to methods and apparatuses for receiving a wafer into a dry development / etch chamber after optical patterning in an EUV scanner, the wafer comprising a optically patterned EUV resist thin film layer disposed on a layer or layer stack to be etched; dry developing the optically patterned EUV resist thin film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein. Referring back to FIG. 4, the processing station 400 is in fluid communication with a reactant delivery system 401 to deliver a processing gas to a distribution showerhead 406. The reactant delivery system 401 optionally includes a mixing vessel 404 for mixing and / or conditioning the processing gas delivered to the showerhead 406. One or more mixing vessel inlet valves 420 can control the processing gas introduced into the mixing vessel 404. In the case of plasma exposure, plasma can also be delivered to the showerhead 406 or can be generated in the processing station 400. As described above, in at least some embodiments, non-plasma thermal exposure is advantageous. FIG. 4 includes an optional vaporization point 403 for vaporizing a liquid reactant to be supplied to the mixing vessel 404. In some embodiments, a liquid flow controller (LFC) can be provided upstream of the vaporization point 403 to control the mass flow rate of the liquid used for vaporization and delivery to the processing station 400. For example, the LFC can include a thermal mass flow meter (MFM) downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller electrically connected to the MFM. The showerhead 406 distributes the processing gas towards the substrate 412. In the embodiment shown in FIG. 4, the substrate 412 is located below the showerhead 406 and is shown as being disposed on a pedestal 408. The showerhead 406 can have any suitable shape and can have any suitable number and configuration of ports for distributing the processing gas to the substrate 412. In some embodiments, the pedestal 408 can be raised or lowered to expose the substrate 412 to the volume between the substrate 412 and the showerhead 406. It will be appreciated that in some embodiments, the pedestal height can be programmatically adjusted by a suitable computer controller. In some embodiments, the pedestal 408 can be temperature controlled by a heater 410. In some embodiments, during non-plasma thermal exposure of the photoresist to dry development chemicals (such as HBr, HCl, or BCl 3During this period, the susceptor 408 can be heated to a temperature greater than 0 °C and up to 300 °C or higher, such as 50 to 120 °C, such as about 65 to 80 °C, as described in the disclosed embodiments. Further, in some embodiments, pressure control of the processing station 400 can be provided by the butterfly valve 418. As shown in the embodiment of FIG. 4, the butterfly valve 418 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the processing station 400 can also be adjusted by changing the flow rate of one or more gases introduced into the processing station 400. In some embodiments, the position of the showerhead 406 can be adjusted relative to the susceptor 408 to change the volume between the substrate 412 and the showerhead 406. Further, it will be appreciated that the vertical position of the susceptor 408 and / or the showerhead 406 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the susceptor 408 can include a rotating shaft for rotating the orientation of the substrate 412. It will be appreciated that in some embodiments, one or more such exemplary adjustments can be programmatically performed by one or more suitable computer controllers. In the case of using plasma, such as in mild plasma-based dry etching embodiments and / or in etching operations performed in the same chamber, the showerhead 406 and the susceptor 408 are electrically connected to a radio frequency (RF) power source 414 and a matching network 416 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the processing station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 414 and the matching network 416 can operate at any suitable power to form a plasma of radical species having a desired composition. Exemplary power ranges are up to about 500 W. In some embodiments, instructions for the controller can be provided via input / output control (IOC) sequencing instructions. In one example, instructions setting the conditions of a processing stage can be included in the corresponding recipe stage of a processing recipe. In some cases, the processing recipe stages can be arranged in sequence such that all instructions for a processing stage are executed simultaneously with that processing stage. In some embodiments, instructions setting one or more reactor parameters can be included in a recipe stage. For example, a recipe stage can include instructions for setting the flow rate of a dry development chemical reaction gas (such as HBr or HCl) and a time delay instruction for the recipe stage. In some embodiments, the controller can include any of the features described below with respect to the system controller 550 of FIG. 5. As described above, a multi-station processing tool may include one or more processing stations. FIG. 5 shows a schematic diagram of an embodiment of a multi-station processing tool 500 having an inbound load lock 502 and an outbound load lock 504, where one or both of the inbound load lock 502 and the outbound load lock 504 may include a remote plasma source. A robot 506 under atmospheric pressure is configured to transfer wafers from a cassette loaded through a cassette 508 through an atmospheric port 510 into the inbound load lock 502. The robot 506 places the wafer on a pedestal 512 in the inbound load lock 502, closes the atmospheric port 510, and evacuates the load lock. Where the inbound load lock 502 includes a remote plasma source, the wafer can be exposed to remote plasma processing in the inbound load lock 502 to process its silicon nitride surface before being introduced into the processing chamber 514. In addition, the wafer can also be heated in the inbound load lock 502 to, for example, remove moisture and adsorbed gases. Then, the chamber transfer port 516 leading to the processing chamber 514 is opened, and another robot (not shown) places the wafer into a reactor on a pedestal of the first station shown in the reactor for processing. Although the embodiment depicted in FIG. 5 includes a load lock, it should be understood that in some embodiments, wafers can be provided to directly enter the processing station. The depicted processing chamber 514 includes four processing stations, numbered from 1 to 4 in the embodiment shown in FIG. 5. Each station has a heated pedestal (shown as 518 in station 1) and a gas pipeline inlet. It will be understood that in some embodiments, each processing station can have different or multiple purposes. For example, in some embodiments, the processing station can switch between dry development and etching processing modes. Additionally or alternatively, in some embodiments, the processing station can include one or more pairs of dry development and etching processing stations. Although the depicted processing chamber 514 includes four stations, it should be understood that a processing chamber according to the present disclosure can have any suitable number of stations. For example, in some embodiments, the processing chamber can have five or more stations, while in other embodiments, the processing chamber can have three or fewer stations. FIG. 5 depicts an embodiment of a wafer processing system 590 for transferring wafers within the processing chamber 514. In some embodiments, the wafer processing system 590 can transfer wafers between various processing stations and / or between the processing station and the load lock. It will be understood that any suitable wafer processing system can be employed. Non-limiting examples include wafer conveyors and wafer processing robots. FIG. 5 also depicts an embodiment of a system controller 550 for controlling the processing conditions and hardware state of the processing tool 500. The system controller 550 can include one or more memory devices 556, one or more mass storage devices 554, and one or more processors 552. The processor 552 can include a CPU or computer, analog and / or digital input / output connectors, a stepper motor controller panel, etc. In some embodiments, system controller 550 controls all activities of processing tool 500. System controller 550 executes system control software 558, which is stored in mass storage device 554, loaded into memory device 556, and executed in processor 552. Alternatively, the control logic can be hard-coded into controller 550. Application-specific integrated circuits, programmable logic devices (such as field-programmable gate arrays or FPGAs), etc. can be used for such purposes. In the following discussion, wherever "software" or "encoding" is used, functionally equivalent hard-coded logic can be used instead. System control software 558 can include instructions for controlling time, gas mixture, gas flow rate, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck, and / or susceptor position, and other parameters for a particular process performed by processing tool 500. System control software 558 can be configured in any suitable manner. For example, numerous processing tool component subroutines or control objects can be written to control the operation of processing tool components for performing individual processing tool processes. System control software 558 can be encoded in any suitable computer-readable programming language. In some embodiments, system control software 558 can include input / output control (IOC) sequencing instructions for controlling the aforementioned parameters. In some embodiments, other computer software and / or programs stored in mass storage device 554 and / or memory device 556 associated with system controller 550 can be employed. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs. The substrate positioning program can include code for processing tool components for loading a substrate onto pedestal 518 and controlling the spacing between the substrate and other parts of processing tool 500. The process gas control program can include encoding for controlling the composition (such as HBr or HCl as described herein) and flow rate of multiple gases, and optionally for flowing the gases into one or more processing stations prior to deposition to stabilize the pressure in the processing stations. The pressure control program can include encoding for controlling the pressure in a processing station by adjusting, for example, a throttle valve in the exhaust system of the processing station, the gas flow rate into the processing station, etc. The heater control program can include encoding for controlling the current flowing to a heating unit (for heating the substrate). Alternatively, the heater control program can control the delivery of a heat transfer gas (such as helium) to the substrate. According to embodiments herein, the plasma control program can include encoding for setting the RF power level applied to a processing electrode in one or more processing stations. According to an embodiment herein, the pressure control program may include encoding for maintaining the pressure in the reaction chamber. In some embodiments, there may be a user interface associated with the system controller 550. The user interface may include a display, a graphical software display of the device and / or processing conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc. In some embodiments, the parameters adjusted by the system controller 550 may relate to processing conditions. Non-limiting examples include processing gas composition and flow rate, temperature, pressure, plasma conditions (such as RF bias power level), etc. These parameters can be provided to the user in the form of a recipe by inputting through the user interface. Signals for monitoring the process can be provided by analog and / or digital input connectors of the system controller 550 from a number of process tool sensors. Signals for controlling the process can be output on the analog and digital output connectors of the process tool 500. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain processing conditions. The system controller 550 can provide program instructions for implementing the deposition process described above. The program instructions can control various processing parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions can control the parameters to operate the dry development and / or etching process according to the various embodiments described herein. The system controller 550 generally includes one or more memory devices and one or more processors, which are configured to execute instructions such that the device performs according to the methods of the disclosed embodiments. A machine-readable medium containing instructions for controlling the processing operations according to the disclosed embodiments can be coupled to the system controller 550. In some embodiments, system controller 550 is part of a system, which may be part of the above examples. Such systems may include semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems can be integrated with electronic equipment to control operations before, during, and after the processing of semiconductor wafers or substrates. The electronic equipment may be referred to as a "controller", which can control each element or sub-component of one or more systems. Depending on the processing conditions and / or the type of system, controller 550 can be programmed to control any of the processing disclosed herein, including the delivery of processing gases, temperature settings (such as heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with a specific system. Broadly speaking, controller 550 can be defined as an electronic device having multiple integrated circuits, logic, memory, and / or software, which receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers executing program instructions (such as software). The program instructions may be instructions communicated with the controller in the form of numerous individual settings (or program files), which define the operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more of the following: layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer. In some embodiments, the system controller 550 may be part of or coupled to the computer, and the computer is integrated into the system, coupled to the system or networked with the system, or a combination of the foregoing. For example, the controller may be in the “cloud” or may be all or part of the fab computer host system, thus allowing remote access to wafer processing. The computer can initiate remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, check trends or performance indicators from multiple manufacturing operations, change the parameters of the current processing, set the processing steps to continue the current processing, or start a new processing. In some examples, a remote computer (e.g., a server) may provide processing recipes to the system via a network that may contain a LAN or an Internet network. The remote computer may contain a user interface that enables input or programming of parameters and / or settings, which are next transmitted from the remote computer to the system. In some examples, the system controller 550 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. We shall understand that the parameters are for the type of processing to be performed as well as the type of tool with which the controller is used to connect or control. Thus as described above, system controllers 550 may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common purpose (e.g., processing and control described herein). Examples of distributed controllers for such purposes are one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer) that are combined to control processing in the chamber. Non-limitingly, a system example may contain a plasma etching chamber or module, a deposition chamber or module, a rotary cleaning chamber or module, a metal plating chamber or module, a cleaning chamber or module, a beveled edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, trajectory chambers or modules, EUV microfilming chambers (scanners) or modules, dry development chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or production of semiconductor wafers. As described above, depending on one or more processing steps to be performed by the tool, the system controller 550 may communicate with one or more of the following: other tool circuits or modules, other tool parts, cluster tools, other tool interfaces, adjacent tools, adjacent tools, tools located throughout the plant, a master computer, another controller, or tools used in the semiconductor manufacturing plant to transport wafer containers to and from tool locations and / or loading ports. An inductively coupled plasma (ICP) reactor is now described, which in certain embodiments may be applicable to etching operations suitable for implementing certain embodiments. Although an ICP reactor is described herein, in some embodiments, it should be understood that a capacitively coupled plasma reactor may also be used. FIG. 6 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus 600 according to certain embodiments herein, which is suitable for implementing certain embodiments or aspects of embodiments, such as dry development and / or etching, an example of which is the Kiyo® reactor manufactured by Lam Research Corporation of Fremont, California. In other embodiments, other tools or tool types having the functions of performing dry development and / or etching processes described herein may also be implemented. The inductively coupled plasma etching apparatus 600 includes an integral processing chamber, which is structurally defined by a chamber wall 601 and a window 611. The chamber wall 601 may be made of stainless steel or aluminum. The window 611 may be made of quartz or other dielectric materials. An optional internal plasma grid 650 divides the integral processing chamber into an upper sub-chamber 602 and a lower sub-chamber 603. In most embodiments, the plasma grid 650 may be removed to utilize the chamber space formed by the sub-chambers 602 and 603. A chuck 617 is positioned near the bottom inner surface within the lower sub-chamber 603. The chuck 617 is configured to receive and support a semiconductor wafer 619 on which etching and deposition processes are performed. The chuck 617 may be an electrostatic chuck for supporting the wafer 619 when the wafer is present. In some embodiments, an edge ring (not shown) surrounds the chuck 617, and when a wafer is present on the chuck 617, the upper surface of the edge ring is substantially flush with the top surface of the wafer 619. The chuck 617 also includes an electrostatic electrode for clamping and unclamping the wafer 619. A filter and a direct current (DC) clamping power supply (not shown) may be provided therefor. Other control systems for lifting the wafer 619 off the chuck 617 may also be provided. The chuck 617 may be charged using an RF power supply 623. The RF power supply 623 is connected to a matching circuit 621 by a connector 627. The matching circuit 621 is connected to the chuck 617 by a connector 625. In this way, the RF power supply 623 is connected to the chuck 617. In various embodiments, the bias power of the electrostatic chuck may be set at about 50 V or may be set at different bias powers depending on the process performed according to the disclosed embodiments. For example, the bias power may be set between about 20 Vb and 100 V, or between about 30 V and 150 V. The component for generating plasma includes a coil 633 located above the window 611. In some embodiments, the coil is not used in the disclosed embodiments. The coil 633 is made of a conductive material and includes at least one complete turn. The exemplary coil 633 shown in FIG. 6 includes three turns. The cross-section of the coil 633 is shown by symbols, where the coil with an "X" symbol rotates and extends into the page, and the coil with a "●" rotates and extends out of the page. The component for generating plasma also includes an RF power source 641 configured to supply RF power to the coil 633. Generally, the RF power source 641 is connected to a matching circuit 639 through a connector 645. The matching circuit 639 is connected to the coil 633 through a connector 643. In this way, the RF power source 641 is connected to the coil 633. An optional Faraday shield 649 is located between the coil 633 and the window 611. The Faraday shield 649 is spaced apart relative to the coil 633. In some embodiments, the Faraday shield 649 is disposed directly above the window 611. In some embodiments, the Faraday shield 649 is disposed between the window 611 and the chuck 617. In some embodiments, the Faraday shield 649 is not spaced apart relative to the coil 633. For example, the Faraday shield 649 is located directly below the window 611 without a gap. The coil 633, the Faraday shield 649, and each of the windows 611 are configured to be substantially parallel to each other. The Faraday shield 649 can prevent metal or other substances from depositing on the window 611 of the processing chamber. The processing gas can be supplied through one or more main gas flow inlets 660 located in the upper sub-chamber 602 and / or through one or more side gas flow inlets 670. Similarly, although not explicitly shown, similar gas flow inlets can be used to supply the processing gas to the inductively coupled plasma processing chamber. For example, a one-stage or two-stage mechanical dry pump and / or a turbo molecular pump 640 can be used to evacuate the processing gas from the processing chamber and maintain the pressure inside the processing chamber. For example, the vacuum pump can be used to evacuate the lower sub-chamber 603 during the ALD purge operation. A valve control circuit can be used to fluidly connect the vacuum pump to the processing chamber to selectively control the vacuum environment application provided by the vacuum pump. This can be achieved by employing a closed-loop flow restriction device during the operation of the plasma processing, such as a throttle valve (not shown), a pendulum valve (not shown). Similarly, a vacuum pump and a valve-controlled fluid connection connected to the inductively coupled plasma processing chamber can also be employed. During operation of the apparatus 600, one or more processing gases may be supplied through gas flow inlets 660 and / or 670. In certain embodiments, the processing gas may be supplied only through the main gas flow inlet 660 or only through the side gas flow inlet 670. In some cases, the gas flow inlets shown in the figures may be replaced with more complex gas flow inlets, such as one or more showerheads. The Faraday shield 649 and / or the optional grid 650 may include internal channels and holes to allow the delivery of the processing gas into the processing chamber. One or both of the Faraday shield 649 and / or the optional grid 650 may be used as a showerhead for delivering the processing gas. In some embodiments, a liquid vaporization and delivery system may be located upstream of the processing chamber such that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the processing chamber through the gas flow inlets 660 and / or 670. RF power is supplied from the RF power source 641 to the coil 633 to cause an RF current to flow through the coil 633. The RF current flowing through the coil 633 generates an electromagnetic field in the vicinity of the coil 633. The electromagnetic field then generates an induced current in the upper sub-chamber 602. The physical and chemical interactions of the generated ions and radicals with the wafer 619 selectively etch features on the wafer 619 and selectively deposit layers on the wafer 619. If the plasma grid 650 is used such that both the upper sub-chamber 602 and the lower sub-chamber 603 are present, the induced current acts on the gas present in the upper sub-chamber 602 to generate an electron-ion plasma in the upper sub-chamber 602. The optional internal plasma grid 650 limits the number of hot electrons in the lower sub-chamber 603. In certain embodiments, the design and operation of this apparatus are such that the plasma present in the lower sub-chamber 603 is an ion-ion plasma. Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, although the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and / or deposition by-products may be removed from the lower sub-chamber 603 through the port 622. The chuck 617 disclosed herein may be operated at elevated temperatures between about 10°C and about 250°C. The temperature will depend on the processing operation and the particular recipe. When installed in a cleanroom or manufacturing facility, the apparatus 600 may be coupled to a facility (not shown). The facility includes piping that provides processing gas, vacuum, temperature control, and environmental particle control. When installed in a target manufacturing facility, these facilities are coupled to the apparatus 600. In addition, the apparatus 600 may be coupled to a transfer chamber that allows a robot to transfer semiconductor wafers in and out of the apparatus 600 using typical automation. In some embodiments, the system controller 630 (which may include one or more physical or logical controllers) controls some or all of the operations of the processing chamber. The system controller 630 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 600 includes a switching system for controlling flow rate and duration during execution of the disclosed embodiments. In some embodiments, the apparatus 600 may have a switching time of up to about 600 ms or up to about 750 ms. The switching time may depend on the flowing chemical, the selected recipe, the reactor configuration, and other factors. In some embodiments, the system controller 630 is part of a system, which may be part of the above examples. Such a system may include semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems may be integrated with an electronic device to control operations before, during, and after the processing of a semiconductor wafer or substrate. The electronic device may be integrated into the system controller 630, which may control each component or sub-component of one or more systems. Depending on the processing parameters and / or system type, the system controller may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of the tool and other transfer tools, and / or load locks connected to or interfaced with a particular system. Broadly speaking, the system controller 630 can be defined as an electronic device having a number of integrated circuits, logic, memory, and / or software, which receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers executing program instructions (e.g., software). The program instructions may be instructions passed to the controller in the form of a number of individual settings (or program files), which define the operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication or removal of one or more of the following: layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer. In some embodiments, system controller 630 can be part of or coupled to a computer, which is integrated with, coupled to, or networked with the system, or a combination of the foregoing. For example, the controller can be in the "cloud" or can be all or part of a fab computer host system, which can allow for remote access to wafer processing. The computer can initiate remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, check trends or performance metrics from multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system via a network, which can include a local area network or the Internet. The remote computer can include a user interface that enables input or programming of parameters and / or settings, and then transmits the parameters and / or settings from the remote computer to the system. In some examples, system controller 630 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of tool that the controller interfaces with or controls. Thus, as described above, system controller 630 can be distributed, for example, through one or more discrete controllers that are networked together and work towards a common purpose (e.g., the processes and controls described herein). Examples of distributed controllers for such purposes are one or more integrated circuits in a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), and these integrated circuits work together to control the process in the chamber. System examples can include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a cleaning chamber or module, an angled edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an extreme ultraviolet (EUV) lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that can be associated with or used in semiconductor wafer manufacturing and / or production, without any limitation. As described above, depending on the one or more processing steps to be performed by the tool, the controller can communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools throughout the factory, a host computer, another controller, or a tool for material transport that can shuttle a wafer container between tool locations and / or load ports in a semiconductor manufacturing facility. EUVL patterning can be performed using any suitable tool, commonly referred to as a scanner, such as the TWINSCAN NXE:3300B® platform provided by ASML of Veldhoven, Netherlands. The EUVL patterning tool can be a stand-alone device that moves substrates into and out of the device for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool can be a module on a larger multi-component tool. FIG. 7 depicts a semiconductor processing cluster tool architecture suitable for implementing the processes described herein, having vacuum integrated deposition, EUV patterning, and dry development / etching modules interfaced with a vacuum transfer module. Although the process can be performed without such vacuum integration equipment, such equipment may be advantageous in some embodiments. FIG. 7 depicts a semiconductor processing cluster tool architecture suitable for implementing the processes described herein, having vacuum integrated deposition and patterning modules interfaced with a vacuum transfer module. The configuration of the transfer module for "transferring" wafers between multiple storage facilities and processing modules can be referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum integrated. Other modules, such as those for etching, can also be included in the cluster. The vacuum transfer module (VTM) 738 is interfaced with four processing modules 720a - 720d, which can be individually optimized to perform a number of manufacturing processes. For example, the processing modules 720a - 720d can be installed to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processes. For example, module 720a can be an ALD reactor that can operate in non-plasma thermal atomic layer deposition as described herein, such as the VECTOR® processing tool available from Lam Research Corporation of Fremont, California. And module 720b can be a PECVD tool, such as a Lam Vector®. It should be understood that the figure is not necessarily drawn to scale. The gas locks 742 and 746, also referred to as load locks or transfer modules, are interfaced with the VTM 738 and the patterning module 740. For example, as described above, a suitable patterning module can be the TWINSCAN NXE:3300B® platform provided by ASML of Veldhoven, Netherlands. Such a tool architecture allows workpieces, such as semiconductor substrates or wafers, to be transferred under vacuum to prevent reactions from occurring prior to exposure. Considering the strong light absorption of incident photons by ambient gases (such as H 2 O, O 2 etc.), EUVL also requires a much lower pressure, and this fact promotes the integration of the deposition module and the lithography tool. As described above, this integration architecture is merely one possible example of a tool for implementing the described process. More traditional stand-alone EUVL scanners and deposition reactors (such as Lam Vector tools) can also be used to implement the process. These reactors can be stand-alone or integrated as modules with other tools (such as etching, stripping, etc.) in a cluster architecture (such as Lam Kiyo or Gamma tools), as described with reference to FIG. 7, but without an integrated patterning module. The air lock 742 can be an "outward" load lock, which means that the substrate is transferred from the VTM 738 serving the deposition module 720a to the patterning module 740, and the air lock 746 can be an "inward" load lock, which means that the substrate is transferred from the patterning module 740 back to the VTM 738. The inward load lock 746 can also provide an interface to the outside of the tool for the entry and exit of the substrate. Each processing module has a facet that interfaces the module to the VTM 738. For example, the deposition processing module 720a has a facet 736. Within each facet, sensors (such as the sensors 1-18 shown) are used to detect the passage of the wafer 726 when moving between the various stations. The patterning module 740 and the air locks 742 and 746 can be similarly equipped with additional facets and sensors (not shown). The main VTM robot 722 transfers the wafer 726 between the air locks 742 and 746 and the modules. In one embodiment, the robot 722 has one arm, and in another embodiment, the robot 722 has two arms, each arm having an end effector 724 for picking up the wafer (such as the wafer 726) for transportation. The front-end robot 744 is used to transfer the wafer 726 from the outward air lock 742 into the patterning module 740 and from the patterning module 740 into the inward air lock 746. The front-end robot 744 can also transfer the wafer 726 between the inward load lock and the outside of the tool to access and remove the substrate. Since the inward air lock module 746 has the ability to match the environment between the atmosphere and the vacuum, the wafer 726 can move between the two pressure environments without being damaged. We should note that EUVL tools typically operate at a higher vacuum than deposition tools. If this is the case, we want to increase the vacuum environment of the substrate during the transfer between the deposition and EUVL tools to allow the substrate to outgas before entering the patterning tool. The outward air lock 742 can provide this function by holding the transferred wafer at a lower pressure (not higher than the pressure in the patterning module 740) for a period of time and exhausting any waste gas, so that the optics of the patterning tool 740 are not contaminated by the waste gas of the substrate. A suitable pressure for the air lock for exhausting waste gas outward does not exceed 1E-8 Torr. FIG. 8 shows an alternative semiconductor process cluster tool architecture of FIG. 7, which does not have a patterning module 740. Instead, the front-end robot 832 in the atmospheric transfer module (ATM) 840 is used to transfer the wafer 826 from the cassette or front-opening unified pod (FOUP) 834 in the load port module (LPM) 842 to the pod 830. The module center 828 within the processing module 820 can be a location for placing the wafer 826. The aligner 844 in the ATM 840 is used to align the wafer. In an exemplary processing method, the wafer is placed in one of the FOUPs 834 of the LPM 842. The front-end robot 832 transfers the wafer from the FOUP 834 to the aligner 844, thus properly centering the wafer 826 before it is etched or processed. After alignment, the wafer is moved by the front-end robot 832 into the pod 830. Since the pod has the ability to match the environments between the ATM and the VTM, the wafer 826 can move between the two pressure environments without being damaged. The wafer 826 is moved by the robot 822 from the pod module 830 through the VTM 838 into one of the processing modules 820a - 820d. To achieve this wafer movement, the robot 822 uses the end effector 824 on each of its arms. Once the wafer 826 has been processed, it is moved by the robot 822 from the processing modules 820a - 820d to the pod module 830. From here, the wafer 826 can be moved by the front-end robot 832 to one of the FOUPs 834 or to the aligner 844. As described above, one or more processing stations may be included in a multi-station processing tool. FIG. 9 shows a schematic diagram of an embodiment of a multi-station processing tool 900 having an inbound load lock 902 and an outbound load lock 904. One or both of the inbound load lock 902 and the outbound load lock 904 may include a remote plasma source. A robot 906 under atmospheric pressure is configured to transfer a substrate or wafer from a cassette loaded through a cassette 908 through an atmospheric port into the inbound load lock 902. The robot 906 places the substrate on a pedestal 912 in the inbound load lock 902, closes the atmospheric port, and evacuates the load lock. Where the inbound load lock 902 includes a remote plasma source, the substrate may be exposed to remote plasma processing in the inbound load lock before being introduced into the processing chambers 914A-C. In addition, the substrate may also be heated in the inbound load lock 902 to, for example, remove moisture and adsorbed gases. Then, the chamber transfer port 916 leading to one of the processing chambers 914A-C is opened, and another robot (not shown) places the substrate in a reactor on a pedestal of the first station shown in the reactor for processing. Although the embodiment depicted in FIG. 9 includes a load lock, it should be understood that in some embodiments, the substrate may be provided to directly enter the processing station. In many embodiments, when the substrate is placed on the pedestal 912 by the robot 906, the soak gas is introduced into the station. The depicted processing chamber 914B includes four processing stations, numbered 1 to 4 in the embodiment shown in FIG. 9. Each station has a heated pedestal (shown as 918 in station 1) and a gas line inlet. It will be understood that in some embodiments, each processing station may have different or multiple purposes. For example, in some embodiments, the processing station may be switched between ALD and PEALD processing modes. Additionally or alternatively, in some embodiments, the processing chamber 914 may include one or more pairs of ALD and plasma enhanced ALD processing stations. Although the depicted processing chamber 914 includes four stations, it should be understood that the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations. In addition, although the multi-station processing tool 900 shown in FIG. 9 includes three processing chambers, in some embodiments, the multi-station processing tool may have four processing chambers. In some embodiments, the multi-station processing tool may have four or more processing chambers, while in other embodiments, the multi-station processing tool may have one, two, or three processing chambers. FIG. 9 depicts an embodiment of a wafer processing system 990 for transporting a substrate within a processing chamber 914. In some embodiments, the wafer processing system 990 can transport wafers between various processing stations and / or between a processing station and a load lock. It will be understood that any suitable wafer processing system can be employed. Non-limiting examples include wafer conveyors and wafer handling robots. FIG. 9 also depicts an embodiment of a system controller 950 for controlling processing conditions and hardware states of the processing tool 900. The system controller 950 can include one or more memory devices 956, one or more mass storage devices 954, and one or more processors 952. The processor 952 can include a CPU or computer, analog and / or digital input / output connectors, a stepper motor controller panel, and the like. In some embodiments, the system controller 950 includes machine-readable instructions for performing the operations described herein. In some embodiments, the system controller 950 controls the activities of the processing tool 900. The system controller 950 executes system control software 958, which is stored in the mass storage device 954, loaded into the memory device 956, and executed in the processor 952. Alternatively, the control logic can be hard-coded into the controller 950. Application-specific integrated circuits, programmable logic devices (such as field-programmable gate arrays or FPGAs), and the like can be used for such purposes. In the following discussion, wherever "software" or "coding" is used, functionally equivalent hard-coded logic can be substituted. The system control software 958 can include instructions for controlling time, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck, and / or susceptor positions, and other parameters for a particular process performed by the processing tool 900. The system control software 958 can be configured in any suitable manner. For example, numerous processing tool component subroutines or control objects can be written to control the operation of processing tool components for performing individual processing tool processes. The system control software 958 can be coded in any suitable computer-readable programming language. In some embodiments, chambers 914A-C can perform the same or different operations. Additionally, although three chambers 914A-C are shown, in some embodiments there can be four or more chambers, or three or fewer chambers. In some embodiments, each of chambers 914A-C can perform a dry deposition process to deposit a photolithography layer. In some embodiments, one or more of chambers 914A-C can be used for a dry deposition process, while a different one or more of chambers 914A-C can be used for a dry development process as described herein. In some embodiments, one chamber can be used for a dry deposition process, one chamber can be used for a PAB process, and one chamber can be used for a dry development process. In some embodiments, the chamber used for the PAB process can also be used for the PEB process or alternatively for the PEB process. In embodiments with four chambers, one chamber can be used for a dry deposition process, one chamber can be used for a PAB process, one chamber can be used for a PEB process, and one chamber can be used for a dry development process. In some embodiments, unequal process times can be addressed by different module ratios (e.g., if the PR deposition time is twice the PAB time, the tool can be configured with twice as many PR deposition modules as PAB modules). In some embodiments, the multi-station processing tool 900 can have different modules in each chamber to facilitate the embodiments discussed herein. For example, a VECTOR® processing module can be used for a deposition process, while a KIYO® processing module can be used for PAB, PEB, or dry development processes. In some embodiments, there can be different numbers of each type of module. For example, there may be one VECTOR module and one or more KIYO modules. In some embodiments, multiple operations can be implemented on different pedestals within the same module of the same tool. In some embodiments, the VECTOR module can be integrated within the same module as the KIYO module. For example, pedestals 1 and 3 of chamber 914 can be used for a dry deposition process, while pedestals 2 and 4 can be used for different processes such as wafer cleaning, PAB, PEB, or dry development processes. A wafer can be processed on one pedestal to deposit a PR film, and then the robot can be used to move the wafer to another pedestal within the chamber for subsequent processes as described herein. In this way, the vacuum can be maintained and transferring the wafer from one pedestal to another is faster than transferring the wafer between processing modules. Thus, efficiency (throughput) is increased without significantly sacrificing technical performance, and cross-contamination is controlled or minimized, resulting in excellent thin film performance. In addition, each station / base can be configured or optimized for each operation, and the bases can be isolated from each other to reduce or minimize cross - contamination / crosstalk between deposition, cleaning, baking, radiation exposure, or development processes, for example, by an air curtain or other barriers specific to the station (such as an air seal), as described in U.S. Patent Application Publication No. 2015 / 0004798 and U.S. Patent Application Publication No. 2017 / 0101710, the disclosures of which are hereby incorporated by reference herein. Within the scope, each base treatment can be at a different temperature and pressure. And the temperatures of the base, showerhead, walls, etc. of each station can be independently and optimally set for each treatment without cycling. The gas distribution to each station can be kept separate. By adding multiple throttle valves, the pressure can be maintained independently. In some embodiments, the exhaust of each station can be local rather than shared, so that the exhaust can be kept independent without cross - mixing / contaminating the gases. In some embodiments, integrated operations can be implemented on the same base. For example, wafer cleaning and PAB / PEB operations can be implemented on the same base. This can provide increased throughput by reducing the transfer or queuing time between wafer cleaning and baking operations. Figures 10A - E illustrate various embodiments in which processing operations can be performed in different chambers of a tool, as well as process flowcharts of operations that can be performed on or outside the tool. In various embodiments, the operations shown in Figures 10A - E can be the same as those described in Figure 1 above (as implied by the use of the same reference numerals). Although the cleaning operation is not shown in Figures 10A - E, the cleaning operation can be performed in some embodiments. We should also understand that certain operations may not be performed, as further explained with reference to Figure 1. Figure 10A(i) shows an embodiment in which each chamber of a cluster tool performs a dry deposition process, as shown in the process flow presented in Figure 10A(ii). Other operations in the lithography process, such as PAB, EUV exposure, PEB, and development processes, can be performed on different tools or clusters. Figure 10B(i) illustrates an embodiment in which dry deposition and dry development processes can be performed within a single tool, as shown in the process flow presented in Figure 10B(ii). In various embodiments, two chambers can be used for the dry deposition process, and one chamber can be used for the dry development process. Other operations can be performed on different tools. Figure 10C(i) shows an embodiment where each of dry deposition, PAB, and dry development is performed within a single tool, as shown in the process flow presented in Figure 10C(ii). In various embodiments, each process may be performed using a single chamber. In some embodiments, the substrate may have a queue time between processes. In some embodiments, the queue time may be spent outside the tool, such as in a FOUP or other controlled environment. In other embodiments, the wafer may be moved directly from the dry EUV deposition chamber to the PAB chamber without a queue time, or the queue time may be spent in either processing chamber. This may be advantageous for reducing the queue time and / or maintaining the vacuum, both of which can improve the quality of the resulting PR film. Figure 10D(i) illustrates an embodiment where the dry deposition, PEB, and dry development processes are performed within a single tool, as shown in the process flow presented in Figure 10D(ii). In some embodiments, the PAB chamber and the PEB chamber may be the same chamber, while in other embodiments they are different chambers. As described above, in some embodiments, the queue time may be spent outside the tool in a controlled environment, while in other embodiments, the wafer may be transferred directly from the PEB chamber to the development chamber. This may be advantageous for reducing the queue time and / or maintaining the vacuum, both of which can improve the quality of the resulting PR film. Figure 10E(i) illustrates an embodiment where dry deposition, PAB, PEB, and dry development are performed within a single tool, as shown in the process flow presented in Figure 10E(ii). In some embodiments, the radiation exposure may be performed outside the tool in a separate scanner chamber. As described above, in some embodiments, the queue time may be spent outside the tool in a controlled environment, while in other embodiments, the substrate may be moved directly from the dry deposition chamber to the PAB chamber, or from the PEB chamber to the dry development chamber. In such embodiments, the queue time may be spent on the tool. Transferring the substrate between chambers on the same tool for different operations may be beneficial for reducing the queue time and maintaining the vacuum / environmental control. Figure 10F (i) illustrates an embodiment where a scanner can be integrated with a deposition chamber and / or a wet or dry development chamber. An organometallic tin precursor ampoule 1000 and an EUV deposition module 1010 can be used for dry deposition of EUV PR. An EUV exposure module 1020 can be used to expose portions of the EUV PR to radiation to chemically alter the exposed portions. An EUV development module 1030 can use wet or dry means to remove portions of the EUV PR, which may treat the PR as a negative or positive resist. A pattern transfer module 1040 can then transfer the pattern of the EUV PR to the underlying layer, for example, by an etching process to form lines based on the developed EUV PR pattern. In some embodiments, by-products from the respective processing environments can be shared or routed to one or more exhaust abatement systems 1050. In some embodiments, the process flow shown in Figure 10F (ii) can be executed in the tool shown in Figure 10F (i). In some embodiments, a system controller (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its different modules. It should be noted that the controller can be located locally within the cluster architecture, outside the cluster architecture on the manufacturing floor, or at a remote location and connected to the cluster architecture through a network. The system controller can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or a computer, analog and / or digital input / output connectors, a stepper motor controller panel, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions can be stored on the memory device associated with the controller, or they can be provided via a network. In certain embodiments, the system controller executes system control software. The system control software can include instructions for controlling the application time and / or amplitude of any aspect of the operation of the tool or module. The system control software can be configured in any suitable manner. For example, individual processing tool component subroutines or control objects can be written to control the operation of the processing tool components necessary for the processing of each individual processing tool. The system control software can be encoded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the above-mentioned various parameters. For example, each stage of semiconductor manufacturing processing can include one or more instructions executed by the system controller. For example, instructions for setting the processing conditions for the condensation, deposition, evaporation, patterning, and / or etching stages can be included in the corresponding recipe stages. In various embodiments, a device for forming a negative pattern photomask is provided. The device can include processing chambers for patterning, deposition, and etching, and a controller that includes instructions for forming a negative pattern photomask. The instructions can include patterning features on a semiconductor substrate with a chemically amplified resist (CAR) by EUV exposure in a processing chamber to expose the substrate surface, dry-developing the photopatterned resist, and using the patterned resist as a mask to etch an underlying layer or layer stack. We should note that the computer controlling wafer movement can be located locally within the cluster architecture, outside the cluster architecture on the manufacturing floor, or at a remote location and connected to the cluster architecture via a network. The controller as described above with respect to FIGS. 6 or 7 can be implemented in any one of FIGS. 4, 5, 6, 7, 8, 9, or 10A-F, and in the tool architectures described in FIGS. 11, 12, and 13. FIGS. 11, 12, and 13 provide configurations of alternative processing tool architectures, such as can be implemented at least in part in EOS or Sens.i products available from Lam Research Corporation of Fremont, California, which can be used in some embodiments. Starting with FIG. 11, a multi-station processing tool 1100 can have an equipment front end module (EFEM) to optionally receive substrates by a FOUP. As shown in the cross-sectional view of the multi-station processing tool 1100 of FIG. 12, an EFEM robot 1204 can move substrates from the EFEM 1104 through a load port 1206. The substrates can be moved by one or more shuttle transporters 1208, which can move substrates on a linear track 1214 or an elevator 1212. Next, a wafer processing robot 1210 can move the substrate into a processing chamber 1108 (in FIG. 12, 8 of the total 16 processing chambers of the multi-station processing tool 1100 are depicted). As discussed herein, each processing chamber can switch between multiple processing modes. Returning to FIG. 11, the multi-station processing tool 1100 can also have a fluid delivery system (FDS) 1112 to deliver process gases and other fluids to each processing chamber, and an FDS controller 1114. Fan filter units 1102 and 1106 can be used to ensure a clean environment for the processing chamber and the corridor section, respectively. In some embodiments, as shown in FIGS. 11 and 12, a resist processing track can be used to implement wet development of a dry-deposited EUV PR. FIG. 13A presents a top view of another multi-station processing tool 1300 having a robot 1304 configured to move wafers from cassettes loaded through a front opening unified pod 1308. A second robot 1306 can move the wafers to one of the various processing chambers 1302 to perform the operations described herein. FIG. 13B presents a side view of the multi-station processing tool 1300. The various embodiments described herein can be implemented using the clustered architecture shown in FIGS. 11, 12, and 13. Conclusion Although some of the foregoing embodiments have been described in detail for purposes of clear understanding, it is apparent that certain changes and modifications may be practiced within the scope of the appended claims. The embodiments disclosed herein may be practiced without some or all of these specific details. In other instances, well-known processing operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Further, while the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways to implement the processing, systems, and devices of this embodiment. Accordingly, this embodiment should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein. 1 - 18: Sensor 100: Processing 102, 104, 106, 108, 110, 112, 150: Block, Operation 102a: Exposed metal film area 102b: Unexposed area 300: Semiconductor substrate 302: Metal-containing film 302a: Exposed area of the metal-containing film 302b: Unexposed area 306: Deposited metal 400: Processing station 401: Reactant delivery system 402: Processing chamber main body 403: Vaporization point 404: Mixing container 406: Showerhead 408: Base 410: Heater 412: Substrate 414: RF power supply 416: Matching network 418: Butterfly valve 420: Mixing container inlet valve 500: Processing tool 502: Inbound load lock 504: Outbound load lock 506: Robot 508: Cassette 510: Atmospheric port 512: Base 514: Processing chamber 516: Chamber transfer port 518: Base 550: Controller 552: Processor 554: Mass storage device 556: Memory device 558: System control software 590: Wafer processing system 600: Inductively coupled plasma etching equipment 601: Chamber wall 602: Upper sub-chamber 603: Lower sub-chamber 611: Window 617: Chuck 619: Wafer 621: Matching circuit 622: Port 623: RF power supply 625: Connector 627: Connector 630: System controller 633: Coil 639: Matching circuit 640: Mechanical dry pump and / or turbomolecular pump 641: RF power supply 643: Connector 645: Connector 649: Faraday shield 650: Grid 660: Main gas flow inlet 670: Side gas flow inlet 720a - 720d: Processing module 722: Robot 724: End effector 726: Wafer 736: Facet 738: Vacuum transfer module (VTM) 740: Patterning module 742: Air lock 744: Front-end robot 746: Air lock 820: Processing module 820a - 820d: Processing module 822: Robot 824: End effector 826: Wafer 828: Module center 830: Cassette 832: Front-end robot 834: Front-opening unified pod (FOUP) 838: Vacuum transfer module (VTM) 840: Atmospheric transfer module (ATM) 842: Loading port module (LPM) 844: Aligner 900: Processing tool 902: Inbound load lock 904: Outbound load lock 906: Robot 908: Cassette 912: Base 914: Processing chamber 914A - C: Processing chamber 916: Chamber transfer port 918: Base 950: Controller 952: Processor 954: Mass storage device 956: Memory device 958: System control software 990: Wafer processing system1000: Organometallic tin precursor ampoule 1010: EUV deposition module 1020: EUV exposure module 1030: EUV development module 1040: Pattern transfer module 1050: Exhaust gas reduction system 1100: Multi-station processing tool 1102: Fan filter unit 1104: Equipment Front End Module (EFEM) 1106: Fan filter unit 1108: Processing chamber 1112: Fluid Delivery System (FDS) 1114: FDS controller 1204: EFEM robot 1206: Loading port 1208: Shuttle transporter 1210: Wafer handling robot 1212: Elevator 1214: Linear track 1300: Multi-station processing tool 1302: Processing chamber 1304: Robot 1306: Second robot 1308: Cassette Figure 1 presents a process flow diagram of an exemplary embodiment. Figure 2 presents an exemplary chemical reaction scheme of the present technology. Figures 3A-E illustrate the representative process flow of an exemplary embodiment. Figures 4-9 are schematic diagrams of exemplary processing chambers for performing the method according to the disclosed embodiments. Figures 10A-F present schematic diagrams of various processing cluster configurations according to the disclosed embodiments. Figures 11-12 and 13A-B present various exemplary tool architectures that can be used to perform the method according to the disclosed embodiments. 100: Processing 102,104,106,108,110,112,150: Blocks, operations

Claims

1. An integrated lithography system comprising: a dry developing chamber; a post-exposure baking (PEB) chamber; and a controller including one or more processors and one or more memory devices, wherein the one or more memory devices store computer-executable instructions for controlling the one or more processors to perform the following: receiving a substrate in the PEB chamber, wherein, The substrate comprises a patterned photoresist (PR), wherein a portion of the patterned photoresist has been chemically altered by exposure to radiation; the substrate is processed in a PEB chamber to modify the material properties of the patterned PR, wherein the processing of the patterned PR in the PEB chamber is performed at a temperature between approximately 170°C and 290°C; the substrate is received in a dry developing chamber; and the patterned PR is dry developed by exposing it to a dry developing chemical to remove the exposed or unexposed portions of the patterned PR, thereby forming a PR mask.

2. The integrated lithography system of claim 1, wherein the dry developing chemical contains a halogenated chemical.

3. As in request item 1, the integrated lithography system, wherein, The dry developing chemicals include hydrohalides, hydrogen and halogen gases, boron trichloride, organohalides, amide halides, carbonyl halides, thionyl halides, or mixtures thereof.

4. As in request item 1, the integrated lithography system, wherein, The dry developing chamber is configured to expose the substrate to temperatures between approximately -60°C and approximately 120°C.

5. As in request item 1, the integrated lithography system, wherein, The computer-executable instructions for controlling one or more processors to dry develop the patterned PR include computer-executable instructions for controlling one or more processors to dry develop the patterned organometallic PR in a non-plasma thermal process.

6. As in request item 5, the integrated lithography system, wherein, Dry development of this patterning PR system is performed at a pressure between approximately 100 Torr and approximately 760 Torr.

7. As in request item 5, the integrated lithography system, wherein, Dry development of this patterning PR system is performed at pressures between approximately 0.1 mTorr and approximately 300 mTorr.

8. As in request item 5, the integrated lithography system, wherein, Dry development of this patterning PR system is performed at pressures between approximately 20 mTorr and approximately 800 mTorr.

9. The integrated lithography system as described in request item 1, wherein, The computer-executable instructions for controlling one or more processors to dry develop the patterned PR include computer-executable instructions for controlling one or more processors to dry develop the patterned organometallic PR in a plasma process.

10. The integrated lithography system as described in request item 9, wherein, Dry development of this patterned PR system is performed at a pressure greater than approximately 5 mTorr.

11. The integrated lithography system as described in request item 9, wherein, The radio frequency (RF) power of this plasma process is less than 1000 W.

12. As in request item 1, the integrated lithography system, wherein, The computer-executable instructions used to control the one or more processors further include instructions for removing residual patterned PR material from the substrate by exposing it to a plasma after dry development of the patterned PR.

13. The integrated lithography system as described in request item 12, wherein, The remaining patterned PR slag removal system is performed at a chamber pressure between approximately 1 mTorr and approximately 300 mTorr.

14. The integrated lithography system as described in request item 12, wherein, The plasma is an inert gas plasma containing helium.

15. The integrated lithography system as described in request item 12, wherein, The power of the plasma is between approximately 50 W and approximately 1000 W.

16. The integrated lithography system as described in request item 12, wherein, The computer-executable instructions used to control the one or more processors to remove residual patterned PR residue include computer-executable instructions for exposing the substrate to the plasma for a duration between about 0.5 seconds and about 5 seconds.

17. The integrated lithography system as described in Request 1, wherein, The atmospheric environment of one or more of the dry developing chamber and the PEB chamber is controlled.

18. The integrated lithography system as described in request item 1, wherein, This PR is a metal-containing PR.

19. The integrated lithography system as described in Request 1, wherein, This PR is an EUV PR.

20. The integrated lithography system as described in request item 1, wherein, The patterned PR system was processed in the PEB chamber at a temperature between approximately 150°C and 250°C.

21. The integrated lithography system as described in Request 1, wherein, The patterned PR system was processed in the PEB chamber at a pressure below 760 Torr.

22. The integrated lithography system as described in Request 1, wherein, Processing the substrate in the PEB chamber involves exposing the patterned PR to a reactive gas.

23. The integrated lithography system as described in claim 22, wherein, The reaction gas system contains H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, N2O, NO, alcohol, acetone, formic acid, Cl2, F2, Br2, I2, Ar, He, or any combination thereof.

24. The integrated lithography system of claim 1 further includes a clustering tool, wherein, The dry developing chamber and the PEB chamber are the processing chambers for the clustering tool.

25. The integrated lithography system of claim 1 further includes a clustering tool, wherein, The dry developing chamber and the PEB chamber are the processing chambers of the clustering tool, wherein the clustering tool further includes an extreme ultraviolet (EUV) scanner, wherein the EUV scanner is configured to expose the substrate to EUV radiation.

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