Microelectronic assembly, and method of forming a microelectronic assembly

Abstract

This invention provides a multilayer structure comprising a plurality of interposer layers and a plurality of electronic components disposed between the plurality of interposer layers. The plurality of interposer layers and the plurality of electronic components are configured in at least two layers, each layer including at least one electronic component disposed between two of the plurality of interposer layers. The at least two layers are stacked adjacent to each other such that one of the plurality of interposer layers is shared by the adjacent layers of the at least two layers. A first external terminal and a second external terminal are electrically connectable to the multilayer structure and an additional electronic component and / or electrically connectable within an assembly. This invention also provides a microelectronic assembly incorporated into a multilayer structure.

Description

Prior Art

[0001] Due to the continuously increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. This increase in integration density mostly comes from the continuously decreasing minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, smaller and more innovative semiconductor chip packaging technologies are needed. To help implement high-density solutions for semiconductor chips, interposers formed of organic, inorganic (such as glass), or silicon materials are typically employed. When the interposer is formed of a semiconductor material (such as silicon), this component is generally referred to as a chip-on-wafer-on-interposer (CoW) structure. The CoW structure can then be attached to a stacked packaging substrate to form a CoWoS structure, and the resulting package can ultimately be connected to a printed circuit board. However, the demand for smaller and smaller electronic devices persists. Thus, there is a current need for improved microelectronic components that employ vertical integration of components. Summary of the Invention

[0002] According to one embodiment of the present invention, a multilayer structure is provided that includes a plurality of interposers and a plurality of electronic components disposed between the plurality of interposers. The plurality of interposers and the plurality of electronic components are configured in at least two layers, each layer including at least one electronic component of the plurality of electronic components disposed between two of the plurality of interposers. The at least two layers are stacked adjacent to each other such that one of the plurality of interposers is shared by adjacent layers of the at least two layers.

[0003] According to another embodiment of the present invention, a microelectronic component includes a semiconductor structure, a component interposer electrically connected to the semiconductor structure, a packaging substrate electrically connected to the component interposer, a multilayer structure, and a circuit board. The multilayer structure includes a plurality of interposers and a plurality of electronic components disposed between the plurality of interposers. The plurality of interposers and the plurality of electronic components are configured in at least two layers, each layer including at least one electronic component of the plurality of electronic components disposed between two of the plurality of interposers. The at least two layers are stacked adjacent to each other such that one of the plurality of interposers is shared by adjacent layers of the at least two layers. The multilayer structure is electrically connected to the packaging substrate and the circuit board.

[0004] Other features and aspects of the present invention are elaborated in more detail below. Brief Description of the Drawings

[0005] More specifically, the remainder of this specification (including the accompanying drawings) sets forth a complete and enabling disclosure of the invention (including its best mode for those of ordinary skill in the art), wherein:

[0006] FIG. 1 shows a cross-sectional view of an embodiment of a microelectronic component of the present invention;

[0007] FIG. 2 shows a cross-sectional view of another embodiment of a microelectronic component of the present invention;

[0008] FIG. 3 shows a cross-sectional view of yet another embodiment of a microelectronic component of the present invention;

[0009] FIG. 4A shows a perspective view of an embodiment of a decoupling capacitor that can be employed in the present invention;

[0010] FIG. 4B shows a side view of the internal electrode layer of the capacitor of FIG. 4A;

[0011] FIG. 5A shows a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0012] FIG. 5B shows an end view of the capacitor of FIG. 5A;

[0013] FIG. 5C shows a side view of the capacitor of FIG. 5A;

[0014] FIG. 6A shows a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0015] FIG. 6B shows a side view of the internal electrode layer of the capacitor of FIG. 6A;

[0016] FIG. 7A shows a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0017] FIG. 7B shows a side view of the internal electrode layer of the capacitor of FIG. 7A;

[0018] FIG. 7C shows a perspective view of the internal electrode layer of the capacitor of FIG. 7A;

[0019] FIG. 7D shows a cross-sectional perspective view of the capacitor of FIG. 7A;

[0020] FIG. 8A shows a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0021] FIG. 8B shows a side view of one side of the internal electrode layer of the capacitor of FIG. 8A;

[0022] FIG. 8C shows a perspective view of one side of the internal electrode layer of the capacitor of FIG. 8A;

[0023] FIG. 8D shows a cross-sectional perspective view of the capacitor of FIG. 8A;

[0024] FIG. 9A shows a perspective view of another embodiment of a decoupling capacitor that can be employed in the present invention;

[0025] FIG. 9B shows a cross-sectional perspective view of the capacitor of FIG. 9A;

[0026] FIG. 10A shows a perspective view of yet another embodiment of a decoupling capacitor that can be employed in the present invention;

[0027] FIG. 10B shows a side perspective view of one configuration of the internal electrode layer of the capacitor of FIG. 10A;

[0028] FIG. 10C shows a side perspective view of another configuration of the internal electrode layer of the capacitor of FIG. 10A;

[0029] FIG. 11 shows a side view of one layer of a multilayer structure that can be employed in the present invention;

[0030] FIG. 12A shows a side view of a multilayer structure that can be employed in the present invention;

[0031] FIG. 12B shows a side view of a multilayer structure having external terminals on opposing outer surfaces that can be employed in the present invention;

[0032] FIG. 12C shows a side view of another multilayer structure having external terminals on opposing outer surfaces that can be employed in the present invention;

[0033] FIG. 13A shows a side view of another embodiment of a multilayer structure that can be employed in the present invention;

[0034] Figure 13B shows a side view of an embodiment of a multilayer structure having longitudinally aligned electronic components that can be employed in the present invention;

[0035] Figure 13C shows a side view of an embodiment of a multilayer structure having longitudinally offset electronic components that can be employed in the present invention;

[0036] Figure 13D shows a view along a stacking direction of another embodiment of a multilayer structure that can be employed in the present invention;

[0037] Figure 13E shows a side perspective view of another embodiment of a multilayer structure that can be employed in the present invention;

[0038] Figure 14A shows a side view of an embodiment of a component structure having a sacrificial plate that can be employed in the present invention;

[0039] Figure 14B shows a side view of the embodiment of Figure 15A in which the sacrificial plate is removed; and

[0040] Figure 14C shows a side view of the embodiment of Figure 15A in which a portion of each sacrificial plate is removed.

[0041] The repeated reference to symbols in this specification and the drawings is intended to represent the same or similar features or elements of the present invention. Embodiments

[0042] Related Applications This application claims priority based on and incorporates by reference herein U.S. Provisional Patent Application No. 63 / 509,036, filed on June 20, 2023.

[0043] One of ordinary skill in the art should understand that this discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0044] Generally, the present invention is directed to a decoupling capacitor structure, a decoupling capacitor assembly, a multi-layer decoupling capacitor structure, and a microelectronic assembly. The microelectronic assembly includes a semiconductor structure, a component interposer electrically connected to the semiconductor structure, an organic packaging substrate electrically connected to the interposer, and at least one of a decoupling capacitor structure, a decoupling capacitor assembly, or a multi-layer decoupling capacitor structure. Each structure or component includes at least one decoupling capacitor disposed adjacent to at least one interposer. The decoupling capacitor has a first surface and an opposing second surface. The decoupling capacitor includes alternating dielectric layers and internal electrode layers, where the internal electrode layers include a first internal electrode layer and a second internal electrode layer. A first external terminal is electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and disposed on a first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative). In any case, in the microelectronic assembly, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the packaging substrate, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to a printed circuit board.

[0045] Various embodiments of the present invention will now be described in more detail below. I. Semiconductor Structure

[0046] One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) are generally used within a microelectronic component. Generally, a semiconductor structure may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. The insulating material may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymeric dielectric, photoimageable dielectric, and / or benzocyclobutene-based polymer). The insulating material may also include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive paths of a die may include conductive traces and / or conductive vias and may connect to any of the conductive contacts within the die in any suitable manner. The semiconductor structure may include a hybrid pitch die (in the sense that the die has a set of conductive contacts with different pitches), e.g., the die may have "rougher" conductive contacts for coupling to an interposer of a microelectronic component. The structure may also include a single-sided die (having conductive contacts on only a single surface) and / or a double-sided die (having conductive contacts on a first surface and an opposing second surface). Optionally, the conductive paths within the die may be bounded by liner materials such as an adhesive liner and / or a barrier liner. The semiconductor structure may also include a wafer. In some embodiments, the semiconductor structure includes a single-crystalline silicon, a fan-out or fan-in packaged die, or a die stack (e.g., a wafer stack, a die stack, or a multi-layer die stack).

[0047] The semiconductor structure may also have an integrated circuit (“IC”) structure such that it is in the form of a discrete IC device or “chip”. Such an IC device may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system including (e.g.) an n-type or p-type material system (or a combination of one of each). The die substrate may include (e.g.) a crystalline substrate formed using a bulk silicon or silicon-on-insulator (SOI) sub-structure. In some embodiments, the die substrate may be formed using alternative materials (which may or may not be combined with silicon, including (but not limited to) germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate. The device layers may include one or more transistors (e.g. metal oxide semiconductor field effect transistors (MOSFETs)), support circuitry for routing electrical signals to the transistors, passive components (e.g. signal traces, resistors, capacitors, or inductors) and / or any other IC components. The device layers may include (e.g.) one or more source and / or drain (S / D) regions, a gate for controlling current in the transistors between the S / D regions, and one or more S / D contacts for routing electrical signals to / from the S / D regions. Each transistor may include a gate formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include (but are not limited to) hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when using a high-k material.

[0048] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal depending on whether the transistor is a PMOS or NMOS transistor. In some embodiments, the gate electrode can be composed of a stack of one of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers can be included for other purposes, such as a barrier layer. For a PMOS transistor, the metals that can be used for the gate electrode include (but are not limited to) ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (such as ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (such as for work function tuning). For an NMOS transistor, the metals that can be used for the gate electrode include (but are not limited to) hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (such as for work function tuning). Electrical signals (such as power and / or input / output (I / O) signals) can be routed to and / or from devices (such as transistors) on the device layer through one or more interconnect layers disposed on the device layer. For example, the conductive features (such as gates and S / D contacts) of the device layer can be electrically coupled to an interconnect structure that can optionally form a metallization stack (also referred to as an "ILD stack") of an IC device. The interconnect structure can include wires and / or vias filled with a conductive material (such as a metal). The wires can be configured to route electrical signals in a direction in a plane substantially parallel to one surface of the die substrate on which a device layer is formed. The vias can be configured to route electrical signals in a direction in a plane substantially perpendicular to the surface of the die substrate on which a device layer is formed.

[0049] An IC device may (for example) include a memory device (such as a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridge RAM (CBRAM) device, an erasable programmable read-only memory (EPROM) chip, a non-volatile memory (such as 3D XPoint), a volatile memory (such as high-bandwidth memory), stacked memory, etc.), a logic device (such as AND, OR, NAND, or NOR gates, programmable logic devices, etc.), a processor device (such as a central processing unit (CPU), a graphics processing unit (GPU), etc.), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a platform controller hub (PCH), and so on and any other suitable memory, logic, and / or processor devices. Multiple devices may be combined on a single structure. For example, a memory array formed by multiple memory devices may be formed on the same die as a processing device or other logic, the processing device or other logic being configured to store information in the memory device or execute instructions stored in the memory array.

[0050] The semiconductor structure can also be a "chiplet", which is a small integrated circuit (IC) containing a well-defined subset of functions that form part of a processing module of a larger integrated circuit such as a computer processor. In some embodiments, one or more chiplets are differently coupled to a host chip, where each of the one or more chiplets includes a respective cache that is accessible by one or more cores of the host chip, such as including a last-level cache (LLC). The host chip can include one or more processor cores that can each operate as a consumer device of a memory resource, and the chiplet can include one or more memory arrays that are coupled to be accessible by a respective processor core of the host chip. In this particular context, the terms "memory", "memory array", "memory resource" and related terms generally refer to cache memory or non-cache memory (such as (for example) system memory). Similarly, the term "memory controller" generally refers to controller circuitry that provides access to one of cache memory or non-cache memory. The host chip can contain a processor core that operates as a consumer device of a memory resource. For example, the host chip can execute any of an operating system, a binary input / output system (BIOS), and / or various other software programs. To facilitate the execution of this software, a chiplet can include one or more memory arrays that are coupled to be accessible by the processor core via a hardware interface. In one embodiment, the memory array includes static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. Additionally or alternatively, the processor core can be coupled to cache data into the memory array, such as where the processor core is coupled to access a last-level cache (LLC) of the memory array. In various other embodiments, the memory array can contain non-volatile memory (NVM) cells. The chiplet can also contain a memory controller coupled between the hardware interface and the memory array to perform program-controlled memory access on behalf of the core. By providing the memory array in a chiplet placed between the hardware interface and the host chip, the data locality for one or more cores of the packaging device can be improved. This improved data locality enables access to relatively more space-saving, time-saving, and / or power-saving memory resources.

[0051] A semiconductor structure can be configured in a two-dimensional configuration or array known in cost-effective semiconductor technologies (such as 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration) or stacked into a 3D configuration. When a stacked configuration is employed, the semiconductor structure can include two or more semiconductor substrates (such as wafers, interposers, etc.) mounted on a circuit board. If implemented as semiconductor wafers, the substrates can be any of various different types of circuit devices used in electronic devices (such as (for example) microprocessors, graphics processors, combined microprocessor / graphics processors, application-specific integrated circuits, memory devices, or the like) and can be single-core or multi-core. The substrates can be constructed from bulk semiconductors (such as silicon or germanium) or semiconductor-on-insulator materials (such as silicon-on-insulator materials). The circuit board can be a semiconductor wafer packaging substrate, a circuit card, or almost any other type of printed circuit board. A single-chip structure can be used for the circuit board, although a more typical configuration will utilize a stacked design. In this regard, the circuit board can consist of a central core on which one or more stacked layers are formed and one or more additional stacked layers are formed beneath. The core itself can consist of a stack of one or more layers. Circuit paths between the substrates and the circuit board and between any of the substrates can be provided by interconnect structures. II. Interposer

[0052] As indicated above, a semiconductor structure is electrically connected to one or more interposers such that the resulting microelectronic assembly is considered a "wafer-on-interposer" structure. Additionally, the interposer can provide an intervening substrate to help bridge the circuit board and the semiconductor structure and help extend a connection to a wider pitch or reroute a connection to a different connection. The semiconductor structure can be electrically connected to the interposer by one or more coupling components. The coupling components can electrically and mechanically couple the wafer-on-interposer structure to the circuit board and can include (for example) solder bumps, solder balls, the male and female parts of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The underfill material can be an insulating material, such as a suitable epoxy resin material. When employed, an underfill material can include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material can include an epoxy flux that aids in soldering the semiconductor structure and then polymerizes and encapsulates the interconnects within the interposer.

[0053] The interposer generally includes an insulating material and one or more conductive paths passing through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). In one embodiment, for example, the insulating material can be an organic material such as a bismaleimide triazine (「BT」) resin material (e.g., BT, BT epoxy resin, etc.), an epoxy resin material (e.g., glass fiber reinforced epoxy resin (e.g., FR4)), a polyimide material, a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). The insulating material can also be an inorganic interposer, such as an inorganic interposer formed of a ceramic material (e.g., glass) and an inorganic interposer formed of a semiconductor material (such as silicon, germanium, and other Group III-V (e.g., gallium nitride) and Group IV materials). The conductive paths serve as a mechanism for electrically connecting the interposer to the semiconductor structure via coupling components. These paths can include one or more metal interconnects and vias known in the art. In one embodiment, for example, the interposer can be formed of silicon and vias can be formed therein, and the vias can be referred to as 「through-silicon vias」 (「TSV」).

[0054] Regardless of how it is formed, depending on the specific embodiment, the interposer can be passive or active. 「Passive」 generally means that the interposer generally does not contain embedded electronic components. On the other hand, an 「active」 interposer generally contains one or more electronic components embedded within the insulating material. Examples of such electronic components can include (e.g.) capacitors (e.g., decoupling capacitors), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical systems (MEMS devices) can also be formed in the interposer. For example, an active interposer can include an active layer and a bulk semiconductor layer. The front surface of the active layer can be referred to herein as an 「active side」 and the opposing surface of the bulk semiconductor layer can be referred to as a 「back side」. In one embodiment, the active layer can include one or more electronic components formed at the active side, such as a level 1 (L1) memory element serving as a memory cache area for storing a configuration bit stream for configuring logic sectors in a coprocessor. The active layer can optionally include decryption / decompression circuitry for processing the encrypted and / or compressed configuration bit stream. The semiconductor layer can include TSVs connecting the electronic components (e.g., L1 memory elements) in the active layer to coupling elements (e.g., solder balls). For example, the L1 cache area can receive the configuration bit stream from a host processor through the solder balls and TSVs. In this way, the energy efficiency of transmitting signals and power between the active layer of the interposer and the package substrate can be improved. III. Package Substrate

[0055] In addition to an interposer, the microelectronic component further includes a "deposited" package substrate to assist in bridging high-density interconnects and functions between a semiconductor structure, the interposer, and a circuit board. The package substrate generally includes an organic insulating material and one or more conductive paths (such as those including conductive traces and / or conductive vias, as shown) through the insulating material. The organic insulating material may include, for example, a bismaleimide triazine ("BT") resin material (such as BT, BT epoxy resin, etc.), an epoxy resin material (such as glass fiber reinforced epoxy resin (such as FR4)), a polyimide material, low-k and ultra-low-k dielectrics (such as carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In some embodiments, the insulating material may be a laminated or deposited film (such as an Ajinomoto deposited film). The conductive paths may couple the semiconductor structure to the circuit board and decoupling capacitors. Any suitable configuration of conductive paths through any number of insulating layers may generally be employed. The conductive paths may be made of any suitable conductive material, such as copper. Optionally, the conductive paths may be bounded by liner materials, such as adhesive liners and / or barrier liners. In certain embodiments, the package substrate may be a lower density medium and the semiconductor structure and / or the interposer may be a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms that indicate that the conductive paths (such as those including conductive lines and conductive vias) in a lower density medium are larger and / or have a greater pitch than the conductive paths in a higher density medium. For example, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive deposition process with advanced lithography (having small vertical interconnect features formed by an advanced laser or lithography process), while a lower density medium may be a PCB manufactured using a standard PCB process (such as a standard subtractive process that uses etching chemicals to remove unwanted copper regions and has rough vertical interconnect features formed by a standard laser process). IV. Decoupling Capacitors

[0056] As indicated above, at least one decoupling capacitor is electrically connected to the package substrate and a circuit board (such as a printed circuit board). Generally, a decoupling capacitor includes a body containing alternating dielectric layers and internal electrode layers. The internal electrode layers include at least a first internal electrode layer and a second internal electrode layer. The capacitor may, for example, include at least two (such as at least three, such as at least four sets) of internal electrode layers. Of course, it should be understood that the capacitor may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited.

[0057] Generally, a capacitor includes an upper surface (e.g., a first surface) and a lower surface (e.g., a second surface) opposite to the upper surface. The capacitor also includes at least one side surface extending between the upper surface and the lower surface, specifically, at least two side surfaces. The capacitor may also include at least one end surface extending between the upper surface and the lower surface, specifically, at least two end surfaces. The side surface may extend in a length (L) direction and have a dimension generally longer than that of the end surface extending in a width (W) direction and having a generally shorter dimension. In one embodiment, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall dimensions of the capacitor may depend on the specific application. However, generally, the height or thickness of the capacitor ranges from about 10 μm to about 5,000 μm, in some embodiments from about 20 μm to about 2,500 μm, in some embodiments from about 50 μm to about 1,500 μm, and in some embodiments from about 100 μm to about 1,000 μm. When surrounded by a ball grid array, the height of the capacitor may be within 10% of the height (or diameter) of the balls of the ball grid array, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1%. For example, this height may be the original height before any reflow soldering. The length of the capacitor in the "L" direction may also be from about 50 μm to about 10,000 μm, in some embodiments from about 100 μm to about 7,500 μm, and in some embodiments from about 1,000 μm to about 5,000 μm, and the width of the capacitor in the "W" direction may be from about 25 μm to about 5,000 μm, in some embodiments from about 50 μm to about 3,500 μm, and in some embodiments from about 500 μm to about 2,500 μm.

[0058] The first internal electrode layer and the second internal electrode layer may be interleaved with a dielectric layer located between the internal electrode layers in an opposed and spaced relationship. The alternating dielectric layers and internal electrode layers of each group may be spaced a specific distance from an adjacent group. For example, the distance may be greater than the thickness of an individual dielectric layer in the group, such as at least 2 times the thickness of a dielectric layer in the group, at least 3 times in some embodiments, at least 5 times in some embodiments, and at least 10 times in some embodiments. Each group of internal electrode layers and / or the entire capacitor may include from about 10 to about 4,000 internal electrode layers, from about 50 to about 2,000 in some embodiments, and from about 100 to about 1,000 in some embodiments. The thickness of the dielectric layer and / or the internal electrode layer is not limited and may be any desired thickness depending on the performance characteristics. For example, the thickness of the internal electrode layer and / or an individual dielectric layer may be in the range of from about 100 nm to about 10 μm, from about 500 nm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. In certain embodiments, if the capacitor includes a second group of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one group and the last internal electrode layer of another group may be greater than the distance between adjacent internal electrode layers within a given group. For example, the distance between the first internal electrode layer of a first group and the last internal electrode layer of a second group may be greater than the distance between the first internal electrode layer and the second internal electrode layer of the first group.

[0059] Although not at all necessary, the dielectric regions of the decoupling capacitors may also include one or more voids. In this regard, a dielectric region may be a region that includes dielectric material but does not include internal electrode material. A dielectric region may thus constitute a region that does not include an alternating configuration of dielectric layers and internal electrode layers. Thus, a dielectric region may include dielectric material that is located between respective sets of alternating dielectric layers and internal electrode layers in a "W" direction. Additionally, a dielectric region may include dielectric material that is located between a lateral edge of an electrode in a given set of alternating dielectric layers and internal electrode layers and an adjacent end face in a longitudinal direction, such as to the extent that these internal electrode layers do not extend to the end face and are offset therefrom. It should be understood that although these dielectric regions may be formed from green sheets of alternating dielectric layers and internal electrode layers, these regions do not include any internal electrode material or corresponding layers. Thus, air gaps may be provided within these regions. Additionally, a dielectric region may include dielectric material that exists between a first internal electrode layer of a respective set and an adjacent side surface of the capacitor. A dielectric region may also include dielectric material that exists between a last internal electrode layer of a respective set and an adjacent side surface of the capacitor. A dielectric region may also include dielectric material between lateral edges of adjacent lead joints that extend from a body of the internal electrode layer. In one particular embodiment, a dielectric region may include a region within the capacitor that exists between two external terminals. Additionally, it should be understood that a dielectric region may include any combination of any of the foregoing regions.

[0060] As indicated above, a dielectric region includes a dielectric region that contains dielectric material but does not contain internal electrode material. Thus, disregarding air gaps, a dielectric region may include 90 volume % or more of dielectric material, such as 93 volume % or more, such as 95 volume % or more, such as 97 volume % or more, such as 98 volume % or more, such as 99 volume % or more, such as 100 volume %. These air gaps may not contain any material, specifically, any dielectric material or internal electrode material. In one embodiment, an air gap may be partially or completely enclosed by an encapsulating material. In one embodiment, an air gap may be partially enclosed by an encapsulating material. By partially enclosing, the encapsulating material only exists internally around a portion of the air gap, such that it is partially separated from the dielectric material. In this regard, at least one particular perimeter of the air gap may be in direct contact with the dielectric material of the dielectric region. In another embodiment, an air gap may be completely or fully enclosed by an encapsulating material. By fully enclosing, the encapsulating material exists around the interior of the air gap, such that it is fully separated from the dielectric material. In any case, the encapsulating material may be used to act as a barrier between the interior of the air gap and the dielectric material of the dielectric region. In one embodiment, the encapsulating material may be a non-conductive material. However, it should be understood that in one embodiment, an air gap may not even be partially enclosed by an encapsulating material.

[0061] A void can be provided and there is no barrier between the air gap and the dielectric material of the dielectric region. The air gap can have any shape and is not necessarily limited. For example, the shape can be a sphere, a cylinder, etc. In one embodiment, the shape can be a sphere. The air gap can have a maximum dimension (such as length, width, diameter, etc.) from about 5 μm to about 5,000 μm, in some embodiments from about 50 μm to about 2,500 μm, and in some embodiments from about 100 μm to about 1,000 μm. The void can be formed using any known technique, such as by printing a specific pattern in a green ceramic sheet and then laminating and firing the stacked laminates. Alternatively, the void can be formed using various drilling techniques to provide any desired shape within the dielectric material of the dielectric region. The void can also be presented using one or more through-holes (such as perforated through-holes). The through-holes can be unfilled with material, such as any conductive or non-conductive material, such that air exists inside. Additionally, in one embodiment, the through-holes can be arranged such that they only exist within the dielectric region. In this regard, the through-holes can be arranged such that they do not contact any of the internal electrode layers. In one embodiment, the through-holes can extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, the through-holes can be columnar to extend through the thickness of the capacitor. Thus, the through-holes can be a perforated conductive through-hole. In another embodiment, the through-holes can only partially extend through the thickness of the capacitor. For example, the through-holes can only partially extend through the thickness of the capacitor, such as from about 10% to about 90% of the capacitor thickness, and in some embodiments from about 20% to about 80%.

[0062] In addition to the alternating internal electrode layers and dielectric layers, the decoupling capacitor also includes a first external terminal electrically connected to the first internal electrode layer and disposed on a first surface (such as the upper surface) of the capacitor and a second external terminal electrically connected to the first internal electrode layer and disposed on a second surface (such as the lower surface) of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor and a fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. Generally, the first and second external terminals have the same polarity (such as positive) and the third and fourth external terminals have the same polarity (such as negative). In any case, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the package substrate, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to a printed circuit board.

[0063] The capacitor may also include external terminals on the opposing end faces. For example, one or more of the external terminals may extend from the first surface (e.g., the upper surface) and / or the second surface (e.g., the lower surface) to an end face. When present on the end face, the external terminals may be only partially present on the end face such that they do not cover the entire end face. In another embodiment, the capacitor may not include any external terminals on the opposing end faces. In a particular embodiment, the external terminals may not be present on one side surface of the capacitor. In any case, the external terminals generally include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitor may include at least one first polarity terminal and / or a second and opposite polarity terminal on an upper surface of the capacitor, such as at least two, such as at least four, such as at least six, such as at least eight. Additionally, the capacitor may include the aforementioned amount of terminals on a lower surface of the capacitor.

[0064] The capacitor may include an equal number of first polarity terminals and / or second polarity terminals on the upper and lower surfaces of the capacitor. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on an upper surface of a capacitor. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on a lower surface of a capacitor. The total number of terminals present on an upper surface of the capacitor may be equal to the total number of terminals present on a lower surface of the capacitor. The total number of first polarity terminals present on an upper surface and a lower surface of the capacitor may be equal to the total number of second and opposite polarity terminals present on an upper surface and a lower surface of the capacitor. Generally, the same polarity terminals on the lower surface of the capacitor corresponding to a particular set of alternating dielectric layers and internal electrode layers are electrically connected to the same polarity terminals on the upper surface of the capacitor. The same polarity terminals located on an upper surface and a lower surface of a capacitor may not refer to being interleaved. In this regard, the corresponding same polarity terminals on an upper and a lower surface may not be offset by a terminal position, but may be directly positioned above or below another same polarity terminal on the opposing upper or lower surface. In other words, the corresponding same polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers and specifically, the corresponding lead joints of this set may be substantially aligned. Substantially aligned means that the offset from one lateral edge of one polarity terminal on an upper surface is within + / - 10% of the offset from one lateral edge of a corresponding polarity terminal on a lower surface, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5%.

[0065] The pitch of the external terminals (i.e., the nominal distance between centers, also referred to as center-to-center spacing) can be specified by a particular circuit board configuration. The pitch between external terminals in one direction (i.e., the x or y direction) can be the same as the pitch between adjacent external terminals in the other direction (i.e., the corresponding y or x direction). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals. The pitch can be (for example) in the range from about 0.1 mm to about 2 mm, in some embodiments from about 0.2 mm to about 1.5 mm, and in some embodiments from about 0.4 mm to about 1.4 mm.

[0066] Optionally, the external terminals can be positioned similar to the configuration of a ball grid array. For example, the external terminals can be arranged to form contacts typically employed by a ball grid array, specifically, a peripheral ball grid array. In this regard, the pitch of the external terminals can be the same as the pitch of a peripheral ball grid array. That is, the pitch can be within 10% of the pitch of a peripheral ball grid array, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1%. Additionally, similar to a ball grid array, the external terminals can be arranged in columns and rows. That is, the external terminals can be arranged such that they exist in at least one column and at least two rows. For example, the external terminals can be presented in at least two columns, such as at least three columns, such as at least four columns. The number of columns can be specified by the number of different sets of alternating dielectric layers and internal electrode layers. Additionally, the external terminals can be presented in at least two rows, such as at least three rows, such as at least four rows. The number of rows can be specified by the number of different columnar contacts of the internal electrodes.

[0067] The length of an external terminal extending along the upper surface (i.e., extending from one end face to the other end face in the longitudinal direction) can be the same as the length of a corresponding external terminal extending along the lower surface. For example, the length of an external terminal can be from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm. The length of an external terminal can also be less than the length of the capacitor, such as 50% or less of the length of the capacitor, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less. Optionally, each external terminal can have a different length. For example, an external terminal adjacent to an end face can have a length greater than that of an external terminal offset from the end face. In this regard, the ratio of the length of an external terminal adjacent to an end face to the length of an external terminal offset from the end face can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. The width of an external terminal extending from one side surface to an opposite side surface can be the same on the upper surface and the lower surface. For example, the width can range from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm.

[0068] Referring to FIGS. 4A to 4B, a particular embodiment of a decoupling capacitor 10 that can be employed in the microelectronic component of the present invention is shown in more detail. The capacitor 10 generally has a thickness "T", width "W", and length "L", such as described above. In addition, as shown, the capacitor 10 has a 1×2 configuration because it includes two external terminals in one dimension along the upper surface and the lower surface. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface and corresponding two third and fourth external terminals (not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) can have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) can also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminals 12 and / or 14 can be within the ranges discussed above. Although not at all necessary, a void 1350 can also be formed in the capacitor 10 between the terminals 12 and 14, as described above.

[0069] The capacitor 10 also includes a dielectric layer (not shown) and an internal electrode layer 110, as depicted in FIG. 4B. That is, the internal electrode layer 110 includes a first internal electrode layer 105 and a second set of internal electrode layers 115. In the particular embodiment shown, the internal electrode layers 105, 115 include at least one lead joint 120, 130, 140, 150 extending from a top edge and a bottom edge of a body of the internal electrode layer. The lead joints 120, 130, 140, 150 of the internal electrode layers 105, 115 can extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead joints 120, 130, 140, 150 can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead joints 120, 130, 140, 150 can include a front edge 123, 133, 143, 153 that extends to an edge of a dielectric layer and allows for the formation of an external terminal. The length of the lead joints 120, 130, 140, 150 can vary according to desire, but is typically from about 0.3 mm to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there is more than one lead joint along an edge, each lead joint can have the same length. In another embodiment, each lead joint can have a different length. For example, a lead joint that is substantially aligned with a side edge of the internal electrode layer can have a length greater than that of a lead joint that is offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of a lead joint that is aligned with a side edge of the internal electrode layer to the length of a lead joint that is offset from the side edge of the internal electrode layer can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Substantially aligned generally means that the offset of a side edge of a first lead joint and / or a second lead joint on a top edge from a side edge of a corresponding lateral edge of a first lead joint and / or a second lead joint on a bottom edge is within + / - 10% of the offset of the corresponding lateral edge, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5%.

[0070] As shown in FIG. 4B, a first internal electrode layer 105 includes lead connectors 120, 130 extending from a body 135 along a top edge 105c and a bottom edge 105d. A second internal electrode layer 115 includes lead connectors 140, 150 extending from a body 145 along a top edge and a bottom edge. The lead connectors 120, 130 on the top edge and the bottom edge of the first internal electrode layer 105 can be aligned in the vertical direction. That is, the lateral edges 121, 122 of a first lead connector 120 along a top edge 105c can be aligned with the lateral edges 131, 132 of a first lead connector 130 along a bottom edge 105d opposite to the top edge 105c. Additionally, these lateral edges 121, 131 can be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that the two lateral edges 121, 122 of the first lead connector 120 along a top edge 105c can be aligned with the lateral edges 131, 132 of a first lead connector 130 along a bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 122, 132 can be aligned and offset the same distance from the side edge 105a to 105b along a bottom edge 105d and a top edge 105c. Similarly, the lead connectors 140, 150 on the top edge and the bottom edge of the second internal electrode layer 115 can be aligned in the vertical direction. That is, the lateral edges 141, 142 of a first lead connector 140 along a top edge can be aligned with the lateral edges 151, 152 of a first lead connector 150 along a bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead connector 140 along a top edge can be aligned with the lateral edges 151, 152 of a first lead connector 150 along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead connector on a top edge and a first lead connector on a bottom edge as mentioned with respect to the internal electrode layer 105 can also be applied to the internal electrode layer 115. With this configuration, a gap can be formed between the lead connector 120 of the first internal electrode layer 105 and the lead connector 140 of the second internal electrode layer 115. Similarly, a gap can be formed between the lead connector 130 of the first internal electrode layer 105 and the lead connector 150 of the second internal electrode layer 115. The size of each respective gap can be substantially the same.

[0071] The lead joints 120 and 140 can be arranged in parallel with the lead joints 130 and 150 respectively, and they extend from the internal electrode layers 105 and 115, such that the lead joints extending from the alternating electrode layers 105 and 115 can be aligned in a respective row. For example, the lead joints 120 and 130 of the internal electrode layer 105 can be arranged in a respective stacked configuration, and the lead joints 140 and 150 of the internal electrode layer 115 can be arranged in a respective stacked configuration.

[0072] It should be understood that the lead joint 120 is connected to the external terminal 12, and the lead joint 140 is connected to the external terminal 14. Thus, the respective lead joints 120 will finger with the respective lead joints 140 in a manner similar to that of the external terminals 12 and 14. The fingered lead joints can provide multiple adjacent current injection points onto the associated main electrode portion.

[0073] The distance between adjacent exposed lead joints of the internal electrode layer in a given row can be specifically designed to help ensure the formation of the terminals. The distance between the exposed lead joints of the internal electrode layer in a given row can be (for example) in the range from about 0.25 μm to about 10 μm, in some embodiments from about 0.5 μm to about 5 μm, and in some embodiments from about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of the electrode joints can be (but is not limited to) at least twice the distance between adjacent lead joints in a given row to ensure that different terminals do not operate together. In some embodiments, the distance between adjacent columnar stacks of the exposed metal plating can be about 4 times the distance between adjacent exposed electrode joints in a particular stack. However, this distance can vary depending on the desired capacitance performance and the circuit board configuration. For example, the distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm, as determined based on the center points of the respective lead joints or based on the distance between adjacent lateral edges of the lead joints. Additionally, this distance can correspond to the ball pitch distance on a ball grid array.

[0074] In the embodiments depicted in FIGS. 4A to 4B, the capacitor contains two external terminals that extend to the ends of the capacitor. However, this is by no means necessary. Referring to FIGS. 5A to 5C, for example, an embodiment of a capacitor 10 is shown, in which a first external terminal 12, a second external terminal 14, and third and fourth external terminals (not shown) do not extend to an end of the capacitor. To help achieve this configuration in this particular embodiment, the capacitor 10 contains internal electrode layers 110, which include a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 may extend to an upper surface of the capacitor 10 and the second internal electrode layer 115 extends to a lower surface of the capacitor. The extensions assist in forming the external terminals. In this regard, the internal electrode layers may be exposed on the upper and lower surfaces of the capacitor and allow for connection between the main body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105, 115 extend to an edge of a dielectric layer and allow for the formation of the external terminals. The lateral or side edges of the internal electrode layers 105, 115 may be aligned in the vertical direction. That is, a lateral edge of a first internal electrode layer 105 may be aligned with a lateral edge of a second internal electrode layer 115. In one embodiment, the two lateral edges may be aligned. In another embodiment, a contact point of a first internal electrode layer 105 with an external terminal may be aligned with a contact point of a second internal electrode layer 115 with an external terminal. Additionally, the capacitor 10 of FIG. 5A includes at least one first polarity terminal and at least one second and opposite polarity terminal on an upper surface. Although not shown, the lower surface includes at least one first polarity terminal and a second and opposite terminal.

[0075] In the embodiments illustrated in FIGS. 4A-4B and FIGS. 5A-5C, the capacitor contains two external terminals on each surface. However, as indicated above, the present invention is not limited to the number of external terminals and / or the number of lead joints extending from a top edge and / or a bottom edge. Referring to FIGS. 6A and 6B, for example, a capacitor 20 is shown having a 1×4 array configuration and thus containing four external terminals on each surface. That is, the capacitor includes four terminals in two dimensions along the upper and lower surfaces. In this regard, the capacitor includes a total of four external terminals on an upper surface (i.e., first external terminals 22a and 22b and second external terminals 24a and 24b) and a corresponding set of third and fourth external terminals (not shown) on a lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). The capacitor 20 generally also has a thickness "T", a width "W" and a length "L" as described above, and the widths "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the ranges discussed above. Although not at all necessary, a void 1350 can also be formed in the capacitor 20 between the external terminals 22a, 24b, 22b and / or 24a, as described above.

[0076] The capacitor 20 also includes internal electrode layers 210, which contain a first internal electrode layer 205 and a second internal electrode layer 215 arranged in an alternating configuration. The internal electrode layers 205, 215 include at least one lead joint 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b extending from a top edge and a bottom edge of the main body of the internal electrode layer. The lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b can be exposed on the upper and lower surfaces of the capacitor and allow connection between the main body of the internal electrode layer and the external terminals. For example, the lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b can contain leading edges 223a to 223b, 233a to 233b, 243a to 243b, 253a to 253b that extend to an edge of a dielectric layer and allow the formation of external terminals. The internal electrode layers 205, 215 include at least two lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b along a top edge and a bottom edge. A first internal electrode layer 205 includes two lead joints 220a to 220b, 230a to 230b extending along each top edge 205c and bottom edge 205d and from the main body 235. A second internal electrode layer 215 includes two lead joints 240a to 240b, 250a to 250b extending along each top edge, bottom edge and from the main body 245.

[0077] The lead joints 220a to 220b and 230a to 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of a first lead joint 220a along a top edge 205c can be aligned with the lateral edges 231a, 232a of a first lead joint 230a along a bottom edge 205d opposite to the top edge 205c. Additionally, these lateral edges 221a, 231a can be aligned with the side edge 205a of the internal electrode layer 205. However, it should be understood that the two lateral edges 221a, 222a of the first lead joint 220a along a top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead joint 230a along a bottom edge 205d opposite to the top edge 205c. In other words, the two lateral edges 222a, 232a can be offset by the same distance from the side edge 205a to 205b along a bottom edge 205d and a top edge 205c. Furthermore, the lateral edges 221b, 222b of the second lead joint 220b along a top edge 205c can be aligned with the lateral edges 231b, 232b of the second lead joint 230b along a bottom edge 205d opposite to the top edge 205c. When a top edge 205c and a bottom edge 205d contain at least two lead joints 220a to 220b and 230a to 230b, at least one lateral edge of each lead joint on a top edge 205c can be aligned with a corresponding lateral edge of a lead joint on the bottom edge 205d. Additionally, the two lateral edges of each lead joint on a top edge 205c can be aligned with the corresponding lateral edges of the lead joints on the bottom edge 205d. Similarly, the lead joints 240a to 240b and 250a to 250b on the top edge and the bottom edge of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of a first lead joint 240a along a top edge can be aligned with the lateral edges 251a, 252a of a first lead joint 250a along a bottom edge opposite to the top edge, and the lateral edges 241b, 242b of a second lead joint 240b along a top edge can be aligned with the lateral edges 251b, 252b of a second lead joint 250b along a bottom edge opposite to the top edge.

[0078] The two lateral edges 241a, 242a of the first lead joint 240 along a top edge can be aligned with the lateral edges 251a, 252a of a first lead joint 250 along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead joint on a top edge and a first lead joint on a bottom edge mentioned with respect to the internal electrode layer 205 can also be applied to the internal electrode layer 215. With this configuration, a gap can be formed between any of the lead joints along the top edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead joints 220a to 220b, 240a to 240b extending from the top edge of the respective internal electrode layer. Additionally, a gap can be formed between any of the lead joints along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead joints 230a to 230b, 250a to 250b extending from the top edge of the respective internal electrode layer. Furthermore, the size of a gap between two respective joints extending from a top edge (whether from the same internal electrode layer or adjacent internal electrode layers) can be substantially the same as the size of a gap between two corresponding respective joints extending from a bottom edge. For example, the gap between the lead joints 220a and 220b can be substantially the same as the gap between the lead joints 230a and 230b. Similarly, the gap between the lead joints 220a and 240a can be substantially the same as the gap between the lead joints 230 and 250a.

[0079] Any or all of the lead joints 220a to 220b, 240a to 240b can be arranged in parallel with the lead joints 230a to 230b, 250a to 250b respectively, which extend from the layers 205 and 215, such that the leads extending from the alternating electrode layers 205 and 215 can be aligned in a respective row. For example, the lead joints 220a to 220b and 230a to 230b of the internal electrode layer 205 can be arranged in a respective stacked configuration, and the lead joints 240a to 240b and 250a to 250b of the internal electrode layer 215 can be arranged in a respective stacked configuration. It should be understood that the lead joints 220a to 220b are respectively connected to the external terminals 22a to 22b, and the lead joints 240a to 240b are respectively connected to the external terminals 24a to 24b. Thus, the respective lead joints 220a to 220b will be finger-crossed with the respective lead joints 240a to 240b in a manner similar to that of the external terminals 22a to 22b and 24a to 24b. The finger-crossed lead joints can provide multiple adjacent current injection points onto the associated main electrode portion.

[0080] In the embodiments discussed above, the external terminals are arranged in a single dimension in a linear manner (e.g., 1×2 or 1×4 configuration). Of course, it should be understood that a multi-dimensional array of external terminals can also be employed. Referring to FIGS. 7A through 7D, for example, a particular embodiment of a capacitor 10 having a 2×2 array configuration is shown. In this configuration, the capacitor includes a total of four external terminals (a first external terminal 12 and a second external terminal 14) on an upper surface and a corresponding number of external terminals (a third and a fourth external terminal, not shown) on a lower surface. The first external terminal 12 and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not at all necessary, a gap 1350 can also be formed in the capacitor 10 between the external terminals 12 and 14, as described above.

[0081] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, which include a first internal electrode layer 105 and a second internal electrode layer 115 in an alternating configuration. Similar to the embodiments discussed in FIGS. 4A through 4B above, the internal electrode layers 105, 115 also include at least one lead joint 120, 130, 140, 150 extending from a top edge and a bottom edge of a body of the internal electrode layer. However, contrary to the internal electrodes of FIGS. 4A through 4B, a lateral edge 121, 122 of a first lead joint 120 along a top edge 105c can be aligned with a lateral edge 131, 132 of a first lead joint 130 along a bottom edge 105d that is opposite to the top edge 105c. In other words, a lateral edge 121, 122 of a first lead joint 120 along a top edge 105c can be offset (indicated by "O") from one side edge 105a to 105b by the same distance as a lateral edge 131, 132 of a first lead joint 130 along a bottom edge 105d that is opposite to the top edge 105c. However, it should be understood that two lateral edges 121, 122 of the first lead joint 120 along a top edge 105c can be aligned with the lateral edges 131, 132 of a first lead joint 130 along a bottom edge 105d that is opposite to the top edge 105c. In other words, two lateral edges 121, 122 of a first lead joint 120 along a top edge 105c can be offset from one side edge 105a to 105b by the same distance as two lateral edges 131, 132 of a first lead joint 130 along a bottom edge 105d that is opposite to the top edge 105c.

[0082] Similarly, the lead joints 140 and 150 on the top edge and the bottom edge of the second internal electrode layer 115 can be aligned in the vertical direction. That is, the lateral edges 141 and 142 of a first lead joint 140 along a top edge can be aligned with the lateral edges 151 and 152 of a first lead joint 150 along a bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141 and 142 of the first lead joint 140 along a top edge can be aligned with the lateral edges 151 and 152 of a first lead joint 150 along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead joint on a top edge and a first lead joint on a bottom edge mentioned with respect to the internal electrode layer 105 can also be applied to the internal electrode layer 115. With this configuration, a gap can be formed between the lead joint 120 of the first internal electrode layer 105 and the lead joint 140 of the second internal electrode layer 115. A gap can be formed between the lead joint 130 of the first internal electrode layer 105 and the lead joint 150 of the second internal electrode layer 115. The size of each respective gap can be substantially the same.

[0083] The lead joints 120 and 140 can be arranged in parallel with the lead joints 130 and 150 respectively, which extend from the internal electrode layers 105 and 115, such that the lead joints extending from the alternating electrode layers 105 and 115 can be aligned in each respective row. For example, the lead joints 120 and 130 of the internal electrode layer 105 can be arranged in a respective stacked configuration, and the lead joints 140 and 150 of the internal electrode layer 115 can be arranged in a respective stacked configuration. It should be understood that the lead joint 120 is connected to the external terminal 12, and the lead joint 140 is connected to the external terminal 14. Accordingly, the respective lead joint 120 will finger with the respective lead joint 140 in a manner similar to the external terminals 12 and 14. The fingered lead joints can provide a plurality of adjacent current injection points onto the associated main electrode portion.

[0084] As shown in FIG. 7D, the plurality of groups 110a and 110b of the internal electrode layer 110 can be used to form the external terminal array shown in FIG. 7A. Generally, the distance "t" between the groups 110a and 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" can be (but is not limited to) at least 2 times (in some embodiments at least about 3 times and in embodiments from about 4 times to about 8 times) the distance between adjacent lead joints in a given row to ensure that different terminals do not operate together.

[0085] Referring to FIGS. 8A through 8D, an embodiment of a capacitor 20 having a 2×4 array configuration is shown. In this configuration, the capacitor includes a total of eight external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) on the upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not at all necessary, voids 1350 may also be formed in the capacitor 20 between the external terminals 22a, 22b, 24a, and / or 24b, as described above.

[0086] The capacitor 20 also includes alternating internal electrode layers 210 of two sets 210a and 210b, as depicted in FIG. 8D. As shown in FIGS. 8B and 8C, the alternating dielectric layers and internal electrode layers 210 of each set include a first internal electrode layer 205 and a second internal electrode layer 215 in an alternating configuration. The internal electrode layers 205, 215 include at least one lead joint 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b extending from a top edge and a bottom edge of the body of the internal electrode layer. The lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and assist in forming the external terminals. In this regard, the lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b may be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b may include leading edges 223a to 223b, 233a to 233b, 243a to 243b, 253a to 253b that extend to an edge of a dielectric layer and allow the formation of the external terminals. The internal electrode layers 205, 215 include at least two lead joints 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b along a top edge and a bottom edge. A first internal electrode layer 205 includes two lead joints 220a to 220b, 230a to 230b along each top edge 205c and bottom edge 205d and extending from the body 235. A second internal electrode layer 215 includes two lead joints 240a to 240b, 250a to 250b along each top edge, bottom edge and extending from the body 245.

[0087] The lead connectors 220a to 220b, 230a to 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of a first lead connector 220a along a top edge 205c can be aligned with the lateral edges 231a, 232a of a first lead connector 230a along a bottom edge 205d opposite to the top edge 205c. In other words, the lateral edges 221a, 222a of a first lead connector 220a along a top edge 205c can be offset (indicated by "O") from one side edge 205a to 205b by the same distance as the lateral edges 231a, 232a of a first lead connector 230a along a bottom edge 205d opposite to the top edge 205c. In addition, the two lateral edges 221a, 222a of the first lead connector 220a along a top edge 205c can be aligned with the lateral edges 231a, 232a of a first lead connector 230 along a bottom edge 205d opposite to the top edge 205c. That is, the two lateral edges can be offset from one side edge 205a to 205b by the same distance. When a top edge 205c and a bottom edge 205d contain at least two lead connectors 220a to 220b, 230a to 230b, at least one lateral edge of each lead connector on a top edge 205c can be aligned with a corresponding lateral edge of a lead connector on the bottom edge 205d. In addition, the two lateral edges of each lead connector on a top edge 205c can be aligned with the corresponding lateral edges of the lead connectors on the bottom edge 205d.

[0088] Similarly, the lead joints 240a to 240b and 250a to 250b on the top and bottom edges of the second electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of a first lead joint 240a along a top edge can be aligned with the lateral edges 251a, 252a of a first lead joint 250a along a bottom edge opposite to the top edge. The two lateral edges 241a, 242a of the first lead joint 240a along a top edge can be aligned with the lateral edges 251a, 252a of the first lead joint 250a along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead joint on a top edge and a first lead joint on a bottom edge mentioned with respect to the internal electrode layer 205 can also be applied to the internal electrode layer 215. With this configuration, a gap can be formed between any of the lead joints along the top edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead joints 220a to 220b, 240a to 240b extending from the top edge of their respective internal electrode layers. Additionally, a gap can be formed between any of the lead joints along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead joints 230a to 230b, 250a to 250b extending from the bottom edge of their respective internal electrode layers. Furthermore, the size of a gap between two respective joints extending from a top edge (whether from the same internal electrode layer or adjacent internal electrode layers) can be substantially the same as the size of a gap between two corresponding respective joints extending from a bottom edge. For example, the gap between lead joints 220a and 220b can be substantially the same as the gap between lead joints 230a and 230b. Similarly, the gap between lead joints 220a and 240a can be substantially the same as the gap between lead joints 230 and 250a.

[0089] Any or all of the lead joints 220a to 220b, 240a to 240b can be arranged in parallel with the lead joints 230a to 230b, 250a to 250b respectively, which extend from the layers 205 and 215, so that the leads extending from the alternating electrode layers 205 and 215 can be aligned in respective rows. For example, the lead joints 220a to 220b and 230a to 230b of the internal electrode layer 205 can be arranged in a respective stacked configuration, and the lead joints 240a to 240b and 250a to 250b of the internal electrode layer 215 can be arranged in a respective stacked configuration. It should be understood that the lead joints 220a to 220b are respectively connected to the external terminals 22a to 22b, and the lead joints 240a to 240b are respectively connected to the external terminals 24a to 24b. Therefore, the respective lead joints 220a to 220b will finger with the respective lead joints 240a to 240b in a manner similar to that of the external terminals 22a to 22b and 24a to 24b. The fingered lead joints can provide multiple adjacent current injection points onto the associated main electrode portion.

[0090] As shown in FIG. 8D, the groups 210a and 210b of the internal electrode layer 110 can be used to form the external terminal array shown in FIG. 8A. Generally, the distance "t" between the groups 110a and 110b ranges from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" can be (but is not limited to) at least 2 times (in some embodiments at least about 3 times and in embodiments from about 4 times to about 8 times) the distance between adjacent lead joints in a given row to ensure that different terminals do not operate together.

[0091] Referring to FIGS. 9A to 9B, an embodiment of a capacitor 30 having a 4×4 array configuration is shown. In this configuration, the capacitor includes a total of sixteen external terminals (first external terminals 32a, 32b and second external terminals 34a, 34b) on the upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on the lower surface. The first external terminals 32a, 32b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not at all necessary, voids 1350 may also be formed in the capacitor 30 between the external terminals 32a, 32b, 34a and / or 34b, as described above. The capacitor 30 also contains an internal electrode layer 210 configured into four groups 210a, 210b, 210c and 210d, as depicted in FIG. 9B. Similar to the embodiments discussed above, the distances "t1", "t2" and / or "t3" between the groups can be from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distances "t1", "t2" and / or "t3" can be (but are not limited to) at least 2 times (in some embodiments at least about 3 times, and in embodiments from about 4 times to about 8 times) the distance between adjacent lead joints in a given row to ensure that different terminals do not operate together.

[0092] In the embodiments referred to above, the internal electrode layer is generally oriented in a vertical configuration. Of course, this is not at all necessary and other geometric configurations, such as a horizontal configuration, are equally suitable. Referring to FIGS. 10A to 10C, for example, a capacitor 20 is shown having a 4×4 configuration similar to the external terminals 32 and 34 of FIGS. 9A to 9B, but employing a horizontal internal electrode configuration. That is, as shown in FIGS. 10B to 10C, the capacitor 20 includes a plurality of internal electrode layers 205 and 215 and a plurality of dielectric layers in an alternating arrangement, where the electrode layers are interleaved with a dielectric layer located between each adjacent electrode layer in an opposing and spaced relationship. The internal electrode layers are electrically connected to an external terminal through conductive paths (such as a first conductive path 225 and a second conductive path 285). The conductive paths extend to an upper surface 235 of the capacitor and a lower surface 245 of the capacitor. In this regard, the conductive paths may be exposed on the upper surface 235 and the lower surface 245 of the capacitor. The exposure can assist in forming the external terminals on the upper surface 235 and the lower surface 245 of the capacitor. Additionally, the internal electrode layers 205 and 215 have a rectangular configuration and are arranged such that they do not extend to a side surface of the capacitor.

[0093] Optionally, capacitor 20 may also include a first shielding region 255 and a second shielding region 265, and each of the shielding regions may include one or more shielding electrode layers 275. As shown, the shielding regions are disposed above and below the active electrode regions and the active electrode layers 205, 215. FIG. 10C similarly illustrates the use of a first anchoring electrode 305 and a second anchoring electrode 295. The first anchoring electrode 305 is disposed in the first active electrode layer 205 with the first active electrode. In this regard, the first active electrode is electrically connected to the first conductive path 225, while the first anchoring electrode is connected to the second conductive path 285. Similarly, the second anchoring electrode 295 is disposed in the second active electrode layer 215 with the second active electrode. In this regard, the second active electrode is electrically connected to the second conductive path 285, while the second anchoring electrode is connected to the first conductive path 225.

[0094] The first conductive path 225 extends through and electrically contacts the first plurality of internal electrode layers 205. However, the first conductive path 225 extends through a non-contact hole 105, where a gap 105 is formed between the first conductive path 225 and the electrodes of the second plurality of internal electrode layers 215. This gap 105 allows the second plurality of internal electrode layers 215 to be insulated from the first conductive path 225. Similarly, the second conductive path 285 extends through and electrically contacts the second plurality of internal electrode layers 215. However, the second conductive path 285 extends through a non-contact hole 115, where a gap 115 is formed between the second conductive path 285 and the electrodes of the first plurality of internal electrode layers 205. This gap 115 allows the first plurality of internal electrode layers 205 to be insulated from the second conductive path 285. When the anchoring (or dummy) electrodes are presented as shown in FIG. 10C, these layers also include gaps 125 and 135. The first conductive path 225 extends through and electrically contacts the first plurality of internal electrode layers 205 and contacts the second anchoring joint 295. However, the second anchoring joint 295 is isolated from the active electrodes of the second plurality of internal electrode layers 215 via a gap 125 formed between the anchoring joint 295 and the active electrode 215. This gap 125 allows the second plurality of internal electrode layers 215 to be insulated from the second anchoring joint 295 and the first conductive path 225.

[0095] The dielectric layer of the decoupling capacitor described herein is typically formed of a ceramic material. The ceramic material may have a relatively high dielectric constant. For example, the dielectric constant may be 3 or more, in some embodiments from about 10 to about 20,000, in some embodiments from about 50 to about 10,000, in some embodiments from about 60 to about 9,000, and in some embodiments from about 80 to about 8,000. Particular suitable examples of ceramic materials having a high dielectric constant are designated as NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V based on the standard classification established by the Electronic Industries Alliance (EIA). These materials may include perovskites such as barium titanate ceramic materials (such as barium titanate, strontium barium titanate, calcium barium titanate, barium zirconate titanate, strontium barium zirconate titanate, calcium barium zirconate titanate, etc.), lead titanate ceramic materials (such as lead zirconate titanate, lanthanum lead zirconate titanate), bismuth sodium titanate, and so on. In one particular embodiment, for example, strontium barium titanate of the formula Ba xSr 1-xTiO 3 (“BSTO”) may be employed, where x ranges from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials may include (for example): Ba xCa 1-xTiO 3, where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; barium calcium zirconate titanate (BaCaZrTiO 3); A[B1 1 / 3B2 2 / 3]O 3 materials, where A is Ba xSr 1-x (x can be a value from 0 to 1), B1 is Mg yZn 1-y (y can be a value from 0 to 1), and B2 is Ta zNb 1-z (z can be a value from 0 to 1); and so on. Other suitable ceramic materials may include (for example): Pb xZr 1-xTiO 3 (“PZT”), where x ranges within from about 0.05 to about 0.4; lanthanum lead zirconate titanate (“PLZT”); lead titanate (PbTiO 3); and so on.

[0096] The internal electrode layer can be formed of any of various different metals known in the art. The internal electrode layer can be made of a metal, such as a conductive metal. The material can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and so on, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloy and respective sputtered layers of chromium, nickel, and gold can also be suitable. In one particular embodiment, the internal electrode layer can include nickel or an alloy thereof. Similarly, the external terminal can be formed of any of various different metals known in the art. The external terminal can be made of a metal, such as a conductive metal. The material can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and so on, as well as various combinations thereof. In one particular embodiment, the external terminal can include copper or an alloy thereof. The external terminal can have an average thickness of about 100 μm or less, in some embodiments from about 1 μm to about 70 μm, and in some embodiments from about 5 μm to about 50 μm.

[0097] The external terminal can be formed using any method generally known in the art. The external terminal can be formed using techniques such as sputtering, brushing, printing, electroless plating or fine copper terminal (FCT), electroplating, plasma deposition, propellant spraying / airbrushing, and so on. The external terminal can be formed such that the external terminal is a thin film electroplating of a metal. This thin film electroplating can be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an internal electrode layer. For example, a leading edge of an internal electrode layer can be exposed such that it allows the formation of a plated terminal. A plated terminal can be formed using techniques known in the art, such as electroless plating, electrolytic electroplating, or a combination thereof. When multiple layers are used to form an external terminal, the external terminal can include an electroplated layer and an electroless plated layer. For example, electroless plating can first be used to deposit an initial material layer. The electroplating technique can then be switched to an electrochemical electroplating system that allows for faster material deposition. When forming a plated terminal using any electroplating method, a leading edge of a lead joint of the internal electrode layer exposed from the body of the capacitor is subjected to a plating solution. In one embodiment, by being subjected, the capacitor can be immersed in the plating solution.

[0098] The electroplating solution used in an electroplating process may include a conductive material, such as a conductive metal. For example, the electroplating solution may be a nickel sulfamate plating solution or other nickel solution, such that the electroplated layer and the external terminals include nickel. Alternatively, the electroplating solution may be a copper acid bath or other suitable copper solution, such that the electroplated layer and the external terminals include copper. Additionally, it should be understood that the electroplating solution may contain other additives generally known in the art. For example, the additives may include other organic additives and media that can assist in the electroplating process. Additionally, the additives can be used to employ an electroplating solution at a desired pH level. In one embodiment, a drag-reducing additive can be employed in the solution to assist in the complete electroplating coverage of the electroplating material and the bonding to the exposed leading edge of the lead joint of the capacitor and the internal electrode layer. The capacitor can be exposed, submerged, or immersed in the electroplating solution for a predetermined amount of time. The exposure time is not necessarily limited, but can be an amount of time sufficient to allow for the deposition of sufficient electroplating material to form the electroplated terminals. In this regard, the time should be sufficient to allow for the formation of a continuous connection between the desired exposed adjacent leading edges of the lead joints of a given polarity of the respective internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[0099] The difference between electrolytic electroplating and electroless electroplating is that electrolytic electroplating employs an electrical bias, such as by using an external power source. The electrolytic electroplating solution typically can be subjected to a high current density range, such as 10 amp / ft 2 to 15 amp / ft 2 (rated at 9.4 volts). A connection can be formed by a negative connection to the capacitor that needs to form the electroplated terminals and a positive connection to a solid material (such as Cu in a Cu electroplating solution) in the same electroplating solution. That is, the capacitor is biased to a polarity opposite to that of the electroplating solution. Using this method, the conductive material of the electroplating solution is attracted to the metal of the exposed leading edge of the lead joint of the internal electrode layer.

[0100] Before submerging or subjecting the capacitor to an electroplating solution, various pretreatment steps can be employed. These steps can be carried out for various purposes, including for catalysis, for acceleration, and / or for promoting the adhesion of the electroplating material to the leading edge of the lead joint. Additionally, an initial cleaning step can be employed before electroplating or any other pretreatment step. This step can be used to remove any oxide deposits formed on the exposed lead joints of the internal electrode layer. The cleaning step can be particularly helpful in assisting in the removal of any deposits of nickel oxide when the internal electrodes or other conductive components are formed of nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning bath, such as a pre-cleaning bath containing an acidic cleaner. In one embodiment, the exposure can be for a predetermined time, such as about 10 minutes. Cleaning can alternatively be achieved by a chemical polishing or grinding step.

[0101] Additionally, a step of activating the exposed metal leading edge of the lead joint for the internal electrode layer that can be executed is to promote the deposition of the conductive material. Activation can be achieved by immersion in a palladium salt, photopatterning of a palladium organometallic precursor (via a mask or laser), screen printing or inkjet deposition of a palladium compound, or electrophoretic palladium deposition. It should be understood that palladium-based activation is currently only disclosed as one example of an activation solution, and the activation solution generally well activates the exposed joint portion formed of nickel or its alloy. However, it should be understood that other activation solutions can also be utilized and thus not necessarily limited. Additionally, instead of or in addition to the foregoing activation step, an activation dopant can be introduced into the conductive material when forming the internal electrode layer of the capacitor. For example, when the internal electrode layer includes nickel and the activation dopant includes palladium, the palladium dopant can be introduced into the nickel ink or composition for forming the internal electrode layer. Thereby, the palladium activation step can be eliminated. It should be further understood that some of the above activation methods (such as organometallic precursors) are also suitable for co-depositing glass formers to increase adhesion to the general ceramic body of the capacitor. When the activation step is employed as described above, a trace amount of activator material can typically remain at the exposed conductive portion before and after the terminal plating. Additionally, a post-treatment step after plating can also be employed according to desire or need. These steps can be carried out for various purposes, including enhancing and / or improving the adhesion of the material. For example, a heating (or annealing) step can be employed after the plating step is executed. This heating can be carried out via baking, exposure to a laser, UV exposure, microwave exposure, arc welding, etc.

[0102] Therefore, as described above, the external terminals employed in the capacitor can contain at least one plating layer. In one embodiment, the external terminal can contain only one plating layer. However, it should be understood that the external terminal can include a plurality of plating layers. For example, the external terminal can include a first plating layer and a second plating layer. Additionally, the external terminal can also include a third plating layer. Moreover, the materials of these plating layers can be any of the foregoing materials and are generally known in the art. For example, one plating layer (such as a first plating layer) can contain copper or its alloy. Another plating layer (such as a second plating layer) can contain nickel or its alloy. Alternatively, another plating layer (such as the second plating layer) can contain copper or its alloy. Another plating layer (such as a third plating layer) can include tin, lead, gold, or a combination, such as an alloy. Alternatively, an initial plating layer can contain nickel, followed by a plating layer of tin or gold. In another embodiment, an initial copper plating layer can be formed and then a nickel layer.

[0103] In one embodiment, the initial or first plating layer can be a conductive metal (such as copper). This area is then covered with a second layer containing a resistive polymeric material for sealing. The area is then polished to selectively remove the resistive polymeric material and then electroplated again with a third layer containing a conductive metal material (such as copper). The aforementioned second layer above the initial plating layer can correspond to a solder mask layer, such as a nickel solder mask layer. In some embodiments, the aforementioned layer can be formed by electroplating an additional metal (such as nickel or copper) layer on top of an initial electroless or electrolytic plating layer (such as electroplated copper). Other exemplary materials for the aforementioned solder mask layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the aforementioned solder mask layer can correspond to a conductive layer, such as electroplated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable electroplated solder. Additionally, an electroplating step can be performed after forming a metal plating layer to provide a resistive alloy or a higher-resistance metal alloy coating on this metal plating, such as electroless Ni-P alloy. However, it should be understood that any metal coating that one of ordinary skill in the art would understand from the complete disclosure herein can be included. It should be understood that any of the aforementioned steps can occur as a bulk process, such as barrel plating, fluidized bed plating, and / or through-hole plating termination procedures, all of which are generally known in the art. These bulk processes are capable of simultaneously processing multiple components to provide an efficient and rapid termination procedure. This is a particular advantage over conventional termination methods, such as thick film terminal printing that requires individual component processing. V. MULTILAYER STRUCTURE

[0104] Multilayer structures (such as two or more electronic components) can be placed between the interlayers and stacked along a stacking direction to form a multilayer structure. The components can include capacitors (including, but not limited to, decoupling capacitors as described herein), resistors, varistors, inductors, transistors, diodes, transformers, sensors, electrostatic discharge devices, memory devices, radio frequency devices, low noise amplifiers, power amplifiers, power management devices, antennas, microelectromechanical systems (such as MEMS devices), parasitic elements, or the like. It should be understood that the interlayers of the multilayer structure can be different and separate from the aforementioned interlayers, which can refer to a component interlayer.

[0105] The multilayer structure can facilitate the formation of a filter or a complex structure (such as a combination of two or more electronic components electrically connected to each other), as an example, which realizes radio frequency (RF) integration. For example, a plurality of interlayers and a plurality of electronic components can be stacked along a stacking or vertical direction to form a module that can be tested for fit, form, and / or function before being assembled with other components, which can improve the yield of the final product. These modules can improve the functionality of the final product, facilitate the integration of electronic components into a microelectronic assembly, and / or improve the yield of the final product.

[0106] Generally, a multilayer structure includes a plurality of interposer layers and a plurality of electronic components disposed between the plurality of interposer layers. The plurality of interposer layers and the plurality of electronic components are disposed in at least two layers, each layer including at least one of the plurality of electronic components disposed between two of the plurality of interposer layers, and the at least two layers are stacked adjacent to each other such that one of the plurality of interposer layers is shared by adjacent layers of the at least two layers.

[0107] For example, referring to FIG. 11, a layer 950 of a multilayer structure 900 (FIGS. 12A to 13E) includes a first interposer layer 902a, a second interposer layer 902b, and an electronic component 904 disposed between the first interposer layer 902a and the second interposer layer 902b. For example, the first interposer layer 902a, the electronic component 904, and the second interposer layer 902b are stacked together along a stacking or thickness direction Z such that the electronic component 904 is sandwiched between the first interposer layer 902a and the second interposer layer 902b. The first interposer layer 902a has a first surface 906 and an opposing second surface 908; the second surface 908 opposes the first surface 906 along the stacking direction Z. Similarly, the second interposer layer 902b has a first surface 906 and an opposing second surface 908 that opposes the first surface 906 along the stacking direction Z. The electronic component 904 has a first surface 910 and an opposing second surface 912 that opposes the first surface 910 along the stacking direction Z. The electronic component 904 is positioned between the first interposer layer 902a and the second interposer layer 902b such that the first surface 910 of the electronic component 904 is adjacent to the second surface 908 of the first interposer layer 902a and the second surface 912 of the electronic component is adjacent to the first surface 906 of the second interposer layer 902b.

[0108] Referring to FIGS. 12A to 13E, a plurality of layers 950 are stacked along a stacking direction Z to form a multilayer structure 900. For example, a plurality of interposer layers 902 and a plurality of electronic components 904 are disposed in at least two layers 950 to form the multilayer structure 900. Further, each layer 950 may include one or more electronic components 904 such that the multilayer structure 900 includes a plurality of electronic components 904. For example, as shown in FIGS. 12A to 12C, each layer 950 may include a single electronic component 904, and two or more layers 950 are stacked together such that the multilayer structure 900 includes two or more electronic components 904, such as two, three, four, or more electronic components 904, and the number of electronic components corresponds to the number of layers 950. As other examples, referring to FIGS. 13A to 13E, each layer 950 may include a plurality of electronic components 904, which may be positioned adjacent to each other along a transverse direction X (FIG. 13E), a longitudinal direction Y, or both. The plurality of electronic components 904 within a single layer 950 may be spaced apart from each other, or two or more of the electronic components 904 may be in contact with each other. In addition, it should be understood that each of the transverse direction X and the longitudinal direction Y is perpendicular to the stacking direction Z, and the transverse direction X is perpendicular to the longitudinal direction Y.

[0109] As further illustrated in FIGS. 12A to 13E, at least two layers 950 of the multilayer structure 900 are stacked adjacent to each other such that one interposer layer 902 is shared by adjacent layers of at least two layers 950. For example, with particular reference to FIG. 12A, a multilayer structure 900 may include a first layer 950a, a second layer 950b, a third layer 950c, and a fourth layer 950d. The first layer 950a, the second layer 950b, the third layer 950c, and the fourth layer 950d are stacked adjacent to each other along the stacking direction Z, which may be a vertical direction when the multilayer structure 900 is incorporated into a product such as a microelectronic component as described herein. In the embodiment depicted in FIG. 12A, the first layer 950a includes a first interposer layer 902a, a second interposer layer 902b, and an electronic component 904. The second layer 950b includes the second interposer layer 902b, a third interposer layer 902c, and an electronic component 904. The third layer 950c includes the third interposer layer 902c, a fourth interposer layer 902d, and an electronic component 904. The fourth layer 950d includes the fourth interposer layer 902d, a fifth interposer layer 902e, and an electronic component 904. Thus, the second interposer layer 902b is shared by the first layer 950a and the second layer 950b, the third interposer layer 902c is shared by the second layer 950b and the third layer 950c, and the fourth interposer layer 902d is shared by the third layer 950c and the fourth layer 950d.

[0110] Referring to FIG. 13A, the illustrated embodiment includes two layers 950. The first layer 950a includes a first intermediate layer 902a, a second intermediate layer 902b, and a first set 952a of electronic components 904 disposed between the first intermediate layer 902a and the second intermediate layer 902b. The second layer 950b includes the second intermediate layer 902b, a third intermediate layer 902c, and a second set 952b of electronic components 904 disposed between the second intermediate layer 902b and the third intermediate layer 902c. Thus, the second intermediate layer 902b is shared by the first layer 950a and the second layer 950b.

[0111] In the embodiment of FIG. 13A, each component 904 of the first set 952a of electronic components 904 is aligned with a respective one of the components 904 of the second set 952b of electronic components 904 along the stacking direction Z. In other embodiments, such as illustrated in FIG. 13C, the first layer 950a and the second layer 950b are stacked adjacent to each other along the stacking direction Z, and each component 904 of the first set 952a of electronic components 904 is offset from a respective one of the components 904 of the second set 9052b of electronic components 904 along a longitudinal direction Y.

[0112] As further shown in FIG. 13C, the multi-layer structure 900 includes a third layer 950c. The third layer 950c includes the third intermediate layer 902c, a fourth intermediate layer 902d, and a third set 952C of electronic components 904 disposed between the third intermediate layer 902c and the fourth intermediate layer 902d. Each electronic component 904 of the third set 952C of electronic components 904 is aligned with a respective one of the electronic components 904 of the first set 952a of electronic components 904 along the stacking direction Z. Thus, each electronic component 904 of the third set 952C of electronic components 904 is offset from a respective one of the electronic components 904 of the second set 952b of electronic components 904 along the longitudinal direction Y.

[0113] Returning to FIG. 12B, in at least some embodiments, the multi-layer structure 900 includes external terminals that can be used to electrically connect the multi-layer structure 900 to one or more external components, an assembly (such as the microelectronic assemblies described herein), or the like. For example, as shown in the exemplary embodiment of FIG. 12B, a first external terminal 920 is disposed on a first outer surface and a second external terminal 922 is disposed on a second outer surface opposite the first outer surface. In the depicted embodiment, the first outer surface is a first surface 906 of a first interposer 902a, and the second outer surface is a second surface 908 of a fifth interposer 902e. That is, two interposers 902 define the opposing outer surfaces of the multi-layer structure 900. However, in some embodiments, one or both of the outer surfaces may not be defined by an interposer 902. For example, referring to FIG. 12C, the first outer surface (on which the first external terminal 920 is disposed) is defined by the first surface 906 of the first interposer 902a, and the second outer surface (on which the second external terminal 922 is disposed) is defined by the second surface 912 of the electronic component 904 of the fourth layer 950d. It should be understood that the first outer surface and the second outer surface face away from the electronic component 904 of the multi-layer structure 900 and may be adjacent to and even in some embodiments contact one or more components or assemblies external to the multi-layer structure 900.

[0114] Referring to FIGS. 13A and 13B, the external terminals 920, 922 may also have other configurations. As shown in FIG. 13A, in addition to the two external terminals 920, 922 shown in FIGS. 12B and 12C, the multi-layer structure 900 may also include external terminals 920, 922. For example, a first external terminal 920 may be formed on the first surface 906 of the first interposer 902a at each electronic component 904 adjacent to the first interposer 902a, and a second external terminal 922 may be formed on the second surface 908 of the third interposer 902c at each electronic component 904 adjacent to the third interposer 902c, such that the multi-layer structure 900 includes a plurality of first external terminals 920 and a plurality of second external terminals 922. As another example, referring to FIG. 13B, although a plurality of electronic components 904 are adjacent to the first outer surface and the second outer surface (defined by the first surface 906 of the first interposer 902a and the second surface 908 of the third interposer 902c in the embodiment of FIG. 13B, respectively), the multi-layer structure 900 may include only one first external terminal 920 and only one second external terminal 922. In some embodiments, a single first external terminal 920 may define an input terminal of the multi-layer structure 900 and a single second external terminal 922 may define an output terminal of the multi-layer structure 900.

[0115] It should be understood that although the embodiments of FIGS. 12A, 13C, 13D, and 13E do not show the external terminals 920, 922, this omission is not intended to exclude the use of external terminals in these embodiments. Rather, the multilayer structure 900 may appropriately and / or as needed include one or more first external terminals 920 and one or more second external terminals 922 to electrically connect the multilayer structure 900 to one or more components or assemblies external to the multilayer structure 900. However, it should also be understood that the multilayer structure 900 may also be connected to one or more components or assemblies external to the multilayer structure 900 in other ways, such that not all embodiments need to include the external terminals 920, 922.

[0116] Referring to FIGS. 12B through 13B, in at least some embodiments, at least one of the plurality of intermediate layers 902 of the multilayer structure 900 includes at least one via 914 extending from a first surface 906 of at least one of the intermediate layers 902 to a second surface 908 of at least one of the intermediate layers 902. The (several) vias 914 may provide an electrical connection from at least one component 904 through the intermediate layer 902 to (for example) an external terminal 920, 922, to a component external to the multilayer structure 900, and / or to another component 904 of the multilayer structure 900. The (several) vias 914 may be lined or filled with a conductive material 916 (such as copper or the like) to provide an electrical contact through the intermediate layer 902. For example, the conductive material 916 of one via 914 may contact a terminal of an electronic component 904 and a terminal of a component external to the multilayer structure to electrically connect the electronic component 904 to the external component. As another example, the conductive material 916 of one via 914 may contact an external terminal 920, 922 of the multilayer structure 900 and a terminal of an electronic component 904 to electrically connect the electronic component 904 to the external terminals 920, 922. The external terminals 920, 922 may then be electrically connected to a component external to the multilayer structure 900 to electrically connect the multilayer structure 900 to the external component.

[0117] For example, referring to FIG. 12B, two or more vias 914 (which may be filled with conductive material 916) can be used to electrically connect a first electronic component 904 to a first external terminal 920. Similarly, two or more vias 914 (which may be filled with conductive material 916) can be used to electrically connect a second electronic component 904 to a second external terminal 922. Additionally, as shown in FIG. 13A, a plurality of vias 914 (one or more of which may be filled with conductive material 916) can be used to electrically connect a plurality of first external terminals 920 to respective ones of the electronic components 904 in a first set 952a of the electronic components 904. Likewise, a plurality of vias 914 (one or more of which may be filled with conductive material 916) can be used to electrically connect a plurality of second external terminals 922 to respective ones of the electronic components 904 in a second set 952b of the electronic components 904. As shown by the vias 914 defined in the second interposer 902b in the embodiment of FIG. 13B, one or more vias 914 (which may be filled with conductive material 916) can be used to electrically connect two or more of the electronic components 904 within the multilayer structure 900 to form internal connections within the multilayer structure 900.

[0118] In other embodiments, any other suitable electrical connections through and / or on one or more of the interposers 902 can be used to electrically connect one or more of the electronic components 904 of the multilayer structure 900 to one or more external components. Additionally, in at least some embodiments, one or more electrical connections can be formed on one surface of and / or through one or more of the interposers 902 of the multilayer structure 900 to electrically connect one or more of the electronic components 904 of the multilayer structure 900 to (e.g.) form one or more filters or the like. That is, the internal connections can be formed such that one or more of the electronic components 904 are electrically connected to one or more other electronic components 904 within the multilayer structure 900 to form, for example, a complex structure or a module for performing one or more desired functions when connected to one of the microelectronic assemblies described herein or when connected to another external component, module, or assembly.

[0119] It should be understood that the electronic components 904 sandwiched between the intermediate layers 902 can be a plurality of identical components or at least one electronic component 904 can be different from the remainder of the plurality of electronic components 904. The electronic components 904 of the multi-layer structure 900 can include one or more capacitors (such as one or more decoupling capacitors, as described herein with respect to FIGS. 4A to 10C), one or more resistors (including one or more varistors), one or more inductors, one or more transistors, one or more diodes, one or more transformers, one or more sensors, one or more electrostatic discharge devices, one or more memory devices, one or more radio frequency devices, one or more power amplifiers, one or more low noise amplifiers, one or more power management devices, one or more antennas, one or more microelectromechanical systems (such as one or more MEMS devices) or one or more parasitic elements, etc. Each electronic component 904 can be a discrete component, and two or more electronic components 904 can be connected within the multi-layer structure using one or more vias 914, conductive traces or other electrical connections described herein to form one or more filters or other such structures. As an example, two or more electronic components 904 can be disposed in a multi-layer structure 900 that is connected to an RF component using a transmission path to provide, for example, parasitic effects in an RF chain.

[0120] In some embodiments, the electronic component 904 includes at least one capacitor and at least one inductor such that the multi-layer structure 900 forms a filter. In other embodiments, the electronic component 904 includes at least one capacitor and at least one inductor such that the multi-layer structure 900 provides impedance matching of a transmission line. For example, the multi-layer structure 900 can be connected between an antenna and a communication circuit to provide impedance matching or can be connected to ground for impedance matching. In other embodiments, the multi-layer structure 900 can include a combination of capacitors and inductors and be electrically connected to at least one parasitic element to provide ground reactance. Additionally, in some embodiments, the multi-layer structure 900 can include electronic components 904 that provide desired RF characteristics when connected to an RF component using, for example, a transmission line. As an example, this multi-layer structure 900 can be connected between a communication circuit and an RF component using a transmission line to provide desired RF characteristics for the component, such as a desired capacitance for RF effects.

[0121] The (some) capacitors and (some) inductors of such exemplary multilayer structures 900 can have any suitable structure or form for inclusion in the multilayer structure 900. For example, when the electronic component 904 includes at least one capacitor, the at least one capacitor can be a decoupling capacitor, a multilayer ceramic capacitor, a tunable capacitor, etc., as described herein. Further, when the electronic component 904 includes at least one inductor, the at least one inductor can be a thin film component, a patterned component, etc. For example, the at least one inductor can include a layer of conductive material formed on a dielectric layer.

[0122] The conductive material for forming at least one capacitor and / or at least one inductor may include copper, nickel, gold, silver, or other metals or alloys. The conductive material of the at least one capacitor and / or the at least one inductor may be deposited or otherwise formed on a dielectric layer formed of a dielectric material, which may be an organic dielectric material or an inorganic dielectric material. Exemplary organic dielectrics include polyphenylene ether (PPE)-based materials (such as LD621 from Polyclad and the N6000 series from Park / Nelco), liquid crystal polymers (LCPs) (such as LCP from Rogers or W. L. Gore & Associates), hydrocarbon composites (such as the 4000 series from Rogers), and epoxy-based laminates (such as the N4000 series from Park / Nelco). For example, examples include epoxy-based N4000-13, a bromine-free material laminated to LCP, an organic layer with a high-K material, an unfilled high-K organic layer, Rogers 4350, Rogers 4003 material, and other thermoplastic materials such as polyphenylene sulfide resin, polyethylene terephthalate resin, polybutylene terephthalate resin, crosslinked polyethylene resin, polyether ketone resin, polytetrafluoroethylene resin, and graft resins or similar low dielectric constant, low loss organic materials. Exemplary inorganic or non-organic dielectric materials that can be used include ceramics, semiconductive or insulating materials such as (but not limited to) barium titanate, calcium titanate, zinc oxide, alumina with low-fire glass, or other suitable ceramic or glass-bonding materials. The dielectric material may be an organic compound such as an epoxy resin mixed with ceramics, with or without glass fibers, for example, an organic compound commonly used as a circuit board material, or other plastics commonly used as dielectrics. In such cases, the conductive material may be a copper foil, which is chemically etched to provide a conductive pattern, such as an inductor pattern. In a further embodiment, the dielectric material may include a material having a relatively high dielectric constant, such as one of NPO (COG), X7R, X5R, X7S, ZSU, Y5V, and strontium titanate, where the dielectric material may have a dielectric constant greater than 100, for example, in a range from about 100 to about 4000, and in some embodiments from about 1000 to about 3000. However, in some embodiments, the dielectric material may have a low dielectric constant. The dielectric constant may be less than about 100, less than about 75 in some embodiments, less than about 50 in some embodiments, less than about 25 in some embodiments, less than about 15 in some embodiments, and less than about 5 in some embodiments. For example, in some embodiments, the dielectric constant may be in a range from about 1.5 to 100, from about 1.5 to about 75 in some embodiments, and from about 2 to about 8 in some embodiments. The dielectric constant may be determined according to IPC TM-650 2.5.5.3 at an operating temperature of 25°C and a frequency of 1 MHz.The dielectric loss tangent can be in the range from about 0.001 to about 0.04, and in some embodiments from about 0.0015 to about 0.0025.

[0123] Referring now to FIG. 13D, a view of a multilayer structure 900 along the stacking direction Z is provided, and in the depicted embodiment, the stacking direction Z extends into and out of the page. It should be understood that all of the intermediate layers 902 are omitted for clarity, except for the intermediate layer 902 that is farthest from the viewing point along the stacking direction Z. For example, the depicted embodiment may provide a top view, where the intermediate layer 902 shown is the bottommost intermediate layer 902 in the multilayer structure 900.

[0124] As shown in FIG. 13D, the electronic components 904 of the multilayer structure 900 need not be positioned in a regular pattern (such as those shown in FIGS. 12A, 12B, 12C, and 12E), but rather can be positioned relative to each other in any configuration. For example, two or more discrete electronic components 904 can be positioned relative to each other to form a filter or other electronic structure.

[0125] Two or more electronic components 904 can overlap each other along the stacking direction Z, and one or more intermediate layers 902 are disposed between the overlapping electronic components 904. The overlapping electronic components 904 can be electrically connected to each other, for example, through one or more intermediate layers 902 disposed between the overlapping electronic components 904, or the overlapping electronic components 904 may not be electrically connected to each other (e.g., the overlapping electronic components 904 can be electrically isolated from each other).

[0126] As further illustrated in FIG. 13D, at least a portion of the plurality of electronic components 904 of the multilayer structure 900 can be spaced apart from each other along the transverse direction X and / or the longitudinal direction Y. In some embodiments, at least two electronic components 904 can be in contact with each other, such as along an adjacent surface of each electronic component 904.

[0127] Turning to FIGS. 14A, 14B, and 14C, in some embodiments, one or more intermediate layers can be sacrificial plates. More specifically, a sacrificial component structure 1000 includes at least one sacrificial plate 1002 and a plurality of components 1004 disposed adjacent thereto. After sacrificing at least a portion of at least one sacrificial plate 1002, a reduced component structure 1050 remains. It should be understood that like reference numerals in FIGS. 14A to 14C refer to similar features described, for example, with respect to the multilayer structure 900 of FIGS. 11A to 13E.

[0128] According to FIGS. 14A, 14B, and 14C, a resin 1034 (such as an epoxy resin or the like, as described elsewhere herein) is applied, injected, or otherwise disposed around a plurality of components 1004. In embodiments where at least one sacrificial plate 1002 includes a first sacrificial plate 1002 and a second sacrificial plate 1002 / 1026, the second sacrificial plate 1002 / 1026 can be disposed adjacent to the plurality of components 1004 after the resin 1034 is applied, such that the second surface 1008 of the first sacrificial plate 1002 and the first surface 1028 of the second sacrificial plate 1002 / 1026 are oriented towards the plurality of components 1004. However, in other embodiments, the second sacrificial plate 1002 / 1026 can be disposed adjacent to the plurality of components 1004 before the resin 1034 is applied. As shown in FIG. 14A, the second sacrificial plate 1002 / 1026 is disposed opposite the first sacrificial plate 1002 along the Z direction, such that the plurality of components 1004 are sandwiched between the first sacrificial plate 1002 and the second sacrificial plate 1002 / 1026.

[0129] One or more vias 1022, 1032 are then formed through one or more sacrificial plates 1002 (e.g., as described above with respect to via 922) and filled with a conductive material 1024, such as a conductive paste or the like. At least one sacrificial plate 1002 is then ground or otherwise reduced in height or thickness along its first surface 1006 in the Z direction, and the component structure 1000 can then be disposed in an assembly (e.g., as described below with respect to FIGS. 13A and 13B). In some embodiments, at least one sacrificial plate 1002 can be reduced in height or thickness after the component structure 1000 is assembled with other elements of the assembly (such as after the component structure 1000 is disposed in a cavity defined in a substrate). Additionally, at least one sacrificial plate 1002 can be completely removed or only a portion of at least one sacrificial plate 1002 can be removed. For example, in the embodiment of FIG. 14B, the two sacrificial plates 1002 shown in FIG. 14A have been ground to zero or completely removed. However, in other embodiments such as those shown in FIG. 14C, at least a portion of one or both plates 1002 can remain and have a non-zero reduced height Hr in the Z direction that is less than an initial height Hi of the sacrificial plate 1002 before reduction. As shown in FIG. 14C, the first and second sacrificial plates 1002 are reduced in height or thickness such that the reduced height Hr of the first sacrificial plate 1002 is different from the reduced height Hr of the second sacrificial plate 1002 / 1026, but in other embodiments, the reduced height Hr of the sacrificial plates 1002 can be the same.

[0130] The sacrificial plate 1002 helps to maintain the parallelism between a plurality of components 1004 during the construction of the component structure 1000. That is, the sacrificial plate 1002 helps to keep the plurality of components 1004 in proper positions, and the first surfaces 1010 of the respective components 1004 are substantially parallel to each other and the second surfaces 1012 of the respective components 1004 are substantially parallel to each other. Thus, after assembly with the resin 1034, the (some) vias 1022, and the conductive material 1024, one or more sacrificial plates 1002 can be wholly or partially removed by grinding along their respective surfaces 1006, 1030 or by another suitable removal technique. As shown in FIG. 14B, removing the sacrificial plate 1002 can expose one or more external terminals 1014, 1016, 1018, 1020 of each of the plurality of components 1004.

[0131] In the depicted embodiments of FIGS. 14A and 14B, the plurality of components 1004 are sandwiched between two sacrificial plates 1002, but it should be understood that in other embodiments, a single sacrificial plate 1002 may be sufficient. When grinding downwards or otherwise removing or reducing the height, one or both of the sacrificial plates 1002 can reduce in height along the Z direction. Further, the second sacrificial plate 1002 can be assembled with the first sacrificial plate 1002 and the plurality of components 1004 before or after adding the resin 1034. One or more vias 1022 can be formed through one or both of the sacrificial plates 1002.

[0132] In addition, as described above, the plurality of components 1004 can be a plurality of electronic components 904. For example, the plurality of components 1004 of the component structure 1000 and the reduced component structure 1050 can include one or more capacitors (such as one or more decoupling capacitors described herein with respect to FIGS. 4A to 10C), one or more resistors (including one or more varistors), one or more inductors, one or more transistors, one or more diodes, one or more transformers, one or more sensors, one or more electrostatic discharge devices, one or more memory devices, one or more radio frequency devices, one or more power amplifiers, one or more low noise amplifiers, one or more power management devices, one or more antennas, one or more microelectromechanical systems (such as one or more MEMS devices), one or more parasitic elements, etc. Each electronic component 1004 can be a discrete component, and two or more electronic components 1004 can be connected within a multilayer structure using one or more vias, conductive traces, or other electrical connections described herein to form one or more filters or other such structures. VI. Microelectronic Components

[0133] A semiconductor structure, a component interposer, a packaging substrate, and at least one of a decoupling capacitor structure, a decoupling capacitor component, or a multilayer decoupling capacitor structure can generally be arranged on a circuit board in various different configurations. Referring to FIG. 1, for example, an embodiment of a microelectronic component 600 is shown, which includes semiconductor structures 610, 620, and 630 electrically connected to a component interposer 650 and a packaging substrate 680 electrically connected to the component interposer 650. The semiconductor structure can be any type of structure described above. In one embodiment, for example, structures 610 and 630 can be a high bandwidth memory structure, a field programmable gate array. The semiconductor structures 610, 620, and 630 can be electrically connected to the component interposer 650 via first-stage coupling components 611, 621, and 631, as shown. In the illustrated embodiment, the coupling component 621 can be a solder ball or bump 623, and the coupling components 611 and 631 can be conductive adhesive or underfill material. Although not at all necessary, a molding compound 760 can also be employed. The molding compound can be an insulating material, such as those described above (e.g., epoxy resin material). The component interposer 650 also includes conductive paths 652 formed in an insulating dielectric material 654. The conductive paths 652 allow the component interposer 650 to be electrically connected to the packaging substrate 680 via second-stage coupling components 656 (e.g., solder balls or bumps). The packaging substrate 680 then includes conductive paths 682 (e.g., vias) in an insulating dielectric material 684. The conductive paths 682 allow the packaging substrate 680 to be electrically connected to a circuit board 800 (e.g., a printed circuit board) via third-stage coupling components 704 (e.g., solder balls).

[0134] It should be noted that a multilayer structure 900 is also positioned between at least a portion of the packaging substrate 680 and the circuit board 800. It should be understood that the multilayer structure 900 can be configured as described in relation to the embodiments of the multilayer structure 900 shown in FIGS. 12A to 12E. As described above, the multilayer structure 900 can provide a module for vertically integrating electronic components (such as discrete components, filters, or other complex structures) into the microelectronic component 600. This module can be tested for fit, form, and / or function prior to assembly with the microelectronic component 600 to (e.g.) improve yield, and can facilitate component size reduction.

[0135] As described herein, in at least some embodiments, the multi-layer structure 900 may include only one or more decoupling capacitors such that one or more decoupling capacitors may be used between the package substrate 680 and the circuit board 800. The external terminals of the (several) decoupling capacitors may be in electrical communication with the current paths of the circuit board 800 respectively and may be connected to the circuit board 800 using any method generally known in the art. For example, instead of solder balls 704, the multi-layer structure 900 may be directly electrically connected to the package substrate 680 and the circuit board 800, or at least may employ coupling components 702 (such as solder bumps or solder balls) that are smaller in size than the coupling component 704. The (several) decoupling capacitors of this multi-layer structure 900 may allow an AC signal to pass through or be transmitted while generally blocking a DC signal. That is, the (several) decoupling capacitors may be used to block low-frequency signals and transmit high-frequency signals. Additionally, by configuring the (several) decoupling capacitors in the manner shown in FIG. 1, certain conductive paths directly above the (several) decoupling capacitors (e.g., directly above the multi-layer structure 900) may be eliminated, thereby further improving performance. Using a decoupling capacitor in this manner may also allow for a significant reduction in inductance. Specifically, minimizing the distance or path of a ground connection may assist in reducing inductance. For example, using a decoupling capacitor may result in an inductance of about 1 nH or less, in some embodiments from about 25 fH to about 900 pF, in some embodiments from about 100 fH to about 500 pF, and in some embodiments from about 250 fH to about 100 pF. The decoupling capacitor may also exhibit a low equivalent series resistance, such as from about 100 mOhm or less, in some embodiments from about 0.01 mOhm to about 50 mOhm, in some embodiments from about 0.1 mOhm to about 40 mOhm, and in some embodiments from about 0.5 mOhm to about 30 mOhm. A low inductance and / or equivalent series resistance may be achieved while also exhibiting a customized capacitance value, such as from about 1 pF to about 1,000 μF, in some embodiments from about 500 pF to about 500 μF, and in some embodiments from about 1 μF to about 100 μF.

[0136] In the embodiment shown in FIG. 1, the component interposer 650 is generally regarded as a "passive" interposer because it does not contain any integrated electronic components. However, it should be understood that an "active" interposer may also be suitably used in the microelectronic components of the present invention. Referring to FIG. 2, for example, an embodiment of a microelectronic component 100 is shown, which includes semiconductor structures 114-3, 114-1, and 114-2 electrically connected to a component interposer 102 and a packaging substrate 104 electrically connected to the component interposer 102. In the illustrated embodiment, a bridge 110 is also embedded in the component interposer 102. More specifically, the component interposer 102 may have a first surface 170-1 and an opposing second surface 170-2, and one surface of the bridge 110 may be flush with the second surface 170-2 of the component interposer 102. The bridge 110 may include a substrate 111a and one or more routing layers 111b, and the routing layers 111b have high-density conductive paths 118 (such as traces and / or vias) passing through an insulating material (such as a dielectric material formed in multiple layers) for routing electrical signals between the dies 114-1 and 114-2. The bridge 110 may be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (such as silicon or germanium), a III-V material (such as gallium nitride), silicon oxide, or glass.

[0137] Although not necessary, the bridge 110 may include one or more integrated electronic components 112 (such as resistors and / or capacitors). The bridge 110 may include multiple integrated electronic components 112 disposed at the surface of the bridge 110, at different distances from the surface of the bridge 110 (i.e., in the z direction), and at different lateral positions in the bridge 110 (such as in the x direction). The bridge 110 may also include conductive paths 115 and 118 passing through the insulating material to couple the integrated electronic components 112 to the semiconductor structures 114-3, 114-1, and 114-2. The semiconductor structures may be coupled to the second surface 170-2 of the component interposer 102 via first-stage conductive paths 108-1, 108-2, 108-3, as shown. The component interposer 102 may also include conductive paths 119 for electrically connecting the semiconductor structures 114-3, 114-1, and 114-2 to the packaging substrate 104 (e.g., via first-stage interconnects 108-3, 108-1, 108-2 and second-stage interconnects 109). Any suitable configuration of the conductive paths 119 may be used to couple the semiconductor structures to each other (e.g., the conductive path 117 couples the structure 114-1 to the structure 114-3) and to couple the structures to the substrate 104 as desired. Although not explicitly shown herein, the packaging substrate 104 is also connected to a circuit board and decoupling capacitors in a manner such as described above.

[0138] Another embodiment of a microelectronic component 800 including an active component interposer 802 is also shown in FIG. 3. In this embodiment, the component interposer 802 is electrically connected to a package substrate 832 and a semiconductor structure 310 (such as a coprocessor) is electrically connected to the component interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (sometimes referred to herein as the non-active layer 390). The active layer 392 may include circuit elements 412 and a register file 394, which may serve as on-chip memory of the structure 310. The active component interposer 802 may similarly include an active layer 806 and a bulk semiconductor layer 804 (sometimes referred to as the non-active layer 804). The active layer 806 may include a plurality of level 1 (L1) memory elements 808 formed on the active side, which may be used as a memory cache area for storing configuration bitstreams for logical sectors in the configuration structure 310. The active component interposer 802 may be electrically connected to a package substrate 832 through coupling components 822 (such as solder bumps or solder balls), and the non-active layer 804 may include through-silicon vias (TSVs) 810, which may connect components such as the L1 memory elements 808 in the active layer 806 to the coupling components 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 through coupling components 820 (such as solder bumps).

[0139] According to expectations, an additional semiconductor structure 812 (e.g., an auxiliary chip) can be directly electrically connected to the substrate 832. The structure 812 can include an active layer 816 and a bulk semiconductor layer 814 (sometimes referred to as the non-active layer 814). The active layer 816 can include level 2 (L2) memory elements 809 formed at the active side, which can be used as a memory cache area for storing configuration bitstreams. For example, the configuration bitstream stored in the L1 memory element 808 on the component interposer 802 can be transmitted to the L2 memory element 809 to free up space on the L1 memory element 808 for new incoming configuration bitstreams (e.g., received from a host processor at the L1 memory element 808). The active layer 816 can face the package substrate 832 and can be electrically connected to the package substrate 832 through coupling components 822 and 824 (e.g., solder balls or bumps). A bridge 826 can also be used to connect the semiconductor structure 812 to the component interposer 802. The bridge 826 can contain interconnects 828 formed in a silicon substrate embedded in the package substrate 832. The interconnects 828 can electrically connect the part of the coupling component 824 connected to the semiconductor structure 812 to the part of the coupling component 824 connected to the component interposer 802. A heat sink 830 can also be placed in contact with the semiconductor structures 310 and 812, as is known in the art. Although not explicitly shown herein, the package substrate 104 is then connected to a circuit board in a manner such as described above. Additionally, a multilayer structure 900 such as described herein can be connected between the substrate 832 and the active component interposer 802.

[0140] One of ordinary skill in the art can practice these and other modifications and variations of the present invention without departing from the spirit and scope of the invention. Additionally, it should be understood that aspects of the various embodiments can be fully or partially interchanged. Furthermore, one of ordinary skill in the art should understand that the foregoing description is for illustration only and is not intended to limit the invention further described in the appended claims.

[0141] 10: Capacitor 12: First external terminal 14: Second external terminal 20: Capacitor 22a: First external terminal 22b: First external terminal 24b: Second external terminal 24a: Second external terminal 30: Capacitor 32: External terminal 32a: First external terminal 32b: First external terminal 34: External terminal 34a: Second external terminal 34b: Second external terminal 100: Microelectronic component 102: Component interposer 104: Package substrate 105: First internal electrode layer / non-contact hole / gap 105a: Side edge 105b: Side edge 105c: Top edge 105d: Bottom edge 108-1: First-level conductive path / first-level interconnect 108-2: First-level conductive path / first-level interconnect 108-3: First-level conductive path / first-level interconnect 109: Second-level interconnect 110: Internal electrode layer / bridge 110a: Group 110b: Group 111a: Substrate 111b: Routing layer 112: Integrated electronic component 114-1: Semiconductor structure / die 114-2: Semiconductor structure / die 114-3: Semiconductor structure 115: Second group of internal electrode layer / non-contact hole / gap / conductive path 117: Conductive path 118: Conductive path 119: Conductive path 120: Lead joint 121: Lateral edge 122: Lateral edge 123: Front edge 125: Gap 130: Lead joint 131: Lateral edge 132: Lateral edge 133: Front edge 135: Body / gap 140: Lead joint 141: Lateral edge 142: Lateral edge 143: Front edge 145: Main body 150: Lead wire joint 151: Transverse edge 152: Transverse edge 153: Front edge 170-1: First surface 170-2: Second surface 205: First internal electrode layer 205a: Side edge 205b: Side edge 205c: Top edge 205d: Bottom edge 210: Internal electrode layer 210a: Group 210b: Group 210c: Group 210d: Group 215: Second internal electrode layer 220a: Lead wire joint 220b: Lead wire joint 221a: Transverse edge 221b: Transverse edge 222a: Transverse edge 222b: Transverse edge 223a: Front edge 223b: Front edge 225: First conductive path 230a: Lead wire joint 230b: Lead wire joint 231a: Transverse edge 231b: Transverse edge 232a: Transverse edge 232b: Transverse edge 233a: Front edge 233b: Front edge 235: Main body / upper surface 240a: Lead wire joint 240b: Lead wire joint 241a: Transverse edge 241b: Transverse edge 242a: Transverse edge 242b: Transverse edge 243a: Front edge 243b: Front edge 245: Main body / lower surface 250a: Lead joint 250b: Lead joint 251a: Lateral edge 251b: Lateral edge 252a: Lateral edge 252b: Lateral edge 253a: Front edge 253b: Front edge 255: First shielding region 265: Second shielding region 275: Shielding electrode layer 285: Second conductive path 295: Second anchor electrode / second anchor joint 305: First anchor electrode 310: Semiconductor structure 390: Bulk semiconductor layer / non-active layer 392: Active layer 394: Register file 412: Circuit element 600: Microelectronic component 610: Semiconductor structure 611: First-stage coupling component 620: Semiconductor structure 621: First-stage coupling component 623: Bump 630: Semiconductor structure 631: First-stage coupling component 650: Component interposer 652: Conductive path 654: Insulating dielectric material 656: Second-stage coupling component 680: Package substrate 682: Conductive path 684: Insulating dielectric material 702: Coupling component 704: Third-stage coupling component 760: Overmolding material 800: Circuit board / microelectronic component 802: Active component interposer 804: Bulk semiconductor layer / non-active layer 806: Active layer 808: Level 1 (L1) memory element 809: Level 2 (L2) Memory Element 810: Through-Silicon Via (TSV) 812: Additional Semiconductor Structure 814: Bulk Semiconductor Layer / Non-Active Layer 816: Active Layer 820: Coupling Component 822: Coupling Component 824: Coupling Component 826: Bridge 828: Interconnect 830: Heat Sink 832: Package Substrate 900: Multilayer Structure 902: Interposer 902a: First Interposer 902b: Second Interposer 902c: Third Interposer 902d: Fourth Interposer 902e: Fifth Interposer 904: Electronic Component 906: First Surface 908: Second Surface 910: First Surface 912: Second Surface 914: Via 916: Conductive Material 920: First External Terminal 922: Second External Terminal 950: Layer 950a: First Layer 950b: Second Layer 950c: Third Layer 950d: Fourth Layer 952a: First Group 952b: Second Group 952c: Third Group 1000: Sacrificial Component Structure 1002: Sacrificial Plate 1004: Component 1006: First Surface 1008: Second Surface 1010: First Surface 1012: Second Surface 1014: External Terminal 1016: External terminal 1018: External terminal 1020: External terminal 1022: Passage 1024: Conductive material 1026: Second sacrificial plate 1028: First surface 1030: Surface 1032: Passage 1034: Resin 1050: Reduced component structure 1350: Void BL: Width BLA: Length BLB: Length BW: Width H i: Initial height H r: Non-zero reduced height L: Length O: Offset t: Distance t 1: Distance t 2: Distance t 3: Distance T: Thickness W: Width

Claims

1. A multi-layer structure comprising: A plurality of interposers, including a first outer interposer and a second outer interposer, the first outer interposer defining a first outer surface and the second outer interposer defining a second outer surface, the second outer surface being opposite to the first outer surface; a plurality of electronic components disposed between the first outer interposer and the second outer interposer; a first external terminal disposed on the first outer surface; and a second external terminal disposed on the second outer surface, wherein the plurality of interposers and the plurality of electronic components are disposed in at least two layers, each layer including two or more electronic components disposed between two interposers, such that the two or more electronic components contact a separate surface of a separate interposer of the plurality of interposers, wherein the at least two layers are stacked adjacent to each other, such that a separate interposer of the plurality of interposers is shared by the adjacent layers of the at least two layers. The first external terminal is electrically connected to one of the plurality of electronic components, and the second external terminal is electrically connected to one of the plurality of electronic components, wherein the first external interposer includes a first via, a second via, a third via, and a third external terminal disposed on the first external surface, wherein the first via contacts the first external terminal and the first electronic component to electrically connect the first external terminal and the first electronic component, wherein the third via contacts the third external terminal and one of the plurality of electronic components, the third electronic component to electrically connect the third external terminal and the third electronic component, wherein the third electronic component is disposed between the first external interposer and the second external interposer, and wherein the multilayer structure is a module configured to be integrated into a microelectronic component.

2. The multilayer structure of claim 1, wherein the plurality of electronic components includes at least one of the following: a capacitor, a resistor, an inductor, a fuse, a transistor, a diode, a transformer, a sensor, an electrostatic discharge device, a memory device, a radio frequency device, a low-noise amplifier, a power amplifier, a power management device, an antenna, a microelectromechanical system, or a parasitic element.

3. The multi-layer structure of claim 1, wherein the at least two layers comprise a first layer and a second layer, wherein the first layer comprises the first outer intermediary layer, a third intermediary layer among the plurality of intermediary layers, and a first group of one of the plurality of electronic components disposed between the first outer intermediary layer and the third intermediary layer, and wherein the second layer comprises the second outer intermediary layer, the third intermediary layer, and a second group of one of the plurality of electronic components disposed between the second outer intermediary layer and the third intermediary layer.

4. The multilayer structure of claim 3, wherein the first layer and the second layer are stacked adjacent to each other along a stacking direction, and wherein each electronic component of the first group of the plurality of electronic components is aligned with one electronic component of each of the second groups of the plurality of electronic components along the stacking direction.

5. The multilayer structure of claim 3, wherein the first layer and the second layer are stacked adjacent to each other along a stacking direction, and wherein each electronic component of the first group of the plurality of electronic components is offset from one electronic component of each of the second group of the plurality of electronic components along a longitudinal direction perpendicular to the stacking direction.

6. The multi-layer structure as claimed in claim 3, wherein the first group of the plurality of electronic components includes the first electronic component.

7. The multi-layer structure as claimed in claim 3, wherein the second group of the plurality of electronic components includes the second electronic component.

8. The multi-layered structure of claim 1, wherein the at least two layers comprise a first layer and a second layer, and wherein the first layer comprises the first external intermediary layer and the second layer comprises the second external intermediary layer.

9. The multilayer structure of claim 1 further includes one or more additional first external terminals disposed along the first outer surface, wherein each additional first external terminal is electrically connected to one of the plurality of electronic components.

10. The multilayer structure of claim 1 further includes one or more additional second external terminals disposed along the second outer surface, wherein each additional second external terminal is electrically connected to one of the plurality of electronic components.

11. The multilayer structure of claim 1 further includes one or more additional first external terminals disposed along the first outer surface and one or more additional second external terminals disposed along the second outer surface, wherein each additional first external terminal and each additional second external terminal is electrically connected to one of the plurality of electronic components.

12. The multilayer structure of claim 1, wherein at least one of the first passage, the second passage, and the third passage is filled with a conductive material.

13. The multilayer structure of claim 1, wherein the plurality of electronic components includes at least one decoupling capacitor having a first surface and a pair of opposing second surfaces, wherein the decoupling capacitor includes alternating dielectric layers and internal electrode layers, the internal electrode layers including a first internal electrode layer and a second internal electrode layer, wherein the decoupling capacitor further includes a first external terminal electrically connected to the first internal electrode layers and disposed on one of the first surfaces of the decoupling capacitor, a second external terminal electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor.

14. The multilayer structure of claim 1, wherein the plurality of electronic components includes at least one capacitor electrically connected to at least one inductor to form a filter, and wherein the at least one capacitor and the at least one inductor are disposed in different layers of the at least two layers, the different layers being stacked together along a stacking direction.

15. The multilayer structure of claim 1, wherein the plurality of electronic components includes at least one capacitor electrically connected to at least one inductor to form a filter, and wherein the at least one capacitor and the at least one inductor are disposed in the same layer of the at least two layers.

16. A microelectronic component comprising: A semiconductor structure; An assembly interposer is electrically connected to the semiconductor structure; A packaging substrate electrically connected to an interposer layer of the component; a multilayer structure comprising: a plurality of interposer layers; and a plurality of electronic components disposed between the plurality of interposers, wherein the plurality of interposers and the plurality of electronic components are disposed in at least two layers, each layer including at least one electronic component of the plurality of electronic components disposed between two interposers, and wherein the at least two layers are stacked adjacent to each other such that one of the plurality of interposers is shared by the adjacent layers of the at least two layers; and a circuit board, wherein the multilayer structure is electrically connected to the packaging substrate and the circuit board.

17. A method for forming a microelectronic component, the method comprising: Forming a multilayer structure includes: disposing a plurality of electronic components adjacent to a first interposer layer, the first interposer layer being configured as a first sacrificial plate; applying a resin around the plurality of electronic components; disposing a second interposer layer adjacent to the plurality of electronic components, the second interposer layer being configured as a second sacrificial plate, the second interposer layer being disposed opposite to the first interposer layer along a Z direction, such that the plurality of electronic components are sandwiched between the first sacrificial plate and the second sacrificial plate; forming one or more pathways through at least one of the first interposer layer or the second interposer layer; filling the one or more pathways with a conductive material; and removing at least a portion of at least one of the first interposer layer or the second interposer layer along the Z direction; electrically connecting the multilayer structure to a package substrate and a circuit board, wherein the package substrate is electrically connected to a component interposer layer, and the component interposer layer is electrically connected to a semiconductor structure.

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