Semiconductor devices and semiconductor memory devices

Abstract

One embodiment provides a semiconductor device and a semiconductor memory device, which can manufacture semiconductor devices of good quality. The semiconductor device of this embodiment includes: an oxide semiconductor having a first end and a second end extending in a first direction from the second end toward the first end; a first electrode connected to the first end of the oxide semiconductor; a second electrode connected to the second end of the oxide semiconductor; a gate electrode surrounding the oxide semiconductor between the first end and the second end of the oxide semiconductor, separated by a first insulating film; and a second insulating film disposed on the first-direction side of the gate electrode, surrounding the oxide semiconductor separated by the first insulating film; and a hole formed by the gate electrode and the second insulating film to accommodate at least a portion of the oxide semiconductor; and a stepped surface formed on the inner wall of the hole in the direction opposite to the first direction.

Description

Semiconductor devices and semiconductor memory devices This embodiment relates to a semiconductor device and a semiconductor memory device. In semiconductor devices, metal oxides containing indium and tin are sometimes used for electrodes. In the manufacturing process of semiconductor devices using metal oxides as electrodes, a technology for manufacturing high-quality semiconductor devices is required. The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor memory device that can manufacture semiconductor devices with good quality. A semiconductor device according to an embodiment comprises: an oxide semiconductor having a first end and a second end, extending in a first direction from the second end toward the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a gate electrode between the first end and the second end of the oxide semiconductor, surrounding the oxide semiconductor via a first insulating film; and a second insulating film disposed on the first direction side of the gate electrode, surrounding the oxide semiconductor via the first insulating film; a hole portion for accommodating at least a portion of the oxide semiconductor is formed by the gate electrode and the second insulating film; and a step surface facing in a direction opposite to the first direction is formed on an inner wall of the hole portion. A semiconductor device according to an embodiment comprises: a plurality of oxide semiconductors having a first end and a second end and extending in a first direction from the second end toward the first end; a plurality of first electrodes respectively connected to the first ends of the plurality of oxide semiconductors; a plurality of second electrodes respectively connected to the second ends of the plurality of oxide semiconductors; a gate electrode extending along the second direction and respectively interposing a plurality of first insulating films between the first end and the second end of each of the plurality of oxide semiconductors arranged along the second direction to surround the oxide semiconductor; a fourth insulating film arranged in a direction opposite to the first direction of the gate electrode; and a fifth insulating film arranged between two oxide semiconductors adjacent in the second direction and in a direction opposite to the first direction of the fourth insulating film; and an etching rate of the fifth insulating film is greater than an etching rate of the fourth insulating film. A semiconductor memory device according to an embodiment includes: the above-mentioned semiconductor device; a first capacitor electrode connected to the above-mentioned first electrode or the above-mentioned second electrode; a second capacitor electrode opposite to the above-mentioned first capacitor electrode; and a dielectric film arranged between the above-mentioned first capacitor electrode and the above-mentioned second capacitor electrode. In order to facilitate understanding of the description, the same reference numerals are used as much as possible in the drawings to identify the same components and duplicate descriptions are omitted. [First embodiment] The structure of the semiconductor memory device of the first embodiment is described. In each figure, the X-axis, Y-axis and Z-axis are sometimes shown. The X-axis, Y-axis and Z-axis form a right-handed three-dimensional orthogonal coordinate. Hereinafter, the arrow direction of the X-axis is sometimes referred to as the X-axis + direction, and the direction opposite to the arrow is referred to as the X-axis - direction, and the same applies to other axes. In addition, the Z-axis + direction and the Z-axis - direction are sometimes referred to as "up" and "down", respectively. In addition, the plane orthogonal to the X-axis, Y-axis or Z-axis is sometimes referred to as the YZ plane, ZX plane or XY plane. In addition, the Z-axis direction is sometimes referred to as the "up and down direction". "Up", "down" and "up and down direction" are always terms that show the relative position relationship in the figure, and are not terms that determine the direction based on the vertical direction. In addition, except for cases where specific explanation is given, the dimensions of components shown in the drawings may be different from the actual dimensions to facilitate understanding of the description. In this specification, “connection” includes not only physical connection but also electrical connection, and unless otherwise specified, it includes not only direct connection but also indirect connection. In this specification, "formed above" includes not only the case of being formed in contact with the upper side but also includes the case of being formed above with another object interposed therebetween, except for specially specified cases. The same applies to the case of "formed below". The semiconductor memory device 101 of the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) having a memory cell array. As shown in FIG. 1 , the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. In FIG. 1 , as an example of a plurality of word lines WL, the word line WL is shown. n , character line WL n+1 and word line WL n+2 (Here, n is a positive integer.) In FIG. 1 , as an example of the bit line BL, the bit line BL is shown. m , bit line BL m+1 and bit line BL m+2(Here, m is a positive integer.) In addition, the number of the plurality of memory cells MC is not limited to the number shown in FIG. 1 . A plurality of memory cells MC are arranged in a matrix, for example, to form a memory cell array. The memory cell MC includes a field effect transistor (FET), namely a memory transistor MTR, and a memory capacitor MCP. A series of memory cells MC arranged along the row direction are connected to the word line WL (eg, word line WL) corresponding to the row to which the memory cell belongs (eg, the nth row). n A series of memory cells MC arranged along the row direction are connected to the bit line BL (eg bit line BL corresponding to the row to which they belong (eg row m+2)). m+2 ). Specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs. Either the source or the drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs. One electrode of the memory capacitor MCP included in the memory cell MC is connected to the other of the source or drain of the memory transistor MTR included in the memory cell MC. The other electrode of the memory cell MC is connected to a power line (not shown) that supplies a specific potential. The memory cell MC is configured to retain data by switching the memory transistor MTR based on the potential of the corresponding word line WL and accumulating charge in the memory capacitor MCP by the current flowing through the corresponding bit line BL. As shown in FIG. 2 , a semiconductor memory device 101 includes a semiconductor substrate 10 , a circuit 11 , a capacitor 20 , a semiconductor device 30 , a conductor 33 , and insulating layers 34 , 35 , 45 , and 63 . The capacitor 20 includes a conductor 21 , an insulating film 22 (an example of a “dielectric film”), a conductor 23 , a capacitor electrode 24 (an example of a “first capacitor electrode”), and a capacitor electrode 25 (an example of a “second capacitor electrode”). The semiconductor device 30 includes a field effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 (an example of a "first electrode") disposed above the field effect transistor 40, and a lower electrode 32 (an example of a "second electrode") disposed below the field effect transistor 40. The field effect transistor 40 includes an oxide semiconductor layer 70 (an example of an “oxide semiconductor”) corresponding to a channel, a gate insulating film 43 (an example of a “first insulating film”), and a conductive layer 42 (an example of a “gate electrode”). The oxide semiconductor layer 70 is formed within the insulating layer 45 and has an upper end 70a (an example of a "first end") and a lower end 70b (an example of a "second end"). The oxide semiconductor layer 70 is a columnar structure extending from the lower end 70b toward the upper end 70a in the Z-axis positive direction (an example of a "first direction"). The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40 and has an amorphous structure. The conductive layer 42 functions as a gate electrode of the field effect transistor 40 and is located between the upper end 70a and the lower end 70b of the oxide semiconductor layer 70, with the gate insulating film 43 interposed therebetween to surround the oxide semiconductor layer 70. The conductive layer 42 includes, for example, tungsten. The gate insulating film 43 includes, for example, a silicon nitride film (SiN) containing silicon and nitrogen. 3N 4). The upper electrode 50 is formed in the Z-axis + direction relative to the oxide semiconductor layer 70 and is in contact with the upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c. The metal film 50c includes tungsten (W). The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70 and includes a metal oxide. The metal oxide may include, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO). The barrier metal layer 50b includes titanium and nitrogen and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is formed of, for example, titanium nitride (TiN). The lower electrode 32 is in contact with the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 is formed of, for example, an ITO layer containing a metal oxide such as indium-tin-oxide (ITO). Furthermore, the lower electrode 32 is not limited to ITO, and may be composed of at least one element selected from the group consisting of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron. Circuit 11 constitutes peripheral circuitry for a plurality of memory cells MC in semiconductor memory device 101, namely, capacitors 20 and field-effect transistors 40, including a decoder for selecting a specific memory cell MC, a sense amplifier connected to bit lines BL, and a register comprising SRAM (Static Random Access Memory). Circuit 11 may include a CMOS circuit having field-effect transistors (FETs) such as P-channel FETs (Pch-FETs) and N-channel FETs (Nch-FETs) formed using a CMOS (Complementary Metal Oxide Semiconductor) process. The field-effect transistors (FETs) in circuit 11 can be formed using, for example, a semiconductor substrate 10 such as a single-crystal silicon substrate. P-type and N-type FETs are so-called lateral field-effect transistors, each having a channel region, a source region, and a drain region on the semiconductor substrate 10. Furthermore, a channel for allowing carriers to flow in the X-axis or Y-axis direction substantially parallel to the surface of the semiconductor substrate 10 is provided in a region near the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 can have a conductivity type ranging from P-type to N-type. For convenience, FIG2 illustrates an example of a field-effect transistor in circuit 11. The capacitor 20 is a memory capacitor MCP included in the memory cell MC (see FIG1 ). Although four capacitors 20 are shown in FIG2 , the number of capacitors 20 is not limited to four. In this embodiment, capacitor 20 is provided above semiconductor substrate 10. Capacitor electrode 24 in capacitor 20 is connected to conductor 21 and lower electrode 32. Capacitor electrode 25 faces capacitor electrode 24. Insulating film 22 is provided between capacitor electrode 24 and capacitor electrode 25. The capacitor 20 is a three-dimensional capacitor such as a pillar capacitor. In addition, other capacitors having a structure capable of storing electric charge may be used as the capacitor of this embodiment. Conductor 21 abuts the lower end surface of lower electrode 32 and extends downward from this end. Capacitor electrode 24 is formed to cover lower electrode 32 and conductor 21. Insulating film 22 is formed to cover capacitor electrode 24. Capacitor electrode 25 surrounds a portion below insulating film 22 and has a lower end abutting the upper end surface of conductor 23. The conductor 21 may include amorphous silicon, etc. The insulating film 22 may include hafnium oxide, etc. The conductor 23 and the capacitor electrodes 24 and 25 may include tungsten (W) and titanium nitride (TiN), etc. Conductor 33 includes wiring that electrically connects circuit 11 to semiconductor device 30. Conductor 33 may include via wiring, for example, as shown in FIG2 , extending in the Z-axis direction to connect word line WL to circuit 11 disposed on semiconductor substrate 10. Conductor 33 includes, for example, copper. The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen. The insulating layer 35 is disposed on the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen. The semiconductor device 30 is disposed above the capacitor 20. The field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (see FIG. 1 ). In the semiconductor device 30, the field effect transistor 40 is disposed above the lower electrode 32. Specifically, the oxide semiconductor layer 70 of the field effect transistor 40 is located in a direction away from the semiconductor substrate 10 relative to the lower electrode 32, that is, above the lower electrode 32. The upper electrode 50 is located away from the semiconductor substrate 10 relative to the oxide semiconductor layer 70, that is, above the semiconductor substrate 10. With this structure, the field effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) substantially perpendicular to the surface of the semiconductor substrate 10. Furthermore, oxide semiconductor layer 70 is an oxygen-deficient semiconductor that serves as a donor. The metal elements include indium (In), zinc (Zn), and gallium (Ga). Specifically, oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely IGZO (InGaZnO). Alternatively, oxide semiconductor layer 70 may be another type of oxide semiconductor. FIG3 is a cross-sectional view of the semiconductor device 30 taken along a cross section 70ZX parallel to the ZX plane, showing the cross section 70ZX included in the oxide semiconductor layer 70. FIG4 is a cross-sectional view of the semiconductor device 30 taken along a cross section 70YZ parallel to the YZ plane, showing the cross section 70YZ included in the oxide semiconductor layer 70. FIG5 is a cross-sectional view taken along the cutting line VV shown in FIG3 and FIG4. Hereinafter, a first example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the first example of the first embodiment) will be described. (First Embodiment, Example 1) As shown in Figures 3 to 5, in the first embodiment, the semiconductor device 30 further includes a liner film 301 (an example of a "third insulating film") and a spacer film 311. The gate insulating film 43 includes insulating films 43a and 43b. The insulating layer 45 includes insulating films 45a, 45b, and 45c. The plurality of conductive layers 42 are repeatedly arranged in the X-axis + direction (an example of the "third direction"). The plurality of oxide semiconductor layers 70 are arranged two-dimensionally. That is, a portion of the plurality of oxide semiconductor layers 70 is arranged along the Y-axis + direction (an example of the "second direction"). Furthermore, other portions of the plurality of oxide semiconductor layers 70 are arranged along the X-axis + direction. The conductive layer 42 extends along the Y-axis + direction and surrounds the plurality of oxide semiconductor layers 70 disposed along the Y-axis + direction through a plurality of gate insulating films 43 . Specifically, the conductive layer 42 includes a surrounding portion 42b (an example of a “first portion”) surrounding the oxide semiconductor layer 70 and a connecting portion 42c (an example of a “second portion”) connecting the two surrounding portions 42b. When the conductive layer 42 is viewed from above, the width of the connecting portion 42 c in the X-axis direction is narrower than the width of the surrounding portion 42 b in the X-axis direction. The spacer film 311 (an example of a "second insulating film") is provided on the Z-axis positive direction side of the conductive layer 42. The spacer film 311 is made of, for example, silicon oxide. The spacer film 311 includes a cylindrical portion 311a and a plate-shaped portion 311b. The cylindrical portion 311a is provided above the surrounding portion 42b in the conductive layer 42 and extends approximately parallel to the Z-axis. Specifically, the lower end of the cylindrical portion 311a forms an annular surface that contacts the upper surface 42a of the conductive layer 42. The cylindrical portion 311a surrounds the oxide semiconductor layer 70 via the gate insulating film 43. The plate-shaped portion 311b is provided above the connecting portion 42c in the conductive layer 42 and extends approximately parallel to the XY plane. Insulating films 45a and 45b are respectively provided above the plate-shaped portion 311b and below the conductive layer 42. The insulating films 45a and 45b are made of, for example, silicon oxide. The insulating film 45c separates two conductive layers 42 adjacent to each other in the X-axis + direction. Specifically, the insulating film 45c is located between the two conductive layers 42 adjacent to each other in the X-axis + direction and extends substantially parallel to the Y-axis. The upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. The lower surface of the insulating film 45c is buried in the insulating film 45b. In this embodiment, the insulating films 45a and 45c are formed integrally. The surrounding portion 42b of the conductive layer 42 and the cylindrical portion 311a of the spacer 311 form a hole 401 that receives at least a portion of the oxide semiconductor layer 70. In this embodiment, the hole 401 receives a portion of the upper portion of the oxide semiconductor layer 70. Alternatively, the hole 401 may receive the entire oxide semiconductor layer 70. A step surface 401a facing the Z-axis direction is formed on the inner wall 401b of the hole 401. The step surface 401a is located between the conductive layer 42 and the upper electrode 50. The step surface 401a is annular when viewed from below. In this embodiment, in hole 401, the inner diameter of the lower end of cylindrical portion 311a is smaller than the inner diameter of the upper portion of surrounding portion 42b. Therefore, the center portion of the lower end surface of cylindrical portion 311a forms a stepped surface 401a. The upper surface 42a of conductive layer 42 is aligned with stepped surface 401a. The gate insulating film 43 completely surrounds a portion of the upper portion of the oxide semiconductor layer 70. The gate insulating film 43 comprises two layers: insulating films 43a and 43b. Insulating film 43a is located closer to the oxide semiconductor layer 70 than insulating film 43b. The upper ends of insulating films 43a and 43b are in contact with the metal oxide layer 50a. Insulating film 43a comprises, for example, silicon oxide. Insulating film 43b comprises, for example, silicon nitride. The liner film 301 is located at least between the conductive layer 42 and the insulating film 45b, and the gate insulating film 43. The liner film 301 surrounds a portion of the oxide semiconductor layer 70 from the outside of the gate insulating film 43 to the entire circumference. Specifically, the lower end of the liner film 301 contacts the lower electrode 32. The upper end of the liner film 301 contacts the step surface 401a of the hole 401, that is, the lower end surface of the cylindrical portion 311a. The liner film 301 includes, for example, at least one element selected from silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one element selected from oxygen and nitrogen. In this embodiment, the liner film 301 includes silicon nitride. Alternatively, the liner film 301 may include silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, or strontium oxide. [Method for Manufacturing Semiconductor Device] Hereinafter, a method for manufacturing the semiconductor device 30 will be described as an example of the method for manufacturing the semiconductor device according to the first embodiment. First, as shown in Figures 6 and 7, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are sequentially formed over the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45ba extend approximately parallel to the XY plane. A transistor hole TH is formed extending approximately parallel to the Z axis and penetrating the insulating film 45ba, the conductive layer 42, and the insulating film 45b. The layer is then cleaned. The lower electrode 32 is exposed at the bottom of the transistor hole TH. 8 and 9 , a liner film 301 having a thickness of 3 nm or more is formed on the semiconductor device 30 by, for example, atomic layer deposition (ALD). Thus, the inner wall of the transistor hole TH is covered by the liner film 301, and the lower electrode 32 is not exposed. 10 and 11 , a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 . Thus, the transistor hole TH is buried by the sacrificial amorphous silicon layer 170 . 12 and 13 , the sacrificial amorphous silicon layer 170 is etched back to remove a portion of the upper portion of the sacrificial amorphous silicon layer 170, exposing the upper surface of the insulating film 45ba. At this point, the upper end of the sacrificial amorphous silicon layer 170 is located above the conductive layer 42, for example, within the transistor hole TH. 14 and 15 , the insulating film 45ba is removed by etching. Furthermore, the liner film 301 exposed above the conductive layer 42 is removed by etching. This aligns the upper surface 42a of the conductive layer 42 with the upper end of the liner film 301. 16 and 17 , a spacer film 311 is formed above the semiconductor device 30 . As a result, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42 a of the conductive layer 42 are covered by the spacer film 311 . Next, as shown in Figures 18 and 19, after forming a mask on the surface of semiconductor device 30 by photolithography, resist coating, exposure, development, and stripping, a groove 45ca extending approximately parallel to the Y-axis is formed in semiconductor device 30 by etching through insulating film 45b. This separates spacer film 311 into cylindrical portion 311a and plate-shaped portion 311b. Furthermore, conductive layer 42 extends approximately parallel to the Y-axis, separating into a plurality of electrodes repeatedly arranged in the X-axis positive direction. These electrodes correspond to word lines WL (see Figure 1). Furthermore, a self-aligned process is used to form the surrounding portion 42b in the conductive layer 42. Specifically, even if the mask formation position during photolithography is offset, the cylindrical portion 311a of the spacer 311 located on the side of the sacrificial amorphous silicon layer 170 also functions as a mask, so the surrounding portion 42b is formed in a self-aligned manner around the transistor hole TH. 20 and 21 , insulating films 45c and 45a are integrally formed above the semiconductor device 30. Furthermore, by chemical mechanical polishing the upper surface of the semiconductor device 30, the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a. Next, as shown in FIG. 22 and FIG. 23 , the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching. Next, as shown in FIG. 24 and FIG. 25 , an insulating film 43 b is formed above the semiconductor device 30 . Next, as shown in FIG. 26 and FIG. 27 , an insulating film 43 a is formed above the semiconductor device 30 . Next, as shown in FIG. 28 and FIG. 29 , the upper portion of the semiconductor device 30 is etched back by reactive ion etching to expose the insulating film 45 a , and the lower electrode 32 is exposed at the bottom of the transistor hole TH. 30 and 31 , an oxide semiconductor layer 70 is formed inside the transistor hole TH. Furthermore, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing. Next, as shown in Figures 32 and 33 , a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30. Furthermore, a landing pad hard mask (LPHM) film 50e, for example, made of silicon oxide, is formed on the metal film 50c. Next, as shown in Figures 34 and 35 , after forming a mask on the surface of the semiconductor device 30 by photolithography, resist coating, exposure, development, and stripping, an upper electrode 50, which functions as a landing pad, is formed on the semiconductor device 30 by etching. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c. Next, as shown in Figures 36 and 37 , an LP liner film 50d, for example, made of silicon oxide, is formed on the upper surface of the semiconductor device 30. An insulating layer 63 is formed above the LP liner film 50d to fill the gap created by the LP liner film 50d. The insulating layer 63 is made of silicon oxide, for example. Furthermore, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing. 38 and 39 , a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the upper surface of the semiconductor device 30. The barrier metal layers 51a and 51c may comprise, for example, titanium nitride, and the conductive layer 51b may comprise, for example, tungsten. Next, BLHM (Bit Line Hard Mask) films 66a and 66b are formed on the upper surface of the barrier metal layer 51c from the bottom to the top. The BLHM films 66a and 66b include, for example, silicon nitride and silicon oxide, respectively. Next, as shown in Figures 40 and 41 , after forming a mask on the surface of the semiconductor device 30 by photolithography, followed by resist coating, exposure, development, and stripping, a trench 66ca is formed in the semiconductor device 30 by etching, penetrating the insulating layer 63 and the metal film 50c and extending approximately parallel to the X-axis. This separates the barrier metal layer 51a, the conductive layer 51b, and the barrier metal layer 51c into electrodes extending approximately parallel to the X-axis and repeatedly arranged in the Y-axis positive direction. These electrodes correspond to the bit lines BL (see Figure 1 ). 3 and 4 , an insulating film 66c is formed over the semiconductor device 30 to fill the groove portion 66ca. The insulating film 66c is made of, for example, silicon oxide. (Effect) If the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere without forming the liner film 301, the sacrificial amorphous silicon layer 170 may be formed directly on the lower electrode 32 made of ITO. In this case, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170. In contrast, in this embodiment, as shown in Figures 10 and 11 , when forming the sacrificial amorphous silicon layer 170, the inner wall of the transistor hole TH is covered by the liner film 301, and the lower electrode 32 is not exposed. This prevents the lower electrode 32 from contacting the sacrificial amorphous silicon layer 170, thereby suppressing the formation of silicon whiskers. Next, a second example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the second example of the first embodiment) will be described. (Second example of the first embodiment) As shown in Figures 42 and 43, the difference between the semiconductor device 30 of the second example of the first embodiment and the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 and 4 is that the step surface 401a in the hole portion 401 is located above the surface 42a of the conductive layer 42 and below the surface below the upper electrode 50. [Method for Manufacturing the Semiconductor Device 30 According to the Second Example of the First Embodiment] In the method for manufacturing the semiconductor device 30 according to the second example of the first embodiment, after removing a portion of the upper portion of the sacrificial amorphous silicon layer 170 by etching back (see Figures 12 and 13), as shown in Figures 44 and 45, a portion of the upper portion of the liner film 301 is removed by etching. As a result, the upper end of the liner film 301 is positioned below the upper end of the sacrificial amorphous silicon layer 170. By controlling the amount of liner film 301 removed, the position of the upper end of the liner film 301 can be adjusted. Next, a third example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the third example of the first embodiment) will be described. (Third example of the first embodiment) As shown in Figures 46 and 47, the difference between the semiconductor device 30 of the third example of the first embodiment and the semiconductor device 30 of the first example of the first embodiment shown in Figures 3 and 4 is that the upper end of the liner film 301 is connected to the upper electrode 50, and the step surface 401a is not formed in the hole portion 401. [Manufacturing method of the semiconductor device 30 of the third example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the third example of the first embodiment, instead of removing the liner film 301 exposed above the conductive layer 42 by etching after removing the insulating film 45ba (refer to Figures 14 and 15), as shown in Figures 48 and 49, only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 remains. Next, a fourth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fourth example of the first embodiment) will be described. (Fourth Example of First Embodiment) As shown in FIG. 50 and FIG. 51 , the semiconductor device 30 of the fourth example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in FIG. 3 and FIG. 4 in that the gate insulating film 43 does not include the insulating film 43 b. [Method for Manufacturing Semiconductor Device 30 According to the Fourth Example of the First Embodiment] In the method for manufacturing the semiconductor device 30 according to the fourth example of the first embodiment, instead of forming the insulating film 43b above the semiconductor device 30 (see FIG. 24 and FIG. 25 ), as shown in FIG. 52 and FIG. 53 , an insulating film 43a is formed above the semiconductor device 30. This can reduce the number of steps required to form the insulating film 43b made of silicon nitride. Next, a fifth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fifth example of the first embodiment) will be described. (Fifth example of the first embodiment) As shown in Figures 54 and 55, the difference between the semiconductor device 30 of the fifth example of the first embodiment and the semiconductor device 30 of the fourth example of the first embodiment shown in Figures 50 and 51 is that the step surface 401a in the hole portion 401 is located above the surface 42a of the conductive layer 42 and below the surface below the upper electrode 50. With this structure, the possibility of contact between the conductive layer 42 and the insulating film 43a can be reduced, thereby suppressing an increase in gate leakage. [Method for Manufacturing Semiconductor Device 30 According to Fifth Example of First Embodiment] In the method for manufacturing the semiconductor device 30 according to the fifth example of the first embodiment, as shown in FIG44 and FIG45 , a portion of the upper portion of the liner film 301 is removed by etching. Furthermore, as shown in FIG52 and FIG53 , an insulating film 43a is formed above the semiconductor device 30. Next, a sixth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the sixth example of the first embodiment) will be described. (Sixth example of the first embodiment) As shown in Figures 56 and 57, the difference between the semiconductor device 30 of the sixth example of the first embodiment and the semiconductor device 30 of the fourth example of the first embodiment shown in Figures 50 and 51 is that the upper end of the liner film 301 is connected to the upper electrode 50, and the step surface 401a is not formed in the hole portion 401. [Method for Manufacturing Semiconductor Device 30 According to Sixth Example of First Embodiment] In the method for manufacturing the semiconductor device 30 according to the sixth example of the first embodiment, as shown in FIG48 and FIG49 , only the insulating film 45ba is removed by etching, leaving the liner film 301 exposed above the conductive layer 42. Furthermore, as shown in FIG52 and FIG53 , an insulating film 43a is formed above the semiconductor device 30. Next, a seventh example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the seventh example of the first embodiment) will be described. (Seventh Example of the First Embodiment) As shown in FIG. 58 and FIG. 59 , the semiconductor device 30 of the seventh example of the first embodiment differs from the semiconductor device 30 of the first example of the first embodiment shown in FIG. 3 and FIG. 4 in that the semiconductor device 30 does not include the liner film 301 . [Manufacturing method of the semiconductor device 30 of the seventh example of the first embodiment] In the manufacturing method of the semiconductor device 30 of the seventh example of the first embodiment, after the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching (refer to Figures 22 and 23), the liner film 301 is removed by etching as shown in Figures 60 and 61. Then, as shown in FIG. 62 and FIG. 63 , an insulating film 43 b and an insulating film 43 a are sequentially formed over the semiconductor device 30 . In the semiconductor device 30 of the seventh example of the first embodiment, since the liner film 301 is removed, the insulating film 43b and the insulating film 43a are formed from the inner surface of the cylindrical portion 311a in the spacing film 311 to the inner surface of the step surface 401a and the surrounding portion 42b in the conductive layer 42. Therefore, the inner surface of the insulating film 43a includes a step surface 43aa that faces the Z-axis direction and has an annular shape when viewed from below. When the semiconductor device 30 is viewed from above, part or all of the insulating film 43a facing the conductive layer 42 is obscured by the step surface 43aa and is therefore invisible. Therefore, when the top of the semiconductor device 30 is etched back using reactive ion etching (see Figures 28 and 29), damage to part or all of the insulating film 43a facing the conductive layer 42 can be suppressed by the reactive ion etching. This can suppress the occurrence of gate leakage. Next, an eighth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the eighth example of the first embodiment) will be described. (Example 8 of the first embodiment) As shown in Figures 64 and 65, the difference between the semiconductor device 30 of the eighth example of the first embodiment and the semiconductor device 30 of the seventh example of the first embodiment shown in Figures 58 and 59 is that the step surface 401a in the hole portion 401 is located above the surface 42a of the conductive layer 42 and below the surface below the upper electrode 50. With this structure, the step surface 43 aa can be separated from the conductive layer 42 , thereby suppressing the generation of gate leakage caused by electric field concentration in the step surface 43 aa . [Method for Manufacturing Semiconductor Device 30 According to the Eighth Example of the First Embodiment] In the method for manufacturing the semiconductor device 30 according to the eighth example of the first embodiment, as shown in FIG44 and FIG45 , a portion of the upper portion of the liner film 301 is removed by etching. As shown in FIG60 and FIG61 , the liner film 301 is removed by etching. Furthermore, as shown in FIG62 and FIG63 , an insulating film 43b and an insulating film 43a are sequentially formed above the semiconductor device 30. Next, a ninth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the ninth example of the first embodiment) will be described. (Ninth example of the first embodiment) As shown in Figures 66 and 67, the difference between the semiconductor device 30 of the ninth example of the first embodiment and the semiconductor device 30 of the seventh example of the first embodiment shown in Figures 58 and 59 is that the upper end of the liner film 301 is in contact with the upper electrode 50, and the step surface 401a in the hole portion 401 and the step surface 43aa in the insulating film 43a are not formed. [Method for Manufacturing Semiconductor Device 30 According to Ninth Example of First Embodiment] In the method for manufacturing the semiconductor device 30 according to the ninth example of the first embodiment, as shown in FIG48 and FIG49 , only the insulating film 45ba is removed by etching, leaving the liner film 301 exposed above the conductive layer 42. As shown in FIG60 and FIG61 , the liner film 301 is removed by etching. Furthermore, as shown in FIG62 and FIG63 , the insulating film 43b and the insulating film 43a are sequentially formed above the semiconductor device 30. [Second Embodiment] A semiconductor device 30B according to a second embodiment will be described. In the second embodiment and beyond, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar functions and effects of similar configurations will not be described sequentially for each embodiment. Figure 68 is a cross-sectional view of the semiconductor device 30B taken along a section 70ZX parallel to the ZX plane, showing the cross-sectional view of the oxide semiconductor layer 70 as viewed through the section 70ZX. Figure 69 is a cross-sectional view of the semiconductor device 30B taken along a section 70YZ parallel to the YZ plane, showing the cross-sectional view of the oxide semiconductor layer 70 as viewed through the section 70YZ. As shown in FIG. 68 and FIG. 69 , the semiconductor device 30B of the second embodiment further includes an insulating film 501 (an example of a “fifth insulating film”) in place of the liner film 301 , compared to the semiconductor device 30 shown in FIG. 3 to FIG. 5 . The insulating layer 45 includes a layer L1 comprising an insulating film 45a, a layer L2 comprising a plate-like portion 311b, a layer L3 comprising a plurality of conductive layers 42 (an example of a "first layer"), a layer L4 comprising an insulating film 45b (an example of a "fourth insulating film") (an example of a "second layer"), and a layer L5 comprising an insulating film 501 (an example of a "third layer"). Layers L1, L2, L3, L4, and L5 are arranged in order from the top. An insulating film 45c (an example of a "sixth insulating film") is located between two adjacent conductive layers 42 in the X-axis + direction and extends in the Y-axis + direction to separate layers L2, L3, L4, and L5. The lower end portion of the insulating film 45 c is in contact with the insulating layer 35 (an example of the “seventh insulating film”) provided between the two lower electrodes 32 . The insulating film 501 is provided between two oxide semiconductor layers 70 adjacent to each other in the Y-axis + direction and below the insulating film 45b (see FIG. 69 ). Furthermore, the insulating film 501 is provided between two oxide semiconductor layers 70 adjacent to each other in the + direction of the X axis, and below the insulating film 45b with both side surfaces sandwiched by two insulating films 45c (see FIG. 68 ). Insulating film 501 contains at least one element selected from aluminum, silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium, and magnesium, and oxygen. In this embodiment, insulating film 501 is aluminum oxide. The etching rate of insulating film 501 is greater than the etching rate of insulating film 45b. The gate insulating film 43 surrounds a portion of the upper portion of the oxide semiconductor layer 70 along the circumference of the oxide semiconductor layer 70. The oxide semiconductor layer 70 includes a large-diameter portion 70c between an end portion 43c below the gate insulating film 43 and the lower electrode 32. The large-diameter portion 70c has a larger diameter than the gate insulating film 43 in the end portion 43c. [Method for Manufacturing Semiconductor Device] Hereinafter, a method for manufacturing the semiconductor device 30B will be described as an example of a method for manufacturing the semiconductor device according to the second embodiment. First, as shown in Figures 70 and 71, an insulating film 501, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are sequentially formed above the insulating layer 35. The insulating film 501, the insulating film 45b, the conductive layer 42, and the insulating film 45ba extend approximately parallel to the XY plane. A transistor hole TH is formed, extending approximately parallel to the Z axis and penetrating through the insulating film 45ba, the conductive layer 42, and the insulating film 45b to the middle of the insulating film 501. The layer is then cleaned. At the bottom of the transistor hole TH, the insulating film 501 is exposed, but the lower electrode 32 is not. 72 and 73 , a sacrificial amorphous silicon layer 170 is formed on the semiconductor device 30B. As a result, the transistor hole TH is buried by the sacrificial amorphous silicon layer 170 . Next, as shown in FIG. 74 and FIG. 75 , the sacrificial amorphous silicon layer 170 is etched back to remove a portion of the upper portion of the sacrificial amorphous silicon layer 170 , thereby exposing the upper surface of the insulating film 45 ba . Next, as shown in FIG. 76 and FIG. 77 , the insulating film 45 ba is removed by etching. 78 and 79 , a spacer film 311 is formed above the semiconductor device 30B. Thus, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42 a of the conductive layer 42 are covered by the spacer film 311 . Next, as shown in Figures 80 and 81 , after forming a mask on the surface of semiconductor device 30B by photolithography, resist coating, exposure, development, and stripping, a groove 45ca extending approximately parallel to the Y-axis is formed in semiconductor device 30B by etching through the insulating film 501. This separates spacer film 311 into a cylindrical portion 311a and a plate-like portion 311b. Furthermore, conductive layer 42 extends approximately parallel to the Y-axis, forming a plurality of electrodes repeatedly arranged in the X-axis positive direction. These electrodes correspond to word lines WL (see Figure 1 ). Next, as shown in FIG. 82 and FIG. 83 , insulating films 45 c and 45 a are integrally formed above the semiconductor device 30B. Next, as shown in FIG. 84 and FIG. 85 , by chemical mechanical polishing the upper surface of the semiconductor device 30B, the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45 a . Next, as shown in FIG. 86 and FIG. 87 , the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching. Next, as shown in FIG. 88 and FIG. 89 , an insulating film 43 b and an insulating film 43 a are sequentially formed over the semiconductor device 30B. Next, as shown in FIG. 90 and FIG. 91 , the top of the semiconductor device 30B is etched back by reactive ion etching to expose the insulating film 45 a , and the insulating film 501 is exposed at the bottom of the transistor hole TH. Next, as shown in Figures 92 and 93 , the insulating film 501 exposed at the bottom of the transistor hole TH is wet-etched to remove a portion of the insulating film 501. Because the etching rate of the insulating film 501 is greater than that of the insulating film 45b, the amount of insulating film 501 removed is greater than that of the insulating film 45b. Furthermore, a space 270 having a larger diameter than the diameter of the gate insulating film 43 at the end 43c below the gate insulating film 43 is formed between the lower electrode 32 and the end 43c below the gate insulating film 43. 94 and 95 , an oxide semiconductor layer 70 is formed inside the transistor hole TH. At this time, the oxide semiconductor layer 70 filling the space 270 forms a large-diameter portion 70 c. Next, as shown in FIG. 96 and FIG. 97 , chemical mechanical polishing is performed on the upper surface of the semiconductor device 30B. 98 and 99, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed on the upper surface of the semiconductor device 30B from bottom to top. Furthermore, an LPHM film 50e, such as one made of silicon oxide, is formed on the metal film 50c. (Effect) If the insulating film 501 is not formed, and after forming the transistor hole TH, the residue inside the transistor hole TH is removed by dry etching or wet etching, the ITO included in the lower electrode 32 may be damaged by the cleaning agent. In contrast, in this embodiment, as shown in FIG. 70 and FIG. 71 , since the lower electrode 32 is not exposed at the bottom of the transistor hole TH, the ITO included in the lower electrode 32 can be prevented from being damaged by the cleaning agent. Furthermore, assuming that the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere without forming the insulating film 501, the sacrificial amorphous silicon layer 170 is formed directly on the lower electrode 32 made of ITO. In this case, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170. In contrast, in this embodiment, as shown in Figures 72 and 73, when forming the sacrificial amorphous silicon layer 170, the insulating film 501 is exposed at the bottom of the transistor hole TH instead of the lower electrode 32. This prevents the lower electrode 32 from contacting the sacrificial amorphous silicon layer 170, thereby suppressing the formation of silicon whiskers. Furthermore, assuming that the insulating film 501 is not formed, when the gate insulating film 43 is formed, the conductive layer 42 made of tungsten and the lower electrode 32 made of ITO are exposed, and thus tungsten whiskers may be generated. In contrast, in this embodiment, as shown in Figures 88 and 89, when forming the gate insulating film 43, the insulating film 501 is exposed at the bottom of the transistor hole TH instead of the lower electrode 32. This prevents both the conductive layer 42 and the lower electrode 32 from being exposed, thereby suppressing the generation of tungsten whiskers. Furthermore, since the large-diameter portion 70 c is formed below the oxide semiconductor layer 70 , the contact area between the lower end 70 b of the oxide semiconductor layer 70 and the lower electrode 32 can be increased, thereby reducing the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 . In the semiconductor devices 30 of the first to ninth examples of the first embodiment, the step surface 401a is provided between the conductive layer 42 and the upper electrode 50. However, the present invention is not limited thereto. The step surface 401a may be provided below the surface 42a of the conductive layer 42. (a) The second electrode contains at least one element selected from the group consisting of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron. (b) The third insulating film is in contact with the gate electrode and the second electrode. (c) The third insulating film contains at least one element selected from the group consisting of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one element selected from the group consisting of oxygen and nitrogen. (d) The third insulating film is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, or strontium oxide. The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Any design changes made by those skilled in the art to these specific examples as appropriate, as long as they possess the characteristics of the present disclosure, are also included in the scope of the present disclosure. The various elements and their configurations, conditions, shapes, etc. of the above-mentioned specific examples are not limited to those exemplified and can be appropriately changed. The various elements of the above-mentioned specific examples can be appropriately changed and combined as long as no technical contradictions arise. [Reference to Related Applications] This application claims the benefit of priority from Japanese Patent Application No. 2023-156463 ​​(filing date: September 21, 2023), which is a basic application, and the present application incorporates all the contents of the basic application by reference. 10: Semiconductor substrate 11: Circuit 20: Capacitor 21: Conductor 22: Insulating film 23: Conductor 24, 25: Capacitor electrodes 30, 30B: Semiconductor device 32: Lower electrode 33: Conductor 34, 35: Insulating layer 40: Field effect transistor 42: Conductive layer 42a: Surface 42b: Surrounding portion 42c: Connecting portion 43: Gate insulating film 43a, 43b: Insulating film 43aa: Step surface 43c: End portion 45: Insulating layers 45a, 45b, 45ba, 45c: Insulating film 45ca: Groove portion 50: Upper electrode 50a: Metal oxide layer 50b: Barrier metal layer 50c: Metal film 50d: LP liner film 51a: Barrier metal layer 51b: Conductive layer 51c: Barrier metal layer 50e: LPHM film 63: Insulating layer 66a, 66b: BLHM film 66c: Insulating film 66ca: Groove 70: Oxide semiconductor layer 70a: Upper end 70b: Lower end 70c: Large diameter portion 70YZ, 70ZX: Cross section 101: Semiconductor memory device 170: Sacrificial amorphous silicon layer 270: Space 301: Liner film 311: Spacer film 311a: Cylindrical portion 311b: Plate-shaped portion 401: Hole 401a: Step surface 401b: Inner wall 501: Insulating films BL, BL m , BL m+1 , BL m+2 : Bit lines L1, L2, L3, L4, L5: Layer MC: Memory cell MCP: Memory capacitor MTR: Memory transistor TH: Transistor hole WL, WL n , WL n+1 , WL n+2 :Character Line FIG1 is a circuit diagram illustrating an example circuit configuration of a memory cell array according to the first embodiment. FIG2 is a schematic cross-sectional view illustrating an example structure of a semiconductor memory device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane. FIG3 is a schematic cross-sectional view illustrating an example structure of a semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the first example of the first embodiment. FIG4 is a schematic cross-sectional view illustrating an example structure of a semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the first example of the first embodiment. FIG5 is a cross-sectional view taken along the cutting line VV shown in FIG3 and FIG4. FIG6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first example of the first embodiment, showing a cross-sectional view parallel to the ZX plane. FIG7 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first example of the first embodiment, showing a cross-sectional view parallel to the YZ plane. FIG8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first example of the first embodiment, showing a cross-sectional view parallel to the ZX plane. FIG9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG16 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG18 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG19 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG20 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG21 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG22 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG23 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG24 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG25 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device of the first example of the first embodiment.FIG26 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG27 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG28 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG29 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG30 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG31 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG32 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG33 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG34 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG35 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG36 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG37 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG38 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG39 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG40 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the ZX plane. FIG41 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first example of the first embodiment, taken along the YZ plane. FIG42 is a schematic cross-sectional view for illustrating an example of the structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the second example of the first embodiment. FIG43 is a schematic cross-sectional view for illustrating an example of the structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the second example of the first embodiment. FIG44 is a schematic cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second example of the first embodiment. FIG45 is a schematic cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second example of the first embodiment. FIG46 is a schematic cross-sectional view for illustrating an example of the structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the third example of the first embodiment. FIG47 is a schematic cross-sectional view for illustrating an example of the structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the third example of the first embodiment. FIG48 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device according to the third example of the first embodiment.FIG49 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device of the third example of the first embodiment. FIG50 is a cross-sectional schematic view for illustrating the structural example of the semiconductor device of the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device of the fourth example of the first embodiment. FIG51 is a cross-sectional schematic view for illustrating the structural example of the semiconductor device of the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device of the fourth example of the first embodiment. FIG52 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the fourth example of the first embodiment. FIG53 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor device of the fourth example of the first embodiment. FIG54 is a cross-sectional schematic view for illustrating the structural example of the semiconductor device of the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device of the fifth example of the first embodiment. FIG55 is a schematic cross-sectional view for illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fifth example of the first embodiment. FIG56 is a schematic cross-sectional view for illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the sixth example of the first embodiment. FIG57 is a schematic cross-sectional view for illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the sixth example of the first embodiment. FIG58 is a schematic cross-sectional view for illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the seventh example of the first embodiment. FIG59 is a schematic cross-sectional view for illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the seventh example of the first embodiment. FIG60 is a schematic cross-sectional view parallel to the ZX plane, showing a manufacturing process of the semiconductor device according to the seventh example of the first embodiment. FIG61 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment. FIG62 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment. FIG63 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment. FIG64 is a cross-sectional schematic view for illustrating a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the eighth example of the first embodiment. FIG65 is a cross-sectional schematic view for illustrating a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the eighth example of the first embodiment. FIG66 is a cross-sectional schematic view for illustrating a structural example of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane of the semiconductor device according to the ninth example of the first embodiment.FIG67 is a schematic cross-sectional view illustrating an example structure of the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device according to the ninth example of the first embodiment. FIG68 is a schematic cross-sectional view illustrating an example structure of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the ZX plane. FIG69 is a schematic cross-sectional view illustrating an example structure of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the YZ plane. FIG70 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the ZX plane. FIG71 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the YZ plane. FIG72 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the ZX plane. FIG73 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the YZ plane. FIG74 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment, showing a cross-sectional view parallel to the ZX plane. FIG75 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG76 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG77 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG78 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG79 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG80 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG81 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG82 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG83 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG84 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG85 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG86 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG87 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG88 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG89 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG90 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG91 is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. FIG92 is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second embodiment.FIG93 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the YZ plane. FIG94 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the ZX plane. FIG95 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the YZ plane. FIG96 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the ZX plane. FIG97 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the YZ plane. FIG98 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the ZX plane. FIG99 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, taken along the YZ plane. 22: Insulation film 24: Capacitor electrode 30: Semiconductor devices 32: Lower electrode 35: Insulation layer 42: conductive layer 42a: Noodles 42b: Encirclement 42c: Connecting part 43: Gate insulation film 43a, 43b: Insulating film 45: Insulation layer 45a, 45b, 45c: Insulating film 50: Upper electrode 50a: Metal oxide layer 50b: Barrier metal layer 50c: Metal film 50d:LP liner film 51a: Barrier metal layer 51b: conductive layer 51c: Barrier metal layer 63: Insulation layer 66a,66b:BLHM membrane 66c: Insulating film 70: oxide semiconductor layer 70a: Top 70b: lower end 70ZX: Cross-section 301: Liner film 311: Spacer membrane 311a: cylindrical part 311b: plate-shaped part 401: Hole 401a: step surface 401b: Inner wall TH: Transistor hole

Claims

1. A semiconductor device comprising: an oxide semiconductor having a first end and a second end extending in a first direction from the second end toward the first end; a first electrode connected to the first end of the oxide semiconductor; a second electrode connected to the second end of the oxide semiconductor; a gate electrode surrounding the oxide semiconductor between the first end and the second end of the oxide semiconductor via a first insulating film; and a second insulating film disposed on the first-direction side of the gate electrode, surrounding the oxide semiconductor via the first insulating film; and a hole formed by the gate electrode and the second insulating film to accommodate at least a portion of the oxide semiconductor; and a stepped surface formed on the inner wall of the hole in the opposite direction to the first direction.

2. The semiconductor device of claim 1, wherein the first insulating film is connected to the first electrode.

3. The semiconductor device of claim 1, wherein the step surface is located between the gate electrode and the first electrode.

4. The semiconductor device of claim 1, wherein the first direction side of the gate electrode is aligned with the step side.

5. The semiconductor device of claim 1, wherein the semiconductor device further comprises: a third insulating film located at least between the gate electrode and the first insulating film, wherein the end on the first direction side and the end on the opposite direction side are respectively connected to the step surface and the second electrode.

6. The semiconductor device of claim 1, wherein the semiconductor device comprises: a plurality of oxide semiconductors disposed along a second direction intersecting the first direction; and a gate electrode extending along the second direction and surrounding the plurality of oxide semiconductors through a plurality of first insulating films; the gate electrode comprising a first portion surrounding the oxide semiconductors and a second portion connecting two of the first portions; the width of the second portion being narrower than the width of the first portion.

7. A semiconductor memory device comprising: the semiconductor device of claim 1 or 6; a first capacitor electrode connected to the first electrode or the second electrode; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode.

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