Semiconductor memory devices

Abstract

[Problem] To provide a semiconductor memory device that can be suitably manufactured. [Solution] A semiconductor memory device includes: a substrate; and a plurality of first wirings arranged side-by-side in a first direction intersecting the surface of the substrate and extending toward a second direction; and a plurality of second wirings arranged side-by-side in the first direction and extending toward the second direction, and arranged side-by-side with the plurality of first wirings in a third direction; and first via wirings and second via wirings disposed between the plurality of first wirings and the plurality of second wirings and extending toward the first direction; and a plurality of first semiconductor layers arranged side-by-side in the first direction, and... It is electrically connected to the first via wiring; and a plurality of second semiconductor layers are arranged side by side in the first direction and are electrically connected to the second via wiring, and are respectively electrically connected to a plurality of second wiring; and a plurality of first gate electrodes are arranged side by side in the first direction and are respectively electrically connected to a plurality of first wiring, and are opposite to a plurality of first semiconductor layers; and a plurality of second gate electrodes are arranged side by side in the first direction and are respectively electrically connected to a plurality of first semiconductor layers, and are opposite to a plurality of second semiconductor layers.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Prior Technology

[0002] With the increasing integration of semiconductor memory devices, there has been progress in the study of the 3D transformation of semiconductor memory devices. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0317132 Summary of the Invention

[0004] [The problem the invention aims to solve]

[0005] A semiconductor memory device that can be suitably manufactured is provided. [Methods used to solve problems]

[0006] One embodiment of a semiconductor memory device includes: a substrate; a plurality of first wirings arranged side-by-side in a first direction intersecting the surface of the substrate and extending toward a second direction intersecting the first direction; a plurality of second wirings arranged side-by-side in the first direction and extending toward the second direction, and arranged side-by-side with the plurality of first wirings in a third direction intersecting the first and second directions; a first via wiring and a second via wiring disposed between the plurality of first wirings and the plurality of second wirings and extending toward the first direction; and a plurality of first semiconductor layers. The first semiconductor layer is arranged side by side in the first direction and electrically connected to the first via wiring; and the second semiconductor layer is arranged side by side in the first direction and electrically connected to the second via wiring, and is electrically connected to the second wiring respectively; the first gate electrode is arranged side by side in the first direction and electrically connected to the first wiring respectively, and faces the first semiconductor layer; and the second gate electrode is arranged side by side in the first direction and electrically connected to the first semiconductor layer respectively, and faces the second semiconductor layer. Simple Explanation of the Diagram

[0007] [Figure 1] is a schematic circuit diagram showing a portion of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] is a schematic perspective view showing a portion of the structure of the semiconductor memory device. [Figure 3] is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 4] is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 5] is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. [Figure 6] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 7] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 8] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 9] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 10] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 11] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 12] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 13] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 14] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 15] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 16] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 17] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 18] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 19] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 20] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 21] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 22] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 23] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 24] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 25] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 26] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 27] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 28] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 29] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 30] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 31] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 32] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 33] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 34] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 35] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 36] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 37] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 38] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 39] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 40] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 41] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 42] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 43] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 44] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 45] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 46] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 47] is a schematic XY cross-sectional view showing the configuration of a part of the semiconductor memory device of the second embodiment. [Figure 48] is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 49] is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. [Figure 50] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 51] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 52] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 53] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 54] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 55] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 56] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 57] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 58] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 59] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 60] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 61] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 62] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 63] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 64] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 65] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 66] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 67] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 68] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 69] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 70] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 71] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 72] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 73] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 74] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 75] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 76] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 77] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 78] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 79] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 80] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 81] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 82] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 83] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 84] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 85] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 86] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 87] is a schematic circuit diagram showing a portion of the configuration of a semiconductor memory device according to the first embodiment. [Figure 88] is a schematic circuit diagram showing a portion of the configuration of a semiconductor memory device according to the third embodiment. [Figure 89] is a schematic XY cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 90] is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 91] is a schematic XY cross-sectional view showing the configuration of a part of the semiconductor memory device of the fourth embodiment. [Figure 92] is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 93] is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. [Figure 94] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 95] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 96] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 97] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 98] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 99] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 100] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 101] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 102] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 103] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 104] is a schematic circuit diagram showing a portion of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 105] is a schematic XY cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 106] is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 107] is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. [Figure 108] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 109] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 110] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 111] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 112] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 113] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 114] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 115] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 116] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 117] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 118] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 119] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 120] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 121] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 122] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 123] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 124] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 125] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 126] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 127] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 128] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 129] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 130] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 131] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 132] is a schematic circuit diagram showing the configuration of a part of the semiconductor memory device of the sixth embodiment. [Figure 133] is a schematic XY cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 134] is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. [Figure 135] is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device. [Figure 136] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 137] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 138] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 139] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 140] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 141] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 142] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 143] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 144] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 145] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 146] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 147] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 148] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 149] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 150] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 151] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 152] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 153] is a schematic circuit diagram showing a portion of the configuration of a semiconductor memory device according to the seventh embodiment. [Figure 154] is a schematic perspective view showing a portion of the structure of the semiconductor memory device. [Figure 155] is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device. Implementation

[0008] Next, with reference to the drawings, the semiconductor memory device of the embodiment will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the present invention. Also, the following drawings are illustrative, and for ease of explanation, some components may be omitted. Furthermore, for multiple embodiments, common parts may be marked with the same component symbols and their descriptions may be omitted.

[0009] Furthermore, in this specification, when referring to "semiconductor memory devices," it may refer to memory chips, or it may refer to memory systems that include controller chips, such as memory chips, memory cards, and SSDs (Solid State Drives). It may also refer to devices that include host computers, such as smartphones, tablets, and personal computers.

[0010] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or it can mean that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor and the third transistor system are still "electrically connected".

[0011] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected between" the second and third components, it may mean that the first, second, and third components are connected in series and the second component is electrically connected to the third component via the first component.

[0012] Furthermore, in this specification, when it is mentioned that a circuit or the like "connects" the wiring of two devices, for example, there may be a situation that means "this circuit or the like includes a transistor or the like, this transistor or the like is placed in the current path between the two wirings, and this transistor or the like is in the ON state".

[0013] Furthermore, in this specification, a specific direction that is parallel to the top surface of the substrate is referred to as the X direction, a direction that is parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction that is perpendicular to the top surface of the substrate is referred to as the Z direction.

[0014] Furthermore, in this specification, there may be instances where a direction along a specific surface is referred to as the first direction, a direction intersecting the first direction along the specific surface is referred to as the second direction, and a direction intersecting the specific surface is referred to as the third direction. These first, second, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond to each other.

[0015] Furthermore, in this specification, the terms "upper" or "lower" are used with the substrate as a reference. For example, if the direction away from the substrate along the Z direction is called "upper," then the direction approaching the substrate along the Z direction is called "lower." Also, when referring to a specific configuration as "below" or "lower end," it refers to the substrate-side surface or end of that configuration; when referring to "upper" or "upper end," it refers to the surface or end of that configuration opposite to the substrate. Furthermore, the surface intersecting the X or Y direction is called a "side surface," etc.

[0016] Furthermore, in this specification, when referring to the "center position" of a certain component, it may refer to, for example, the position of the center of the circumscribed circle of the component, or the center of gravity of the image of the component.

[0017] Furthermore, in this specification, when referring to "semiconductor layer" and "semiconductor section," "semiconductor section" may be a part of the "semiconductor layer" or the entirety of the "semiconductor layer." Also, a "semiconductor layer" may be composed of one "semiconductor section" or may contain multiple "semiconductor sections."

[0018] [First Implementation Form] [Circuit Structure] Figure 1 is a schematic circuit diagram illustrating a portion of the configuration of a semiconductor memory device according to a first embodiment. As shown in Figure 1, the semiconductor memory device of this embodiment includes a memory cell array (MCA). The memory cell array (MCA) includes a plurality of memory layers ML, a plurality of write bit lines WBL connected to the plurality of memory layers ML, and a plurality of read bit lines RBL connected to the plurality of memory layers ML.

[0019] The memory layer ML comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC connected to these write word lines WWL and read word lines RWL. Each memory cell MC comprises a write transistor WTr, a sense node SN, and a read transistor RTr.

[0020] The write transistor WTr is, for example, a field-effect NMOS transistor. One electrode of the write transistor WTr is connected to the write bit line WBL. The other electrode of the write transistor WTr is connected to the sense node SN. One and the other electrodes of the write transistor WTr function as source or drain electrodes depending on the voltage supplied to the write transistor WTr. The gate electrode of the write transistor WTr is connected to the write word line WWL.

[0021] The sense transistor RTr is, for example, a field-effect NMOS transistor. One electrode of the sense transistor RTr is connected to the sense bit line RBL. The other electrode of the sense transistor RTr is connected to the sense word line RWL. One and the other electrodes of the sense transistor RTr function as source or drain electrodes depending on the voltage supplied to the sense transistor RTr. The gate electrode of the sense transistor RTr is connected to the sense node SN.

[0022] During a write operation, for example, a power supply voltage Vdd is supplied to the write target of the multiple write character lines WWL, and a ground voltage Vss is supplied to the others. Furthermore, for the write bit lines WBL, either a power supply voltage Vdd or a ground voltage Vss is supplied depending on the data being written.

[0023] Furthermore, during a write operation, all write bit lines (WBLs) within the memory cell array (MCA) can be used as the target of the write operation, or a portion (e.g., one) of the write bit lines (WBLs) can be used as the target of the write operation. In the latter case, those write bit lines (WBLs) that are not the target of the write operation can be set to a floating state, for example.

[0024] During a read operation, for example, a power supply voltage Vdd is supplied to the read target among the multiple read word lines RWL, and a ground voltage Vss is supplied to the others. Similarly, a ground voltage Vss is supplied to the read target among the multiple read bit lines RBL, or such read bit lines are set to a floating state. Here, when the sensing node SN of the memory cell MC (hereinafter referred to as "selected memory cell MC") that is the target of the read operation is charged by the power supply voltage Vdd, the read transistor RTr is turned on, current flows at the read bit line RBL, or the read bit line RBL is charged. On the other hand, when the sensing node SN of the selected memory cell MC is discharged to the ground voltage Vss, the read transistor RTr becomes OFF, and no current flows at the read bit line RBL, or the read bit line RBL is not charged.

[0025] Furthermore, during a read operation, all read lines RBL within the memory cell array (MCA) can be used as the read target, or only a portion (e.g., one) of the read lines RBL can be used. In the latter case, those read lines RBL that are not used as the read target can be supplied with the power supply voltage Vdd, for example.

[0026] [structure] Figure 2 is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment. Figure 3 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. Figure 4 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, illustrating the configuration shown in Figure 3 when cut along line A-A' and viewed in the direction of the arrow.

[0027] Figure 2 shows a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub.

[0028] The semiconductor substrate Sub, for example, is a silicon (Si) semiconductor substrate containing P-type impurities such as boron (B). An insulating layer (not shown) and an electrode layer are disposed on the top of the semiconductor substrate Sub. The insulating layer and electrode layer (not shown) on the top of the semiconductor substrate Sub constitute a control circuit for controlling the semiconductor memory device. For example, a sense amplifier circuit is disposed in the area directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the read bit line RBL. During readout operation, the sense amplifier circuit can read out the data stored in the select memory cell MC by detecting changes in voltage or current on the read bit line RBL.

[0029] The memory cell array (MCA) has a plurality of memory layers ML arranged side by side in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML.

[0030] Furthermore, via wirings 102 and 103 are provided at the memory cell array MCA. Via wiring 102 functions as the write bit line WBL. Via wiring 103 functions as the read bit line RBL. Via wirings 102 and 103 are arranged side by side in the X direction and extend through multiple memory layers ML in the Z direction.

[0031] The through-hole wiring 102, for example, includes: a conductive oxide film 102a comprising a conductive oxide, a barrier conductive film 102b such as titanium nitride (TiN), and a conductive component 102c such as tungsten (W). Alternatively, the through-hole wiring 102 may replace the conductive oxide film 102a by including ruthenium (Ru), iridium (Ir), or other metals. Furthermore, the through-hole wiring 102 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0032] In this specification, "conductive oxide" is, for example, defined as containing indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0033] The through-hole wiring 103 may, for example, include: a conductive oxide film 103a comprising a conductive oxide, a barrier conductive film 103b such as titanium nitride (TiN), and a conductive component 103c such as tungsten (W). Alternatively, the through-hole wiring 103 may replace the conductive oxide film 103a by including ruthenium (Ru), iridium (Ir), or other metals. Furthermore, the through-hole wiring 103 may also consist only of a conductive oxide, or only of ruthenium (Ru), iridium (Ir), or other metals.

[0034] Conductive components 102c and 103c each have a slightly cylindrical shape extending in the Z direction. Barrier conductive films 102b and 103b each have a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of conductive components 102c and 103c. Conductive oxide films 102a and 103a each have a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of barrier conductive films 102b and 103b.

[0035] Furthermore, at the memory cell array MCA, an insulating member 104, such as silicon oxide (SiO2), is provided. The insulating member 104 is provided between the through-hole wirings 102 and 103, and extends in the Z direction through multiple memory layers ML.

[0036] Furthermore, at the memory cell array MCA, an insulating layer 105, such as silicon oxide (SiO2), is disposed. The insulating layer 105 extends in the Z direction through a plurality of memory layers ML. The insulating layer 105 is arranged side by side in the Y direction and extends in the X direction, thereby electrically disconnecting the plurality of memory cells MC arranged side by side in the Y direction.

[0037] The memory layer ML includes "wiring 110, 120 arranged side-by-side in the X direction and extending in the Y direction", "transistor structures 130, 140 disposed between these wirings 110, 120", and "conductive member 150 disposed between these transistor structures 130, 140". Transistor structures 130, 140 are respectively disposed at positions corresponding to via wirings 102, 103. Conductive member 150 is disposed at a position corresponding to insulating member 104. In the illustrated example, transistor structures 130, 140 and conductive member 150 are arranged side-by-side in the X direction.

[0038] Wiring 110, for example, functions as a write character line WWL (FIG. 1). Wiring 110, for example, includes a barrier conductive film 111 of titanium nitride (TiN) and a conductive film 112 of tungsten (W).

[0039] Wiring 120, for example, functions as a readout character line RWL (Fig. 1). Wiring 120, for example, includes a barrier conductive film 121 of titanium nitride (TiN) and a conductive film 122 of tungsten (W).

[0040] The transistor structure 130 includes a semiconductor layer 131 that is connected to the outer peripheral surface of the through-hole wiring 102 and extends in the X direction, an insulating layer 132 disposed on the upper and lower surfaces, both sides in the Y direction and one side (wiring 110 side) of the semiconductor layer 131, and a conductive layer 133 disposed on the upper and lower surfaces, both sides in the Y direction and one side (wiring 110 side) of the insulating layer 132.

[0041] In the XY cross-section illustrated in Figure 3, one side of the semiconductor layer 131 in the X direction (the wiring 120 side) can also be formed along a circle centered on the center of the via wiring 102. Furthermore, the other side of the semiconductor layer 131, insulating layer 132, and conductive layer 133 in the X direction (the wiring 110 side) can also be formed in a straight line along the side of wiring 110. Additionally, the two sides of the semiconductor layer 131, insulating layer 132, and conductive layer 133 in the Y direction can also be formed in a straight line along the side of insulating layer 105.

[0042] Semiconductor layer 131, for example, functions as a channel region for writing transistor WTr (FIG. 1). Semiconductor layer 131 may be, for example, a semiconductor containing at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. A plurality of semiconductor layers 131 arranged side-by-side in the Z direction are commonly connected to via wiring 102 extending in the Z direction. Furthermore, one side of semiconductor layer 131 in the X direction (the wiring 120 side) is connected to conductive member 150.

[0043] The insulating layer 132, for example, functions as a gate insulating film for the write transistor WTr (FIG. 1). The insulating layer 132 may contain silicon oxide (SiO2) or the like.

[0044] The conductive layer 133, for example, functions as the gate electrode of the write transistor WTr (FIG. 1). The conductive layer 133 is, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 is separated from the semiconductor layer 131 by an insulating layer 132 and faces the top, bottom, two sides in the Y direction, and one side in the X direction (the wiring 110 side). Furthermore, the side of the conductive layer 133 in the X direction (the wiring 110 side) is connected to the wiring 110.

[0045] The transistor structure 140 includes a semiconductor layer 141 that is connected to the outer peripheral surface of the through-hole wiring 103 and extends in the X direction, an insulating layer 142 that is disposed on the upper surface, lower surface, two sides in the Y direction and one side (wiring 120 side) of the semiconductor layer 141, and a conductive layer 143 that is disposed on the upper surface, lower surface, two sides in the Y direction and one side (wiring 120 side) of the insulating layer 142.

[0046] In the XY cross-section illustrated in Figure 3, one side of the semiconductor layer 141 in the X direction (the wiring 110 side) can also be formed along a circle centered on the center of the via wiring 103. Furthermore, the other side of the semiconductor layer 141, insulating layer 142, and conductive layer 143 in the X direction (the wiring 120 side) can also be formed in a straight line along the side of wiring 120. Additionally, the two sides of the semiconductor layer 141, insulating layer 142, and conductive layer 143 in the Y direction can also be formed in a straight line along the side of insulating layer 105.

[0047] Semiconductor layer 141, for example, functions as a channel region for a readout transistor RTr (FIG. 1). Semiconductor layer 141 may be, for example, a semiconductor containing at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. A plurality of semiconductor layers 141 arranged side-by-side in the Z direction are commonly connected to via wiring 103 extending in the Z direction. One side of the conductive layer 143 in the X direction (the wiring 110 side) is connected to the conductive member 150. Furthermore, in the illustrated example, the other side of the semiconductor layer 141 in the X direction (the wiring 120 side) is connected to the wiring 120 via a conductive oxide layer 144 such as indium tin oxide (ITO).

[0048] The insulating layer 142, for example, functions as a gate insulating film for the readout transistor RTr (FIG. 1). The insulating layer 142 may contain silicon oxide (SiO2) or the like.

[0049] The conductive layer 143, for example, functions as the gate electrode of the readout transistor RTr (FIG. 1). The conductive layer 143, for example, contains a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 143 is separated from the insulating layer 142 and faces the top, bottom, two sides in the Y direction, and one side in the X direction (the side of wiring 110) of the semiconductor layer 141.

[0050] The conductive member 150, for example, functions as a sensing node SN (FIG. 1). The conductive member 150, for example, comprises a conductive oxide. However, the conductive member 150 may also comprise ruthenium (Ru), iridium (Ir), or other metals. A plurality of conductive members 150 arranged side by side in the Z direction are commonly connected to an insulating member 104 extending in the Z direction.

[0051] [Manufacturing Method] Figures 5 to 46 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment. Figures 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, and 45 show cross-sections corresponding to Figure 3. Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, and 46 show cross-sections corresponding to Figure 4.

[0052] In this manufacturing method, for example as shown in Figure 6, a plurality of insulating layers 101 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA may contain, for example, silicon nitride (Si3N4). This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0053] Next, as shown in Figure 5, an insulating layer 105 is formed. This process, for example, involves forming an opening at a position corresponding to the insulating layer 105. This opening extends in the Z direction and penetrates the plurality of insulating layers 101 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction. This process, for example, is performed by RIE (Reactive Ion Etching). After the opening is formed, the insulating layer 105 is formed. This process, for example, is performed by CVD.

[0054] Next, as shown in Figures 7 and 8, openings 110A and 120A are formed near the positions corresponding to wirings 110 and 120. Openings 110A and 120A extend in the Y and Z directions, penetrating the plurality of insulating layers 101 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction, thus interrupting this configuration in the X direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0055] Furthermore, openings 110B and 120B are formed at positions corresponding to wirings 110 and 120. Inside openings 110B and 120B, a portion of the upper and lower parts of insulating layer 101, a portion of the Y-direction side of insulating layer 105, and a portion of the X-direction side of sacrificial layer MLA are exposed. In this process, for example, a portion of sacrificial layer MLA is selectively removed through openings 110A and 120A. This process is performed, for example, by wet etching.

[0056] Next, as shown in Figures 9 and 10, sacrificial layers 110C and 120C of silicon (Si) are embedded inside the openings 110A, 120A and 110B, 120B. This process is carried out, for example, by CVD.

[0057] Next, as shown in Figures 11 and 12, openings 102A and 103A are formed at positions corresponding to the through-hole wirings 102 and 103. Openings 102A and 103A, as shown in Figure 12, extend in the Z-direction and penetrate the plurality of insulating layers 101 and the plurality of sacrificial layers MLA arranged side-by-side in the Z-direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0058] Next, as shown in Figures 13 and 14, openings 130A and 140A are formed at positions corresponding to transistor structures 130 and 140. Inside openings 130A and 140A, a portion of the upper and lower parts of the insulating layer 101, a portion of the X-direction side of the sacrificial layer MLA, and a portion of the Y-direction side of the insulating layer 105 are exposed. Also, inside opening 130A, a portion of the X-direction side of the sacrificial layer 110C is exposed. Also, inside opening 140A, a portion of the X-direction side of the sacrificial layer 120C is exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed via openings 102A and 103A. This process is performed, for example, by wet etching.

[0059] Next, as shown in Figures 15 and 16, a conductive layer 133A and a sacrificial layer 130B of silicon (Si) are formed inside openings 130A and 102A. Similarly, a conductive layer 143A and a sacrificial layer 140B of silicon (Si) are formed inside openings 140A and 103A. The conductive layers 133A and 143A are formed on "the upper part, the lower part, and the exposed surface of openings 102A and 103A of the insulating layer 101", "a portion of the side surface of the sacrificial layer MLA in the X direction", "a portion of the side surface of the insulating layer 105 in the Y direction", and "a portion of the side surface of the sacrificial layers 110C and 120C in the X direction". Furthermore, opening 130A is filled by the sacrificial layer 130B, while opening 102A is not filled by the sacrificial layer 130B. Similarly, opening 140A is filled with sacrificial layer 140B, while opening 103A is not filled with sacrificial layer 140B. This work is carried out, for example, by CVD.

[0060] Next, as shown in Figures 17 and 18, a portion of the conductive layers 133A and 143A is removed. In this process, for example, the portion of the sacrificial layers 130B and 140B located within the inner peripheral surfaces of the openings 102A and 103A is removed. Next, the portion of the conductive layers 133A and 143A located within the inner peripheral surfaces of the openings 102A and 103A is removed, thus severing the conductive layers 133A and 143A in the Z-direction. This process is performed, for example, by wet etching.

[0061] Next, as shown in Figures 19 and 20, sacrificial layers 130B and 140B are formed inside the openings 102A and 103A. This process is performed, for example, by CVD. Although the figures are omitted, after this process is completed, the upper part of the openings 102A and 103A is closed with an insulating layer or the like.

[0062] Next, as shown in Figures 21 and 22, an opening 104A is formed at a position corresponding to the insulating member 104. The opening 104A, as shown in Figure 22, extends in the Z direction and penetrates the plurality of insulating layers 101 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0063] Next, as shown in Figures 23 and 24, an opening 150A is formed at a location corresponding to the conductive member 150. Inside the opening 150A, a portion of the upper and lower parts of the insulating layer 101, a portion of the X-direction side of the sacrificial layer MLA, a portion of the Y-direction side of the insulating layer 105, and a portion of the X-direction side of the conductive layer 133A are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed via the opening 104A. In this process, a portion of the sacrificial layer MLA remains, and the conductive layer 143A is not exposed inside the opening 150A. This process is performed, for example, by wet etching.

[0064] Next, conductive layers 133 and 143 are formed, for example, as shown in Figures 25 and 26. In this process, for example, the sacrificial layer 120C is removed. Also, for example, the portion of conductive layer 133A covering one side of the sacrificial layer 130B in the X direction (the side facing opening 120A) is removed. This exposes one side of the sacrificial layer 130B in the X direction inside opening 150A. Also, the portion of conductive layer 143A covering one side of the sacrificial layer 140B in the X direction (the side facing opening 120A) is removed. This exposes one side of the sacrificial layer 140B in the X direction inside opening 120B. This process is performed, for example, by wet etching.

[0065] Next, as shown in Figures 27 and 28, the sacrificial layers 130B and MLA are oxidized through openings 104A and 150A to form an insulating layer 150C. Similarly, the sacrificial layer 140B is oxidized through openings 120A and 120B to form an insulating layer 140C. Furthermore, sacrificial layers 150B and 120C of silicon (Si) are formed inside the openings 104A, 120A, and 150A and 120B. This process is performed, for example, by CVD. Although not shown in the figures, after this process is completed, the upper part of the openings 104A and 120A is closed with an insulating layer or the like.

[0066] Next, as shown in Figures 29 and 30, the sacrificial layers 130B and 140B are removed. This process is performed, for example, by wet etching.

[0067] Next, as shown in Figures 31 and 32, portions of the insulating layer 150C exposed inside the opening 130A, the insulating layer 140C exposed inside the opening 140A, and the sacrificial layers 150B and 120C are removed. This process is performed, for example, by wet etching.

[0068] Next, as shown in Figures 33 and 34, an insulating layer 132A and a sacrificial layer 130B are formed inside openings 102A and 130A. The insulating layer 132A is formed on the exposed surfaces of the conductive layer 133 (above and below) facing the opening 130A, a portion of the insulating layer 101 (above and below) and the exposed surface facing the opening 102A, a portion of the side surface of the sacrificial layer 150B in the X direction, and a portion of the side surface of the insulating layer 105 in the Y direction. Furthermore, opening 130A is filled by the sacrificial layer 130B, while opening 102A is not filled by the sacrificial layer 130B.

[0069] Similarly, an insulating layer 142A and a sacrificial layer 140B are formed inside openings 103A and 140A. The insulating layer 142A is formed on the exposed surfaces of the conductive layer 143 above and below the opening 140A, a portion of the insulating layer 101 above and below the opening 103A, a portion of the side surface of the sacrificial layer 120C in the X direction, and a portion of the side surface of the insulating layer 105 in the Y direction. Furthermore, opening 140A is filled by the sacrificial layer 140B, while opening 103A is not filled by the sacrificial layer 140B.

[0070] This process is carried out, for example, by CVD. In addition, although the illustration is omitted, after the sacrificial layers 130B and 140B are formed, the upper part of the openings 102A and 103A is closed by an insulating layer or the like.

[0071] Next, as shown in Figures 35 and 36, the sacrificial layers 150B and 120C are removed. This process is performed, for example, by wet etching.

[0072] Next, insulating layers 132 and 142 are formed, for example, as shown in Figures 37 and 38. In this process, the portion of insulating layer 132A covering one side of the sacrificial layer 130B in the X direction (the side facing opening 150A) is removed via openings 104A and 150A. This exposes the side facing the sacrificial layer 130B in the X direction inside opening 150A. Similarly, the portion of insulating layer 142A covering one side of the sacrificial layer 140B in the X direction (the side facing opening 120A) is removed via openings 120A and 120B. This exposes the side facing the sacrificial layer 140B in the X direction inside opening 120B. This process is performed, for example, by wet etching. Additionally, insulating layer 150C is also removed in this process.

[0073] Next, as shown in Figures 39 and 40, the sacrificial layer MLA is removed via openings 104A and 150A. Then, a conductive member 150 is formed on one side of the sacrificial layer 130B in the X direction (the side of opening 120A), one side of the conductive layer 143 in the X direction (the side of opening 110A), both sides of the insulating layer 105 in the Y direction, and above and below the insulating layer 101. Similarly, a conductive oxide layer 144 is formed on one side of the sacrificial layer 140B in the X direction (the side of opening 120A), one side of the insulating layer 105 in the X direction (the side of opening 120A), both sides in the Y direction, and above and below the insulating layer 101. This process is performed, for example, by ALD (Atomic Layer Deposition) and wet etching. By wet etching, the conductive member 150 is cut in the Z direction.

[0074] Furthermore, an insulating member 104 is formed inside the opening 104A. This process is carried out, for example, by means of CVD.

[0075] Next, as shown in Figures 41 and 42, the sacrificial layers 130B and 140B are removed. This process is performed, for example, by wet etching.

[0076] Next, as shown in Figures 43 and 44, semiconductor layers 131 and 141 are formed inside the openings 130A and 140A. Furthermore, via wiring 102 and 103 are formed inside the openings 102A and 103A. This process is performed, for example, by ALD and CVD.

[0077] Next, for example as shown in Figures 45 and 46, a portion of the sacrificial layer 110C and the conductive oxide layer 144 are removed. This process is performed, for example, by wet etching.

[0078] Then, as shown in Figures 3-5, wiring 110 and 120 are formed inside openings 110B and 120B. This process is performed, for example, by CVD.

[0079] [Effect] If the general method described with reference to Figures 5-46 is followed, the number of memory layers ML contained in the memory cell array MCA can be increased simply by increasing the number of sacrificial layers MLA and insulating layers 101 deposited in the process described with reference to Figure 6. Therefore, the high integration of the memory cell array MCA can be achieved more easily without increasing manufacturing costs.

[0080] The semiconductor memory device manufactured by this method comprises a plurality of memory layers ML arranged side by side in the Z direction, and via wirings 102 and 103 extending in the Z direction. Furthermore, the configurations of the plurality of memory layers ML (wirings 110 and 120, transistor structures 130 and 140, etc.) are all different when viewed from the Z direction. Moreover, the configuration of the memory layers ML is a top-to-bottom symmetrical structure.

[0081] Furthermore, as explained with reference to Figures 2 to 4, in the transistor structure 130 of this embodiment, the conductive layer 133 faces the top, bottom, and two sides in the Y direction of the semiconductor layer 131.

[0082] In this configuration, interference of electric fields between multiple semiconductor layers 131 arranged side by side in the Z direction can be suppressed. Therefore, even when the memory cell array (MCA) is highly integrated in the Z direction, the semiconductor layers 131 can be appropriately controlled to be in the ON or OFF state, thereby providing a semiconductor memory device that can operate appropriately.

[0083] Furthermore, when the write transistor WTr is set to the ON state, channels are formed on the top, bottom, and both sides in the Y direction of the semiconductor layer 131. Therefore, the ON current of the write transistor WTr can be set to a larger value. This allows for faster and more stable operation. The same applies to the transistor structure 140.

[0084] For example, it is also possible to arrange the wiring 110, which functions as the write word line (WWL), between the via wiring 102 and the conductive member 150, and utilize a portion of this wiring as the gate electrode of the write transistor WTr. However, in this configuration, the semiconductor layer, which functions as the channel region of the write transistor WTr, and the wiring, which functions as the write word line (WWL), will intersect when viewed from the Z direction. Therefore, for example, it would be necessary to process the wiring extending in the Y direction without breaking the semiconductor layer in the X direction, which would increase the manufacturing difficulty. Furthermore, the width of the memory layer in the Z direction would become larger.

[0085] Regarding this point, in this embodiment, the wiring 110, which functions as the write character line WWL, is positioned opposite the transistor structure 140 to the transistor structure 130, and is located at a position that does not overlap with the transistor structure 130 when viewed from the Z direction. Therefore, the wiring 110 and the transistor structure 130 can be formed independently of each other, making manufacturing easier. Furthermore, the wiring resistance of the wiring 110 can be set to a smaller value while suppressing the width of the memory layer ML in the Z direction. The relationship between the wiring 120 and the transistor structure 140 is also the same.

[0086] [Second Implementation] [structure] Next, referring to Figures 47 and 48, the semiconductor memory device of the second embodiment will be described. Figure 47 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. Figure 48 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration shown in Figure 47 cut along line A-A' and observed in the direction of the arrow. In the following description, the same component symbols are used for configurations identical to those in the first embodiment, and their descriptions are omitted.

[0087] The semiconductor memory device of the second embodiment is basically constructed in the same manner as the semiconductor memory device of the first embodiment.

[0088] However, the semiconductor memory device of the second embodiment replaces the wiring 120 and the transistor structure 140, and has wiring 220 and transistor structure 240. Furthermore, the semiconductor memory device of the second embodiment does not have conductive member 150 and insulating member 104; the semiconductor layer 131 in the transistor structure 130 is directly connected to the conductive layer 243 in the transistor structure 240 (described later).

[0089] Wiring 220 is basically constructed in the same manner as wiring 120. However, in addition to the barrier conductive film 121 and the conductive film 122, wiring 220 also has a conductive oxide film 221 containing conductive oxide. The conductive oxide film 221 covers the top and bottom surfaces of the barrier conductive film 121, both sides in the Y direction, one side in the X direction (the side of wiring 110), and one side in the X direction (the side of transistor structure 240), and is connected to the transistor structure 240.

[0090] Transistor structure 240 is basically constructed in the same manner as transistor structure 140. However, transistor structure 240 has semiconductor layer 241, insulating layer 242 and conductive layer 243 instead of semiconductor layer 141, insulating layer 142 and conductive layer 143.

[0091] Semiconductor layer 241, insulating layer 242 and conductive layer 243 are basically constructed in the same manner as semiconductor layer 141, insulating layer 142 and conductive layer 143.

[0092] However, in the XY cross-section as illustrated in Figure 47, the side of one side (transistor structure 130 side) of the semiconductor layer 241, insulating layer 242 and conductive layer 243 in the X direction can also be formed along a circle centered on the center position of the via wiring 102.

[0093] Furthermore, the conductive layer 243, for example, functions not only as the gate electrode of the readout transistor RTr (FIG. 1) but also as the sensing node SN. The conductive layer 243, for example, comprises a conductive oxide such as indium tin oxide (ITO).

[0094] [Manufacturing Method] Figures 49-86 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Figures 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, and 85 show cross-sections corresponding to Figure 47. Figures 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, and 86 show cross-sections corresponding to Figure 48.

[0095] In this manufacturing method, for example, it is carried out as shown in Figures 49 and 50 until the process described with reference to Figures 11 and 12 in the manufacturing process of the semiconductor memory device of the first embodiment.

[0096] Next, as shown in Figures 51 and 52, a sacrificial layer 103B of silicon (Si) or the like is formed inside the opening 103A. This process is performed, for example, by CVD. Although the figures are omitted, after this process is completed, the upper part of the opening 103A is sealed with an insulating layer or the like.

[0097] Furthermore, an opening 130A is formed at a position corresponding to the transistor structure 130. Inside the opening 130A, a portion of the upper and lower parts of the insulating layer 101, a portion of the X-direction side of the sacrificial layer MLA, a portion of the Y-direction side of the insulating layer 105, and a portion of the X-direction side of the sacrificial layer 110C are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A. This process is performed, for example, by wet etching.

[0098] Next, as shown in Figures 53 and 54, a conductive layer 133A and a sacrificial layer 130B are formed inside openings 130A and 102A. This process is performed, for example, in the same manner as the process described with reference to Figures 15 and 16.

[0099] Next, the sacrificial layer 103B is removed, for example as shown in Figures 55 and 56. This process is performed, for example, by wet etching.

[0100] Next, as shown in Figures 57 and 58, an opening 240A is formed at a position corresponding to the transistor structure 240. Inside the opening 240A, a portion of the upper and lower parts of the insulating layer 101, a portion of the X-direction side of the conductive layer 133A, a portion of the Y-direction side of the insulating layer 105, and a portion of the X-direction side of the sacrificial layer 120C are exposed. In this process, for example, the sacrificial layer MLA is removed through the opening 103A. This process is performed, for example, by wet etching.

[0101] Next, for example as shown in Figures 59 and 60, a portion of the conductive layer 133A is removed, exposing one side of the sacrificial layer 130B in the X direction. This process is performed, for example, in the same manner as that described with reference to Figures 25 and 26.

[0102] Next, as shown in Figures 61 and 62, sacrificial layers 130B and 120C are oxidized through openings 103A and 240A to form insulating layers 130C and 120D. Then, a sacrificial layer 240B of silicon (Si) or the like is formed inside 103A and 240A. This process is performed, for example, by CVD. Although not shown in the figures, after this process is completed, the upper part of opening 103A is closed using an insulating layer or the like.

[0103] Next, as shown in Figures 63 and 64, the sacrificial layer 130B is removed. This process is performed, for example, by wet etching. In this process, the exposed surface of the conductive layer 133A relative to the opening 102A is removed, and the conductive layer 133A is cut in the Z direction.

[0104] Next, for example as shown in Figures 65 and 66, a portion of the insulating layer 130C and the sacrificial layer 240B is removed. This process is performed, for example, by wet etching.

[0105] Next, as shown in Figures 67 and 68, an insulating layer 132A and a sacrificial layer 130B are formed inside the openings 102A and 130A. This process is performed, for example, in the same manner as the process described with reference to Figures 33 and 34.

[0106] Next, the sacrificial layer 240B is removed, for example as shown in Figures 69 and 70. This process is performed, for example, by wet etching.

[0107] Furthermore, this is part of forming the insulating layer 132A. This process, for example, is performed in the same manner as the process described with reference to Figures 37 and 38. In this process, the insulating layer 120D is also removed.

[0108] Next, as shown in Figures 71 and 72, a conductive layer 243A and a sacrificial layer 240B are formed inside openings 240A and 103A. This process is performed, for example, in the same manner as the process described with reference to Figures 15 and 16.

[0109] Next, for example as shown in Figures 73 and 74, a portion of the conductive layer 243A is removed, exposing one side of the sacrificial layer 240B in the X direction. In this process, for example, the sacrificial layer 120C is removed by wet etching, and then the same process as described with reference to Figures 25 and 26 is performed.

[0110] Furthermore, the sacrificial layer 240B is oxidized through openings 120A and 120B to form an insulating layer 240C. Then, a sacrificial layer 120C of silicon (Si) or similar material is formed inside the openings 120A and 120B. This process is performed, for example, by CVD.

[0111] Next, as shown in Figures 75 and 76, the sacrificial layer 240B is removed. This process is performed, for example, by wet etching. In this process, the exposed surface of the conductive layer 243A relative to the opening 103A is removed, and the conductive layer 243A is cut in the Z direction.

[0112] Furthermore, a portion of the insulating layer 240C and the sacrificial layer 120C is removed. This process is performed, for example, by wet etching.

[0113] Next, as shown in Figures 77 and 78, an insulating layer 242A and a sacrificial layer 240B are formed inside the openings 103A and 240A. This process is performed, for example, in the same manner as the process described with reference to Figures 33 and 34. Although the figures are omitted, after this process is completed, the upper part of the opening 103A is closed by the insulating layer or the like.

[0114] Next, the sacrificial layer 120C is removed, for example as shown in Figures 79 and 80. This process is performed, for example, by wet etching.

[0115] Furthermore, this forms part of the insulating layer 242A, and exposes one side of the sacrificial layer 240B in the X direction. This process, for example, is performed in the same manner as the process described with reference to Figures 37 and 38.

[0116] Next, as shown in Figures 81 and 82, a conductive oxide film 221 and a sacrificial layer 120C are formed at the opening 120B. This process is performed, for example, by ALD, CVD, wet etching, etc.

[0117] Next, as shown in Figures 83 and 84, the sacrificial layers 110C and 120C are removed. This process is performed, for example, by wet etching. In this process, the exposed surface of the conductive oxide film 221 opposite to the opening 102A is removed, and the conductive oxide film 221 is segmented in the Z direction.

[0118] Next, as shown in Figures 85 and 86, wiring 110 and 220 are formed inside the openings 110B and 120B. This process is performed, for example, by CVD.

[0119] Next, sacrificial layers 130B and 240B are removed, and semiconductor layers 131 and 241 are formed inside the openings 130A and 240A, as shown in Figures 47 and 48, for example. Furthermore, via wiring 102 and 103 are formed inside the openings 102A and 103A. This process is performed, for example, by ALD and CVD.

[0120] [Effect] As described above, the semiconductor memory device of the second embodiment does not include the conductive member 150 and the insulating member 104; the semiconductor layer 131 in the transistor structure 130 is directly connected to the conductive layer 243. With this configuration, compared to the semiconductor memory device of the first embodiment, the unit area of ​​a memory cell MC can be reduced. Therefore, according to the second embodiment, a high degree of integration of the semiconductor memory device can be achieved.

[0121] [Third Implementation Form] Figure 87 is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor memory device according to the first embodiment. In Figure 87, the readout operation of the semiconductor memory device is illustrated.

[0122] As explained with reference to FIG1, during the readout operation of the semiconductor memory device of the first embodiment, for example, a power supply voltage Vdd is supplied to the readout word line RWL that is the object of the readout operation, and a ground voltage Vss is supplied to the others. Here, when the sensing node SN of the selected memory cell MCs is charged by the power supply voltage Vdd, the voltage of the readout word line RBL rises because the readout transistor RTr is in the ON state.

[0123] Here, the read bit line RBL is connected to the read word line RWL via multiple read transistors RTR. Therefore, if the voltage of the read bit line RBL increases, a leakage current IL will occur from the read bit line RBL to the read word line RWL via an ON-state memory cell MC that is not the object of the read operation. Consequently, the current flowing in the read bit line RBL decreases, and the charge on the read bit line RBL will be discharged. This could lead to an increase in the time required for the read operation or even prevent the read operation from being performed properly.

[0124] Therefore, in the semiconductor memory device of the third embodiment, a transistor is added to the memory cell MC, thereby suppressing the occurrence of leakage current IL.

[0125] The semiconductor memory device of the third embodiment will now be described with reference to the drawings. In the following description, components identical to those in the first embodiment will be represented by the same reference numerals and their descriptions will be omitted.

[0126] [Circuit Structure] Figure 88 is a schematic circuit diagram illustrating a portion of the configuration of a semiconductor memory device according to the third embodiment.

[0127] As shown in Figure 88, the semiconductor memory device of this embodiment includes a memory cell array MCA3. The memory cell array MCA3 includes a plurality of memory layers ML3, a plurality of write bit lines WBL connected to the plurality of memory layers ML3, a plurality of voltage supply lines VDD connected to the plurality of memory layers ML3, and a plurality of read bit lines RBL connected to the plurality of memory layers ML3. The voltage supply line VDD supplies the power supply voltage Vdd.

[0128] The memory layer ML3 comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC3 connected to these write word lines WWL and read word lines RWL. Each memory cell MC3 comprises a write transistor WTr, a sense node SN, a read transistor RTr3, a connection node CN, and a switching transistor STr.

[0129] The readout transistor RTr3 is, for example, a field-effect NMOS transistor. One electrode of the readout transistor RTr3 is connected to the voltage supply line VDD. The other electrode of the readout transistor RTr3 is connected to the connection node CN. One and the other electrodes of the readout transistor RTr3 function as source or drain electrodes depending on the voltage supplied to the readout transistor RTr3. The gate electrode of the readout transistor RTr3 is connected to the sensing node SN.

[0130] The switching transistor STr is, for example, a field-effect NMOS transistor. One electrode of the switching transistor STr is connected to the read bit line RBL. The other electrode of the switching transistor STr is connected to the connection node CN. One and the other electrodes of the switching transistor STr function as source or drain electrodes depending on the voltage supplied to the switching transistor STr. The gate electrode of the switching transistor STr is connected to the read word line RWL.

[0131] The write operation of the semiconductor memory device in the third embodiment can be performed in the same way as the write operation of the semiconductor memory device in the first embodiment.

[0132] The read operation of the semiconductor memory device in the third embodiment is basically the same as that of the semiconductor memory device in the first embodiment. However, in the read operation of the semiconductor memory device in the third embodiment, a power supply voltage Vdd is supplied to the voltage supply line VDD.

[0133] In the third embodiment, similarly, during the read operation, a power supply voltage Vdd is supplied to the read-target among the plurality of read word lines RWL, and a ground voltage Vss is supplied to the others. As a result, the transistor STr in the memory layer ML3, which is the read-target, is in the ON state, while the transistors STr in other memory layers ML3 are in the OFF state. Therefore, the read bit line RBL is connected to the read transistor RTr3 in the memory layer ML3, which is the read-target, and is electrically disconnected from the read transistors RTr3 in other memory layers ML3. This suppresses the occurrence of the aforementioned general leakage current IL.

[0134] [structure] Figure 89 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment. Figure 90 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration of the structure shown in Figure 89 cut along line A-A' and observed in the direction of the arrow.

[0135] The memory cell array MCA3 has a plurality of memory layers ML3 arranged side by side in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML3.

[0136] Furthermore, via wirings 102, 302, and 103 are provided at the memory cell array MCA3. Via wiring 302 functions as a voltage supply line VDD. Via wirings 102, 302, and 103 are arranged sequentially side by side in the X direction and extend through multiple memory layers ML3 in the Z direction.

[0137] The through-hole wiring 302, for example, includes: a conductive oxide film 302a comprising a conductive oxide, a barrier conductive film 302b such as titanium nitride (TiN), and a conductive component 302c such as tungsten (W). Alternatively, the through-hole wiring 302 may replace the conductive oxide film 302a by including ruthenium (Ru), iridium (Ir), or other metals. Furthermore, the through-hole wiring 302 may also consist only of a conductive oxide, or only of ruthenium (Ru), iridium (Ir), or other metals.

[0138] The conductive component 302c has a slightly cylindrical shape extending in the Z direction. The barrier conductive film 302b has a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive component 302c. The conductive oxide film 302a has a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 302b.

[0139] Furthermore, at the memory cell array MCA3, insulating members 104 and 304, such as silicon oxide (SiO2), are disposed. Insulating member 104 is disposed between via wirings 102 and 302, and extends in the Z direction through multiple memory layers ML3. Insulating member 304 is disposed between via wirings 302 and 103, and extends in the Z direction through multiple memory layers ML3.

[0140] The memory layer ML3 includes "wiring 110, 120 arranged side-by-side in the X direction and extending in the Y direction", "transistor structures 130, 340 disposed between these wiring 110, 120", "transistor structure 330 disposed between these transistor structures 130, 340", "conductive member 150 disposed between the transistor structures 130, 330", and "conductive member 350 disposed between the transistor structures 330, 340". Transistor structures 130, 330, and 340 are respectively disposed at positions corresponding to via wirings 102, 302, and 103. Conductive member 150 is disposed at a position corresponding to insulating member 104. Conductive member 350 is disposed at a position corresponding to insulating member 304. In the illustrated example, transistor structures 130, 330, and 340 and conductive components 150 and 350 are arranged side by side in the X direction.

[0141] Transistor structure 330 is basically constructed in the same way as transistor structure 140. However, transistor structure 330 replaces semiconductor layer 141, insulating layer 142 and conductive layer 143, and has semiconductor layer (semiconductor part) 331, insulating layer (insulating part) 332 and conductive layer 333.

[0142] Semiconductor layer 331, insulating layer 332 and conductive layer 333 are basically constructed in the same manner as semiconductor layer 141, insulating layer 142 and conductive layer 143.

[0143] However, in the XY cross-section as illustrated in Figure 89, one side of the semiconductor layer 331 in the X direction (the wiring 120 side) can also be formed along a circle centered on the center position of the via wiring 302. Furthermore, the other side of the semiconductor layer 331, the insulating layer 332, and the conductive layer 333 in the X direction (the wiring 110 side) can also be formed along a circle centered on the center position of the via wiring 302.

[0144] In addition, the conductive layer 333 is disposed at a position that overlaps with the semiconductor layer 331 but does not overlap with the semiconductor layer 341 when viewed from the Z direction.

[0145] The transistor structure 340, for example as shown in FIG89, includes a semiconductor layer (semiconductor portion) 341 that is connected to the outer peripheral surface of the via wiring 103 and extends in the X direction, an insulating layer (insulating portion) 342 disposed on the upper surface, lower surface, two sides in the Y direction and one side (wiring 120 side) of the semiconductor layer 341, and a conductive layer 343 disposed on the upper surface, lower surface, two sides in the Y direction and one side (wiring 120 side) of the insulating layer 342.

[0146] In the XY cross-section illustrated in Figure 89, one side of the semiconductor layer 341 in the X direction (the wiring 110 side) can also be formed along a circle centered on the center of the via wiring 103. Furthermore, the other side of the semiconductor layer 341, insulating layer 342, and conductive layer 343 in the X direction (the wiring 120 side) can also be formed in a straight line along the side of wiring 120. Additionally, the two sides of the semiconductor layer 341, insulating layer 342, and conductive layer 343 in the Y direction can also be formed in a straight line along the side of insulating layer 105.

[0147] Semiconductor layer 341, for example, functions as a channel region for a switching transistor STr (FIG. 88). Semiconductor layer 341 may be, for example, a semiconductor containing at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. A plurality of semiconductor layers 341 arranged side-by-side in the Z-direction are commonly connected to via wiring 103 extending in the Z-direction.

[0148] The insulating layer 342, for example, functions as the gate insulating film of the switching transistor STr (Fig. 88). The insulating layer 342, for example, contains silicon oxide (SiO2) or the like.

[0149] The conductive layer 343, for example, functions as the gate electrode of a switching transistor STr (FIG. 88). The conductive layer 343 may be, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 343 is positioned across the insulating layer 342 and faces the top, bottom, both sides in the Y direction, and one side (the wiring 120 side) of the semiconductor layer 341. The conductive layer 343 is disposed at a location that overlaps with the semiconductor layer 341 when viewed from the Z direction but does not overlap with the semiconductor layer 331.

[0150] [Manufacturing Method] The semiconductor memory device of the third embodiment can be manufactured in the same manner as the semiconductor memory device of the first embodiment.

[0151] However, in the manufacturing of the semiconductor memory device of the third embodiment, in the process described with reference to Figures 11 and 12, an opening is also formed at the position corresponding to the through-hole wiring 302.

[0152] Furthermore, in the project described with reference to Figures 21 and 22, an opening is also formed at a position corresponding to the insulating member 304.

[0153] Furthermore, in the process described with reference to Figures 35 and 36, the sacrificial layer 120C is not removed; instead, the sacrificial layer inside the opening located at the position corresponding to the insulating member 304 is removed.

[0154] [Fourth Implementation Form] In the second embodiment, the conductive member 150 and the insulating member 104 are omitted from the semiconductor memory device of the first embodiment, thereby achieving high integration of the semiconductor memory device of the first embodiment. Similarly, the semiconductor memory device of the third embodiment can also achieve high integration by omitting the conductive members 150 and 350 and the insulating members 104 and 304.

[0155] The semiconductor memory device of the fourth embodiment will now be described with reference to the drawings. In the following description, components identical to those in the first to third embodiments will be represented by the same component symbols, and their descriptions will be omitted.

[0156] [structure] Figure 91 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. Figure 92 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration of the structure shown in Figure 91 cut along line A-A' and observed in the direction of the arrow.

[0157] The semiconductor memory device of the fourth embodiment is basically constructed in the same manner as the semiconductor memory device of the third embodiment.

[0158] However, the semiconductor memory device in the fourth embodiment does not have a conductive member 150 and an insulating member 104. The semiconductor layer 131 in the transistor structure 130 is directly connected to the conductive layer 243 in the transistor structure 430 described later.

[0159] Furthermore, the semiconductor memory device in the fourth embodiment does not have transistor structures 330 and 340, conductive member 350 and insulating member 304, but instead has transistor structures 430 and 440.

[0160] Transistor structure 430 is basically constructed in the same way as transistor structure 240 (Figs. 47 and 48). However, transistor structure 430 has a semiconductor portion 431 and an insulating portion 432 instead of semiconductor layer 241 and insulating layer 242.

[0161] Transistor structure 440 is basically constructed in the same manner as transistor structure 340 (Figs. 89 and 90). However, transistor structure 440 has a semiconductor portion 441 and an insulating portion 442 instead of semiconductor layer 341 and insulating layer 342.

[0162] Semiconductor portion 431 and insulating portion 432 are basically constructed in the same manner as semiconductor layer 241 and insulating layer 242. Similarly, semiconductor portion 441 and insulating portion 442 are basically constructed in the same manner as semiconductor layer 341 and insulating layer 342.

[0163] However, semiconductor portion 431 is continuous with semiconductor portion 441 and is directly connected to it. Semiconductor portion 431 and semiconductor portion 441 are each part of a semiconductor layer extending in the X direction. Similarly, insulating portion 432 is continuous with insulating portion 442 and is directly connected to it. Insulating portion 432 and insulating portion 442 are each part of an insulating layer.

[0164] Furthermore, in this embodiment, the conductive layer 243 is disposed at a position that overlaps with the semiconductor portion 431 but not with the semiconductor portion 441 when viewed from the Z direction. Similarly, the conductive layer 343 is disposed at a position that overlaps with the semiconductor portion 441 but not with the semiconductor portion 431 when viewed from the Z direction.

[0165] [Manufacturing Method] Figures 93-103 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device in the fourth embodiment. Figures 93-103 show cross-sections corresponding to those in Figure 92.

[0166] In this manufacturing method, for example, it is carried out as shown in FIG. 93 until the process described with reference to FIG. 19 and FIG. 20 in the manufacturing process of the semiconductor memory device of the first embodiment.

[0167] Furthermore, an opening 302A is formed at a position corresponding to the through-hole wiring 302. The opening 302A extends in the Z direction and penetrates a plurality of insulating layers 101 and a plurality of sacrificial layers MLA arranged side by side in the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0168] Next, as shown in Figure 94, an opening 430A is formed at a position corresponding to the transistor structure 430. Inside the opening 430A, a portion of the upper and lower parts of the insulating layer 101, a portion of the X-direction side of the conductive layer 143A, a portion of the Y-direction side of the insulating layer 105, and a portion of the X-direction side of the conductive layer 133A are exposed. In this process, for example, the sacrificial layer MLA is selectively removed through the opening 302A. This process is performed, for example, by wet etching.

[0169] Furthermore, conductive layers 133 and 343 are formed. Conductive layer 133 is formed, for example, in the same manner as described with reference to Figures 25 and 26. Also, a portion of the conductive layer 143A covering one side of the sacrificial layer 140B in the X direction (the side facing the opening 110A) is removed. This exposes one side of the sacrificial layer 140B in the X direction inside the opening 430A. This process is performed, for example, by wet etching.

[0170] Next, as shown in Figure 95, a sacrificial layer 430B of silicon (Si) or the like is formed inside the openings 302A and 430A. This process is performed, for example, by CVD. Although not shown in the figure, after this process is completed, the upper part of the opening 302A is sealed with an insulating layer or the like.

[0171] Next, for example as shown in Figure 96, the sacrificial layer 130B is removed. This process is performed, for example, by wet etching.

[0172] Furthermore, a portion of the sacrificial layer 430B is removed. This process is performed, for example, by wet etching.

[0173] Next, for example as shown in FIG97, an insulating layer 132A and a sacrificial layer 130B are formed inside the openings 130A and 102A. This process is performed, for example, in the same manner as the process described with reference to FIG33 and FIG34.

[0174] Next, for example as shown in Figure 98, the sacrificial layer 430B is removed. This process is performed, for example, by wet etching.

[0175] Furthermore, an insulating layer 132 is formed. This process, for example, is carried out in the same manner as the process described with reference to Figures 37 and 38.

[0176] Next, as shown in Figure 99, a conductive layer 243A is formed via opening 302A on one side of the sacrificial layer 130B in the X direction (the side of opening 120A), one side of the sacrificial layer 140B in the X direction (the side of opening 110A), both sides of the insulating layer 105 in the Y direction, and above and below the insulating layer 101. This process is performed, for example, by CVD.

[0177] Furthermore, a sacrificial layer 430B is formed inside the openings 430A and 302A. This process is performed, for example, by CVD. Additionally, although the illustration is omitted, after this process is completed, the upper part of the opening 302A is sealed with an insulating layer or the like.

[0178] Next, for example, as shown in Figure 100, the sacrificial layer 140B is removed. Also, for example, the portion of the conductive layer 243A that covers one side of the sacrificial layer 430B in the X direction (the side facing the opening 120A) is removed. Thus, inside the opening 103A, one side of the sacrificial layer 430B in the X direction is exposed. This process is performed, for example, by wet etching.

[0179] Next, for example as shown in Figure 101, the sacrificial layer 430B is removed. This process is performed, for example, by wet etching.

[0180] Next, as shown in Figure 102, a conductive layer 243 is formed. In this process, for example, a sacrificial layer 430B, such as silicon, is formed inside the openings 430A and 302A. Next, the portion of the sacrificial layer 430B that is disposed at the inner peripheral surface of the opening 302A is removed. Next, the portion of the conductive layer 243A that is disposed at the inner peripheral surface of the opening 302A is removed, and the conductive layer 243A is divided in the Z direction. Then, the sacrificial layer 430B is removed. This process is performed, for example, by CVD and wet etching.

[0181] Next, as shown in Figure 103, insulating portions 432 and 442 are formed inside the openings 430A, 302A, 140A, and 103A. The insulating portions 432 and 442 are formed on the "above and below the conductive layers 243 and 343", "a portion of the upper part and a portion of the lower part of the insulating layer 101 and the exposed surface of the openings 302A and 103A", and "a portion of the side surface of the insulating layer 105 in the Y direction".

[0182] Subsequently, as shown in Figures 91 and 92, semiconductor portions 431 and 441 are formed inside openings 430A and 140A. Through-hole wirings 302 and 103 are formed inside openings 302A and 103A. A semiconductor layer 131 is formed inside opening 130A, and through-hole wiring 102 is formed inside opening 102A. Furthermore, wirings 110 and 120 are formed. This process is performed, for example, by ALD, CVD, wet etching, etc.

[0183] [Effect] As explained with reference to Figures 91 and 92, the semiconductor memory device of the fourth embodiment does not include the conductive member 150 and the insulating member 104. The semiconductor layer 131 in the transistor structure 130 is directly connected to the conductive layer 243 in the transistor structure 430. Furthermore, the semiconductor memory device of the fourth embodiment does not include the conductive member 350 and the insulating member 304. The semiconductor portion 431 in the transistor structure 430 is directly connected to the semiconductor portion 441 in the transistor structure 440. With this configuration, compared to the semiconductor memory device of the third embodiment, the unit area of ​​a memory cell MC3 can be reduced. Therefore, according to the fourth embodiment, a high degree of integration of the semiconductor memory device can be achieved.

[0184] [Fifth Implementation Form] As described above, the semiconductor memory device according to the third embodiment can suppress the occurrence of leakage current IL during readout. However, as explained with reference to FIG88, the memory cell MC3 of the third embodiment includes a switching transistor STr in addition to the write transistor WTr and the read transistor RTr. Therefore, as explained with reference to FIGS89 and 90, the memory cell MC3 of the semiconductor memory device of the third embodiment includes three through-hole wirings 102, 302, and 103 and two insulating members 104 and 304, which makes high integration more difficult compared to the semiconductor memory device of the first embodiment.

[0185] Therefore, in the semiconductor memory device of the fifth embodiment, a readout transistor RTr with a floating gate is used to suppress the occurrence of the leakage current IL. With this configuration, since the occurrence of leakage current IL can be suppressed by two transistors, the high integration is easier compared to the semiconductor memory device of the third embodiment.

[0186] The semiconductor memory device of the fifth embodiment will now be described with reference to the drawings. In the following description, components identical to those in the first to fourth embodiments will be represented by the same component symbols, and their descriptions will be omitted.

[0187] [Circuit Structure] Figure 104 is a schematic circuit diagram illustrating a portion of the configuration of a semiconductor memory device according to the fifth embodiment.

[0188] As shown in Figure 104, the semiconductor memory device of this embodiment includes a memory cell array MCA5. The memory cell array MCA5 includes a plurality of memory layers ML5, a plurality of write bit lines WBL connected to the plurality of memory layers ML5, a voltage supply line VDD supplying a power supply voltage Vdd, and a plurality of read bit lines RBL connected to the plurality of memory layers ML5.

[0189] The memory layer ML5 comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC5 connected to these write word lines WWL and read word lines RWL. Each memory cell MC5 comprises a write transistor WTr, a sense node SN, and a read transistor RTr5.

[0190] The readout transistor RTr5 is, for example, a field-effect NMOS transistor with a floating gate. One electrode of the readout transistor RTr5 is connected to the voltage supply line VDD. The other electrode of the readout transistor RTr5 is connected to the read bit line RBL. One and the other electrodes of the readout transistor RTr5 function as source or drain electrodes depending on the voltage supplied to the readout transistor RTr5. The gate electrode of the readout transistor RTr5 is connected to the read word line RWL. The floating gate of the readout transistor RTr5 is connected to the sensing node SN.

[0191] The write operation of the semiconductor memory device in the fifth embodiment can be performed in the same way as the write operation of the semiconductor memory device in the first embodiment.

[0192] The read operation of the semiconductor memory device in the fifth embodiment can be performed in the same way as the read operation of the semiconductor memory device in the third embodiment.

[0193] Therefore, in the fifth embodiment, similarly, during the read operation, a power supply voltage Vdd is supplied to the read character lines RWL that are the objects of the read operation, and a ground voltage Vss is supplied to the others. Thus, the sensing nodes SN in the read transistor RTr5 of the memory layer ML5 that are the objects of the read operation are in the ON state if they are charged by the power supply voltage Vdd, and in the OFF state if they are not charged by the power supply voltage Vdd. Furthermore, the read transistors RTr5 in the memory layer ML5 that are not the objects of the read operation are in the OFF state. This allows for the suppression of the aforementioned general leakage current IL.

[0194] [structure] Figure 105 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the fifth embodiment. Figure 106 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration of the structure shown in Figure 105 cut along line A-A' and observed in the direction of the arrow.

[0195] The memory cell array MCA5 has a plurality of memory layers ML5 arranged side by side in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML5.

[0196] Furthermore, via wirings 102, 302, and 103 are provided at the memory cell array MCA5. The via wirings 102, 302, and 103 are arranged side by side in the X direction and extend through multiple memory layers ML5 in the Z direction.

[0197] The memory layer ML5 includes "wirings 110 and 120 arranged side-by-side in the X direction and extending in the Y direction", and "transistor structures 530 and 540 disposed between these wirings 110 and 120". Transistor structure 530 is disposed at a position corresponding to via wiring 102. Transistor structure 540 is disposed at a position corresponding to via wirings 302 and 103.

[0198] Transistor structure 530 is basically constructed in the same manner as transistor structure 130. However, transistor structure 530 replaces insulating layer 132 with insulating portion 532. Insulating portion 532 is basically constructed in the same manner as insulating layer 132. However, insulating portion 532 is continuous with insulating portion 544 (described later in transistor structure 540) and is directly connected to each other. Insulating portion 532 and insulating portion 544 are each part of a single insulating layer.

[0199] The transistor structure 540, for example as shown in FIG106, includes a semiconductor layer 541 that is connected to the outer peripheral surface of the via wirings 302 and 103 and extends in the X direction, an insulating layer 542 disposed on the upper and lower surfaces, both sides in the Y direction and both sides in the X direction of the semiconductor layer 541, a conductive layer 543 disposed on the upper and lower surfaces, both sides in the Y direction and both sides in the X direction of the insulating layer 542, an insulating portion 544 disposed on the upper and lower surfaces, both sides in the Y direction and one side (wiring 120 side) of the conductive layer 543, and a conductive layer 545 disposed on the upper and lower surfaces, both sides in the Y direction and one side (wiring 120 side) of the insulating portion 544.

[0200] In the XY cross-section as illustrated in Figure 105, the side surface of one side (the wiring 110 side) of the semiconductor layer 541, insulating layer 542, and conductive layer 543 in the X direction can also be formed along a circle centered on the center position of the via wiring 302. Furthermore, the side surface of the other side (the wiring 120 side) of the semiconductor layer 541, insulating layer 542, conductive layer 543, insulating portion 544, and conductive layer 545 in the X direction can also be formed in a straight line along the side surface of wiring 120. Additionally, the two side surfaces of the semiconductor layer 541, insulating layer 542, conductive layer 543, insulating portion 544, and conductive layer 545 in the Y direction can also be formed in a straight line along the side surface of insulating layer 105.

[0201] Semiconductor layer 541, for example, functions as a channel region for a readout transistor RTr5 (FIG. 104). Semiconductor layer 541 may be, for example, a semiconductor containing at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. Semiconductor layer 541 includes a semiconductor portion 541a connected to the outer peripheral surface of via wiring 302, and a semiconductor portion 541b connected to the outer peripheral surface of via wiring 103. A plurality of semiconductor portions 541a arranged side-by-side in the Z-direction are commonly connected to via wiring 302 extending in the Z-direction. A plurality of semiconductor portions 541b arranged side-by-side in the Z-direction are commonly connected to via wiring 103 extending in the Z-direction. In the example of Figure 106, the length of semiconductor section 541a in the Z direction is greater than the length of semiconductor section 541b in the Z direction.

[0202] The insulating layer 542, for example, functions as the gate insulating film of the readout transistor RTr5 (FIG. 104). The insulating layer 542, for example, contains silicon oxide (SiO2) or the like.

[0203] The conductive layer 543, for example, functions as the floating gate of the readout transistor RTr5 (FIG. 104) and the sensing node SN (FIG. 104). The conductive layer 543, for example, is a conductive oxide containing indium tin oxide (ITO). The conductive layer 543 is separated from the semiconductor layer 541 by the insulating layer 542 and faces the top, bottom, two sides in the Y direction, and two sides in the X direction. Furthermore, the conductive layer 543 is connected to one side (the wiring 120 side) of the semiconductor layer 131 in the X direction. The conductive layer 543 is positioned at a location that overlaps with both the semiconductor portion 541b and the semiconductor portion 541a when viewed from the Z direction.

[0204] The insulating portion 544, for example, functions as the gate insulating film of the readout transistor RTr5 (FIG. 104). The insulating layer 542, for example, contains silicon oxide (SiO2) or the like.

[0205] The conductive layer 545, for example, functions as the gate electrode of the readout transistor RTr5 (FIG. 104). The conductive layer 545 may be, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 545 is positioned across the insulating portion 544, the conductive layer 543, and the insulating layer 542, facing the top, bottom, both sides in the Y direction, and one side (the wiring 120 side) of the semiconductor layer 541. The conductive layer 545 is located at a position that overlaps with the semiconductor portion 541b but not with the semiconductor portion 541a when viewed from the Z direction.

[0206] [Manufacturing Method] Figures 107-131 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Figures 107, 109, 111, 113, 115, 117, 119, 121, 123, 126, 128, and 130 show cross-sections corresponding to Figure 105. Figures 108, 110, 112, 114, 116, 118, 120, 122, 124, 125, 127, 129, and 131 show cross-sections corresponding to Figure 106.

[0207] In this manufacturing method, for example, the process is carried out up to the part of the manufacturing process of the semiconductor memory device of the first embodiment, as described with reference to FIG9 and FIG10.

[0208] Next, as shown in Figures 107 and 108, openings 102A, 302A, and 103A are formed at positions corresponding to the through-hole wirings 102, 302, and 103. This process is performed, for example, by means of a RIE (Rail Interchange).

[0209] Next, as shown in Figures 109 and 110, the sacrificial layer MLA is removed, and an opening 540A is formed. This process is performed, for example, by wet etching.

[0210] Next, as shown in Figures 111 and 112, a conductive layer 545A and a sacrificial layer 540B of silicon (Si) are formed inside the openings 540A, 102A, 302A, and 103A. The conductive layer 545A and the sacrificial layer 540B are formed on "the upper portion, the lower portion, and the exposed surfaces of openings 102A, 302A, and 103A of the insulating layer 101", "a portion of the side surface of the insulating layer 105 in the Y direction", and "a portion of the side surface of the sacrificial layers 110C and 120C in the X direction". Furthermore, opening 540A is filled by the sacrificial layer 540B, while openings 102A, 302A, and 103A are not filled by the sacrificial layer 540B. This process is performed, for example, by CVD.

[0211] Next, as shown in Figures 113 and 114, the portions of the sacrificial layer 540B "located on the inner peripheral surfaces of openings 102A, 302A, and 103A" and "located near opening 302A" are removed. This process is performed, for example, by wet etching.

[0212] Next, conductive layers 133 and 545 are formed, for example, as shown in Figures 115 and 116. In this process, for example, the portion of conductive layer 545A located on the inner peripheral surfaces of openings 102A, 302A, and 103A, and the portion located near opening 302A, are removed, thus dividing conductive layer 545A in the Z and X directions. Furthermore, sacrificial layer 540B is removed. This process is performed, for example, by wet etching.

[0213] Next, as shown in Figures 117 and 118, insulating portions 532 and 544 are formed inside the openings 540A, 102A, 302A, and 103A. Insulating portions 532 and 544 are formed on the "top and bottom surfaces, both sides in the X direction, and both sides in the Y direction of conductive layers 133 and 545", "a portion of the top surface of insulating layer 101, a portion of the bottom surface, and the exposed surfaces of openings 102A, 302A, and 103A", and "a portion of the side surface of insulating layer 105 in the Y direction". This process is performed, for example, by CVD.

[0214] Next, as shown in Figures 119 and 120, a sacrificial layer 540B is formed inside the openings 540A, 102A, 302A, and 103A. This process is performed, for example, by CVD. Although not shown in the figures, after this process, the upper part of opening 102A is sealed with an insulating layer or the like.

[0215] Next, as shown in Figures 121 and 122, the portions of the sacrificial layer 540B "located on the inner peripheral surfaces of openings 302A and 103A" and "located near openings 302A and 103A" are removed. This process is performed, for example, by wet etching.

[0216] Next, as shown in Figures 123 and 124, a conductive layer 543A and a sacrificial layer 540B are formed inside the openings 540A, 302A, and 103A. This process is performed, for example, by ALD, CVD, etc.

[0217] Next, as shown in Figure 125, a conductive layer 543 is formed. In this process, for example, the portion of the sacrificial layer 540B located at the inner peripheral surfaces of openings 302A and 103A is removed. Next, the portion of the conductive layer 543A located at the inner peripheral surfaces of openings 302A and 103A is removed, and the conductive layer 543A is divided in the Z direction. Then, the sacrificial layer 540B is removed. This process is performed, for example, by wet etching.

[0218] Next, as shown in Figures 126 and 127, an insulating layer 542 and a semiconductor layer 541 are formed inside the openings 540A, 302A, and 103A. This process is performed, for example, by CVD, ALD, or the like. Although not shown in the figures, after this process, the upper parts of the openings 302A and 103A are closed by the insulating layer or the like.

[0219] Next, as shown in Figures 128 and 129, a semiconductor layer 131 is formed. In this process, for example, the sacrificial layer 540B is removed through opening 102A. Furthermore, the semiconductor layer 131 is formed inside openings 540A and 102A. This process is performed, for example, by wet etching and ALD.

[0220] Next, as shown in Figures 130 and 131, through-hole wiring 102, 302, and 103 are formed inside the openings 102A, 302A, and 103A. This process is performed, for example, by ALD and CVD.

[0221] Then, for example, the sacrificial layers 110C and 120C are removed. Also, as shown in Figures 105 and 106, wiring 110 and 120 are formed inside the openings 110B and 120B. This process is performed, for example, by CVD.

[0222] [Variation Example] In the examples of Figures 105 and 106, the semiconductor layer 131 is directly connected to the conductive layer 543. However, the semiconductor memory device of the fifth embodiment may also include, for example, a plurality of conductive members 150 and insulating members 104 as described with reference to Figures 2-4. Furthermore, the plurality of semiconductor layers 131 arranged side by side in the Z direction may also be connected to the conductive layer 543 via conductive members 150.

[0223] [Sixth Implementation Form] As described above, the semiconductor memory device according to the fifth embodiment, like the semiconductor memory device of the third embodiment, is able to suppress the occurrence of leakage current IL during readout. Furthermore, the semiconductor memory device of the fifth embodiment is easier to integrate than the semiconductor memory device of the third embodiment.

[0224] As described with reference to FIG106, in the semiconductor memory device of the fifth embodiment, the conductive layer 543 is disposed at a position that overlaps with both the semiconductor portion 541b and the semiconductor portion 541a when viewed from the Z direction. The conductive layer 545 is disposed at a position that overlaps with the semiconductor portion 541b but not with the semiconductor portion 541a when viewed from the Z direction. In this configuration, the portion of the conductive layer 543 covering the upper and lower surfaces of the semiconductor portion 541a is adjacent to other memory layers ML5 in the Z direction, separated by an insulating layer 101.

[0225] Here, the conductive layer 543 functions as a sensing node SN. The sensing node SN is essentially in a floating state except during write operations. Therefore, if the voltage of the conductive layer 543 of a memory layer ML5 changes due to a write operation, the voltage of the conductive layer 543 at adjacent memory layers ML5 in the Z direction will also change. This could potentially lead to problems such as inability to properly perform read operations. This voltage variation of the sensing node SN can also occur in the semiconductor memory devices of the first to fourth embodiments.

[0226] Therefore, in the semiconductor memory device of the sixth embodiment, the configuration that functions as a sensing node SN is provided inside at least one of the "semiconductor layer that functions as a channel region of a readout transistor RTR" and the "gate electrode" to suppress the intrusion of the electric field to the sensing node SN, thereby suppressing the voltage fluctuation of the sensing node SN.

[0227] The following description refers to the semiconductor memory device according to the sixth embodiment. In the following description, the same component symbols are added for the same configuration as in the first to fifth embodiments, and their descriptions are omitted.

[0228] [Circuit Structure] Figure 132 is a schematic circuit diagram illustrating a portion of the configuration of a semiconductor memory device according to the sixth embodiment.

[0229] As shown in Figure 132, the semiconductor memory device of this embodiment includes a memory cell array MCA6. The memory cell array MCA6 includes a plurality of memory layers ML6, a plurality of write bit lines WBL connected to the plurality of memory layers ML6, a voltage supply line VDD supplying a power supply voltage Vdd, and a plurality of read bit lines RBL connected to the plurality of memory layers ML6.

[0230] The memory layer ML6 comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC6 connected to these write word lines WWL and read word lines RWL. Each memory cell MC6 comprises a write transistor WTr, a sense node SN, and a read transistor RTr6.

[0231] The readout transistor RTr6 is basically constructed in the same way as the readout transistor RTr5 described with reference to FIG104. However, instead of a floating gate, the readout transistor RTr6 has a back gate. The back gate of the readout transistor RTr6 is connected to the sensing node SN.

[0232] The write operation of the semiconductor memory device in the sixth embodiment can be performed in the same way as the write operation of the semiconductor memory device in the first embodiment.

[0233] The read operation of the semiconductor memory device in the sixth embodiment can be performed in the same way as the read operation of the semiconductor memory device in the third embodiment.

[0234] [structure] Figure 133 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the sixth embodiment. Figure 134 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration of the structure shown in Figure 133 cut along line A-A' and observed in the direction of the arrow.

[0235] The memory cell array MCA6 has a plurality of memory layers ML6 arranged side by side in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML6.

[0236] Furthermore, via wirings 102, 302, and 103 are provided at the memory cell array MCA6. The via wirings 102, 302, and 103 are arranged side by side in the X direction and extend through multiple memory layers ML6 in the Z direction.

[0237] The memory layer ML6 includes "wirings 110 and 120 arranged side-by-side in the X direction and extending in the Y direction", and "transistor structures 630 and 640 disposed between these wirings 110 and 120". Transistor structure 630 is disposed at a position corresponding to via wiring 102. Transistor structure 640 is disposed at a position corresponding to via wirings 302 and 103.

[0238] Transistor structure 630 is basically constructed the same as transistor structure 130. However, instead of insulating layer 132, transistor structure 630 has insulating portion 632 and insulating portion 532 disposed between semiconductor layer 131 and conductive layer 133. Insulating portion 632, for example, together with insulating portion 532, functions as a gate insulating film for writing transistor WTr (FIG. 132). Insulating portion 632, for example, includes silicon oxide (SiO2) or the like.

[0239] The transistor structure 640, for example, as shown in FIG134, includes a conductive layer 641 extending in the X direction, an insulating portion 642 disposed on the top, bottom, two sides in the Y direction, and one side (wiring 120 side) of the conductive layer 641, a semiconductor layer 643 disposed on the top, bottom, two sides in the Y direction, and one side (wiring 120 side) of the insulating portion 642 and connected to the outer peripheral surface of the via wirings 302 and 103, an insulating portion 544 disposed on the top, bottom, two sides in the Y direction, and one side (wiring 120 side) of the semiconductor layer 643, and a conductive layer 545 disposed on the top, bottom, two sides in the Y direction, and one side (wiring 120 side) of the insulating portion 544.

[0240] In the XY cross-section illustrated in Figure 133, one side of the conductive layer 641 in the X direction (the side of wiring 110) can also be formed along one side of the semiconductor layer 131 in the X direction (the side of wiring 120). Furthermore, the other side of the conductive layer 641, insulating portion 642, semiconductor layer 643, insulating portion 544, and conductive layer 545 in the X direction (the side of wiring 120) can also be formed in a straight line along the side of wiring 120. Additionally, the two sides of the conductive layer 641, insulating portion 642, semiconductor layer 643, insulating portion 544, and conductive layer 545 in the Y direction can also be formed in a straight line along the side of insulating layer 105.

[0241] The conductive layer 641, for example, functions as the back gate of the readout transistor RTr6 (FIG. 132) and the sensing node SN (FIG. 132). The conductive layer 641, for example, comprises a conductive oxide such as indium tin oxide (ITO). The conductive layer 641 is connected to one side of the semiconductor layer 131 in the X direction (the side of wiring 120). The conductive layer 641 includes a conductive portion 641a surrounding the outer peripheral surface of the via wiring 302 and a conductive portion 641b surrounding the outer peripheral surface of the via wiring 103. In the example of FIG. 134, the length of the conductive portion 641a in the Z direction is greater than the length of the conductive portion 641b in the Z direction.

[0242] The insulating portion 642, for example, functions as a gate insulating film between the back gate and the channel region of the readout transistor RTr6 (FIG. 132). The insulating portion 642, for example, contains silicon oxide (SiO2) or the like.

[0243] Semiconductor layer 643, for example, functions as a channel region for the readout transistor RTr6 (FIG. 132). Semiconductor layer 643 may be, for example, a semiconductor containing at least one of gallium (Ga) and aluminum (Al), and indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. Semiconductor layer 643 is separated from the conductive layer 641 by insulating portion 642 and faces the top, bottom, both sides in the Y direction, and one side in the X direction (the side of wiring 120).

[0244] Semiconductor layer 643 includes a semiconductor portion 643a connected to the outer peripheral surface of via wiring 302, and a semiconductor portion 643b connected to the outer peripheral surface of via wiring 103. Semiconductor portion 643a is positioned where it overlaps with conductive portion 641a when viewed from the Z direction. A plurality of semiconductor portions 643a arranged side-by-side in the Z direction are connected in common to via wiring 302 extending in the Z direction. Semiconductor portion 643b is positioned where it overlaps with conductive portion 641b when viewed from the Z direction. A plurality of semiconductor portions 643b arranged side-by-side in the Z direction are connected in common to via wiring 103 extending in the Z direction.

[0245] In addition, in this embodiment, the conductive layer 545 is disposed at a position that overlaps with the conductive portion 641b and the semiconductor portion 643b when viewed from the Z direction, but does not overlap with the conductive portion 641a and the semiconductor portion 643a.

[0246] [Manufacturing Method] Figures 135-152 are schematic cross-sectional views used to illustrate the manufacturing method of the semiconductor memory device according to the sixth embodiment. Figures 135, 137, 139, 141, 143, 145, 147, 149, and 151 show cross-sections corresponding to Figure 133. Figures 136, 138, 140, 142, 144, 146, 148, 150, and 152 show cross-sections corresponding to Figure 134.

[0247] In this manufacturing method, for example, the process described with reference to FIG121 and FIG122 is carried out up to the manufacturing process of the semiconductor memory device in the fifth embodiment.

[0248] Next, as shown in Figures 135 and 136, a semiconductor layer 643A and a sacrificial layer 540B are formed inside the openings 540A, 302A, and 103A. This process is performed, for example, by ALD, CVD, or the like.

[0249] Next, as shown in Figures 137 and 138, the semiconductor layer 643A is cut in the Z direction. In this process, for example, the portion of the sacrificial layer 540B located at the inner peripheral surfaces of openings 302A and 103A is removed. Next, the portion of the semiconductor layer 643A located at the inner peripheral surfaces of openings 302A and 103A is removed. This process is performed, for example, by wet etching.

[0250] Next, as shown in Figures 139 and 140, sacrificial layers 302B and 103C are formed inside the openings 302A and 103A. This process is performed, for example, by CVD. Furthermore, although not shown in the figures, after this process, the upper parts of the openings 302A and 103A are sealed with an insulating layer or the like.

[0251] Next, for example as shown in Figures 141 and 142, the sacrificial layer 540B is removed through opening 102A. This process is performed, for example, by wet etching.

[0252] Next, as shown in Figures 143 and 144, a semiconductor layer 643 is formed. In this process, for example, a portion of the side of the semiconductor layer 643A covering the sacrificial layer 540B in the X direction (the side of opening 110A) is removed. This process is performed, for example, by wet etching.

[0253] Next, as shown in Figures 145 and 146, the sacrificial layer 540B is removed. This process is performed, for example, by wet etching.

[0254] Next, as shown in Figures 147 and 148, insulating portions 642 and 632 and a conductive layer 641A are formed inside the openings 540A and 102A. This process is performed, for example, by means of an ALD or the like.

[0255] Next, as shown in Figures 149 and 150, a conductive layer 641 is formed. In this process, for example, the portion of the conductive layer 641A covering the inner peripheral surface of the opening 102A and the portion disposed at the position corresponding to the semiconductor layer 131 are removed through the opening 102A, thereby dividing the conductive layer 641A in the Z direction. This process is performed, for example, by wet etching.

[0256] Next, as shown in Figures 151 and 152, a semiconductor layer 131 is formed inside the openings 540A and 102A. This process is performed, for example, by CVD.

[0257] Furthermore, the sacrificial layers 302B and 103C are removed by wet etching and other methods, and through-hole wiring 102, 302, and 103 are formed inside the openings 102A, 302A, and 103A by ALD and CVD methods.

[0258] Then, for example, the sacrificial layers 110C and 120C are removed. Also, as shown in Figures 133 and 134, wiring 110 and 120 are formed inside the openings 110B and 120B. This process is performed, for example, by CVD.

[0259] [Variation Example] In the examples of Figures 133 and 134, the semiconductor layer 131 is directly connected to the conductive layer 641. However, the semiconductor memory device of the sixth embodiment may also include, for example, a plurality of conductive members 150 and insulating members 104 as described with reference to Figures 2-4. Furthermore, the plurality of semiconductor layers 131 arranged side by side in the Z direction may also be connected to the conductive layer 641 via conductive members 150.

[0260] [Seventh Implementation Form] Next, the semiconductor memory device of the seventh embodiment will be described. In the following description, for configurations that are the same as those of the first to sixth embodiments, the same component symbols will be added and their descriptions will be omitted.

[0261] [Circuit Structure] Figure 153 is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor memory device in the seventh embodiment.

[0262] As shown in Figure 153, the semiconductor memory device of this embodiment includes a memory cell array MCA7. The memory cell array MCA7 includes a plurality of memory layers ML7, a plurality of write bit lines WBL connected to the plurality of memory layers ML7, a plurality of voltage supply lines GND connected to the plurality of memory layers ML7, and a plurality of read bit lines RBL connected to the plurality of memory layers ML7. The voltage supply line GND supplies a ground voltage Vss.

[0263] The memory layer ML7 comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC7 connected to these write word lines WWL and read word lines RWL. Each memory cell MC7 comprises a write transistor WTr, a sense node SN, a capacitor CP, and a read transistor RTr.

[0264] One electrode of capacitor CP is connected to the sensing node SN. The other electrode of capacitor CP is connected to the voltage supply line GND.

[0265] [structure] Figure 154 is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the seventh embodiment. Figure 155 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, and shows the configuration of the structure shown in Figure 154 cut along line A-A' and observed in the direction of the arrow.

[0266] The memory cell array MCA7 has a plurality of memory layers ML7 arranged side by side in the Z direction. Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML7.

[0267] Furthermore, via wirings 102, 704, and 103 are provided at the memory cell array MCA7. Via wiring 704 functions as the voltage supply line GND.

[0268] The through-hole wiring 704, as shown in Figure 155, has, for example, a slightly cylindrical shape extending in the Z direction. The through-hole wiring 704 may, for example, include a barrier conductive film such as titanium nitride (TiN) and a conductive component such as tungsten (W).

[0269] The memory layer ML7 includes "wiring 110 and 120 arranged side-by-side in the X direction and extending in the Y direction", "transistor structures 130 and 140 disposed between these wirings 110 and 120", and "capacitor structure 750 disposed between these transistor structures 130 and 140". Transistor structures 130 and 140 are respectively disposed at positions corresponding to via wirings 102 and 103. Capacitor structure 750 is disposed at a position corresponding to via wiring 704. In the illustrated example, transistor structures 130 and 140 and capacitor structure 750 are arranged side-by-side in the X direction.

[0270] The capacitor structure 750, for example as shown in FIG154, includes a conductive portion 751 that is connected to the outer peripheral surface of the through-hole wiring 704 and extends in the X direction, an insulating layer 752 disposed on the top, bottom, two sides in the Y direction and two sides in the X direction of the conductive portion 751, and a conductive layer 753 disposed on the top, bottom, two sides in the Y direction and two sides in the X direction of the insulating layer 752.

[0271] In the XY cross-section as illustrated in Figure 154, the side surface of one side (wiring 110 side) of the conductive portion 751, insulating layer 752, and conductive layer 753 in the X direction can also be formed along a circle centered on the center position of the through-hole wiring 102. Furthermore, the side surface of the other side (wiring 120 side) of the conductive portion 751, insulating layer 752, and conductive layer 753 in the X direction can also be formed along a circle centered on the center position of the through-hole wiring 103. Additionally, the two side surfaces of the conductive portion 751, insulating layer 752, and conductive layer 753 in the Y direction can also be formed in a straight line along the side surface of the insulating layer 105.

[0272] The conductive portion 751, for example, functions as one electrode of a capacitor CP (FIG. 153). The conductive portion 751 may include, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive component such as tungsten (W), or may only include titanium nitride (TiN), or may include other materials. A plurality of conductive portions 751 arranged side-by-side in the Z direction are connected in common with a through-hole wiring 704 extending in the Z direction. The conductive portions 751 are continuous with the through-hole wiring 704 and are directly connected to each other. The plurality of conductive portions 751 and the through-hole wiring 704 are each part of a single conductive component.

[0273] Insulating layer 752, for example, functions as an insulating film between the electrodes of capacitor CP (Fig. 153). Insulating layer 752 may also be, for example, zirconium dioxide (ZrO₂), aluminum oxide (Al₂O₃), or other insulating metal oxides. Furthermore, insulating layer 132 may also be, for example, a laminate of multiple insulating metal oxides (e.g., a laminate of zirconium dioxide and aluminum oxide).

[0274] The conductive layer 753, for example, functions as the other electrode of the capacitor CP (FIG. 153). The conductive layer 753 may also contain conductive oxides such as indium tin oxide (ITO). The conductive layer 753 is separated from the insulating layer 752 and faces the top, bottom, two sides in the Y direction, and two sides in the X direction of the conductive portion 751.

[0275] [Variation Example] In the seventh embodiment, the example described is "a capacitor CP connected to the sensing node SN in a circuit configuration as described with reference to FIG1". However, for example, a capacitor CP can also be connected to the sensing node SN in a circuit configuration as described with reference to FIG88, FIG104 or FIG132.

[0276] For example, in a configuration as described with reference to Figures 89 and 90, a plurality of conductive members 150 and insulating members 104 can be provided in place of a plurality of capacitor structures 750 and through-hole wiring 704. Also, for example, in a configuration as described with reference to Figures 91 and 92, a plurality of capacitor structures 750 and through-hole wiring 704 can be provided between the semiconductor layer 131 and the conductive layer 243. Similarly, in a configuration as described with reference to Figures 105 and 106, a plurality of capacitor structures 750 and through-hole wiring 704 can be provided between the semiconductor layer 131 and the conductive layer 543. Similarly, in a configuration as described with reference to Figures 133 and 134, a plurality of capacitor structures 750 and through-hole wiring 704 can be provided between the semiconductor layer 131 and the conductive layer 641.

[0277] [Other Implementation Forms] The above description pertains to the semiconductor memory devices of embodiments 1 through 7. However, these semiconductor memory devices are merely illustrative examples and may be adjusted appropriately for specific configurations.

[0278] For example, the semiconductor memory devices of embodiments 3 to 6 can also replace the voltage supply line VDD and have a voltage supply line GND.

[0279] Furthermore, in the semiconductor memory devices of embodiments 1 to 7, the components (e.g., transistor structures 130, 140, etc.) of the memory cells MC, MC3, MC5, MC6, and MC7 (hereinafter referred to as "memory cells MC, etc.") are arranged side-by-side in the X direction, and the wirings 110, 120, etc. extend in the Y direction. However, for example, the components of the memory cells MC, etc., may also be arranged side-by-side in the direction in which the wirings 110, 120, etc. extend, for example, in the Y direction. Furthermore, the components of the memory cells MC, etc., may also be arranged side-by-side covering two rows in the X direction or the Y direction, or may be configured in other ways.

[0280] Furthermore, the manufacturing methods of the semiconductor memory devices in embodiments 1 to 7 can also be appropriately adjusted. For example, the order of any two of the above-mentioned processes can be interchanged, or any two of the above-mentioned processes can be performed simultaneously.

[0281] [other] Although several embodiments of the present invention have been described, these embodiments are merely illustrative examples and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or their variations are also included in the scope or spirit of the invention, and are also included within the scope of the invention described in the patent application and its equivalents.

[0282] Sub: Semiconductor substrate ML: Memory Layer WBL: Write Bit Line WWL: Write character line WTr: Write transistor RBL: Readout bitline RWL: Read out character lines RTr: Write transistor SN: Sensing Node 101: Insulation layer 102, 103: Through-hole wiring 104: Insulating components 110, 120: Wiring 130, 140: Transistor Structure 131, 141: Semiconductor layer 132, 142: Insulation layer 133, 143: Conductive layer 150: Conductive component

Claims

1. A semiconductor memory device comprising: a substrate; and a plurality of first wirings arranged side-by-side in a first direction intersecting the surface of the substrate and extending toward a second direction intersecting the first direction; and a plurality of second wirings arranged side-by-side in the first direction and extending toward the second direction, and arranged side-by-side with the plurality of first wirings in a third direction intersecting the first and second directions; and a first via wiring and a second via wiring disposed between the plurality of first wirings and the plurality of second wirings and extending toward the first direction; and a plurality of first semiconductor layers arranged side-by-side in the first direction. The first semiconductor layer is arranged in a row and electrically connected to the first via wiring; and a plurality of second semiconductor layers are arranged side by side in the first direction and electrically connected to the second via wiring, and are respectively electrically connected to the plurality of second wiring; and a plurality of first gate electrodes are arranged side by side in the first direction and electrically connected to the plurality of first wiring, and are opposite to the plurality of first semiconductor layers; and a plurality of second gate electrodes are arranged side by side in the first direction and electrically connected to the plurality of first semiconductor layers, and are opposite to the plurality of second semiconductor layers.

2. The semiconductor memory device as described in claim 1, wherein, The aforementioned plurality of first semiconductor layers surround the outer peripheral surface of the aforementioned first via wiring, and the aforementioned plurality of second semiconductor layers surround the outer peripheral surface of the aforementioned second via wiring.

3. The semiconductor memory device as described in claim 1, wherein, The aforementioned plurality of first gate electrodes are opposite to one side and the other side of the aforementioned plurality of first semiconductor layers in the first direction. The aforementioned plurality of second gate electrodes are opposite to one side and the other side of the aforementioned plurality of second semiconductor layers in the first direction.

4. The semiconductor memory device as described in claim 1, wherein, The aforementioned first wiring is positioned at a location that does not overlap with the aforementioned first gate electrode when viewed from the aforementioned first direction, and the aforementioned second wiring is positioned at a location that does not overlap with the aforementioned second gate electrode when viewed from the aforementioned first direction.

5. The semiconductor memory device as described in claim 1, wherein, The system comprises: a plurality of conductive members arranged side by side in the aforementioned first direction; and a plurality of second gate electrodes electrically connected to the plurality of first semiconductor layers via the aforementioned plurality of conductive members.

6. The semiconductor memory device as described in claim 1, wherein, The aforementioned complex second gate electrode is directly connected to the aforementioned complex first semiconductor layer.

7. The semiconductor memory device as described in claim 1, wherein, The system comprises: a voltage supply line disposed between the aforementioned plurality of first wirings and the aforementioned plurality of second wirings, and extending toward the aforementioned first direction; and a plurality of first electrodes arranged side by side in the aforementioned first direction, surrounding the outer peripheral surface of the aforementioned voltage supply line, and electrically connected to the aforementioned voltage supply line; and a plurality of second electrodes arranged side by side in the aforementioned first direction, and electrically connected to the aforementioned plurality of first semiconductor layers and the aforementioned plurality of second gate electrodes, respectively, and facing the aforementioned plurality of first electrodes, wherein the aforementioned plurality of second electrodes face one side and the other side of the aforementioned plurality of first electrodes in the aforementioned first direction.

8. A semiconductor memory device comprising: a substrate; and a plurality of first wirings arranged side-by-side in a first direction intersecting the surface of the substrate and extending toward a second direction intersecting the first direction; and a plurality of second wirings arranged side-by-side in the first direction and extending toward the second direction, and arranged side-by-side with the plurality of first wirings in a third direction intersecting the first and second directions; and a first via wiring, a second via wiring, and a third via wiring disposed between the plurality of first wirings and the plurality of second wirings and extending toward the first direction; and a plurality of first semiconductor portions arranged side-by-side in the first direction and electrically connected to the first via wirings; and a plurality of second semiconductor portions arranged side-by-side in the first direction and electrically connected to the first via wirings. The second via wiring is electrically connected; and a plurality of third semiconductor portions are arranged side by side in the first direction and electrically connected to the third via wiring, and are respectively electrically connected to the plurality of second semiconductor portions; and a plurality of first gate electrodes are arranged side by side in the first direction and electrically connected to the plurality of first wiring, and face the plurality of first semiconductor portions; and a plurality of second gate electrodes are arranged side by side in the first direction and electrically connected to the plurality of second wiring, and face the plurality of second semiconductor portions; and a plurality of third gate electrodes are arranged side by side in the first direction and electrically connected to the plurality of first semiconductor portions, and face the plurality of third semiconductor portions.

9. The semiconductor memory device as described in claim 8, wherein, The aforementioned plurality of first semiconductor portions surround the outer peripheral surface of the aforementioned first through-hole wiring; the aforementioned plurality of second semiconductor portions surround the outer peripheral surface of the aforementioned second through-hole wiring; and the aforementioned plurality of third semiconductor portions surround the outer peripheral surface of the aforementioned third through-hole wiring.

10. The semiconductor memory device as described in claim 8, wherein, The aforementioned plurality of first gate electrodes face one side and the other side of the aforementioned plurality of first semiconductor portions in the first direction. The aforementioned plurality of second gate electrodes face one side and the other side of the aforementioned plurality of second semiconductor portions in the first direction. The aforementioned plurality of third gate electrodes face one side and the other side of the aforementioned plurality of third semiconductor portions in the first direction.

11. The semiconductor memory device as described in claim 8, wherein, The aforementioned first wiring is positioned at a location that does not overlap with the aforementioned first gate electrode when viewed from the aforementioned first direction, and the aforementioned second wiring is positioned at a location that does not overlap with the aforementioned second gate electrode when viewed from the aforementioned first direction.

12. The semiconductor memory device as described in claim 8, wherein, The system comprises: a plurality of first conductive members arranged side by side in the aforementioned first direction; and a plurality of third gate electrodes electrically connected to the plurality of first semiconductor portions via the aforementioned plurality of first conductive members.

13. The semiconductor memory device as described in claim 8, wherein, The aforementioned third gate electrode is directly connected to the aforementioned first semiconductor unit.

14. The semiconductor memory device as described in claim 8, wherein, The system comprises: a plurality of second conductive members arranged side by side in the aforementioned first direction; and a plurality of third semiconductor portions electrically connected to the plurality of second semiconductor portions via the aforementioned plurality of second conductive members.

15. The semiconductor memory device as described in claim 8, wherein, The aforementioned third semiconductor section is continuous with the aforementioned second semiconductor section.

16. The semiconductor memory device as described in claim 8, wherein, The aforementioned plurality of second gate electrodes are disposed at a position that overlaps with the aforementioned plurality of second semiconductor portions but does not overlap with the aforementioned plurality of third semiconductor portions when viewed from the aforementioned first direction. The aforementioned plurality of third gate electrodes are disposed at a position that overlaps with the aforementioned plurality of third semiconductor portions but does not overlap with the aforementioned plurality of second semiconductor portions when viewed from the aforementioned first direction.

17. The semiconductor memory device as described in claim 8, wherein, The aforementioned plurality of second gate electrodes are disposed at a position that overlaps with the aforementioned second semiconductor portion when viewed from the aforementioned first direction. The aforementioned plurality of third gate electrodes are disposed at a position that overlaps with both the aforementioned second semiconductor portion and the aforementioned third semiconductor portion when viewed from the aforementioned first direction.

18. The semiconductor memory device as described in claim 17, wherein, The aforementioned plurality of third gate electrodes are opposite to one side and the other side of the aforementioned plurality of second semiconductor portions and the aforementioned plurality of third semiconductor portions in the first direction.

19. The semiconductor memory device as described in claim 17, wherein, The aforementioned plurality of second semiconductor portions and the aforementioned plurality of third semiconductor portions are respectively facing one side and the other side of the aforementioned plurality of third gate electrodes in the first direction.

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