Method of fabricating semiconductor devices with isolated superlattice structures

Abstract

A method for manufacturing a semiconductor device may include implanting non-semiconductor atoms into a local region of a semiconductor layer and forming a superlattice over the local region of the semiconductor layer. The superlattice may include a plurality of stacked layers, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor atom monolayer confined within a lattice of an adjacent substrate semiconductor portion. The method may also include performing a heat treatment to cause the non-semiconductor atoms of the superlattice to be displaced, and to cause non-semiconductor atoms from the local region to migrate into the superlattice and replace at least a portion of the displaced non-semiconductor atoms.

Description

Method for manufacturing a semiconductor device having an isolated superlattice structure The present disclosure relates generally to semiconductor devices, and more particularly to methods for fabricating semiconductor devices using enhanced semiconductor materials. Many structures and techniques have been proposed to improve semiconductor device performance by, for example, enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon, which also include impurity-free zones that would otherwise degrade performance. The biaxial strain created by these strained material layers in the upper silicon layer alters carrier mobility, thereby enabling the fabrication of higher-speed and / or lower-power devices. U.S. Patent Application Publication No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on similar strained silicon technology. U.S. Patent No. 6,472,685 B2 issued to Takagi discloses a semiconductor device comprising a silicon and carbon layer sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. This allows electrons with a smaller effective mass, induced by an electric field applied to the gate, to be confined within the second silicon layer, resulting in an N-type channel MOSFET having higher mobility. U.S. Patent No. 4,937,204 issued to Ishibashi et al. discloses a superlattice comprising a plurality of layers, each comprising fewer than eight monolayers and containing fractional or binary semiconductor layers or a binary compound semiconductor layer, grown alternately by epitaxial growth, wherein the main current flow direction is perpendicular to the layers of the superlattice. U.S. Patent No. 5,357,119 issued to Wang et al. discloses a silicon-germanium short-period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on similar principles, U.S. Patent No. 5,683,934 issued to Candelaria discloses a MOSFET with improved mobility, which includes a channel layer comprising an alloy of silicon and a second material, the second material being present in the silicon lattice at a percentage that places the channel layer under tensile stress. U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions sandwiched by an epitaxially grown semiconductor layer. Each barrier region is composed of alternating SiO2 / Si monolayers with a thickness ranging from two to six. A much thicker silicon segment is sandwiched between the barrier regions. In an article titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in Applied Physics and Materials Science & Processing, pp. 391–402, Tsu describes a semiconductor-atomic superlattice (SAS) of silicon and oxygen. This silicon / oxygen superlattice structure is described as useful for silicon quantum doping and light-emitting devices. Specifically, the article describes how to fabricate and test a green electroluminescence diode structure. The current flow in the diode structure is perpendicular to the SAS layer. The SAS described in the article can include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. Silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One SAS structure contained a 1.1 nm thick silicon portion, equivalent to about eight atomic layers of silicon, while the other structure had a silicon portion twice as thick. Luo et al. further discussed Tsu's light-emitting SAS structure in an article titled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002). U.S. Patent No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen that can reduce the vertical current flowing through the lattice by more than four orders of magnitude. The insulating / barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer. Published UK patent application No. 2,347,520 by Mears et al. discloses that aperiodic photonic band-gap (APBG) structures can be used in electronic bandgap engineering. Specifically, the application discloses that material parameters, such as the position of the band minimum and effective mass, can be tuned to produce new aperiodic materials with desired band structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric permittivity or magnetic permeability, are also potentially engineered into the material. Additionally, U.S. Patent No. 6,376,337 issued to Wang et al. discloses a method for forming an insulating or barrier layer for a semiconductor device. The method comprises depositing a layer of silicon and at least one other element on a silicon substrate, such that the deposited layer is substantially defect-free, thereby enabling the deposition of substantially defect-free epitaxial silicon on the deposited layer. Alternatively, a single layer of one or more elements, preferably including oxygen, is absorbed on the silicon substrate. Multiple insulating layers are sandwiched between the epitaxial silicon to form a barrier composite. Although the above methods exist, it is desirable to further enhance the use of advanced semiconductor materials and processing technologies in order to achieve improved performance of semiconductor devices. A method for fabricating a semiconductor device may include implanting non-semiconductor atoms into a localized region of a semiconductor layer and forming a superlattice over the localized region of the semiconductor layer. The superlattice may include a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor atomic monolayer confined within a lattice of an adjacent base semiconductor portion. The method may also include performing a heat treatment to displace the non-semiconductor atoms of the superlattice and to cause the non-semiconductor atoms of the localized region to migrate into the superlattice and replace at least a portion of the displaced non-semiconductor atoms. In one exemplary embodiment, forming the superlattice may include forming the superlattice so that it extends laterally above the local region and outward from the local region. In addition, the method may also include amorphizing the portion of the superlattice that extends laterally beyond the local region before performing the heat treatment. For example, the amorphizing may include implanting at least one of silicon, argon, neon, xenon, carbon, fluorine, and germanium. More specifically, the implantation may include implanting at a range of, for example, 5x10 14 -1x10 16 / cm 2 According to another exemplary embodiment, forming the superlattice may include selectively forming the superlattice over the local region. In an exemplary embodiment, the method may further include forming a first element overlying the superlattice and a second element overlying an adjacent portion of the semiconductor layer after performing the thermal treatment. For example, the base semiconductor monolayers may include silicon, and the non-semiconductor atoms may include oxygen atoms. Example embodiments are described in detail with reference to the accompanying drawings, which illustrate exemplary embodiments. However, the embodiments may be implemented in many different forms and should not be construed as limited to the specific examples provided herein. Rather, these examples are provided solely to provide a more complete and comprehensive overview of the present invention. Throughout this specification and the drawings, like reference numerals refer to like elements, and a prime symbol (') is used to denote similar elements in different embodiments. Generally speaking, the present disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide improved performance. In the present disclosure, the enhanced semiconductor superlattice may also be referred to as an MST layer or "MST technology." Specifically, MST technology involves advanced semiconductor materials, such as superlattices 25, which are described further below. In prior literature, applicants have theorized that the superlattice structures described herein can reduce the effective mass of charge carriers, thereby increasing charge carrier mobility. For example, see U.S. Patent No. 6,897,472, the entire contents of which are incorporated herein by reference. Further developments by the applicant have shown that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials, for example in the case of silicon and insulators such as SiO 2 or HfO 2) The interface between the two layers. The applicant theorizes (but the applicant does not wish to be bound by this theory) that this may occur due to various mechanisms. One mechanism is to reduce the concentration of charged impurities near the interface, reduce the diffusion of these impurities and / or capture impurities so that they cannot reach the interface. Charged impurities will cause Coulomb scattering, thereby reducing mobility. Another mechanism is to improve the interface quality. For example, oxygen released from the MST film can be transferred to the Si-SiO 2 The interface provides oxygen, thereby reducing the sub-stoichiometric SiO xAlternatively, the capture of interstitials by the MST layer can reduce the Si-SiO 2. The interstitial silicon concentration near the interface reduces the formation of substoichiometric SiO x It is known that in Si-SiO 2 Substoichiometric SiO at the interface x Relative to stoichiometric SiO 2 exhibits poor insulation properties. Reduce the substoichiometric SiO at the interface x The amount of scattering can more effectively confine free carriers (electrons or holes) in silicon, thereby increasing their mobility under the action of an electric field parallel to the interface. This is a standard practice in field-effect-transistor (FET) structures. Scattering due to the direct influence of the interface is called "surface-roughness scattering", which can be advantageously reduced by the adjacent MST layer after tempering or during thermal oxidation. In addition to having better mobility characteristics, these MST structures can be formed or used in a manner that allows them to provide piezoelectric, pyroelectric and / or ferroelectric properties that are beneficial for various device types, as will be discussed further below. 1 and 2 , the material or structure is in the form of a superlattice 25, whose structure is controlled at the atomic or molecular level and can be formed using conventional techniques of atomic or molecular layer deposition. Superlattice 25 comprises a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of FIG1 . As shown, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked base semiconductor layers 46 (which define respective base semiconductor portions 46a-46n) and a non-semiconductor layer 50 thereon. For clarity of presentation, the non-semiconductor layer 50 is represented by dots in FIG. As shown, the non-semiconductor monolayer 50 comprises a non-semiconductor monolayer that is confined within a crystal lattice of adjacent base semiconductor portions. The term "confined within a crystal lattice of adjacent base semiconductor portions" refers to the fact that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bonded together through the non-semiconductor monolayer 50 between the opposing base semiconductor portions, as shown in FIG2 . Generally, this configuration is achieved by controlling the amount of non-semiconductor material deposited onto the semiconductor portions 46a-46n using atomic layer deposition techniques so that the available semiconductor bonding sites are not completely occupied (i.e., not completely or less than 100% covered) by bonds to non-semiconductor atoms, as discussed further below. Therefore, as more semiconductor material monolayers 46 are deposited onto or above a non-semiconductor monolayer 50, the newly deposited semiconductor atoms can fill in the remaining unoccupied semiconductor atomic bonding sites beneath the non-semiconductor monolayer. In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it refers to a monolayer made of a material that would be a non-semiconductor or semiconductor if formed into a bulk form. That is, the properties exhibited by a single monolayer of a material (e.g., silicon) do not necessarily correspond to the properties exhibited when formed into a bulk form or a relatively thick layer, as will be understood by those skilled in the art. The applicant theorizes (though the applicant does not wish to be bound by this theory) that the non-semiconductor monolayer 50 and the adjacent base semiconductor portions 46a-46n impart to the superlattice 25 a lower effective mass for suitable charge carrier conductivity than would otherwise be possible in a direction parallel to the layers. Alternatively, this parallel direction is perpendicular to the stacking direction. The non-semiconductor monolayer 50 also imparts a conventional band structure to the superlattice 25 while advantageously acting as an insulator between layers or regions perpendicularly above and below the superlattice. Furthermore, the superlattice structure can also advantageously serve as a barrier to dopant and / or material diffusion between multiple layers vertically above and below the superlattice 25. Therefore, these properties can advantageously allow the superlattice 25 to provide an interface for the high-K dielectric, which not only reduces the diffusion of high-K materials into the channel region, but also advantageously reduces unwanted scattering effects and improves device mobility, as will be understood by those skilled in the art to which the present invention relates. The present invention also proposes that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility due to their lower effective mass for conductivity. In certain embodiments, due to the band engineering achieved by these embodiments, superlattice 25 can further have a substantially direct band gap, which is particularly advantageous for applications such as optoelectronic devices. As shown, the superlattice 25 may also include a cap layer 52 above an upper layer group 45n. The cap layer 52 may include a plurality of base semiconductor monolayers 46. The cap layer 52 may include between 2 and 100 monolayers of the base semiconductor, preferably between 10 and 50 monolayers. Each base semiconductor portion 46a-46n may include a base semiconductor selected from the group consisting of a Group IV semiconductor, a Group III-V semiconductor, and a Group II-VI semiconductor. Of course, Group IV semiconductors also include Group IV-IV semiconductors, as will be understood by those skilled in the art. More specifically, the base semiconductor may include, for example, at least one of silicon and germanium. Each non-semiconductor single layer 50 may comprise a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor also preferably remains thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art. More specifically, the base semiconductor may comprise, for example, at least one of silicon and germanium. It should be noted that the term "monolayer" herein refers to a single atomic layer, as well as a single molecular layer. It should also be noted that the non-semiconductor monolayer 50 provided by a single monolayer also includes a monolayer in which all possible positions in the layer are not completely occupied (i.e., not completely or less than 100% coverage). For example, referring to the atomic diagram in FIG2 , a 4 / 1 repeating structure is shown with silicon as the base semiconductor material and oxygen as the band-modifying material. Only half of the possible oxygen atom positions are occupied. In other embodiments and / or when using different materials, a one-half occupancy situation is not necessarily true, as will be understood by those skilled in the art to which the present invention relates. In fact, those skilled in the art of atomic deposition will understand that, even in this schematic diagram, individual oxygen atoms in a given monolayer are not arranged precisely along a flat plane. For example, a preferred occupancy range is one-eighth to one-half of the possible oxygen positions being filled, but other occupancy ranges may be used in certain embodiments. Because silicon and oxygen are currently widely used in general semiconductor manufacturing processes, manufacturers will be able to immediately utilize the materials described in this specification. Atomic deposition or monolayer deposition is also a widely used technique. Therefore, semiconductor devices incorporating the superlattice 25 of the embodiments described herein can be readily adopted and implemented, as will be readily understood by those skilled in the art. Referring now to FIG. 3 , another embodiment of a superlattice 25′ according to the present invention having different characteristics is described. In this embodiment, the repeating pattern is 3 / 1 / 5 / 1. More specifically, the bottommost base semiconductor portion 46a′ has three monolayers, and the second bottom base semiconductor portion 46b′ has five monolayers. This pattern repeats throughout the superlattice 25′. Each non-semiconductor monolayer 50′ may comprise a single monolayer. For this superlattice 25′ comprising silicon / oxygen, the charge carrier mobility enhancement is independent of the orientation of the planes of the layers. Other elements not mentioned in FIG. 3 are similar to those discussed above with reference to FIG. 1 and will not be discussed again. In some device embodiments, each base semiconductor portion of the superlattice may be the same number of monolayers thick. In other embodiments, at least some base semiconductor portions of the superlattice may be different numbers of monolayers thick. In yet another embodiment, each base semiconductor portion of the superlattice may be different numbers of monolayers thick. Referring to Figures 4 to 6, a method for selectively fabricating the aforementioned laterally separated MST films, and related components, will now be described. As background information, as further discussed in U.S. Patent No. 10,109,479 (also from the applicant of this application, the entire contents of which are hereby incorporated into this specification), the relatively high temperature treatment (annealing) step performed after the formation of the MST film can, in some cases, cause non-semiconductor atoms (e.g., oxygen) to dissociate from the non-semiconductor monolayer and migrate away from the superlattice. If this occurs in sufficient quantities, there will no longer be a superlattice, and only bulk semiconductor material will be present. The method of the present invention advantageously improves the thermal stability of the MST film in this regard by introducing additional oxygen and / or nitrogen sources to compensate for the non-semiconductor (e.g., oxygen) lost during the heat treatment. In the illustrated method, non-semiconductor atoms 101 (e.g., oxygen, or other atoms listed above) are implanted into an implant region 102 ( FIG. 4 ) in a semiconductor (e.g., silicon) layer. In some embodiments, these non-semiconductor atoms (e.g., oxygen) are the same atoms that will be used to subsequently form the MST superlattice 125 ( FIG. 5 ), since they will replace the same type of atoms that have left the superlattice. For example, the implant dose can be close to the dose used to subsequently form the MST layer 125, e.g., at 1×10 14 – 5x10 15 / cm 2 within the dosage range. In some embodiments, in addition to the non-semiconductor atoms 101, other atoms (e.g., nitrogen) may be implanted in the implant region 102 as needed. According to one example, nitrogen atoms may be included together with oxygen atoms. In some embodiments, although oxygen is a non-semiconductor used in the MST superlattice 125, nitrogen may be implanted without oxygen. The range of nitrogen implantation is similar to the oxygen dose range described above. For more information on combining nitrogen with MST-oxygen films, see U.S. Patent No. 2020 / 0135489, which has been assigned to the applicant of the present case and is incorporated herein in its entirety as a part of this specification. As described above, the MST film 125 (MST-O) using oxygen as the non-semiconductor material may lose oxygen during thermal processing. Oxygen atoms 101 introduced as an element into the implanted region 102 of the silicon layer 100 during processing diffuse and compensate for the oxygen flux leaving the MST layer 125. For example, nitrogen introduced by implantation can optionally be used to help stabilize the oxygen atoms within the MST film 125. This can offer several technical advantages. For example, MST stability across the wafer may be improved compared to a baseline MST deposition process. Furthermore, by adjusting the subsequent thermal treatment and patterned implantation of these elements, some devices or portions thereof may experience greater or lesser effects from MST doping profile control. Referring to FIG6 , the implanted oxygen atoms 101 replace some of the oxygen atoms within the MST film 125 during the high temperature heat treatment. In contrast, FIG7 illustrates what would happen to the MST film 125 if the implanted oxygen atoms 101 were not used to replace some of the displaced or “evaporated” oxygen atoms from the MST film. The SIMS cross-section 180 of FIG8 illustrates how, in one exemplary embodiment, the oxygen dose in the MST film 125 changes from 2.1×10 15 Basically doubled to 4.5x10 15 / cm 2 Furthermore, the SIMS cross section 190 of FIG. 9 shows that end of range (EOR) damage can accumulate oxygen, and the depth of the EOR can be advantageously adjusted to help minimize any negative impact on the semiconductor device, as will be understood by those skilled in the art. With additional reference to FIG. 10 , while the above-described method can be used to enhance the thermal stability of a blanket MST film covering an entire wafer or substrate, in other embodiments, by adjusting the subsequent thermal treatment and patterned implantation steps of these elements, the MST doping profile can be controlled to tailor specific devices or portions of devices, such that the MST film 225 remains at desired locations and not at other locations. In other words, MST doping profile control can be used to produce laterally separated MST films 225 from blanket film deposition on a semiconductor layer or substrate 200, thereby providing the MST film only at specific desired locations within a given semiconductor device (i.e., where the implanted regions 202 are located). This allows different metal oxide semiconductor field effect transistors (MOSFETs) 230 and 231 to be fabricated in semiconductor layers 200 with and without the MST film 225 (standard MOSFETs), respectively. Various examples of using this method to manufacture the MST MOS device 230 can be found in US Pat. No. 10,847,618 issued to Takeuchi et al., which is owned by the applicant of the present application and is incorporated herein in its entirety as a part of this specification. Please refer to the flowchart 240 of Figure 11, which illustrates an exemplary method for fabricating a laterally separated MST film from a blanket MST deposition using a "damage" and neutralization process. More specifically, starting from box 241, a non-semiconductor (e.g., oxygen and, optionally, nitrogen) is implanted into the localized region 102 of the semiconductor layer 100 (box 242), followed by the deposition of a blanket MST film 125 (box 243). Thereafter, at box 244, the MST film 125 is disordered or amorphized at the desired locations where no MST film is present in the final device, thereby reducing the stability to oxygen retention during the thermal treatment. For example, with a sufficient dose (e.g., 5x10 14 – 1x10 16 ) is implanted with one of silicon, argon, neon, xenon, carbon, fluorine, germanium, or a combination of these elements to amorphize the MST film 125 in areas where the MST film is not desired. In some embodiments, a relatively high dose of fluorine can be used to neutralize arsenic activation. Thereafter, a thermal treatment (e.g., rapid thermal annealing (RTA)) can be performed to displace non-semiconductor atoms 101 from the MST layer 125 while simultaneously causing implanted atoms from the implanted region 102 to migrate into the MST layer and replace the displaced atoms (block 245), as discussed further above. As shown, the method of FIG. 11 ends at block 246. More specifically, as described above, the MST superlattice is an ordered structure (e.g., a regular silicon monolayer). If the ordering is significantly disturbed, the thermal stability of the MST film 125 during subsequent thermal treatments may be significantly reduced. Because the implant can be patterned, the MST structure can be laterally modified so that the MST film 125 is effectively confined to certain elements or portions of elements, thereby achieving positional doping profile control, as described above. Please refer to flowchart 240' of Figure 12, which provides another exemplary method for manufacturing a laterally separated MST film. In the illustrated method, the implantation and heat treatment steps (boxes 242' and 245') are similar to those described above. However, this example does not use blanket deposition, but rather selectively grows a local MST film 125 above the corresponding implanted region 102 (box 247'). Although this avoids the need to amorphize a portion of the blanket deposition described above, it involves different photomask steps. Therefore, which method is more ideal will depend on factors such as the chamber and / or tool used, the type of device being manufactured, etc., which should be understood by those familiar with the technical field to which the present invention relates. The aforementioned methods can advantageously allow the application of MST technology to selected components without affecting standard components on the chip, as shown in FIG10 . This can advantageously help reduce IC redesign work and design kit redevelopment by simply adding MST component enhancements where specifically needed. In addition, the MST technology of the present invention can also be applied to desired portions of a component to provide additional flexibility in 2D doping distribution engineering, thereby enhancing component performance with relatively simple process integration (e.g., for high voltage components such as eDMOS or LDMOS). Furthermore, the above-described embodiments provide a relatively low-cost process for manufacturing ICs using enhanced MST technology in desired locations. Those skilled in the art will benefit from the disclosure of this specification and the accompanying drawings to devise various modifications and other embodiments. Therefore, it should be understood that the disclosure is not limited to the specific embodiments described in this specification, and that related modifications and embodiments also fall within the scope of the appended patent applications. 21, 21': Substrate 25, 25', 125: Superlattice / MST layer 45a-45n, 45a'-45n-1', 45n': Layer group 46, 46': Base semiconductor layer 46a-46n, 46a'-46n-1', 46n': Base semiconductor portion 50, 50': Band-modified layer / non-semiconductor layer 52, 52': Cap layer 100: Silicon layer / semiconductor layer 101: Non-semiconductor atoms / oxygen atoms 102, 202: Implanted region 200: Semiconductor layer / substrate 225: MST film 230: MST MOSFET 231: Standard MOSFET FIG1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an exemplary embodiment. FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1 . FIG3 is an enlarged schematic cross-sectional view of a superlattice according to another exemplary embodiment. 4-6 illustrate a series of schematic cross-sectional views of a method for fabricating a semiconductor device including a superlattice according to an exemplary embodiment. FIG. 7 is a schematic cross-sectional view illustrating what would happen to the superlattice shown in FIG. 5 if the method shown in FIG. 4 to 6 were not employed. 8 and 9 depict SIMS graphs of oxygen concentration versus depth for an exemplary embodiment of the method of FIGs. 4-6. FIG. 10 shows a schematic cross-sectional view of a semiconductor device fabricated using the method of FIG. 4 to 6 , including a MOSFET with and without a superlattice layer. FIG. 11 is a flow chart illustrating an exemplary method for manufacturing a semiconductor device using the method shown in FIG. 4 to FIG. 6 . FIG. 12 is a flow chart illustrating an alternative embodiment of the method shown in FIG. 11 . As shown in the picture.

Claims

1. A method for manufacturing a semiconductor device, comprising: Non-semiconductor atoms are implanted into a local region of a semiconductor layer; a superlattice is formed over the local region of the semiconductor layer, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor atom monolayer confined within a lattice of an adjacent substrate semiconductor portion; and a heat treatment is performed to cause the non-semiconductor atoms of the superlattice to be displaced, and to cause the non-semiconductor atoms of the local region to migrate into the superlattice and replace at least a portion of the displaced non-semiconductor atoms.

2. The method of claim 1, wherein forming the superlattice includes forming the superlattice such that it extends laterally over and outward from the local region.

3. The method of claim 2, which includes amorphizing the superlattice portion extending laterally beyond the local region prior to performing the heat treatment.

4. The method of claim 3, wherein the amorphization comprises implanting at least one of silicon, argon, neon, xenon, carbon, fluorine, and germanium.

5. The method of claim 3, wherein implantation includes implantation at a dose ranging from 5 x 10 14 to 1 x 10 16 / cm².

6. The method of claim 1, wherein forming the superlattice includes selectively forming the superlattice over the local region.

7. The method of claim 1, further comprising, after performing the heat treatment, forming a first element covering the superlattice and a second element covering an adjacent portion of the semiconductor layer.

8. The method of claim 1, wherein the substrate semiconductor monolayer comprises silicon.

9. The method of claim 1, wherein the non-semiconductor atoms include oxygen atoms.

10. A method for manufacturing a semiconductor device, comprising: Non-semiconductor atoms are implanted into a local region of a semiconductor layer; a superlattice is formed over the local region of the semiconductor layer, the superlattice comprising a plurality of stacked layer groups extending laterally outward from the local region, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor atom monolayer confined within a lattice of an adjacent substrate semiconductor portion; a heat treatment is performed to cause the non-semiconductor atoms of the superlattice to be displaced, and to cause the non-semiconductor atoms of the local region to migrate into the superlattice and replace at least a portion of the displaced non-semiconductor atoms; and after the heat treatment, a first element is formed covering the superlattice, and a second element is formed covering an adjacent portion of the semiconductor layer.

11. The method of claim 10, which includes amorphizing the superlattice portion extending laterally beyond the local region prior to performing the heat treatment.

12. The method of claim 11, wherein the amorphization comprises implanting at least one of silicon, argon, neon, xenon, carbon, fluorine, and germanium.

13. The method of claim 11, wherein implantation includes implantation at a dose ranging from 5 x 10¹⁴ to 1 x 10¹⁶ / cm².

14. A method for manufacturing a semiconductor device, comprising: Oxygen atoms are implanted into a local region of a semiconductor layer; a superlattice is formed over the local region of the semiconductor layer, the superlattice comprising a plurality of stacked layers, each layer group comprising a plurality of stacked substrate silicon monolayers defining a substrate silicon portion, and at least one oxygen atom monolayer confined within a lattice of an adjacent substrate silicon portion; and a heat treatment is performed to cause oxygen atoms in the superlattice to be displaced, and to cause oxygen atoms in the local region to migrate into the superlattice and replace at least a portion of the displaced oxygen atoms.

15. The method of claim 14, wherein forming the superlattice includes forming the superlattice such that it extends laterally over and outward from the local region.

16. The method of claim 15, comprising amorphizing the superlattice portion extending laterally beyond the local region prior to performing the heat treatment.

17. The method of claim 16, wherein the amorphization comprises implanting at least one of silicon, argon, neon, xenon, carbon, fluorine, and germanium.

18. The method of claim 16, wherein implantation includes implantation at a dose ranging from 5 x 10¹⁴ to 1 x 10¹⁶ / cm².

19. The method of claim 14, wherein forming the superlattice includes selectively forming the superlattice over the local region.

20. The method of claim 14, further comprising, after performing the heat treatment, forming a first element covering the superlattice and a second element covering an adjacent portion of the semiconductor layer.

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