Manufacturing method of display device

Abstract

Generally speaking, according to an embodiment, the method for manufacturing the display device of the present invention includes: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall, the partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from the side of the lower portion; disposing a resist covering the partition wall on the insulating layer; forming ribs and pixel openings surrounded by the ribs by etching away the portion of the insulating layer exposed from the resist; forming an organic layer that covers the lower electrode through the pixel opening and emits light according to the application of voltage; and forming an upper electrode covering the organic layer; and during the etching process, the upper portion of the upper portion is exposed from the resist.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a display device. Prior Technology

[0002] In recent years, display devices using Organic Light Emitting Diodes (OLEDs) as display elements have become practical. For these display devices, technologies to improve yield are needed. Summary of the Invention

[0003] Generally speaking, according to the embodiment, the method for manufacturing a display device includes the following steps: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall, the partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from the side of the lower portion; disposing a resist covering the partition wall on the insulating layer; forming ribs and pixel openings surrounded by the ribs by etching away the portion of the insulating layer exposed from the resist; forming an organic layer that covers the lower electrode through the pixel opening and emits light according to the application of voltage; and forming an upper electrode covering the organic layer; and during the etching process, the upper portion of the upper portion is exposed from the resist.

[0004] Depending on the implementation, a method for manufacturing a display device that can improve yield can be provided. Simple Explanation of the Diagram

[0005] Figure 1 is a diagram showing an example of the configuration of a display device in one embodiment. Figure 2 is a schematic top view showing an example of the layout of subpixels. Figure 3 is a schematic cross-sectional view of the display device along line III-III in Figure 2. Figure 4 shows an example of a layer structure that can be applied to organic layers. Figure 5 is a schematic cross-sectional view showing an example of a structure that can be applied to a partition wall. Figure 6 is a schematic cross-sectional view showing the manufacturing steps of the display device according to this embodiment. Figure 7 is a schematic cross-sectional view showing the steps following Figure 6. Figure 8A shows a schematic cross-sectional view of the steps following Figure 7. Figure 8B is a schematic cross-sectional view showing the steps following Figure 8A. Figure 8C shows a schematic cross-sectional view of the steps following Figure 8B. Figure 8D shows a schematic cross-sectional view of the steps following Figure 8C. Figure 9 shows a schematic cross-sectional view of the steps following Figure 8D. Figure 10 is a schematic cross-sectional view showing the steps following Figure 9. Figure 11 is a schematic cross-sectional view showing the steps following Figure 10. Figure 12 is a schematic cross-sectional view showing the steps following Figure 11. Figure 13 is a schematic cross-sectional view showing the steps following Figure 12. Figure 14 is a schematic cross-sectional view showing the steps following Figure 13. Figure 15 is a schematic cross-sectional view showing the steps following Figure 14. Implementation

[0006] The diagram is used as a reference while several implementation forms are explained.

[0007] The illustration is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art to maintain the essence of the invention are naturally included within the scope of this invention. Furthermore, the drawings, for the purpose of greater clarity, depict the width, thickness, shape, etc., of various parts in a patterned manner compared to the actual form; however, this is merely one example and is not intended to limit the interpretation of the invention. Also, in this specification and the various drawings, sometimes the same reference numerals are used to mark constituent elements that have the same or similar functions as those described above in previously shown figures, and repeated detailed descriptions are appropriately omitted.

[0008] Furthermore, in the diagram, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are shown. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The third direction Z is the normal direction of the plane that includes the first direction X and the second direction Y. Also, observing various elements parallel to the third direction Z is called a top view.

[0009] The display devices in each embodiment are organic electroluminescent display devices with organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle machines, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] Figure 1 is a diagram showing an embodiment of a display device DSP (Digital Signal Processor). The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 can be glass or a flexible resin film.

[0011] In this embodiment, the substrate 10 is rectangular when viewed from above. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0012] The display area DA has a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Pixel PX includes a plurality of subpixels SP displaying different colors. In this embodiment, it is envisioned that pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, pixel PX may include subpixels SP of other colors such as white, either together with subpixels SP1, SP2, and SP3, or in place of any one of subpixels SP1, SP2, and SP3.

[0013] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements made of thin-film transistors.

[0014] In the display area DA, there are a plurality of scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines SL that supply image signals to the pixel circuit 1 of each sub-pixel SP, and a plurality of power lines PL. In the example of Figure 1, the scan lines GL and power lines PL extend in the first direction X, and the signal lines SL extend in the second direction Y.

[0015] The gate electrode of pixel switch 2 is connected to scan line GL. The source electrode of pixel switch 2 is connected to signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of driving transistor 3 and capacitor 4. The source electrode of driving transistor 3 is connected to power line PL and capacitor 4. The drain electrode of driving transistor 3 is connected to display element DE.

[0016] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may include more thin-film transistors and capacitors.

[0017] Figure 2 is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Figure 2, subpixels SP2 and SP3 are arranged with subpixel SP1 in the first direction X. Furthermore, subpixels SP2 and SP3 are arranged in the second direction Y.

[0018] When subpixels SP1, SP2, and SP3 are arranged in this layout, in the display area DA, subpixels SP2 and SP3 are alternately arranged in rows in the second direction Y, and a plurality of subpixels SP1 are repeatedly arranged in rows in the second direction Y. These rows are alternately arranged in the first direction X. Furthermore, the layout of subpixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0019] Ribs 5 are configured in the display area DA. Ribs 5 have pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example of Figure 2, pixel opening AP1 is larger than pixel opening AP2, and pixel opening AP2 is larger than pixel opening AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Furthermore, the size of pixel openings AP1, AP2, and AP3 is not limited to this example. For example, pixel openings AP2 and AP3 may have the same size.

[0020] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0021] The portion of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of the sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include the capping layer described later. Rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0022] A partition wall 6 is disposed in the display area DA. The partition wall 6 is located above the rib 5 and overlaps with the rib 5 in its entirety. In the example of Figure 2, the partition wall 6 has the same planar shape as the rib 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 respectively. From another viewpoint, the rib 5 and the partition wall 6 are grid-like when viewed from above, surrounding each of the display elements DE1, DE2, and DE3. The partition wall 6 serves as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0023] Figure 3 is a schematic cross-sectional view of the display device DSP along line III-III in Figure 2. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits or wirings such as pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by the circuit layer 11.

[0024] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Ribs 5 are disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by ribs 5. Not shown in the cross-section of Figure 3, but the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the driving transistor 3 shown in Figure 1) through contact holes provided in the organic insulating layer 12.

[0025] The partition wall 6 includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. Consequently, the two ends of the upper portion 62 protrude beyond the sides of the lower portion 61. This shape of the partition wall 6 is referred to as overhanging.

[0026] In the example of Figure 3, the lower part 61 has a bottom layer 63 and a axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib 5 and is thinner than the axial layer 64. Also, in the example of Figure 3, the two ends of the bottom layer 63 protrude from the side of the axial layer 64. Furthermore, the ends of the bottom layer 63, when viewed from above, are located between the ends of the upper part 62 and the side of the axial layer 64.

[0027] In the example of Figure 3, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed above the shaft layer 64 of the lower part 61. The second top layer 66 is disposed above the first top layer 65.

[0028] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and faces lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and faces lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and faces lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of partition wall 6.

[0029] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3.

[0030] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as stacked film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as stacked film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as stacked film FL3.

[0031] A portion of the laminated film FL1 is located above the upper portion 62. This portion is separate from the portion of the laminated film FL1 surrounding the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminated film FL2 is located above the upper portion 62, and this portion is separate from the portion of the laminated film FL2 surrounding the partition wall 6 (the portion constituting the display element DE2). Furthermore, a portion of the laminated film FL3 is located above the upper portion 62, and this portion is separate from the portion of the laminated film FL3 surrounding the partition wall 6 (the portion constituting the display element DE3).

[0032] For subpixels SP1, SP2, and SP3, sealing layers SE11, SE12, and SE13 are respectively provided to cover the stacked films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the partition wall 6 surrounding the capping layer CP1 or subpixel SP1. Sealing layer SE12 continuously covers the partition wall 6 surrounding the capping layer CP2 or subpixel SP2. Sealing layer SE13 continuously covers the partition wall 6 surrounding the capping layer CP3 or subpixel SP3.

[0033] In the example of Figure 3, the laminated film FL1 and sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 are separated from the laminated film FL2 and sealing layer SE12 on the partition wall 6. Also, the laminated film FL1 and sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the laminated film FL3 and sealing layer SE13 on the partition wall 6.

[0034] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed over the entire display area DA, and a portion of them also extends to the surrounding area SA.

[0035] A cover element, such as a polarizing plate, a protective film, or a cover glass, can then be disposed above the resin layer RS2. This cover element can be bonded to the resin layer RS2 through an adhesive layer such as OCA (Optical Clear Adhesive).

[0036] Organic insulating layer 12 is formed of organic insulating materials such as polyimide. Ribs 5 and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, rib 5 is formed of silicon oxynitride, and sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. Resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0037] The lower electrodes LE1, LE2, and LE3 have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed of a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0038] The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 are equivalent to anodes, and the upper electrodes UE1, UE2, and UE3 are equivalent to cathodes.

[0039] The bottom layer 63 and the axial layer 64 of the partition wall 6 are formed of, for example, metallic materials. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. Furthermore, at least one of the bottom layer 63 and the axial layer 64 may have a multilayered structure. Also, the axial layer 64 may include a layer formed of an insulating material.

[0040] For example, the first top layer 65 is formed of a metallic material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of metallic materials used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys. Examples of conductive oxides used to form the second top layer 66 include ITO, IZO, or IGZO. Alternatively, the upper portion 62 may have a single-layer structure of metallic material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0041] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side of the lower part 61. The pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively supply pixel voltages corresponding to the image signals of the signal line SL to the lower electrodes LE1, LE2, and LE3.

[0042] Figure 4 shows an example of the layer structure applicable to organic layers OR1, OR2, and OR3. Organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In this embodiment, it is envisioned that organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are sequentially deposited in the third direction Z. However, organic layers OR1, OR2, and OR3 may have other structures, such as a so-called cascaded structure including a plurality of light-emitting layers EML.

[0043] The capping layers CP1, CP2, and CP3 have a laminated structure, for example, by overlapping a plurality of transparent layers. These transparent layers may comprise layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. Alternatively, at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0044] Organic layers OR1, OR2, and OR3 emit light according to the applied voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emissive layer EML of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the emissive layer EML of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the emissive layer EML of organic layer OR3 emits light in the red wavelength range.

[0045] As another example, the emissive layers (EMLs) of organic layers OR1, OR2, and OR3 can emit light of the same color (e.g., white). In this case, the display device DSP can include a color filter that converts the light emitted by the emissive layers EML into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can include a layer containing quantum dots, which are excited by the light emitted by the emissive layers EML to produce light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0046] Figure 5 is a schematic cross-sectional view showing an example of the configuration that can be applied to the partition wall 6. In Figure 5, the portion of the partition wall 6 located between sub-pixels SP1 and SP2 is illustrated. The same configuration as in Figure 5 can also be applied to the portion of the partition wall 6 located between sub-pixels SP1 and SP3, or between sub-pixels SP2 and SP3.

[0047] The upper layer 62 has an end point E11 on the side of sub-pixel SP1 and an end point E12 on the side of sub-pixel SP2. The first top layer 65 has a lower surface L1. The second top layer 66 has an upper surface U1. The axial layer 64 has a side surface F21 on the side of sub-pixel SP1 and a side surface F22 on the side of sub-pixel SP2. The bottom layer 63 has an end point E31 on the side of sub-pixel SP1, an end point E32 on the side of sub-pixel SP2, and an upper surface U3.

[0048] In the example of Figure 5, the end E11 of the upper part 62 protrudes beyond the end E31 of the bottom layer 63 and the side F21 of the shaft layer 64. Similarly, the end E12 of the upper part 62 protrudes beyond the end E32 of the bottom layer 63 and the side F22 of the shaft layer 64. Furthermore, the end E31 of the bottom layer 63 protrudes beyond the side F21 of the shaft layer 64. Similarly, the end E32 of the bottom layer 63 protrudes beyond the side F22 of the shaft layer 64. Additionally, in the example of Figure 5, the width of the second top layer 66 is the same as the width of the first top layer 65, but the width of the second top layer 66 may be smaller than the width of the first top layer 65. The shaft layer 64 is formed to be thicker than the bottom layer 63, the first top layer 65, and the second top layer 66.

[0049] Rib 5 has a first portion 51 and second portions 521 and 522. The first portion 51 is the portion of rib 5 with a fixed thickness. "Fixed" here includes not only the case where the thickness of rib 5 corresponding to its position in the XY plane remains completely unchanged, but also the case where there are minor variations that are not intentionally formed. In one example, the first portion 51 corresponds to the area not exposed to the etching described later using Figures 8A to 8D. The second portion 521 is the portion of rib 5 whose thickness decreases as it faces the pixel opening AP1. The second portion 522 is the portion of rib 5 whose thickness decreases as it faces the pixel opening AP2. The first portion 51 is located between the second portions 521 and 522.

[0050] In the example of Figure 5, the boundary B1 of part 1 51 and part 2 521 coincides with the end E11 of the upper part 62 in top view. Also, the boundary B2 of part 1 51 and part 2 522 coincides with the end E12 of the upper part 62 in top view. In other examples, boundary B1 and end E11 may be offset. Also, boundary B2 and end E12 may be offset.

[0051] Part 1 51 has an upper surface U5. Part 2 521 has an inclined surface 531 that slopes from boundary B1 toward pixel opening AP1. Part 2 522 has an inclined surface 532 that slopes from boundary B2 toward pixel opening AP2. Lower electrode LE1 has an upper surface Uc1 and an end point Ec1. Lower electrode LE2 has an upper surface Uc2 and an end point Ec2. End points Ec1 and Ec2 overlap with partition wall 6 in top view. Specifically, end points Ec1 and Ec2 overlap with shaft layer 64 in top view.

[0052] As shown in Figure 5, a step difference ST is generated on the upper surface U5 of the rib 5 due to the ends Ec1 and Ec2 of the lower electrodes LE1 and LE2. In this embodiment, the step difference ST is covered by the bottom layer 63 and the shaft layer 64. As shown in Figure 5, the upper surfaces of the shaft layer 64, the first top layer 65 and the second top layer 66 can be deformed according to the step difference ST.

[0053] In the example of Figure 5, the angle θ1 formed by the inclined surface 531 and the upper surface Uc1 of the lower electrode LE1, and the angle θ2 formed by the inclined surface 532 and the upper surface Uc2 of the lower electrode LE2 are equal (θ1=θ2). However, angles θ1 and θ2 may be different. In one example, angles θ1 and θ2 are less than 50°.

[0054] As shown in Figure 5, regions AR1 and AR2 are formed below the upper part 62. Regions AR1 and AR2 are areas surrounded by the lower surface of the upper part 62, the side surface of the lower part 61, and the upper surface of the rib 5. Specifically, region AR1 is surrounded by the lower surface L1 of the first top layer 65, the side surface F21 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end point E31 of the bottom layer 63, and the upper surface U5 of the first part 51. Similarly, region AR2 is surrounded by the lower surface L1 of the first top layer 65, the side surface F22 of the shaft layer 64, the upper surface U3 of the bottom layer 63, the end point E32 of the bottom layer 63, and the upper surface U5 of the first part 51.

[0055] Next, an example of a manufacturing method for the display device DSP of this embodiment will be described. Figures 6 to 15 are schematic cross-sectional views showing the manufacturing steps of the display device DSP of this embodiment. In these figures, the illustrations of the substrate 10 and the circuit layer 11 are omitted. Furthermore, in Figures 6, 7, and 9 to 15, the illustrations of the step difference ST caused by the end of the lower electrode are omitted.

[0056] In manufacturing the display device DSP, firstly, a circuit layer 11, an organic insulating layer 12, and lower electrodes LE1, LE2, and LE3 are formed on the substrate 10. Then, as shown in FIG6, an insulating layer L5 for processing to the rib 5 is formed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3; a first layer L63 for processing to the bottom layer 63 is formed on the insulating layer L5; a second layer L64 for processing to the shaft layer 64 is formed on the first layer L63; a third layer L65 for processing to the first top layer 65 is formed on the second layer L64; and a fourth layer L66 for processing to the second top layer 66 is formed on the third layer L65.

[0057] Next, layers L63 (1st layer), L64 (2nd layer), L65 (3rd layer), and L66 (4th layer) are patterned. This patterning includes the steps of placing a planar resist of the partition wall 6 on layer L66, forming a second top layer 66 by etching layer L66, forming a first top layer 65 by etching layer L65, forming an axial layer 64 by etching layer L64, and forming a bottom layer 63 by etching layer L63. After these steps, as shown in FIG. 7, a partition wall 6 having a lower portion 61 and an upper portion 62 is formed on the insulating layer L5. As shown in FIG. 5, the lower portion 61 includes the bottom layer 63 and the axial layer 64. Also, as shown in FIG. 5, the upper portion 62 includes the first top layer 65 and the second top layer 66.

[0058] Next, the formation of rib 5 will be explained using Figures 8A to 8D. Furthermore, in Figures 8A to 8D, the portions of insulating layer L5 and partition wall 6 located between lower electrodes LE1 and LE2 will be explained. The portions of insulating layer L5 and partition wall 6 located between lower electrodes LE1 and LE3, or between lower electrodes LE2 and LE3, are also formed using the same process as in Figures 8A to 8D.

[0059] First, as shown in Figure 8A, the resist R1 covering the partition wall 6 is disposed on the insulating layer L5. The resist R1 has the same grid-like planar shape as the partition wall 6. For example, the resist R1 has a cross-sectional shape in which the thickness decreases as it approaches the two ends. It is desirable that the size of the resist R1 is such that the ends E11 and E12 are not exposed from the resist R1. In the example of Figure 8A, the ends E11 and E12 of the upper part 62 are covered by the resist R1.

[0060] Next, as shown in Figure 8B, anisotropic dry etching is performed on the insulating layer L5 using the photoresist R1 as a mask. The two-point chain lines shown in Figures 8B to 8D represent the shapes of the insulating layer L5 and the photoresist R1 before etching. During this etching, the portion of the insulating layer L5 exposed from the photoresist R1 is etched. Furthermore, the photoresist R1 is also etched during this etching. Therefore, the width of the photoresist R1 gradually decreases during etching. Thus, as shown in Figure 8B, inclined surfaces L51 and L52 are formed on the insulating layer L5.

[0061] Furthermore, as the width of the resist R1 gradually decreases during the etching process, portions of the ends E11 and E12 of the upper part 62 and a portion of the upper surface U1 are exposed. Therefore, by means of the partition wall 6, the resist R1 is divided into resist R1a located on the AR1 side of the resist below the upper part 62, resist R1b located on the AR2 side of the resist below the upper part 62, and resist R1c located above the upper part 62. Additionally, the second top layer 66, formed of conductive oxide, is less affected by the etching. Therefore, the portion of the upper surface U1 exposed from resist R1c and the ends E11 and E12 are hardly etched.

[0062] During etching, the width of the resist R1 is further reduced, as shown in FIG8C, and the ends E11 and E12 of the upper part 62 are fully exposed. Furthermore, the resist R1a in region AR1 and the resist R1b in region AR2 are located directly below the upper part 62 in the third direction Z. Therefore, during this etching, the erosion of the resist R1a in region AR1 and the resist R1b in region AR2 is suppressed by the upper part 62. On the other hand, since the resist R1a outside region AR1 and the resist R1b outside region AR2 do not overlap with the upper part 62 when viewed from above, they are eroded by this etching. Therefore, the end Ea aligned with the end E11 of the upper part 62 in the third direction Z is formed in the resist R1a. Similarly, the end Eb aligned with the end E12 of the upper part 62 in the third direction Z is formed in the resist R1b. Additionally, during the etching process, a protective film can be formed at the ends Ea and Eb to prevent the etching from eroding.

[0063] As the etching is further performed, as shown in Figure 8D, the width of the resist R1 is further reduced. This etching removes portions of the insulating layer L5 exposed from the resists R1a and R1b, forming rib 5 and pixel openings AP1 and AP2 surrounded by rib 5. Furthermore, this etching forms a first portion 51 of fixed thickness, a second portion 521 whose thickness decreases as it faces pixel opening AP1, and a second portion 522 whose thickness decreases as it faces pixel opening AP2 within the rib 5. In the second portion 521, an inclined surface 531 is formed, sloping from the boundary B1 between the first portion 51 and the second portion 521 towards pixel opening AP1. Similarly, in the second portion 522, an inclined surface 532 is formed, sloping from the boundary B2 between the first portion 51 and the second portion 522 towards pixel opening AP2. The etching ends at the point where the rib 5 and pixel openings AP1 and AP2 are formed. After this etching, the resist R1 is removed.

[0064] As shown in Figure 8D, at the end of the etching, resist R1a remains in region AR1, and resist R1b remains in region AR2. Furthermore, resist R1c remains on the upper surface U1 of the upper part 62. Moreover, the lower surface L1 of the first top layer 65, the side surface F21 of the shaft layer 64, the end E31 of the bottom layer 63, and the upper surface U5 of the first part 51 in region AR1 are covered by resist R1a. Similarly, the lower surface L1 of the first top layer 65, the side surface F22 of the shaft layer 64, the end E32 of the bottom layer 63, and the upper surface U5 of the first part 51 in region AR2 are covered by resist R1b. In the example of Figure 8D, the end E11 of the upper part 62, the end Ea of the resist R1a, and the boundary B1 are consistent in top view. Similarly, the end E12 of the upper part 62, the end Eb of the resist R1b, and the boundary B2 are consistent when viewed from above.

[0065] After forming rib 5, the steps for forming display elements DE1, DE2, and DE3 are performed. In this embodiment, it is envisioned that display element DE1 is formed first, followed by display element DE2, and finally display element DE3. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0066] When forming the display element DE1, as shown in FIG9, a multilayer film FL1 and a sealing layer SE11 are first formed. As shown in FIG3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1.

[0067] The organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The laminated film FL1 is divided into multiple parts by overhanging partitions 6. The sealing layer SE11 continuously covers each of the divided parts of the laminated film FL1 and the partitions 6.

[0068] After forming the stacked film FL1 and the sealing layer SE11, as shown in Figure 9, a photoresist R2 is disposed on the sealing layer SE11. The photoresist R2 covers a portion of the sub-pixel SP1 and the surrounding partition wall 6.

[0069] Subsequently, as shown in FIG10, the portions of the stacked film FL1 and the sealing layer SE11 exposed from the resist R2 are removed by etching with resist R2 as a mask. This forms the display element DE1 on the sub-pixel SP1. For example, this etching includes wet or dry etching of the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1 in sequence. After these etchings, the resist R2 is removed.

[0070] Display element DE2 is formed in the same order as display element DE1. That is, when forming display element DE2, as shown in FIG11, a multilayer film FL2 and a sealing layer SE12 are formed. As shown in FIG3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2.

[0071] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each of the divided parts of the laminated film FL2 and the partitions 6.

[0072] After forming the stacked film FL2 and the sealing layer SE12, as shown in Figure 11, resist R3 is applied on the sealing layer SE12. Resist R3 covers a portion of the sub-pixel SP2 and its surrounding partition wall 6.

[0073] Subsequently, as shown in FIG12, the portions of the stacked film FL2 and the sealing layer SE12 exposed from the resist R3 are removed by etching with resist R3 as a mask. This forms the display element DE2 on the sub-pixel SP2. For example, this etching includes wet or dry etching of the sealing layer SE12, the capping layer CP2, the upper electrode UE2, and the organic layer OR2 in sequence. After these etchings, the resist R3 is removed.

[0074] Display element DE3 is formed in the same order as display elements DE1 and DE2. That is, when forming display element DE3, as shown in FIG13, a multilayer film FL3 and a sealing layer SE13 are formed. As shown in FIG3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0075] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into multiple parts by overhanging partitions 6. The sealing layer SE13 continuously covers each of the divided parts of the laminated film FL3 and the partitions 6.

[0076] After forming the stacked film FL3 and the sealing layer SE13, as shown in Figure 13, resist R4 is disposed on the sealing layer SE13. Resist R4 covers a portion of the sub-pixel SP3 and the surrounding partition wall 6.

[0077] Subsequently, as shown in FIG14, the portions of the stacked film FL3 and the sealing layer SE13 exposed from the resist R4 are removed by etching with resist R4 as a mask. This forms the display element DE3 on the sub-pixel SP3. For example, this etching includes wet or dry etching of the sealing layer SE13, the capping layer CP3, the upper electrode UE3, and the organic layer OR3 in sequence. After these etchings, the resist R3 is removed.

[0078] After forming display elements DE1, DE2, and DE3, as shown in Figure 15, resin layer RS1, sealing layer SE2, and resin layer RS2 are formed sequentially. After these steps, the display device DSP is completed.

[0079] In this embodiment, as shown in Figures 8A to 8D, due to the anisotropic dry etching performed during the steps of forming ribs 5 and pixel openings AP1 and AP2, the width of the resist R1 is reduced, thereby exposing the ends E11 and E12 of the upper portion 62. That is, by means of the partition wall 6, the resist R1 is divided into resists R1a and R1b located below the upper portion 62, and resist R1c located above the upper portion 62. The portions of resists R1a and R1b that overlap with the upper portion 62 in the third direction Z are almost not etched because the upper portion 62 shields the etching. Therefore, through this etching, pixel openings AP1 and AP2 are formed on the rib 5 such that the end E11 of the upper part 62 aligns with the boundary B1 of the first part 51 and the second part 521 in a top view, and the end E12 of the upper part 62 aligns with the boundary B2 of the first part 51 and the second part 522 in a top view. That is, the width of the first part 51 of the rib 5 is determined by the width of the upper part 62. The same applies to the first part 51 located between pixel openings AP1 and AP3 or between pixel openings AP2 and AP3.

[0080] On the other hand, when the amount of resist R1 applied is relatively large, the etching ends before the resist R1 is separated by the separator 6. In this case, the width of the first portion 51 of the rib 5 is determined by the width of the resist R1 at the end of the etching. Therefore, due to the deviation in the amount of resist applied, there is a possibility that pixel openings of different sizes or positions may be formed for each pixel.

[0081] In contrast, in this embodiment, as described above, the width of the first portion 51 of the rib 5 is determined by the width of the upper portion 62. Therefore, pixel openings of approximately the same size or position can be formed for each pixel. Furthermore, compared to the case where a larger amount of resist is applied, larger pixel openings can be formed.

[0082] Thus, the manufacturing method of the display device DSP according to this embodiment can improve the yield rate when manufacturing the display device DSP. In addition, various better effects can be obtained from this embodiment.

[0083] The above description of the manufacturing method of the display device, which is an embodiment of the present invention, is provided above. Any manufacturing method of the display device that can be appropriately modified and implemented by those skilled in the art, as long as it contains the spirit of the present invention, is within the scope of the present invention.

[0084] Within the scope of the present invention, various variations can be conceived by those skilled in the art, and such variations are also considered to fall within the scope of the present invention. For example, regarding the above embodiments, those skilled in the art may appropriately add, delete, or modify the constituent elements, or add, omit, or modify the steps or conditions, as long as the spirit of the present invention is present, it is included within the scope of the present invention.

[0085] Furthermore, any other effects resulting from the embodiments described above should be interpreted as being caused by the present invention, as clearly stated in this specification or as reasonably conceived by those skilled in the art.

[0086] Cross-reference of related applications This application asserts priority based on Japanese Patent Application No. 2023-193014, filed on November 13, 2023, and incorporates all the contents described in that Japanese Patent Application.

[0087] 1: Pixel circuit 2: Pixel switch 3: Driving transistor 4: Capacitor 5: Ribs 6: Partition wall 10:Substrate 11: Circuit Layer 12: Organic insulating layer 51: Part 1 61: Lower part 62: Upper part 63: Bottom layer 64: Axis Layer 65: Top Floor 1 66: Second Top Floor 521, 522: Part 2 531, 532: Inclined surfaces AP1, AP2, AP3: Pixel apertures AR1, AR2: Areas B1, B2: Boundaries CP1, CP2, CP3: Cap layer DA: Display area DE: Display element DE1, DE2, DE3: Display elements DSP: Display device E11, E12: Ends E31, E32: Ends Ea: End EBL: Electron Blocking Layer Eb: End Ec1, Ec2: Ends EIL: Electron Injection Layer EML: Emissive Layer ETL: Electron Transport Layer F21, F22: Side view FL1, FL2, FL3: Stacked films GL: Scan line HBL: Hole Barrier Layer HIL: Hole Injection Layer HTL: Hole Transport Layer L1: Lower surface L5: Insulation layer L51, L52: Inclined surfaces L63: Level 1 L64: Level 2 L65: 3rd Floor L66: 4th Floor LE1, LE2, LE3: Lower electrodes OR1, OR2, OR3: Organic layer PL: Power cord PX: pixel R1~R4: Corrosion resist R1a: Corrosion resist R1b: Corrosion resist R1c: Corrosion resist RS1, RS2: Resin layer SA: Surrounding Area SE2, SE11, SE12, SE13: Sealing layer SL: Signal line SP, SP1, SP2, SP3: Subpixels ST: Step division U1, U3, U5: Upper surface Uc1, Uc2: Upper surface UE1, UE2, UE3: Upper electrode X: First direction Y: 2nd direction Z: Third direction θ1: Angle θ2: Angle III-III: Line

Claims

1. A method of manufacturing a display device, comprising: forming a lower electrode; forming an insulating layer on the lower electrode; forming a partition wall, the partition wall including a lower portion disposed above the insulating layer and an upper portion having an end portion protruding from the side of the lower portion; disposing a resist covering the partition wall on the insulating layer; forming ribs and pixel openings surrounded by the ribs by etching away portions of the insulating layer exposed from the resist; forming an organic layer that covers the lower electrode through the pixel openings and emits light according to the application of voltage; and forming an upper electrode covering the organic layer; wherein, during the etching process, the end portion of the upper portion is exposed from the resist.

2. The method for manufacturing the display device as claimed in claim 1, wherein the width of the resist is gradually reduced by the etching process described above.

3. The method of manufacturing the display device as claimed in claim 1, wherein at the end of the etching process, the resist remains in the area surrounded by the lower surface of the upper part, the side surface of the lower part, and the upper surface of the rib.

4. The method of manufacturing the display device as claimed in claim 3, wherein at the end of the etching, the end of the upper portion and the end of the resist remaining in the region are aligned in plan view.

5. The method of manufacturing the display device as claimed in claim 1, wherein at the end of the etching process, the resist remains on the upper surface of the upper part.

6. The method of manufacturing the display device as claimed in claim 1, wherein the rib is formed by the above-described etching, comprising a first portion with a fixed thickness and a second portion with a thickness decreasing as it moves toward the pixel opening.

7. The method of manufacturing the display device as claimed in claim 6, wherein at the end of the etching, the boundary of the upper part is consistent with the boundary of the first part and the second part in a top view.

8. A method for manufacturing a display device as claimed in claim 7, wherein the second part has an inclined surface that slopes from the boundary toward the pixel opening; and the angle between the inclined surface and the upper surface of the lower electrode is 50° or less.

9. A method for manufacturing a display device as claimed in claim 1, wherein the end of the lower electrode overlaps with the partition wall when viewed from above.

10. A method for manufacturing a display device as claimed in claim 1, wherein the upper portion has a first top layer disposed above the lower portion and a second top layer disposed above the first top layer; and the second top layer is formed of a conductive oxide.

11. The method of manufacturing a display device as claimed in claim 10, wherein at the end of the etching process, the surface below the first top layer is covered with the resist.

12. A method for manufacturing a display device as claimed in claim 1, wherein the lower part has a shaft layer and a bottom layer disposed between the shaft layer and the rib; and the end of the bottom layer, viewed from above, is located between the end of the upper part and the side of the shaft layer.

13. A method for manufacturing a display device as claimed in claim 12, wherein the end of the lower electrode overlaps with the shaft layer in a top view.

14. The method of manufacturing a display device as claimed in claim 12, wherein at the end of the etching process, the end of the substrate is covered by the resist.

15. A method for manufacturing a display device as claimed in claim 12, wherein at the end of the etching process, the side surface of the axial layer is covered by the resist.

16. The method for manufacturing the display device as claimed in claim 1, wherein the etching described above is dry etching.

17. The method for manufacturing a display device as claimed in claim 1, wherein the etching is anisotropic etching.

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