Semiconductor device and methods for manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a multilayer stack on a semiconductor substrate, patterning the multilayer stack into a plurality of fins located in a first region and a second region, the first region having a higher density than the second region, rounding a plurality of corners of the fins, depositing a first dielectric layer between the fins, removing a portion of the first dielectric layer to form a first mask, and forming a gate structure on the first mask.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device. [Previous Technology]

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry increases the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby enabling more components to be integrated into a given area. However, as the minimum feature size decreases, more problems arise that need to be solved. [Summary of the Invention]

[0004] The present invention provides a method for manufacturing a semiconductor device, comprising forming a multilayer stack on a semiconductor substrate, patterning the multilayer stack into a plurality of fins, the plurality of fins being located in a first region and a second region, the density of the first region being higher than that of the second region, rounding a plurality of corners of the plurality of fins, depositing a first dielectric layer between the plurality of fins, removing a portion of the first dielectric layer to form a first mask, and forming a gate structure on the first mask.

[0005] Another embodiment provides a method of manufacturing a semiconductor device, including forming an isolation region between a plurality of fins on a semiconductor substrate, each of the plurality of fins including a plurality of alternating material layers, depositing a first dielectric material on the isolation region, the first dielectric material having a first thickness in a first region and a second thickness in a second region, the first thickness being different from the second thickness, and reducing the first thickness to a third thickness and reducing the second thickness to a fourth thickness.

[0006] Another embodiment provides a semiconductor device including a metal gate, an isolation region, and a masking layer. The metal gate is on a semiconductor substrate and surrounds at least a portion of a plurality of nanostructures extending between a first source / drain region and a second source / drain region; the isolation region is located between the metal gate and the semiconductor substrate; and the masking layer is located between the metal gate and the isolation region, the masking layer including a first portion and a second portion. The first portion has a first thickness; and the second portion has a second thickness different from the first thickness.

Implementation Method

[0008] The following description of the invention provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the content of the invention. Of course, these are merely examples and are not restrictive. For example, the formation of a first feature on or above a second feature in the following description may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, the invention may repeat reference numerals and / or letters in various embodiments. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship of one element or feature to another element or feature shown in the figure. In addition to the orientations described in the figure, spatial relative terms also include different orientations of the apparatus during use or operation. The instrument may also be in other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0010] This embodiment will now be described with reference to a particular embodiment in which a masking layer is formed on an isolation region, and a rounding process is used prior to deposition to reduce load between different regions. However, embodiments will be described below in a specific scenario, comprising a wafer containing multiple nano-FETs. Various embodiments may also be applied to wafers containing other types of transistors (e.g., FinFETs, planar transistors, or similar devices) instead of or in combination with nano-FETs.

[0011] Figure 1 shows an example of a three-dimensional view of a nanofield-effect transistor (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like) according to some embodiments. The nanofield-effect transistor includes a nanostructure 55 (such as a nanosheet, nanowire, or the like) located above a fin 66 on a substrate 50 (such as a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanofield-effect transistor. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination of both. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as being separated from the substrate 50, the term "substrate" herein may refer solely to a semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of fin 66 is illustrated as being made of a single, continuous material with the base 50, the bottom portion of fin 66 and / or the base 50 may be composed of a single material or multiple materials. In this case, fin 66 refers to the portion extending between adjacent STI regions 68.

[0012] The gate dielectric layer 100 is located above the top surface of the fin 66 and is disposed along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 and are located on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The epitaxial source / drain regions 92 may be referred to individually or collectively as a source or a drain depending on the context.

[0013] Figure 1 further illustrates the reference sections used in the following figures. Sections A to A' are along the longitudinal axis of the gate electrode 102, for example, their direction is perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanofield-effect transistor. Sections B to B' are perpendicular to sections A to A' and parallel to the longitudinal axis of the fins 66 of the nanofield-effect transistor, for example, their direction is consistent with the current flow direction between the epitaxial source / drain regions 92 of the nanofield-effect transistor. Sections C to C' are parallel to sections A to A' and extend through the epitaxial source / drain regions 92 of the nanofield-effect transistor. For clarity, the following figures will refer to these reference sections.

[0014] Some embodiments discussed herein are discussed in the context of forming nano-field-effect transistors using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments also consider aspects used in planar devices, such as planar field-effect transistors or fin field-effect transistors (FinFETs).

[0015] Figures 2 through 23C are cross-sectional views of intermediate stages in the fabrication of nano-field-effect transistors according to certain embodiments. Figures 2 through 9A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, and 25 through 30 show reference cross-sections A through A' as shown in Figure 1. Figures 9B, 10B, 11B, 12B, 13B, 14B, 15B, 15D, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B show reference cross-sections B through B' as shown in Figure 1. Figures 10A, 11A, 12A, 13A, 14A, 15A, 15C, 16C, 21C, 22C, 23C and 24C show the reference sections C to C' shown in Figure 1.

[0016] A substrate 50 is provided in Figure 2. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be a doped (e.g., p-type or n-type dopant) or undoped substrate. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator. For example, the insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, or a similar layer. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide) or combinations thereof.

[0017] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type nano-field-effect transistor), while the p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type nano-field-effect transistor). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator line 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown in the figure, any number of n-type regions 50N and p-type regions 50P can be provided.

[0018] Further in Figure 2, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layer 53). For ease of explanation, as will be discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nano-field-effect transistor in the p-type region 50P. Additionally, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nano-field-effect transistor in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nano-field-effect transistor in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nano-field-effect transistor in the p-type region 50P.

[0019] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of nano-field-effect transistors in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of non-field-effect transistors in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (such as silicon or another semiconductor material) and be formed simultaneously. Figures 24A, 24B, and 24C illustrate structures resulting from such embodiments, wherein the channel regions in both the p-type region 50P and the n-type region 50N are composed of silicon.

[0020] For illustrative purposes, the multilayer stack 64 includes a first semiconductor layer 51 and a second semiconductor layer 53, each of which has three layers. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Vapor Phase Epitaxy (VPE), and Molecular Beam Epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanofield-effect transistors (such as silicon germanium or similar materials), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanofield-effect transistors (such as silicon, silicon carbon, or similar materials). For illustrative purposes, the multilayer stack 64 has a bottom semiconductor layer suitable for p-type nanofield-effect transistors. In some embodiments, the multilayer stack 64 may form a bottom layer that is a semiconductor layer suitable for n-type nanofield-effect transistors.

[0021] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nano-field-effect transistor. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nano-field-effect transistor.

[0022] Referring now to Figure 3, according to some embodiments, fins 66 are formed in a substrate 50 and nanostructures 55 are formed in a multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. The formation of nanostructures 55 by etching the multilayer stack 64 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from a first semiconductor layer 51 and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from a second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0023] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the created patterns to have a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, lithography forms a sacrificial layer on a substrate and patterning is performed using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process, and then the sacrificial layer is removed, leaving spacers that can be used for patterning the fins 66.

[0024] Figure 3 further shows that the widths of the fins 66 in the n-type region 50N and the p-type region 50P are substantially equal. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or thinner than the width of the fins 66 in the p-type region 50P. Furthermore, while each fin 66 and nanostructure 55 has a consistent width in the figures, in other embodiments, the fins 66 and / or nanostructure 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 continuously increases in the direction toward the substrate 50. In these embodiments, the width of each nanostructure 55 may be different and its shape may be trapezoidal.

[0025] Furthermore, Figure 3 shows that some nanostructures 55 can be disposed in a dense region (represented in Figure 3 as an n-type region 50N, although it could also be a p-type region 50P or any other suitable region), wherein the nanostructures 55 are disposed close to each other. In a particular embodiment, the nanostructures 55 within the n-type region 50N can be disposed such that a first spacing S1 is between about 30 nm and about 50 nm, thus giving the nanostructures 55 a first density. However, any suitable spacing can also be used.

[0026] Other nanostructures are also disposed in non-dense regions (represented by p-type region 50P in Figure 3, although it could also be n-type region 50N or any other suitable region), in which the distance between nanostructures 55 is greater than that between nanostructures 55 in dense regions. In a particular embodiment, the nanostructures 55 within the p-type region 50P can be configured such that the second spacing S2 (the spacing between the nanostructure shown in Figure 3 and other nanostructures 55 not shown separately in Figure 3) is between about 50 nm and about 200 nm, such that the second density of nanostructures 55 is less than the first density. However, any suitable spacing can also be used.

[0027] In Figure 4, the STI region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. The insulating material can be annealed after formation. In one embodiment, the insulating material is formed such that an excess of insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, multiple layers can be used in some embodiments. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. A filler material, such as the material discussed above, can then be formed on the liner.

[0028] The insulating material is then removed to remove excess insulating material from the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. The planarization process exposes the nanostructure 55 so that the top surfaces of the nanostructure 55 and the insulating material are flat after the planarization process is completed.

[0029] The insulating material is then recessed to form the STI region 68. After the insulating material is recessed, the upper portions of the fins 66 of the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a planar, convex, concave (e.g., dish-shaped) or combination thereof, as shown. The top surface of the STI region 68 may be formed into a planar, convex, and / or concave surface by appropriate etching. The STI region 68 may be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the insulating material faster than etching the fins 66 and the nanostructure 55). For example, deoxides such as dilute hydrofluoric acid (dHF) may be used.

[0030] The process described in Figures 2 to 4 above is only one example of forming the fin 66 and nanostructure 55. In some embodiments, the fin 66 and / or nanostructure 55 can be formed using a masking and epitaxial growth process. For example, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched in the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed to allow the epitaxial structure to protrude from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material for epitaxial growth can be in-situ doped during the growth process, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping can be used simultaneously.

[0031] Furthermore, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) described and discussed herein are composed of the same material in the p-type region 50P and the n-type region 50N, for illustrative purposes only. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials, or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0032] Furthermore, in Figure 4, suitable well regions (not shown separately) can be formed in the fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different types of well regions, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed on the fins 66 and STI regions 68 of the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by spin coating or patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurities are implanted in the p-type region 50P. The photoresist can act as a mask to substantially prevent n-type impurities from implanting into the n-type region 50N. The n-type impurities implanted in this region can be phosphorus, arsenic, antimony, etc., with a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed by an acceptable ashing process, etc.

[0033] Before or after implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed on the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed by spin coating or patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurities implanted in this region can be boron, boron fluoride, indium, etc., with a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist can be removed by acceptable ashing processes, etc.

[0034] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair the implantation damage and stimulate the implanted p-type impurities and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during the epitaxial process, which can avoid implantation, although in-situ doping and implantation doping can be used simultaneously.

[0035] In Figure 5, a rounding process (indicated by the arrow marked 57 in Figure 5) is used to trim the topmost second nanostructure 54C, rounding its edges. In one embodiment, the rounding process 57 is one or more etching processes, such as one or more wet or dry etching processes (e.g., anisotropic wet etching), which removes material from the top surface and sides of the topmost second nanostructure 54C. However, any suitable trimming process may also be used.

[0036] In one embodiment, one or more wet or dry etching processes can remove material from the top and corners of the topmost second nanostructure 54C to round the topmost second nanostructure 54C. In a particular embodiment, material between about 1 nm and about 2 nm can be removed from the top of the topmost second nanostructure 54C. Furthermore, one or more wet or dry etching processes can remove material between about 0.5 nm and about 1.5 nm or more from the corners of the topmost second nanostructure 54C, and can be performed in the horizontal direction or the vertical direction in Figure 5.

[0037] By using the cylindrical process 57, the corners of the openings between the nanostructures 55 are also made more rounded. Therefore, materials (such as subsequently used precursors) can more easily enter and exit the openings between the nanostructures 55 without being blocked by sharp corners. As described below, this improvement helps to reduce the load between different regions on the substrate 50.

[0038] In Figure 6, a first dielectric layer 62 is deposited between the nanostructures 55 and above the STI region 68. In one embodiment, the first dielectric layer 62 may be a dielectric material, such as silicon nitride, silicon carbide, silicon carbide nitride, combinations of these materials, or similar materials, deposited using a deposition process, such as chemical vapor deposition, atomic layer deposition, combinations of these depositions, or similar depositions. However, any suitable material and deposition process may also be used.

[0039] Unfortunately, during the deposition process, different spacings (e.g., the difference between the first spacing S1 and the second spacing S2) between nanostructures 55 in dense regions (e.g., the first spacing S1) and non-dense regions (e.g., the second spacing S2) will have different effects on the deposition process of dense regions (e.g., n-type region 50N) and non-dense regions (e.g., p-type region 50P). In particular, different spacings will affect the ability of precursors to penetrate to the bottom of the trenches between nanostructures 55. This effect will result in varying amounts of material deposited in the first dielectric layer 62 between nanostructures 55 in different regions.

[0040] However, as described in Figure 5 above, by rounding the corners of the nanostructure 55, the impact of the nanostructure 55 on the deposition process can be reduced. In particular, by rounding the corners of the openings between the nanostructures 55, the openings are enlarged along the top surface, allowing the first dielectric layer 62 to be deposited more compliantly compared to the case where the nanostructure 55 remains non-rounded. Therefore, the first dielectric layer 62 can be deposited in dense regions (e.g., n-type region 50N) with a first thickness T1 between approximately 5 nm and approximately 30 nm, while the same process can deposit the first dielectric layer 62 in non-dense regions (e.g., p-type region 50P) with a second thickness T2 between approximately 5 nm and approximately 30 nm, the second thickness T2 being greater than the first thickness T1. However, any suitable thickness can also be used.

[0041] Figure 7 shows the formation of an STI hard mask 67 from the first dielectric layer 62 by reducing the thickness of the first dielectric layer 62 (e.g., a first thickness T1 and a second thickness T2). In one embodiment, the STI hard mask 67 can be formed using one or more wet or dry etching processes, or a combination of dry and wet etching processes. Any suitable combination of removal processes can be used.

[0042] However, since the first dielectric layer 62 has a different thickness (e.g., a first thickness T1 and a second thickness T2) at the start of the reduction process, the reduction process forming the STI hard mask 67 from the first dielectric layer 62 will also have different thicknesses in dense regions (e.g., n-type region 50N) and non-dense regions (e.g., p-type region 50P). In a particular embodiment, the STI hard mask 67 in the dense region (e.g., n-type region 50N) may have a third thickness T3 between about 5 nm and about 15 nm, and the STI hard mask 67 in the non-dense region (e.g., p-type region 50P) may have a fourth thickness T4 between about 5 nm and about 15 nm. However, any suitable thickness may also be used.

[0043] The cylindrical process 57 discussed in Figure 5 above can reduce the difference between the third thickness T3 and the fourth thickness T4. In particular, the load between dense regions (e.g., n-type region 50N) and non-dense regions (e.g., p-type region 50P) can be reduced to less than about 6.6 nm. However, any suitable load can also be used.

[0044] In Figure 8, a dummy dielectric layer 70 is formed on the STI hard mask 67, the fin 66, and / or the nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a masking layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The masking layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 72 can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques to deposit a selected material. The dummy gate layer 72 can be made of other materials that exhibit high etch selectivity when etching the isolation region. For example, the mask layer 74 may comprise silicon nitride, silicon oxynitride, or similar materials. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 in the figure only covers the fin 66 and nanostructure 55 for reference only. In some embodiments, the dummy dielectric layer 70 may be deposited such that it covers the STI region 68, extending between the dummy gate layer 72 and the STI region 68.

[0045] Figures 9A to 23C show various additional steps in the fabrication of the embodiment apparatus. Figures 9A, 10A, 11A, 12A, 13A, 14A, 15A, 15C, 16A, 16C, 17A, 18A, 21C, 22C, and 23C show features in the n-type region 50N or p-type region 50P. In Figures 9A and 9B, the mask layer 74 can be patterned using acceptable lithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric layer 71, respectively. The dummy gate 76 covers the respective channel regions of the fin 66. The pattern of the mask 78 can be used to physically isolate each dummy gate 76 from its adjacent dummy gate 76. The length direction of the dummy gate 76 can also be substantially perpendicular to the length direction of each fin 66.

[0046] In Figures 10A and 10B, a first spacer layer 80 and a second spacer layer 82 are formed on the structures shown in Figures 9A and 9B, respectively. The first spacer layer 80 and the second spacer layer 82 will then be patterned to serve as spacers for forming self-aligned source / drain regions. In Figures 10A and 10B, the first spacer layer 80 is formed on the top surface of the STI region 68, on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78, and on the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. The second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques including thermal oxidation or deposition via CVD, ALD, etc. The second spacer layer 82 may be formed of a material with an etch rate different from that of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or similar materials, and may be deposited by CVD, ALD, or similar methods.

[0047] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, a lightly doped source / drain (LDD) region (not shown separately) may be implanted. In embodiments with different device types, similar to the implantation discussed in Figure 4 above, a mask (e.g., photoresist) may be formed on the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P, and then the mask may be removed. Subsequently, a mask (e.g., photoresist) may be formed on the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N, and then the mask may be removed. The n-type impurity may be any n-type impurity discussed above, and the p-type impurity may be any p-type impurity discussed above. Impurity concentrations in the LDD region range from approximately 1 x 10¹⁵ atoms / cm³ to approximately 1 x 10¹⁹ atoms / cm³. Annealing can be used to repair implanted damage and excite implanted impurities.

[0048] In Figures 11A and 11B, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using suitable etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), or similar processes. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch barrier layer when the second spacer layer 82 is patterned. The second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etching barrier layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83 (as shown in Figure 11A). Subsequently, the second spacer 83 acts as a mask while the exposed portion of the first spacer layer 80 is etched, thereby forming the first spacer 81 (as shown in Figure 11A).

[0049] As shown in Figure 11A, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. As shown in Figure 11B, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 of the adjacent mask 78, dummy gate 76, and dummy gate dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric layer 70. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 of the adjacent mask 78, dummy gate 76, and dummy gate dielectric layer 71.

[0050] It is worth noting that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences may be used; for example, fewer or additional spacers may be used, steps may be used in a different sequence (e.g., the first spacer 81 may be patterned before the deposition of the second spacer layer 82), additional spacers and / or similar spacers may be formed and removed. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0051] In Figures 12A and 12B, according to some embodiments, a first groove 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region will subsequently be formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. As shown in Figure 12A, the top surface of the STI hard mask 67 may be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed below the top surface of the STI hard mask 67, or similarly. The first groove 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). A first spacer 81, a second spacer 83, and a mask 78 shield portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the first groove 86. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or a multi-pass etching process. A timed etching process can be used to stop etching the first groove 86 after it has reached the desired depth.

[0052] In Figures 13A and 13B, the portions of the sidewalls of each layer of the multilayer stack 64 formed of a first semiconductor material (such as a first nanostructure 52) exposed by the first groove 86 are etched in an n-type region 50N to form sidewall grooves 88, and the portions of the sidewalls of each layer of the multilayer stack 64 formed of a second semiconductor material (such as a second nanostructure 54) exposed by the first groove 86 are etched in a p-type region 50P to form sidewall grooves 88. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall grooves 88 are shown as upright in Figure 13B, the sidewalls can be concave or convex. Isotropic etching processes such as wet etching can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P, while an etchant selectively applied to the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, a mask (not shown) can be used to protect the n-type region 50N, while an etchant selectively applied to the second semiconductor material is used to etch the second nanostructure 54, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In embodiments where the first nanostructure 52 comprises silicon germanium and the second nanostructure 54 comprises silicon or silicon carbide, a dry etching process can be performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, etc., can be used to etch the sidewalls of the second nanostructure 54 in the n-type region 50N.

[0053] In Figures 14A to 14C, a first internal spacer 90 is formed in a sidewall recess 88. The first internal spacer 90 may be formed by depositing an internal spacer layer (not shown separately) on the structure shown in Figures 13A and 13B. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain region and the gate structure. As will be discussed in more detail below, the source / drain region will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0054] The internal spacer layer can be deposited by a conformal deposition process, such as CVD, ALD, etc. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low k) material having a k value of less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer sidewalls of the first internal spacer 90 are shown to be flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first internal spacer 90 may extend beyond or recess from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0055] Furthermore, although the outer wall of the first internal spacer 90 is shown as upright in Figure 14B, the outer wall of the first internal spacer 90 can be concave or convex. As an example, Figure 14C shows an embodiment in which the sidewall of the first nanostructure 52 is concave, the outer wall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54 in the n-type region 50N. An embodiment also shows that the sidewall of the second nanostructure 54 is concave, the outer wall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the first nanostructure 52 in the p-type region 50P. The internal spacer layer can be etched by anisotropic etching processes, such as RIE, NBE, etc. The first internal spacer 90 can be used to prevent the subsequently formed source / drain regions (such as epitaxial source / drain regions 92, which are discussed below with reference to Figures 15A to 15C) from being damaged by subsequent etching processes (e.g., etching processes used to form gate structures).

[0056] In Figures 15A to 15C, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the epitaxial source / drain regions 92 may exert pressure on the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 15B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between each pair of adjacent epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance such that the epitaxial source / drain regions 92 are not short-circuited with the gate of the subsequently formed nanoFET.

[0057] The epitaxial source / drain region 92 in the n-type region 50N (such as an NMOS region) can be formed by shielding the p-type region 50P (such as a PMOS region). The epitaxial source / drain region 92 is then grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may comprise any acceptable material suitable for an n-type nanofield-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from its respective upper surface of the nanostructure 55 and may have an end face.

[0058] The epitaxial source / drain region 92 in the p-type region 50P (such as a PMOS region) can be formed by shielding the n-type region 50N (such as an NMOS region). The epitaxial source / drain region 92 is then grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may comprise any acceptable material suitable for a p-type nanofield-effect transistor. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 may comprise a material that applies compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or similar materials. The epitaxial source / drain region 92 may also have surfaces protruding from their respective surfaces of the multilayer stack 56 and may have end faces.

[0059] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming LDDs, followed by annealing. The source / drain region may have an impurity concentration between approximately 1 × 10¹⁹ atoms / cubic centimeter and approximately 1 × 10²¹ atoms / cubic centimeter. The n-type and / or p-type impurities used for the source / drain region may be any impurities discussed previously. In some embodiments, the epitaxial source / drain region 92 may be doped in situ during growth.

[0060] Due to the epitaxial process in which the epitaxial source / drain regions 92 are formed in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has end faces that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these end faces cause adjacent epitaxial source / drain regions 92 of the same nanofield-effect transistor to merge, as shown in Figure 15A. In other embodiments, as shown in Figure 15C, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. In the embodiments shown in Figures 15A and 15C, a first spacer 81 may be formed to the top surface of the STI hard mask 67 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the STI hard mask 67.

[0061] The epitaxial source / drain region 92 may include one or more layers of semiconductor material. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0062] Figure 15D shows an embodiment in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. As shown in Figure 15D, the epitaxial source / drain region 92 may be formed in contact with the first internal spacer 90 and may extend beyond the sidewalls of the second nanostructure 54 in the n-type region 50N and beyond the sidewalls of the first nanostructure 52 in the p-type region 50P.

[0063] In Figures 16A to 16C, the first interlayer dielectric (ILD) 96 is deposited over the structures shown in Figures 9A, 15B, and 15A, respectively (the fabrication process in Figures 10A to 15D does not change the cross-section shown in Figure 9A). The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed through any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric layer 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The contact etch stop layer 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the covering first interlayer dielectric layer 96.

[0064] In Figures 17A and 17B, a planarization process such as CMP can be performed to make the top surface of the first interlayer dielectric layer 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first interlayer dielectric layer 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric layer 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric layer 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0065] In Figures 18A and 18B, the dummy gate 76 and mask 78 (if present) are removed in one or more etching steps to form the second groove 98, and a portion of the dummy dielectric layer 70 in the second groove 98 is also removed. In some embodiments, the dummy gate 76 and dummy dielectric layer 70 are removed via an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 at a faster rate than the first interlayer dielectric layer 96 or the first spacer 81. Each second groove 98 exposes and / or covers a portion of the nanostructure 55, which acts as a channel region in the subsequently completed nanofield-effect transistor. A portion of the nanostructure 55 acting as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when the dummy gate 76 is etched, the dummy dielectric layer 70 can be used as an etch barrier layer, and then the dummy dielectric layer 70 can be removed after the dummy gate 76 is removed.

[0066] In Figures 19A and 19B, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending into the second groove 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process, such as wet etching, using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, the STI hard mask 67, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises silicon germanium and the second nanostructures 54A to 54C comprise silicon or silicon carbide, tetramethylammonium hydroxide, ammonium hydroxide, etc., can be used to remove the first nanostructure 52 in the n-type region 50N.

[0067] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (such as wet etching) using a selective etchant. Meanwhile, compared to the second nanostructure 54, the first nanostructure 52, the substrate 50, the STI hard mask 67, and the STI region 68 remain relatively unetched. In embodiments where the second nanostructure 54 comprises silicon germanium and the first nanostructure 52 comprises silicon or silicon carbide, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the second nanostructure 54.

[0068] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanofield-effect transistor and the p-type nanofield-effect transistor can have the same material composition, such as silicon, silicon-germanium, etc. Figures 24A, 24B, and 24C show the structure resulting from such embodiments, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and include, for example, silicon.

[0069] In Figures 20A and 20B, a gate dielectric layer 100 and a gate electrode 102 are formed as alternative gates. The gate dielectric layer 100 is compliantly deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first interlayer dielectric layer 96, the contact etch barrier layer 94, the first spacer 81, the STI hard mask 67, and the STI region 68.

[0070] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0071] Gate electrodes 102 are deposited above gate dielectric layer 100 and fill the remaining portion of second groove 98. Gate electrodes 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102 is shown in Figures 20A and 20B, gate electrode 102 may include any number of pads, any number of work function adjustment layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited between adjacent second nanostructures 54 in n-type region 50N and between second nanostructure 54A and substrate 50, and may be deposited between adjacent first nanostructures 52 in p-type region 50P.

[0072] The gate dielectric layers 100 in the n-type region 50N and the p-type region 50P can be formed simultaneously, such that the gate dielectric layers 100 in each region are formed of the same material, and the gate electrodes 102 can be formed simultaneously, such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, the gate dielectric layers 100 in each region can be formed through different processes, such that the gate dielectric layers 100 in each region can be different materials and / or have different numbers of layers, and / or the gate electrodes 102 can be formed through different processes, such that the gate electrodes 102 can be different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0073] After filling the second groove 98, a planarization process (such as CMP) can be performed to remove excess portions of the gate dielectric layer 100 and material of the gate electrode 102, which are located above the gate dielectric layer 100. The remaining portions of the gate electrode 102 and the gate dielectric layer 100 thus form a replacement gate structure for the resulting nanofield-effect transistor. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0074] In Figures 21A to 21C, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 covering it) is recessed such that the recess is formed directly on the gate structure and between the opposing portions of the first spacer 81. The gate shield 104 includes one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) which are filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first interlayer dielectric layer 96. The subsequently formed gate contact (such as contact 114, discussed below with reference to Figures 23A to 23C) penetrates the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0075] As further shown in Figures 21A to 21C, the second interlayer dielectric layer 106 is deposited above the first interlayer dielectric layer 96 and above the gate shield 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable thin film formed via FCVD. In some embodiments, the second interlayer dielectric layer 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0076] In Figures 22A to 22C, a third groove 108 is formed by etching the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch barrier layer 94, and the gate mask 104 to expose the surface of the epitaxial source / drain region 92 and / or the gate structure. The third groove 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, etc.). In some embodiments, the third groove 108 can be etched through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96 using a first etching process, the gate mask 104 can be etched through using a second etching process, and the contact etch barrier layer 94 can be etched through using a third etching process. A mask (e.g., photoresist) can be formed and patterned over the second interlayer dielectric layer 106 to shield portions of the second interlayer dielectric layer 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch; therefore, the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figures 22A through 22C show the third groove 108 exposing the epitaxial source / drain region 92 and gate structure in the same cross section, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the third groove 108, a siliconized region 110 is formed above the epitaxial source / drain region 92. In some embodiments, a silicate region 110 is first formed by depositing a metal (not shown) capable of reacting with a semiconductor material (such as silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicate or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92. A thermal annealing process is then performed to form the silicate region 110. Next, unreacted portions of the deposited metal are removed (e.g., through an etching process). While the silicate region 110 is referred to as a silicate region, it can also be a germanide region or a germanide-siliconized region (e.g., a region comprising both silicate and germanide). In an embodiment, the silicate region 110 comprises titanium silicate and has a thickness ranging from about 2 nm to about 10 nm.

[0077] Next, in Figures 23A to 23C, contacts 112 and 114 (also referred to as contact plugs) are formed in the third groove 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. In some embodiments, for example, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive components (e.g., the gate electrode 102 and / or the silicate region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicate region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0078] Additionally, in this process, the sheet width of the topmost second nanostructure 54C can be smaller than the width of the fin 66. Specifically, various processes used to form the structures shown in Figures 23A to 23C may consume exposed structures, such as the topmost second nanostructure 54C, while other structures like the fin 66 remain protected by the STI region 68 and the STI hard mask 67. In a particular embodiment, the width of the fin 66 minus the sheet width of the topmost second nanostructure 54C can be greater than about 1.5 nm. However, any suitable gap can be used.

[0079] Figures 24A to 24C show cross-sectional views of an apparatus according to some alternative embodiments. Figure 24A shows reference sections A to A' as shown in Figure 1, Figure 24B shows reference sections B to B' as shown in Figure 1, and Figure 24C shows reference sections C to C' as shown in Figure 1. In Figures 24A to 24C, the same reference numerals indicate the same elements formed through the same process as the structures in Figures 23A to 23C. However, in Figures 24A to 24C, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon provides channel regions for the p-type nanofield-effect transistor in the p-type region 50P and the n-type nanofield-effect transistor in the n-type region 50N. For example, the structures shown in Figures 24A to 24C can be formed by simultaneously removing the first nanostructure 52 from the p-type region 50P and the n-type region 50N, depositing a gate dielectric layer 100 and a gate electrode 102P (e.g., a gate electrode suitable for a p-type nanofield-effect transistor) around the second nanostructure 54 in the p-type region 50P, and depositing a gate dielectric layer 100 and a gate electrode 102N (e.g., a gate electrode suitable for an n-type nanofield-effect transistor) around the second nanostructure 54 in the n-type region 50N. In such embodiments, as described above, the material of the epitaxial source / drain region 92 in the n-type region 50N can be different from that in the p-type region 50P.

[0080] Figure 25 shows another embodiment in which the nanostructure 55 is rounded to help reduce load, and a pad 116 is located along the fin 66 and the sidewalls of the nanostructure 55. In the embodiment shown in Figure 25, the process described in Figures 2 through 4 as above is used, and the pad 116 is deposited on the nanostructure 55. In a particular embodiment, the pad 116 comprises a material such as silicon, silicon nitride, silicon oxide, or combinations thereof, which is deposited using deposition processes such as chemical vapor deposition, epitaxial growth, atomic layer deposition, or combinations thereof, or similar deposition. The pad 116 may be deposited to a thickness between about 2 nm and about 3 nm. Once the material of the pad 116 has been deposited, the horizontal portion of the pad 116 above the nanostructure 55 can be removed using, for example, an etching process. However, any suitable material, process, and thickness can be used.

[0081] Figure 26 shows the dashed box 118 marked in Figure 25 and a close-up view after the STI region 68 has been formed. In an embodiment, the STI region 68 may be formed as described above with respect to Figure 4, such as by depositing material for the STI region 68, planarizing the material, and recessing the material to form the STI region 68. However, any suitable material and process can be used.

[0082] Figure 27 shows a close-up of the dashed box 118 after the cylindrical process 57 has rounded the top layer of the nanostructure 55. In an embodiment, the cylindrical process 57 can be performed as described above with reference to Figure 5, such as an anisotropic wet etching process. However, any suitable reduction process can be used.

[0083] However, in this embodiment, in addition to etching away material from the nanostructure 55, the cylindrical process 57 also etches away material from the exposed portion of the pad 116. In some embodiments, the cylindrical process 57 may remove material from a first distance D1 between about 0.5 nm and about 1.5 nm, thereby leaving material in the exposed portion of the pad 116 having a fifth thickness T5 between about 0.5 nm and about 1.5 nm, and also forming a platform (marked as a circular dashed line 119) of the pad 116 adjacent to the STI region 68. However, any suitable amount of material may be removed, including removing all exposed material, and all amounts removed are fully included within the scope of this embodiment.

[0084] Figure 28 shows that once the cylindricalization process 57 is performed, a capping layer 121 can be formed over the exposed portions of the nanostructure 55 and the pad 116. In an embodiment, the capping layer 121 can be a semiconductor material, such as silicon formed using an epitaxial growth process. However, any suitable material and any suitable deposition or growth process can be used.

[0085] However, because the growth process is an epitaxial growth process, the capping layer 121 will grow on the exposed pad 116, but not on the STI region 68, thus exposing most of the STI region 68. However, because the growth process will grow on multiple surfaces of the pad 116 at the plateau (see Figure 27), the capping layer 121 will form a protrusion that extends at least partially above the STI region 68 (marked as a circular dashed line 123). However, any suitable shape can be formed.

[0086] Figure 29 shows that once the capping layer 121 is formed, the first dielectric layer 62 can be deposited. In one embodiment, the first dielectric layer 62 can be formed as described above with respect to Figure 6, for example by depositing a material such as silicon nitride using a deposition process such as chemical vapor deposition or atomic layer deposition. However, any suitable material and method can be used.

[0087] Figure 30 shows that once the first dielectric layer 62 is deposited, the STI hard mask 67 is formed by reducing the material of the first dielectric layer 62. In an embodiment, the STI hard mask 67 is formed using a combination of one or more dry and / or wet etching processes. However, any suitable process or combination of processes can be used.

[0088] Additionally, although not explicitly shown in Figure 30, once the STI hard mask 67 is formed, the remainder of the process discussed above can be used. Specifically, the first nanostructure 52 is formed, the second nanostructure 54 is formed, and the gate electrode 102 (along with other structures) is formed. However, any suitable structure and any suitable process can be used.

[0089] By using an STI hard mask 67 with a pad layer 116 and a cap layer 121, the thickness loading between dense regions (such as n-type region 50N) and non-dense regions (such as p-type region 50P) can be reduced and improved. In a particular embodiment, for an oxide definition space (OD space) between approximately 35 nm and 83 nm, the thickness loading can be improved from 7.9 nm to 6.6 nm or less, achieving an overall improvement of 1.3 nm.

[0090] Therefore, by utilizing the embodiments described herein, a fin structure that facilitates filling gaps can be formed for the nanostructure 55 to help improve (e.g., reduce) the thickness load of the STI hard mask 67 formed on the STI region 68 between the dense and non-dense regions, thereby making the thickness of the STI hard mask 67 forming the bottom in the dense and non-dense regions more uniform. Furthermore, by improving the thickness load, the mesa height of the STI hard mask 67 can also be reduced. A reduction in mesa height can further improve the gain RO%.

[0091] In one embodiment, a method of manufacturing a semiconductor device includes: forming a multilayer stack on a semiconductor substrate, patterning the multilayer stack into a plurality of fins, the plurality of fins being located in a first region and a second region, the density of the first region being higher than that of the second region, rounding a plurality of corners of the plurality of fins, depositing a first dielectric layer between the plurality of fins, removing a portion of the first dielectric layer to form a first mask, and forming a gate structure on the first mask.

[0092] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding a plurality of corners can remove about 0.5 nm to about 1.5 nm of material from at least one of the plurality of corners.

[0093] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding multiple edges and corners can remove about 1 nm to about 2 nm of material from the top surface of at least one of multiple fins.

[0094] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding multiple corners can remove material from a silicon pad layer, the silicon pad layer being in physical contact with one of the multiple fins.

[0095] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding multiple corners can remove about 0.5 nm to about 1.5 nm from the silicon pad layer.

[0096] In some embodiments, the method of manufacturing the semiconductor device further includes growing a capping layer on the exposed surfaces of the silicon pad layer and the plurality of fins.

[0097] In some embodiments, regarding the method of manufacturing a semiconductor device, the growth of the capping layer forms a protrusion that extends over an isolation region.

[0098] In another embodiment, the method of manufacturing a semiconductor device includes: forming an isolation region between a plurality of fins on a semiconductor substrate, each of the plurality of fins including a plurality of alternating material layers; depositing a first dielectric material on the isolation region, the first dielectric material having a first thickness in a first region and a second thickness in a second region, the first thickness being different from the second thickness; and reducing the first thickness to a third thickness and reducing the second thickness to a fourth thickness.

[0099] In some embodiments, the method of manufacturing the semiconductor device further includes rounding a plurality of corners between the operations of forming an isolation region and depositing a first dielectric material.

[0100] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding a plurality of corners can remove about 0.5 nm to about 1.5 nm of material from at least one of the plurality of corners.

[0101] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding multiple corners may further remove material from a silicon pad layer adjacent to one of a plurality of fins.

[0102] In some embodiments, regarding the method of manufacturing a semiconductor device, the operation of rounding multiple corners can remove a silicon pad layer of about 0.5 nm to about 1.5 nm.

[0103] In some embodiments, the method of manufacturing the semiconductor device further includes forming a silicon capping layer prior to depositing a first dielectric material, wherein the silicon capping layer includes a protrusion extending over the isolation region.

[0104] In some embodiments, regarding the method of manufacturing a semiconductor device, wherein: after the reduction operation, a load between the first region and the second region is greater than zero and not greater than 6.6 nm.

[0105] In another embodiment, the semiconductor device includes: a metal gate, an isolation region, and a masking layer. The metal gate is on a semiconductor substrate and surrounds at least a portion of a plurality of nanostructures extending between a first source / drain region and a second source / drain region; the isolation region is located between the metal gate and the semiconductor substrate; and the masking layer is located between the metal gate and the isolation region, the masking layer including: a first portion and a second portion. The first portion has a first thickness; and the second portion has a second thickness different from the first thickness.

[0106] In some embodiments, regarding the semiconductor device, a first portion is located in a first region and a second portion is located in a second region, wherein the density of a plurality of nanostructures in the first region is greater than the density of a plurality of nanostructures in the second region.

[0107] In some embodiments, with respect to the semiconductor device, one of the plurality of nanostructures is located above a first fin, and a first width of the first fin is greater than a second width of the plurality of nanostructures.

[0108] In some embodiments, regarding the semiconductor device, the difference between the first width and the second width is greater than 1.5 nm.

[0109] In some embodiments, regarding the semiconductor device, the masking layer comprises silicon nitride.

[0110] In some embodiments, regarding the semiconductor device, a non-zero load between the first portion and the second portion is less than or equal to 6.6 nm.

[0111] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that they can readily use the content of this invention as the basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and they can make various changes, substitutions, and modifications to this document without departing from the spirit and scope of the invention. [Simplified Explanation of the Diagram]

[0007] A better understanding of the various aspects of the present invention can be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 shows an example of a nano-structured field-effect transistor (nano-FET) according to certain embodiments in a three-dimensional view. Figures 2, 3, 4, 5, 6, 7, 8, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 14C, 15A, 15B, 15C, 15D, 16A, 16B, 16 ...6C, 15B, 15C, 15B, 15C, 15C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, 16C, Figures 16C, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, and 23C are cross-sectional views of intermediate stages in the fabrication of nano-field-effect transistors according to certain embodiments. Figures 24A, 24B, and 24C are cross-sectional views of nano-field-effect transistors according to certain embodiments. Figures 25, 26, 27, 28, 29, and 30 show embodiments with padding according to certain embodiments.

Claims

1. A method for manufacturing a semiconductor device, comprising: A multilayer stack is formed on a semiconductor substrate; The multilayer stack is patterned into multiple fins located in a first region and a second region, the density of which is higher in the first region than in the second region; multiple edges of the topmost nanostructure of each of the fins are rounded; a first dielectric layer is deposited between the fins; a portion of the first dielectric layer is removed to form a first mask; and a gate structure is formed on the first mask.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the operation of rounding the equal corners can remove about 0.5 nm to about 1.5 nm of material from at least one of the equal corners.

3. The method of manufacturing a semiconductor device as described in claim 2, wherein the operation of rounding the edges and corners can remove about 1 nm to about 2 nm from the top surface of at least one of the topmost nanostructures of the fins.

4. The method of manufacturing a semiconductor device as claimed in claim 3, wherein the operation of rounding the edges and corners can remove material from a silicon pad layer that is in physical contact with one of the fins.

5. The method of manufacturing a semiconductor device as described in claim 4, wherein the operation of rounding the edges and corners can remove about 0.5 nm to about 1.5 nm from the silicon pad layer.

6. The method of manufacturing a semiconductor device as described in claim 5 further includes: A capping layer is grown on the exposed surfaces of the silica pad and the fins.

7. A method for manufacturing a semiconductor device, comprising: An isolation region is formed between a plurality of fins on a semiconductor substrate, each of the fins comprising a plurality of alternating material layers; A first dielectric material is deposited on the isolation region, the first dielectric material having a first thickness in a first region and a second thickness in a second region, the first thickness being different from the second thickness; between the operations of forming the isolation region and depositing the first dielectric material, a plurality of edges and corners of a topmost material layer of each of the fins are rounded; the first thickness is reduced to a third thickness, the second thickness is reduced to a fourth thickness; and a gate structure is formed on the first dielectric material.

8. A semiconductor device, comprising: A metal gate on a semiconductor substrate, the metal gate surrounding at least a portion of a plurality of nanostructures extending between a first source / drain region and a second source / drain region and forming a plurality of stacks over a plurality of fins, wherein the topmost nanostructure of one of the nanostructures in each of the stacks has rounded corners; an isolation region located between the metal gate and the semiconductor substrate; and a shielding layer located between the metal gate and the isolation region, the shielding layer comprising: a first portion having a first thickness; And a second part having a second thickness different from the first thickness.

9. The semiconductor device as claimed in claim 8, wherein the first portion is located in a first region and the second portion is located in a second region, wherein the density of the nanostructures in the first region is greater than the density of the nanostructures in the second region.

10. The semiconductor device of claim 8, wherein a first width of a first fin of the fins is greater than a second width of the topmost nanostructure of a first stack of the fins above the first fin.

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