Nonvolatile memory device and method for operating nonvolatile memory cells

Abstract

To program MRAM memory cells, current must flow from the corresponding bit line of the memory cell to its corresponding word line or from the word line to the bit line. To achieve this, the bit line and word line decoders must be able to supply current (when the line is driven positive) and draw current (when the line is pulled negative) to account for the bipolar nature of the memory cell. Therefore, the decoders must be bipolar. NMOS devices are used for the negative selection switches, and PMOS switches are used for the positive selection switches. To reduce circuit wiring area and routing, the negative and positive selection switches are grouped separately, with a subgroup of the positive selection switches located between subgroups of the negative selection switches, and vice versa. The connection of the decoder switches is routed to a central wiring area for connection to the control lines of the crosspoint array.

Description

Technical Field

[0001] This invention relates to a bipolar decoder for non-volatile memory. Prior Technology

[0002] Memory systems are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery pack).

[0003] One example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use electron charges to store data. Typically, MRAM comprises a large number of magnetic memory cells formed on a semiconductor substrate, each memory cell representing at least one bit of data. A bit of data is written to the memory cell by changing the magnetization direction of the magnetic elements within the memory cell, and a bit is read by measuring the resistance of the memory cell (low resistance generally represents a "0" bit and high resistance generally represents a "1" bit). As used herein, the magnetization direction is the direction of the magnetic moment orientation.

[0004] Some non-volatile memory arrays are configured with cross-point configurations, where word lines extend perpendicularly to bit lines and memory cells are formed at their intersections. Some cross-point memory arrays have two or more stories or levels of memory cells.

[0005] Read / write circuitry is used to read data from and write data to non-volatile memory cells. Data can be read by sensing the current or voltage at a sense node as current flows through the selected memory cell. A sense amplifier can be provided to perform the sensing. The sense amplifier and / or other read / write circuitry can occupy a significant area on the memory die. Efficient design can reduce the area occupied by the sense amplifier and / or other circuitry. Summary of the Invention

[0006] To program an MRAM memory cell, current must flow from the corresponding bit line of the memory cell to its corresponding word line or from the word line to the bit line. To achieve this, the bit line and word line decoders must be able to supply current (when the line is driven positive) and draw current (when the line is pulled negative) to account for the bipolar nature of the memory cell. Therefore, these decoders must be bipolar. NMOS devices are used for the negative selection switches, and PMOS switches are used for the positive selection switches. To reduce circuit wiring area and routing, the negative and positive selection switches are grouped separately, with a subgroup of the positive selection switches located between subgroups of the negative selection switches, and vice versa. The connection route of these decoder switches is routed to a central wiring area for connection to the control lines of the crosspoint array. Simple Explanation of the Diagram

[0007] Components with similar numbers are referenced to common components in different diagrams. [Figure 1] is a block diagram of an embodiment of a memory system connected to a host computer. [Figure 2] is a block diagram of an embodiment of memory packaging. [Figure 3] is a block diagram of one embodiment of a memory chip. [Figure 4] is a block diagram of one embodiment of an integrated memory assembly. [Figure 5] shows an example of a sense amplifier. [Figure 6] shows an example of a memory access operation (read operation). [Figure 7A] An embodiment of a memory array forming a cross-point architecture is depicted in oblique view. [Figure 7B] and [Figure 7C] respectively present the side view and top view of the intersection structure in Figure 7A. [Figure 7D] An embodiment of a second-order memory array forming a crosspoint architecture is depicted in oblique view. [Figure 8] illustrates an embodiment of the structure of an MRAM memory cell. [Figure 9] illustrates in more detail an embodiment of an MRAM memory cell design when implemented as a cross-point array. [Figure 10A] and [Figure 10B] illustrate the writing of MRAM memory cells using a spin torque transfer (STT) mechanism. [Figure 11] illustrates an embodiment of a threshold switching selector in an MRAM memory array with a crosspoint architecture. Figures 12A and 12B illustrate reading from an MRAM cell. Figures 13A and 13B illustrate the current flow during read operations in different layers of a multilayer nonvolatile memory structure. [Figures 14A] to [Figures 14B] illustrate examples of different sense amplifiers used for different layers. Figures 15A to 15C illustrate various configurations of the present technology, including a sense amplifier and control circuitry configured to enable the sense amplifier to read non-volatile memory cells in different layers. [Figure 16] illustrates an example of a memory die including a common sense amplifier. [Figure 17] illustrates a portion of a data storage system according to an example of the present technology. [Figure 18A] illustrates an example of a method that connects a sense amplifier to a bit line and to a word line based on the layer in which the non-volatile memory cell is located. [Figure 18B] illustrates an example that uses the same sensing amplifier to sense non-volatile memory cells in different layers. [Figure 19A] and [Figure 19B] present an embodiment of a bipolar decoder, wherein the two figures show different parts of the circuit system and together constitute an embodiment of the circuit. [Figure 20] illustrates an embodiment of a triple-well transistor, such as a decoder switch that can be used in Figures 19A and 19B. [Figure 21] is an embodiment of the layout of the decoder in Figures 19A and 19B. [Figure 22] and [Figure 23] illustrate an embodiment of the wiring for the location of array vias connecting the decoder circuit, the associated crosspoint array of word lines, and the bit lines. [Figure 24] is a side view of an embodiment of different decoder blocks of Figure 21 and how such decoder blocks are connected to the metal layer of Figure 22. [Figure 25] Repeat the decoder of Figure 21, but show a portion of the route from Figure 24 in a top view. [Figure 26] shows details of the lower left quadrant of Figure 25 used to illustrate the route. [Figure 27] is a flowchart of an embodiment for forming a memory device including the decoder structure of Figures 19A to 26. Implementation

[0008] In a memory array with a crosspoint type architecture, a first set of conductive lines travels across the surface of the substrate (e.g., word lines or WL), and a second set of conductive lines travels above the substrate in a direction perpendicular to the first set of conductive lines (e.g., bit lines or BL). The memory cell is located at the crosspoint junction of the two sets of conductive lines. Embodiments of the memory cell may include programmable resistive elements (such as MRAM elements) that can be connected in series with a selector switch (selector) in the crosspoint memory structure.

[0009] In some memory structures, including cross-point MRAM memory structures, memory cells can be formed in two or more layers (e.g., a first layer formed between a first word line layer and a bit line layer, and a second layer formed between a bit line layer and a second word line layer). Accessing memory cells in such structures can be challenging. For example, when the current direction is the same in both layers (e.g., current flows upward through the memory cell), current flows from the word line to the bit line in the first layer and from the bit line to the word line in the second layer. This may require dedicated circuitry (e.g., sense amplifiers) for each layer.

[0010] To program MRAM memory cells (i.e., change the state from logic 1 to logic 0 or vice versa), current must flow from the corresponding bit line of the memory cell to its corresponding word line, or vice versa. To achieve this, the bit line and word line decoder must be able to supply current (when the line is driven positive) and draw current (when the line is pulled negative) to account for the bipolar nature of the memory cell. Therefore, the decoder must be bipolar. For the negative selection switch, an NMOS device is used, and for the positive selection switch, a PMOS switch is used. To reduce circuit wiring area and routing, in the bipolar decoder embodiment, the negative and positive selection switches are grouped separately, with subgroups of positive selection switches located between subgroups of negative selection switches, and vice versa. The decoder switch connections are routed to a central wiring area for connection to the control lines of the crosspoint array.

[0011] Figure 1 is a block diagram of one embodiment of a memory system 100 connected to host 120. The memory system 100 may implement the techniques for managing error rates presented herein. Many different types of memory systems may be used with the techniques presented herein. Example memory systems include solid-state drives ("SSDs"), memory cards (including dual in-line memory modules (DIMMs) for DRAM replacement), and embedded memory devices; however, other types of memory systems may also be used.

[0012] The memory system 100 of Figure 1 includes a controller 102, non-volatile memory 104 for storing data, and local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 includes a front-end processor (FEP) circuitry 110 and one or more back-end processor (BEP) circuitry 112. In one embodiment, the FEP circuitry 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuitry 112 is implemented on a separate ASIC. In other embodiments, a unified controller ASIC can combine both front-end and back-end functions. Implementing the ASICs for each of the BEP circuitry 112 and the FEP circuitry 110 on the same semiconductor allows the controller 102 to be fabricated as a system-on-a-chip (SoC). Both the FEP circuitry 110 and the BEP circuitry 112 include their own processors. In one embodiment, FEP circuit 110 and BEP circuit 112 operate in a master-slave configuration, where FEP circuit 110 is the master circuit and each BEP circuit 112 is a slave circuit. For example, FEP circuit 110 implements a Flash Translation Layer (FTL) or performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and a Media Management Layer (MLL) for the overall operation of SSDs (or other non-volatile storage systems). When requested by FEP circuit 110, BEP circuit 112 manages memory operations within the memory package / die. For example, BEP circuit 112 can perform read, erase, and programming operations. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels requested by FEP circuit 110, perform error correction (ECC), and control the dual-state thixotropic interface to the memory package. In one embodiment, each BEP circuit 112 is responsible for its own memory package group.

[0013] In one embodiment, the non-volatile memory 104 comprises a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, the controller 102 is connected to one or more non-volatile memory chips. In one embodiment, each memory chip in the memory package 104 utilizes inverse NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other types of memory, such as storage class memory (SCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In other embodiments, a BEP or FEP may be included on the memory chip.

[0014] Controller 102 communicates with host 120 via an interface 130 implementing protocols such as, for example, Fast NVM (NVM Express, NVMe) or Compute Express Link (CXL) via PCI Express (PCIe) or using a JEDEC standard Double Data Rate or Low-Power Double Data Rate (LPDDR) interface (such as DDR5 or LPDDR5). To work with memory system 100, host 120 includes host processor 122, host memory 124, and a PCIe interface 126 connected along bus 128. Host memory 124 is the host's physical memory and may be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host 120.

[0015] Figure 2 is a block diagram of one embodiment of a memory package 104 including a plurality of memory chips 292 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a dual-state thixotropic interface 296 for communication with a TM interface of BEP circuitry. In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory chips. In one embodiment, each memory package includes eight or 16 memory chips; however, other numbers of memory chips may also be implemented. In another embodiment, the dual-state thixotropic interface is replaced by DDR or LPDDR of the JEDEC standard, with or without variations (such as relaxed time-sets or smaller page sizes). The techniques described herein are not limited to any particular number of memory chips.

[0016] Figure 3 is a block diagram depicting an example of a memory system 500 that can implement the techniques described herein. The memory system 500 includes a memory array 502 that may include any of the memory cells described below. The array terminal lines of the memory array 502 include word lines(s) organized in columns and bit lines(s) organized in rows. However, other orientations may also be implemented. The memory system 500 includes a column control circuitry 520 connected to the individual word lines of the memory array 502 via line 508. The column control circuitry 520 receives column address signals and one or more various control signals from system control logic 560, and generally includes circuitry such as a column decoder 522 and a word line (WL) driver 524 for both read and write operations.

[0017] The memory system 500 also includes a row control circuitry system 510, whose inputs / outputs 506 are connected to individual bit lines of the memory array 502. Although only a single block is displayed for the memory array 502, the memory die may include multiple arrays or "tiles" that can be accessed individually. The row control circuitry system 510 receives row address signals and one or more various control signals from the system control logic 560, and generally includes circuitry such as a row decoder 512, a bit line (BL) driver 514, and read / write (R / W) circuitry 516 (which may include, for example, a sense amplifier for reading).

[0018] System control logic 560 receives data and commands from the host and provides output data and status to the host. In other embodiments, system control logic 560 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host. In some embodiments, system control logic 560 may include a state machine that provides grain-level control for memory operation. In one embodiment, the state machine may be software-programmable. In other embodiments, the state machine is implemented entirely in hardware (e.g., circuitry) without using software. In another embodiment, the state machine is replaced by a microcontroller, which may be on the memory chip or off-chip. System control logic 560 may also include a power control module that controls the power and voltage supplied to the columns and rows of memory array 502 during memory operation and may include charge pump and regulator circuitry for generating regulated voltages. System control logic 560 may include one or more state machines, registers, and other control logic for controlling the operation of memory system 500.

[0019] In some embodiments, all components of the memory system 500 (including system control logic 560) may be formed as part of a single die (e.g., memory die 292 of FIG. 2). In other embodiments, some or all of the system control logic 560 may be formed on different dies.

[0020] For the purposes of this document, the phrase "one or more control circuits" may include a controller, state machine, microcontroller, and / or other control circuit system as represented by system control logic 560, and / or other similar circuits for controlling non-volatile memory.

[0021] In one embodiment, memory structure 502 comprises a three-dimensional memory array of non-volatile memory cells, wherein multiple memory layers are formed on a single substrate (such as a wafer). The memory structure may comprise any type of non-volatile memory, such non-volatile memory systems being monolithically formed in one or more solid layers of memory cells having active regions disposed above a silicon (or other type) substrate. In another embodiment, memory structure 502 comprises a two-dimensional memory array of non-volatile memory cells.

[0022] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to any specific instance. Many different types of memory array architectures or memory technologies can be used to form memory structure 502. Examples of suitable technologies for the memory cells of memory structure 502 include NAND flash memory, ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, Spin-orbit MRAM, Spin-orbit MRAM), FeRAM, phase-change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architecture of memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0023] One example of a ReRAM crosspoint memory includes a reversible resistance-switching element configured in a crosspoint array accessed via X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes (one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper)) having a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programmability threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element has a wide range of programmability thresholds over a temperature range.

[0024] Another example is magnetoresistive random access memory (MRAM), which uses magnetic storage elements to store data. The element is formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of the two layers is set as a permanent magnet of a specific polarity; the magnetization of the other layer can be changed to match the magnetization of an external field storing the memory. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below it. An induced magnetic field is generated when current passes through them. MRAM-based memory embodiments will be discussed in more detail below.

[0025] Phase change memory (PCM) utilizes the unique behavior of sulfide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by simply changing the coordination state of germanium atoms using programmable current pulses. It should be noted that the use of "pulse" in this document does not require a square pulse, but rather includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. These memory elements (or bits) within individual selectable memory cells may include further series elements of selectors (such as bidirectional limit switches or metal-insulator substrates).

[0026] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory construction, or material composition, but encompass a wide range of related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0027] The components in Figure 3 can be divided into two parts: the memory structure 502 containing the memory cells and the peripheral circuitry system including all other components. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die delivered to the memory system 500 of the memory structure 502; however, this reduces the area of ​​the memory die available for the peripheral circuitry system. This can place significant limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 560, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die for the memory system 500 is the amount of area dedicated to the memory structure 502 versus the amount of area dedicated to the peripheral circuitry system.

[0028] Another reason for the inconsistency between memory structure 502 and its peripheral circuitry is the processing involved in forming these regions, as these regions often involve different processing techniques and trade-offs between different techniques on a single die. For example, when memory structure 502 is a NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For instance, components in system control logic 560 (such as sense amplifier circuitry, charge pumps, logic elements in the state machine, and other peripheral circuitry) typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0029] To mitigate these limitations, the embodiments described below can separate the elements of FIG3 onto separately formed dies that are subsequently bonded together. More specifically, the memory structure 502 can be formed on a single die, and some or all of the peripheral circuitry elements, including one or more control circuits, can be formed on separate dies. For example, the memory die can be formed solely from memory elements (such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or arrays of memory cells of other memory types). Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to separate dies. This allows each memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without concern for the CMOS elements now moved to separate peripheral circuitry dies that can be optimized for CMOS processing. This allows for more space to be used for peripheral components, which can now be combined with the additional ability that was previously limited by the margin of maintaining identical chips in the memory cell array. Two chips can then be bonded together in a bonded multi-chip memory circuit, where an array on one chip is connected to peripheral components on the other memory circuit. While the following focuses on a bonded memory circuit with one memory chip and one peripheral circuit system chip, other embodiments may use more chips, such as two memory chips and one peripheral circuit system chip.

[0030] Figure 4 shows an alternative configuration to the arrangement of Figure 3, which can be implemented using wafer-to-wafer bonding to provide bonded die pairs for integrated memory assembly 600. Figure 4 shows an example of a peripheral circuitry system (including control circuitry) coupled to the peripheral circuitry of the memory structure 602 formed in memory die 601 or formed in control die 611. As with 502 in Figure 3, memory die 601 may include multiple independently accessible arrays or "tiles". Common components are labeled similarly to those in Figure 3 (e.g., 502 is now 602, 510 is now 610, and so on). System control logic 660, column control circuitry system 620, and row control circuitry system 610 (which may be formed by CMOS programming) are visible in control die 611. Additional components (such as functionality from controller 102) may also be moved to control die 611. System control logic 660, column control circuitry 620, and row control circuitry 610 can be formed using a common program (e.g., a CMOS program), so that adding components and functionality more commonly found on memory controller 102 may require few or no additional programming steps (i.e., the same programming steps used to manufacture controller 102 can also be used to manufacture system control logic 660, column control circuitry 620, and row control circuitry 610). Therefore, while moving such circuitry from a memory die such as memory system 500 can reduce the number of steps required to manufacture that die, adding such circuitry to a die such as control die 611 may require no additional programming steps.

[0031] Figure 4 shows that the row control circuitry 610 on the control die 611 is coupled to the memory structure 602 on the memory die 601 via an electrical path 606. For example, the electrical path 606 can provide electrical connections between the row decoder 612, the driver circuitry 614, and the R / W circuitry 616 and the bit lines of the memory structure 602. The electrical path can extend from the row control circuitry 610 in the control die 611 through corresponding pads on the control die 611 bonded to the memory die 601, these corresponding pads connecting to the bit lines of the memory structure 602. Each bit line of the memory structure 602 can have a corresponding electrical path connected to the row control circuitry 610 in the electrical path 606 (including a pair of bonded pads). Similarly, the column control circuitry 620, including the column decoder 622, the array driver 624, and the block select 626, is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 611 and the memory die 601.

[0032] Compared to Figure 3, the on-chip control circuitry in Figure 4 can be more versatile than the capabilities typically found in memory controller 102 and some CPU capabilities, but also includes additive functionality specific to certain applications within its logic elements.

[0033] In the following text, the system control logic 560 / 660, row control circuitry 510 / 610, column control circuitry 520 / 620, and / or controller 102 (or equivalent functional circuitry), in combination with all or subgroups of other circuitry depicted on the control die 611 in Figure 3 or Figure 4, may be considered as part of one or more control circuitry that performs the functions described herein. Control circuitry may consist only of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0034] In the following discussion, the memory arrays 502 / 602 of Figures 3 and 4 will be discussed primarily within the context of crosspoint architecture, although much of this discussion is applicable more generally. The following discussion will focus primarily on embodiments based on crosspoint architecture using MRAM memory cells, although much of this discussion is applicable more generally to non-volatile memory cells.

[0035] Figure 5 shows an example of a sense amplifier 570 (e.g., in read / write circuitry 516 or 616). Figure 5 shows a sense node 572 that can be connected to a selected non-volatile memory cell (NVMC) via a selected bit line selectable by line decoder 512 or 612. A current mirror 574 connected to the supply voltage VNN controls the current through the selected NNVMC during sensing. The sense amplifier 570 includes a comparator 576 that receives a voltage from the sense node 572 and compares it to a reference voltage (Vref) from a reference voltage source 578. For example, the comparator 576 may generate a digital output (logic 1 or 0) depending on whether the voltage at the sense node 572 is higher or lower than the reference voltage. The digital output from the comparator 576 is latched in a data latch 580 and serves as sense data output.

[0036] Figure 6 illustrates a read operation for a selected memory cell 680 located at the intersection of a selected word line 682 and a selected bit line 684 (e.g., in structure 502 / 602). A word line driver 542 generates a first supply voltage VPP (e.g., a positive voltage), which is then applied to the selected word line 682 by a column decoder 522. The column decoder 512 selects the selected bit line 684 and connects it to a sensing node 572, where a sensing amplifier 570 senses a voltage as current flows through a current mirror that receives a second supply voltage VNN (e.g., a negative voltage) from the bit line driver 514. The sensing amplifier 570 senses the state of the selected memory cell 680 based on the voltage at the sensing node 572 as a predetermined current from the current mirror 574 flows through the selected memory cell 680.

[0037] Figure 7A depicts an embodiment of a memory array forming a crosspoint architecture in an oblique view. The memory arrays 502 / 602 of Figure 7A are examples of embodiments of memory array 502 in Figure 3 or memory array 602 in Figure 4, wherein the memory die may include multiple such array structures. Bit lines BL1 to BL5 are arranged in a first direction (e.g., indicated as the "bit line direction" traveling into the page) relative to the substrate below the die, and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction (e.g., the "word line direction") (and across the page). Figure 7A is an example of a horizontal crosspoint structure, wherein both word lines WL1 to WL5 and BL1 to BL5 travel in a horizontal direction relative to the substrate, and memory cells (both indicated by 701) are oriented such that current flows through the memory cells (such as shown as I cells) in a vertical direction. In memory arrays with additional memory cell layers, such as those related to Figure 7D discussed below, there will be corresponding layers of additional bit lines and word lines.

[0038] As depicted in Figure 7A, memory arrays 502 / 602 include a plurality of memory cells 701. Memory cells 701 may include rewritable memory cells, such as those implemented using ReRAM, MRAM, PCM, FeRAM, or other materials with programmable resistors. Current in the memory cells of the first memory layer is shown to flow upwards, as indicated by the arrow I cell, but current can flow in either direction, as discussed in more detail below.

[0039] Figures 7B and 7C present the side and top views, respectively, of the intersection structure in Figure 7A. The side view of Figure 7B shows a bottom conductor (or word line) WL1 and top conductors (or bit lines) BL1 to BLn. The intersections between the top and bottom conductors are MRAM memory cells; however, PCM, FeRAM, ReRAM, or other technologies can be used. Figure 7C is a top view illustrating the intersection structure of M bottom conductors WL1 to WLM and N top conductors BL1 to BLN. In a binary embodiment, the MRAM cell at each intersection can be programmed into one of two resistance states: high and low. Further details of embodiments of MRAM memory cell designs and techniques for programming such cells are given below.

[0040] Figure 7A illustrates an embodiment of a single-layer (story) with word lines and bit lines, where MRAM or other memory cells are located at the intersection of two sets of conductive lines. To increase the storage density of memory chips, multiple layers (story) of such memory cells and conductive lines can be formed. A two-layer (story) example is illustrated in Figure 7D.

[0041] Figure 7D depicts an embodiment of a portion of a two-tier (two-layer) memory array forming a crossover architecture in an oblique view. As shown in Figure 7A, Figure 7D shows the first layer 718 (first layer) of memory cells 701 at the crossover points of word lines WL1,1 to WL1,4 and bit lines BL1 to BL5 of array 502 / 602. A second layer (second layer) 720 of memory cells is formed above bit lines BL1 to BL5 and between these bit lines and a second set of word lines WL2,1 to WL2,4. Although Figure 7D shows two layers (layers) 718 and 720 of memory cells, the structure can extend upwards through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array in Figure 7D can be biased for read or programmable operations, allowing current in each layer to flow from the word line layer to the bit line layer or other surrounding paths.

[0042] The use of a cross-point architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be resistive memory cells, where data values ​​are encoded into different resistance levels. Depending on the embodiment, the memory cells can be binary values ​​having a low-resistance state or a high-resistance state, or can be multi-level cells (MLCs) with additional resistance between the low-resistance and high-resistance states. The cross-point array described herein can be used as memory die 292 of FIG4, replacing local memory 106, or both.

[0043] Figure 8 illustrates one embodiment of the structure of an MRAM memory cell. The voltage applied across the memory cell (between the corresponding word line and bit line of the memory cell) is represented as a voltage source Vapp813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by, in this example, a separating or tunneling layer of magnesium oxide (MgO) 805, and a top electrode 811 subsequently separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 803 is fixed, and in the example of Figure 15, it is oriented upwards. Reference layer 803 is also known as the fixed layer or pinned layer.

[0044] Data is written to MRAM memory cells by programming the free layer 807 to have the same or opposite orientation. The reference layer 803 is formed such that it retains its orientation when the free layer 807 is programmed. The reference layer 803 can have a more complex design, including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the diagrams and discussion, which focus only on the fixed magnetic layer of the tunneling magnetoresistance in the main responsible cell.

[0045] Figure 9 illustrates in more detail one embodiment of an MRAM memory cell design when implemented using a cross-point array. When placed in a cross-point array, the top and bottom electrodes of the MRAM memory cell are connected to two layers of adjacent conductor layers of the array, such as the top and bottom conductors of a second-order or double-layer array. In the embodiment shown here, the bottom electrode is the word line 901 of the memory cell, and the top electrode is the bit line 911 of the memory cell; however, in some embodiments, this can be reversed by reversing the orientation of the memory element. Between the word line 901 and the bit line 911 are a reference layer 903 and a free layer 907, which are again separated by a MgO barrier 905. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. Pads 921 and 923 are attached to either side of the memory cell structure. These pads may be part of the same structure, but are shown as separate parts in the cross section of FIG9. Some of the filler materials 925 and 927 used to fill the originally empty areas of the intersection structure are shown on either side of pads 921 and 923.

[0046] Regarding the free layer 907, embodiments include a CoFe or CoFeB alloy having a thickness of about 1 to 2 nm, wherein an Ir layer may be intercalated in the free layer adjacent to the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments of the reference layer 903 may include a bilayer of CoFeB and CoPt multilayers coupled to Ir or Ru spacers 902. An MgO cap 908 is optional but may be used to increase the anisotropy of the free layer 907. The conductive spacers may be conductive metals such as Ta, W, Ru, CN, TiN, and TaN.

[0047] To sense the state of data stored in MRAM, a voltage, represented by Vapp, is applied across the memory cell to determine its resistance state. To read an MRAM memory cell, the voltage difference Vapp can be applied in either direction; however, MRAM memory cells are directional, and therefore, in some cases, reading in one direction takes precedence over reading in another. For example, the optimal current amplitude for writing bits to AP (high resistance state, HRS) can be 50% or more larger than the current amplitude for writing to P (low resistance state), so a lower bit error rate (read interference) is less likely when reading from AP (2AP). Some of these situations and the resulting read directionality are discussed below. The directionality of the bias voltage is particularly relevant in some embodiments of MRAM memory cell programming.

[0048] The following discussion will primarily focus on MRAM memory cells with vertical spin-transfer torque (STT), where the free layers 807 / 907 in Figures 8 and 9 contain switchable magnetization directions perpendicular to the plane of the free layers. Spin-transfer torque ("STT") is the effect of modifying the orientation of the magnetic layer in the magnetic tunneling interface using spin-polarized current. Charge carriers (such as electrons) have a known property of spin, which is a small amount of angular momentum inherent to the carrier. Current is typically non-polarized (e.g., composed of 50% high-spin electrons and 50% low-spin electrons). Spin-polarized current is the current of more electrons with either spin (e.g., mostly high-spin electrons or mostly low-spin electrons). Spin-polarized current is generated by passing current through a thick magnetic layer (reference layer). If this spin-polarized current is directed into a second magnetic layer (free layer), angular momentum is transferred to this second magnetic layer, changing the magnetization direction of the second magnetic layer. This is called spin-transfer torque. Figures 10A and 10B illustrate the use of spin-transfer torque to program or write MRAM memory. Spin-transfer torque magnetic random access memory (STT MRAM) offers advantages over MRAM variations (such as bi-state thixotropic MRAM) in terms of lower power consumption and better scalability. Compared to other MRAM implementations, STT switching technology requires relatively low power, effectively eliminates the problem of adjacent bit interference, and has more favorable scaling for higher memory cell densities (reducing MRAM cell size). The latter is also advantageous for STT MRAM, where the magnetization systems of the free layer and reference layer are perpendicular to the film plane rather than in-plane oriented.

[0049] Since the STT phenomenon is more easily described in terms of electronic behavior, the discussion in Figures 10A and 10B, and others, is given in the terminology of electronic current, where the direction of the write current is defined as the direction of electron flow. Therefore, the term write current in Figures 10A and 10B refers to electronic current. Because electrons are negatively charged, the electronic current will be in the opposite direction to the conventionally defined current, causing the electronic current to flow from a lower voltage level to a higher voltage level, rather than the conventional current flow from a higher voltage level to a lower voltage level.

[0050] Figures 10A and 10B illustrate writing to and reading from MRAM memory cells using the STT mechanism. These figures depict a simplified schematic representation of an example of STT switching of MRAM memory cell 1000, where the magnetization of both the reference layer and the free layer is in the vertical direction. Memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002, which comprises an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 serving as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and its magnetization direction is switchable. The lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and its magnetization direction is not switchable. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. Data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. In this regard, electrical conductors 1006 / 1008 attached to the memory cell 1000 are used to read MRAM data. By design, both the parallel and antiparallel configurations remain stable in the quiescent state and / or during read operations (with sufficiently low read current).

[0051] For both the reference layer RL 1012 and the free layer FL 1010, the magnetization direction is in the vertical direction (that is, perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). Figures 10A and 10B show the magnetization direction of the reference layer RL 1012 as upward and the magnetization direction of the free layer FL 1010, which is also perpendicular to the plane, as being switchable between upward and downward.

[0052] In one embodiment, the tunneling barrier 1014 is made of magnesium oxide (MgO); however, other materials may also be used. The free layer 1010 is a ferromagnetic metal capable of changing / switching its magnetization direction. Multiple layers based on transition metals (such as Co, Fe, and their alloys) can be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be made of many different types of materials, including (but not limited to) multiple layers of cobalt and platinum and / or an alloy of cobalt and iron.

[0053] To "set" the MRAM memory cell bit values ​​(i.e., select the free layer magnetization direction), an electron write current 1050 is applied from conductor 1008 to conductor 1006, as depicted in Figure 10A. Due to the negative charge of electrons, the top conductor 1006 is placed at a higher voltage level than the bottom conductor 1008 to generate the electron write current 1050. Because the reference layer 1012 is a ferromagnetic metal, electrons in the electron write current 1050 become spin-polarized as they pass through the reference layer 1012. When spin-polarized electrons tunnel across the tunneling barrier 1014, the conservation of angular momentum results in a spin-transfer torque being applied to both the free layer 1010 and the reference layer 1012, but this torque (by design) is insufficient to affect the magnetization direction of the reference layer 1012. Conversely, if the initial magnetization orientation of free layer 1010 is antiparallel (AP) to reference layer 1012, this spin-transfer torque (by design) is sufficient to switch the magnetization orientation in free layer 1010 to be parallel (P) to the magnetization orientation of reference layer 1012, a process known as anti-parallel-to-parallel (AP2P) writing. Parallel magnetization then remains stable before or after the electronic writing current is turned off.

[0054] Conversely, if the magnetization of free layer 1010 and reference layer 1012 is initially parallel, the magnetization direction of free layer 1010 can be switched to become antiparallel to reference layer 1012 by applying an electron write current in the opposite direction to the above case. For example, electron write current 1052 is applied from conductor 1006 to conductor 1008, as depicted in FIG10B, by setting a higher voltage level on lower conductor 1008. This writes free layer 1010 from the P state to the AP state, called parallel-to-anti-parallel (P2AP) writing. Therefore, by the same STT physics, the magnetization direction of free layer 1010 can be definitively set to either of two stable orientations by the deliberate choice of the direction (polarity) of the electron write current.

[0055] Data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. Low resistance generally represents a "0" bit and high resistance generally represents a "1" bit, although alternation sometimes occurs. A read current can be applied across memory cells (e.g., across magnetic tunneling junction 1002) by applying an electronic read current flowing from conductor 1008 to conductor 1006 as shown at 1050 in FIG. 10A ("AP2P direction"); alternatively, an electronic read current can be applied from conductor 1006 to conductor 1008 as shown at 1052 in FIG. 10B ("P2AP direction"). During a read operation, if the electronic write current is too high, this can interfere with the data stored in the memory cell and change its state. For example, if the electronic read current uses the P2AP direction of FIG. 10B, a current or voltage level that is too high can switch any memory cell in the low-resistance P state to the high-resistance AP state. Therefore, although MRAM memory cells can be read in either direction, the directional nature of write operations can make one read direction superior to another, such as the P2AP direction in various embodiments, because more current is required to write bits in that direction.

[0056] Although the discussion in Figures 10A and 10B takes place in the context of electronic currents used for reading and writing currents, unless otherwise specified, the subsequent discussion will take place in the context of conventional currents.

[0057] Whether reading from or writing to the selected memory cells in the array structures of Figures 7A through 7D, the bit lines and word lines corresponding to the selected memory cells are biased to apply a voltage across the selected memory cells, causing an electron flow as illustrated in Figures 10A or 10B. This also applies a voltage across the non-selected memory cells of the array, which can induce current in the non-selected memory cells. While this wasted power consumption can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high and low resistance states, this still results in increased current and power consumption and places additional design constraints on the design of the memory cells and the array.

[0058] One approach to address this unwanted current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, the selector transistor can be placed in series with each resistive memory cell element in Figures 7A through 7D, such that memory cell 701 is now a combination of a selector and a programmable resistor. However, the use of transistors requires the introduction of additional control lines to enable the corresponding transistor via the selected memory cell. Furthermore, transistors often cannot scale in the same way as resistive memory elements, making the use of transistor-based selectors a limiting factor when memory arrays are moved to smaller sizes.

[0059] An alternative to the selector element is a threshold switching selector device connected in series with a programmable resistive element. When the threshold switching selector is biased to a voltage lower than its threshold voltage, it has high resistance (in the off or non-conducting state); when biased to a voltage higher than its threshold voltage, it has low resistance (in the on or conducting state). The threshold switching selector remains on until its current falls below a holding current, or its voltage falls below a holding voltage. When this occurs, the threshold switching selector returns to the off state. Therefore, to program memory cells at the crossover point, a voltage or current sufficient to turn on the associated threshold switching selector is applied to set or reset the memory cell; and to read the memory cell, the threshold switching selector must similarly be activated by turning on before the resistive state of the memory cell can be determined. One example of a threshold switching selector is the bidirectional threshold switching material of an ovonic threshold switch (OTS).

[0060] Figure 11 illustrates an embodiment of incorporating an adjacency switching selector into an MRAM memory array with a crosspoint architecture. The example in Figure 11 shows two MRAM cells in a two-layer (2-layer) crosspoint array, as shown in Figure 7D, but in a side view. Figure 11 shows the lower first conductive line of word line 1 1100 (in the first or lower word line layer), the upper first conductive line of word line 2 1120 (in the second or upper word line layer), and the middle conductive line of bit line 1110 (in the bit line layer). In Figure 11, for ease of representation, all such lines are shown as traveling across the page from left to right. More accurately, in the crosspoint array, such lines are represented as a perspective view as in Figure 7D, where the word line (or first conductive line or wire) travels in a direction parallel to the surface of the underlying substrate, and the bit line (or second conductive line or wire) travels in a second direction, primarily orthogonal to the first direction and parallel to the surface of the substrate. MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and intermediate tunneling barrier. However, in actual implementations, additional structures related to Figure 9 described above are generally included.

[0061] An MRAM device 1102, comprising a free layer 1101, a tunneling barrier 1103, and a reference layer 1105, is formed on a threshold switching selector 1109. This series combination of the MRAM device 1102 and the threshold switching selector 1109 forms a layer 0 cell between bit line 1110 and word line 11100. When the threshold switching selector 1109 is turned on, the series combination of the MRAM device 1102 and the threshold switching selector 1109 operates as described above as relating to Figures 10A and 10B, except for some voltage drop across the threshold switching selector 1109. Although the threshold switching selector 1109 initially needs to be turned on by applying a voltage higher than the threshold voltage Vth of the threshold switching selector 1109, the bias current or voltage then needs to be maintained high enough to be higher than the holding current or holding voltage of the threshold switching selector 1109 to keep it on during subsequent read or write operations.

[0062] In Layer 1, an MRAM device 1112, comprising a free layer 1111, a tunneling barrier 1113, and a reference layer 1115, is formed on a threshold switching selector 1119. The series connection of the MRAM device 1112 and the threshold switching selector 1119 forms a Layer 1 cell between bit line 1110 and word line 2 1120. The Layer 1 cell operates as a Layer 0 cell, except that the lower conductor now corresponds to bit line 1110 and the upper conductor now corresponds to word line 2 1120.

[0063] In the embodiment of FIG11, threshold switching selectors 1109 / 1119 (selectors) are formed below MRAM devices 1102 / 1112, such that selector 1109 contacts the first word line 1100 of the first word line layer, and MRAM device 1102 is formed between selector 1109 and bit line 1110. In an alternative embodiment, threshold switching selectors may be formed above one or two layers of MRAM devices. As discussed with respect to FIGS. 10A and 10B, MRAM memory cells are directional. In FIG11, MRAM devices 1102 and 1112 have the same orientation, wherein free layers 1101 / 1111 are above reference layers 1105 / 1115 (relative to a substrate not shown). When forming a multilayer non-volatile memory structure, since each of the two layers and subsequent layers in embodiments with more layers can be formed according to the same manufacturing process sequence, forming such layers with the same structure between conductive lines can have several advantages, particularly regarding process advantages.

[0064] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switching selector is placed in series with the MRAM device, the threshold switching selector needs to be turned on by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device before current can pass through the MRAM device.

[0065] Figure 12A shows a schematic diagram of reading an example of a non-volatile memory cell 1220 including an MRAM cell 1222 connected in series with a selector 1224. The MRAM cell 1222 is schematically illustrated as having two resistors, RP and RAP, corresponding to the resistance of the MRAM cell 1222 in parallel and anti-parallel states. A constant current Iread is maintained through the MRAM cell 1222 during reading (e.g., by means of a current mirror, such as current mirror 574), such that VMRAM can have two different values ​​depending on whether the MRAM cell 1222 is in a parallel or anti-parallel state (e.g., VMRAM = Iread * RP or VMRAM = Iread * RAP). The selector 1224 is schematically represented as a voltage source providing a constant voltage difference Voffset when in an ON condition (e.g., once a threshold voltage is exceeded). A sense amplifier 570 is connected to a sense voltage at a sense node 572 (e.g., the voltage varies depending on the resistance of the MRAM cell 1222 and the resulting voltage VMRAM).

[0066] FIG. 12B illustrates voltage distributions that can be compared by a comparator (e.g., comparator 576) of the sense amplifier 570 during a sensing operation. The first voltage distribution labeled "P" (e.g., at the sense node 572) corresponds to the MRAM cells in the parallel or "P" state. The second voltage distribution labeled "AP" corresponds to the MRAM cells in the anti-parallel or "AP" state. The reference voltage Vref (e.g., from the Vref source 578) is between these distributions. By comparing the voltage at the sense node 572 with the reference voltage Vref, it can be determined which state the MRAM cell is in (e.g., a sense voltage < Vref indicates the P state and a sense voltage > Vref indicates the AP state).

[0067] In non-volatile memory cells including a selector connected in series with an MRAM cell, conventional current can flow from the selector side to the MRAM side. In a multi-layer non-volatile memory structure such as shown in FIG. 11, this can result in some differences when accessing non-volatile memory cells in different layers.

[0068] FIGS. 13A to 13B illustrate the differences in accessing non-volatile memory cells in different layers. In the first layer (Story0 in FIG. 13A), current flows from the word line side to the bit line side. For example, FIG. 13A shows a positive voltage VPP applied to the selected word line (schematically shown as variable resistor RWL) through the WL driver 624 and a negative voltage VNN applied to the selected bit line (schematically shown as variable resistor RBL), such that the current Iread flows from the word line side to the bit line side. In contrast, in the second layer (Story1 in FIG. 13B), current flows from the bit line side to the word line side. For example, FIG. 13B shows a positive voltage VPP applied to the selected bit line (RBL) through the BL driver 614 and a negative voltage VNN applied to the selected word line (RWL), such that the current Iread flows from the bit line side to the word line side.

[0069] To read memory cells in different layers of a multi-layer MRAM memory structure (e.g., as depicted in FIG. 11), the read / write circuit can include separate sense amplifiers for reading the memory cells in each layer. For example, FIGS. 14A to 14B show an example in which two different sense amplifiers are used to read non-volatile memory in different layers.

[0070] Figure 14A illustrates an example of a read operation (Story0 read) for a non-volatile memory cell in the first layer (e.g., Story0 cell in Figure 11). A positive voltage VPP is connected to the selected non-volatile memory cell 1472 via switch 1470 (e.g., a switch of the WL decoder) and the selected word line (e.g., first word line 1100, schematically shown as a variable resistor R WL). The selected bit line (e.g., bit line 1110, schematically shown as R BL) connects the selected non-volatile memory cell 1472 to a current mirror 574 via switch 1474 (e.g., a switch of the BL decoder), which is connected to a negative voltage VNN and configured to maintain a read current Iread during the read operation. A low-voltage sensing amplifier 1478 is connected to sense the voltage between a selected bit line and a current mirror 574 (e.g., the low-voltage sensing amplifier 1478 can be configured to sense low voltages, including, for example, negative voltages in the range of -2.5 volts to -3.0 volts).

[0071] Figure 14B shows an example of a read operation (Story1 read) for a non-volatile memory cell in the second layer (e.g., Story1 cell in Figure 11). A positive voltage VPP is connected to the selected non-volatile memory cell 1482 via switch 1480 and a selected bit line (e.g., bit line 1110, schematically shown as R BL). A selected word line (e.g., word line 1120, schematically shown as R WL) connects the selected non-volatile memory cell 1482 to a negative voltage VNN via switch 1484. A high-voltage sensing amplifier 1483 is connected to sense the voltage between the selected bit line and the current mirror 574 (e.g., the high-voltage sensing amplifier 1483 can be configured to sense high voltages, including positive voltages in the range of, for example, 2.5 volts to 3.0 volts).

[0072] Variations of this technology include using a single sensing amplifier to perform sensing during a read operation for memory cells in two different layers (e.g., as illustrated in FIG11), wherein the current flow is different for reading memory cells in different layers (e.g., word line to bit line in the first layer story0 and bit line to word line in the second layer story1).

[0073] Figure 15A shows an example of control circuitry connected to a non-volatile memory cell 1552 (e.g., a non-volatile memory cell in any layer of an MRAM memory structure, such as that illustrated in Figure 11). The non-volatile memory cell 1552 is connected to a bit line (RBL) and a word line (RWL), which are respectively connected to bit line switches 1554 and word line switches 1556. Bit line switches 1554 include a first set of switches 1558 connected between a first voltage VPP (e.g., a positive voltage) and the bit line, and a second set of switches 1560 connected between the bit line and a sense amplifier 1478. Word line switches 1556 include a third set of switches 1562 connected between the first voltage VPP and the word line, and a fourth set of switches 1564 connected between the word line and the sense amplifier 1478. Individual switches may correspond to different switching ratios and transistor types. For example, the first letter indicated next to each transistor / switch may indicate a ratio (e.g., L = local, G = global, and P = planar). The second letter indicates whether it is connected to a line extending in the x or y direction (e.g., Y represents a bit line and X represents a word line). The third letter indicates the transistor type (e.g., P represents PMOS and N represents NMOS, such that the first switch 1558 and the third switch 1562 are formed by PMOS transistors, and the second switch 1560 and the fourth switch 1564 are formed by NMOS transistors). Figure 15A also shows the library control circuit 1566 and the module control circuit 1568, which can control the signals used to turn on / off the bit line switch 1554 and the word line switch 1556. For example, the control gates of the transistors in the first, second, third, and fourth sets of transistors can be connected to the module control circuit 1568 and / or the library control circuit 1566 (control lines are omitted for clarity). A sense amplifier 1478 is connected above a current mirror 574, which is connected to a second voltage VNN (e.g., a negative voltage).

[0074] Figure 15B shows an example of a read operation for the first non-volatile memory cell 1552 in the first layer (e.g., Story0 cell in Figure 11). In this example, by turning on the third switch 1562, a first voltage VPP (e.g., a positive voltage) is connected to the first non-volatile memory cell 1552 through the selected word line. By turning on the second switch 1560, a sense amplifier 1478 and a first voltage VNN (e.g., a negative voltage) are connected to the first non-volatile memory cell 1552 through a bit line. For this read operation, the first switch 1558 and the fourth switch 1564 are turned off. In this configuration, the read current Iread flows through switch 1562, the selected bit line, the first non-volatile memory cell 1552, the selected bit line, switch 1560, and current mirror 574, as illustrated by the dashed arrows. The sensing amplifier 1478 senses the voltage above the current mirror 574 to determine the state of the first non-volatile memory cell 1552.

[0075] Figure 15C shows an example of a read operation for a second non-volatile memory cell 1592 in the second layer (e.g., the Story1 cell in Figure 11). In this example, by turning on the first switch 1558, a first voltage VPP (e.g., a positive voltage) is connected to the second non-volatile memory cell 1592 through the selected bit line. By turning on the fourth switch 1564, a sense amplifier 1478 and a first voltage VNN (e.g., a negative voltage) are connected to the second non-volatile memory cell 1592 through the word line. For this read operation, switches 1560 and 1562 are turned off. In this configuration, the read current Iread flows through switch 1558, the selected bit line, the second non-volatile memory cell 1592, the selected word line, switch 1564, and current mirror 574, as illustrated by the dashed arrows. The sensing amplifier 1478 senses the voltage above the current mirror 574 to determine the state of the second non-volatile memory cell 1592.

[0076] The library control circuit 1566 and / or the module control circuit 1568 (e.g., in combination with other control circuits such as system control logic 560 / 660) can control the first switch 1558, the second switch 1560, the third switch 1562, and the fourth switch 1564 to be configured as shown in FIG15B when reading memory cells in the first layer (e.g., Story0), and to be configured as shown in FIG15C when reading memory cells in the second layer (e.g., Story1). For example, control circuitry (e.g., library control circuitry 1566, module control circuitry 1568, and / or system control logic 560 / 660) can receive the address of the selected non-volatile memory cell and, for each selected non-volatile memory cell, determine which of a plurality of layers the selected non-volatile memory cell is located in, including a first layer between a first word line layer and a bit line layer (e.g., Story0 between word line 1 1100 and bit line 1110 in FIG. 11) and a second layer between a bit line layer and a second word line layer (e.g., Story1 between bit line 1110 and word line 2 1120). The control circuitry can then apply appropriate voltages to a first switch, a second switch, a third switch, and a fourth switch to perform configuration according to the layer in which the non-volatile memory cell is located. Library control circuitry 1566, module control circuitry 1568, bit line switch 1554, and word line switch 1556 (alone or in combination with additional switches such as system control logic 560 / 660) can be considered as examples of components for reading non-volatile memory cells located in a plurality of layers, including a first layer between a first word line layer and a bit line layer (e.g., Story 0 of FIG. 11) and a second layer between a bit line layer and a second word line layer (e.g., Story 1 of FIG. 11), including connecting a sense amplifier to a first selected non-volatile memory cell in the first layer via bit lines of the bit line layer (e.g., see FIG. 15B), and connecting a sense amplifier to a second selected non-volatile memory cell in the second layer via second word lines of the second word line layer (e.g., see FIG. 15C). Although the examples in Figures 15B to 15C pertain to read operations, using the same techniques, any memory access operation (e.g., write operation) can be similarly applied to memory cells in different layers.

[0077] Figure 16 shows a simplified schematic diagram of various types of memory chips 1600 implementing the present technology. For example, Figure 16 shows a bit line switch 1554 connected to the bit lines of the memory array 502 via input / output 506 and a word line switch 1556 connected to the word lines of the memory array 502 via input / output lines 508. The bit line switch 1554 and the word line switch 1556 are connected to a common control circuit 1602, which includes a common sense amplifier 1604 and a common driver 1606. For example, each sense amplifier in the common sense amplifier 1604 can be connected to a bit line (via bit line switch 1554) or a word line (via word line switch 1556), and in this way can be used to sense non-volatile memory cells in different layers. Similarly, each driver in the common driver 1606 can be connected to a bit line (via bit line switch 1554) or a word line (via word line switch 1556), and in this way can be used to drive appropriate voltages (e.g., VPP and VNN) on the bit line or word line. In this way, the common driver 1606 can be used for read operations on memory cells in different layers. Other components of the memory die 1600 may be similar to those of the memory system 500 and will not be described further herein. The integrated memory assembly can be implemented using WL switches, bit line switches, and common circuitry that can be connected to any of them (e.g., the integrated memory assembly 600 may be configured to include word line switch 1665, bit line switch 1554, and common control circuitry 1602).

[0078] Figure 17 shows an example implementation of the present technology in a data storage system comprising a core formed by N libraries, each library having n modules. Figure 17 also shows an example of a control circuit that can be used to control switches connecting a common sense amplifier and / or driver to word lines and bit lines.

[0079] Digital media control circuitry 1780 receives address 1782 (e.g., a logical address in a read command for one or more non-volatile memory cells). Digital media control circuitry 1780 can use address 1782 to generate location information 1786 (e.g., a physical address) in an appropriately formatted manner. For example, location information 1786 may include the library, module, layer, and coordinates (e.g., bit lines and word lines) in which the selected non-volatile memory cells to be read are located (e.g., in which the memory structure has different characteristics in stories or layers, as illustrated in FIG11).

[0080] Digital media control circuitry 1780 sends location information 1786 to library control circuitry 1566. Library control circuitry can use location information 1786 to determine which layer (e.g., first layer Story0 or second layer Story1) the non-volatile memory cell is located in. Library control circuitry 1566 sends signal 1792 to module control circuitry 1568. Module control circuitry 1568 generates signals to enable / disable switches in bit line switches 1554 (e.g., first set of switches 1558 and second set of switches 1560) and word line switches 1556 (e.g., third set of switches 1562 and fourth set of switches 1564). For example, for a read operation targeting a non-volatile memory cell in the first layer, module control circuitry 1568 can generate signals to configure the switches as shown in FIG15B, while for a read operation targeting a non-volatile memory cell in the second layer, module control circuitry 1568 can generate signals to configure the switches as shown in FIG15C. Although Figure 17 shows a specific configuration of the components, this technique is not limited to any specific configuration and can be implemented using a variety of components.

[0081] Figure 18A illustrates an example of a method, which includes receiving the first address 1820 of a first selected non-volatile memory cell (e.g., the lower cell in Figure 11) at the intersection of the first word line and the first bit line in a non-volatile memory cell structure; determining that the first selected non-volatile memory cell is in the first layer (e.g., Story 0) 1822; and in response to determining that the first selected non-volatile memory cell is in the first layer, connecting a sense amplifier to the first bit line to read the first selected non-volatile memory cell 1824 (e.g., as illustrated in Figure 15B). The method further includes receiving the second address 1826 of the intersection of the first word line and the second word line of the second selected non-volatile memory cell (e.g., the upper cell of FIG11) in the non-volatile memory cell structure, determining that the second selected non-volatile memory cell is in the second layer (e.g., Story 1) 1828, and in response to determining that the second selected non-volatile memory cell is in the second layer, connecting a sense amplifier to the second word line to read the second selected non-volatile memory cell 1830 (e.g., as illustrated in FIG15C).

[0082] Figure 18B illustrates method steps that can be performed individually or in combination with the steps shown in Figure 18A. These steps include passing a first current through a first word line, a first non-volatile memory cell, a first bit line, and a current mirror to read a first non-volatile memory cell 1840 (e.g., Iread in Figure 15B); sensing the first non-volatile memory cell 1842 by comparing a sensed voltage between the first bit line and the current mirror with a reference voltage while passing the first current; passing the first current through a first bit line, a second non-volatile memory cell, a second word line, and a current mirror to read a second non-volatile memory cell 1844 (e.g., Iread in Figure 15C); and sensing the second non-volatile memory cell by the sense amplifier, including comparing a sensed voltage between the second word line and the current mirror with a reference voltage 1846 while passing the first current.

[0083] The memory device embodiments presented above use a cross-point architecture, where each MRAM cell is constructed in a cross-sectional area between a vertical bit line (on one level) and a horizontal word line (constructed above or below). To save die size, embodiments may use an architecture that allows CMOS select transistors to be placed below the memory array. Accessing a given memory cell requires charging one of several (e.g., 256, 512, 1024, or 2048) bit lines and word lines through a set of select transistors in decoder (multiplexer) circuitry (such as the column control circuitry 520 / 620 and row control circuitry 510 / 610 of Figures 3 or 4). As discussed above, the MRAM cross-point array embodiments use both positive and negative bias levels. The following discussion presents embodiments of such bipolar decoder circuitry. The example embodiments used in this discussion are for cross-point MRAM memory, wherein the decoder circuitry is located on the same die as the memory cell and below the memory cell, but can be more generally applied to other embodiments, such as those based on other programmable resistive elements, such as ReRAM, FeRAM, RRAM, or PCM memory cells, and embodiments in which the decoder circuitry is formed on the periphery of the memory array or on a separate control die as in the embodiment of FIG4.

[0084] The decoder circuitry and its requirements are now discussed. The decoder is a multiplexer that provides unique connections (and current delivery capabilities) to each of the lines it drives. In an example embodiment, the bit-line decoder drives one of 1024 bit lines, and the word-line decoder drives one of 1024 word lines. In a crosspoint configuration, the decoder can be the same in both cases. In the inactive state, the deselect transistor drives both the bit and word lines to ground (0V). To program an MRAM cell (i.e., change its state from logic 1 to logic 0, or vice versa), current must flow from the bit line to the word line, or vice versa. Therefore, the decoder must be able to supply current (when the line is driven positive) and draw current (when the line is pulled negative). The cells are bipolar. Therefore, the decoder must be bipolar.

[0085] Figures 19A and 19B illustrate an embodiment of a bipolar decoder, showing different parts of the circuit system that together constitute an embodiment of the circuit. The decoder includes a positive decoding path (above the upper horizontal break line), a ground decoding path (between the horizontal break lines), and a negative decoding path (below the lower break line). Figures 19A and 19B are for a bitline decoder, but a wordline decoder can be configured similarly. In the illustrated example embodiment, layered decoding is used, initially at the "pane" (i.e., cross-dot array segment) level, then at the global level, and finally at the local level. Considering the pane selection, a local control signal 1911 is connected to the positive pane selection PMOS switch PPS 1913 and the positive pane deselect NMOS switch PPD 1915 to supply a bias level pos_MUX to the pos_pane supply line when the pane is selected (local value low), which feeds to (in this example) the 32 global selections. The positive bias level pos_MUX will depend on the operation being performed. Global positive selection switch GPS <0> 1903-0 to GPS <31> 1903-31 is connected to the pos_pane and receives its enable signal pos_global_enb (where "b" stands for bar or inverted because 1903 is a PMOS) via a set of inverters / drivers from the level offset 1901 of the termination circuit 1900 to feed the corresponding pos_global signal (as in this example) to the 32 local select switches. The pos_global line is connected to the global positive deselect switch GPD. <0> 1905-0 to GPS <31> 1905-31 is connected to ground and receives local control signal 1907.

[0086] The positive global supply lines pos_global used for each global select / deselect switch of GPS 1903 / GPD 1905 are connected to a corresponding set of bit lines via local positive select switches. For example, as shown in Figures 19A and 19B, from GPS <0> The pos_global line of 1903-0 is transmitted through individual local positive selection switches LPS. <0> 1925-0 to LPS <31> 1925-31 connected to the local bit line LBL <0> To LBL <31> And from GPS <31> The pos_global line of 1903-31 is transmitted through individual local positive selection switches LPS. <0> 1927-0 to LPS <31> 1927-31 connected to the local bit line LBL <991> To LBL <1023> Similarly, other unshown bit lines are connected. The control signal (pos_local_enable) for the local positive selector switch is also provided from the level offset 1921 in the terminal circuit 1900 via a set of drivers in the terminal circuit 1900. An additional driver / inverter 1923 for each of the 32 local positive control signals (pos_local_enb) for the local positive selector switch drives the PMOS selector gate, wherein the additional driver / inverter 1923 is located near the actual switch, as discussed further below. The positive local deselect signal and the negative local deselect signal are part of the ground decoding path of the terminal circuit system 1900. For the positive decoding side, the level offset 1941, via a set of drivers / inverters, is used for decoding via GPS. <0> PMOS LPD for bit lines supplied by 1903-0 <0> 1947-0 to LPD <31> 1947-31 and used by GPS <31> PMOS LPD for bit lines supplied 1903-31 <0> 1949-0 to LPD <31> The local positive deselect switch 1949-31 provides a positive deselect enable signal (pos_desel_en). An additional set of drivers / inverters 1945 is also placed on the periphery of the array to generate an inverted deselect enable signal (desel_enb) from pos_desel_en and also from the negative deselect enable signal (neg_desel_en) from the level offset 1943, because when a bit line is deselected, the deselected bit line is set to ground regardless of whether the bit line is positive or negative. Therefore, in this example embodiment, there is a pane select (PPS) fed to one of the 32 global selects (GPS). Each global select is fed to one of the 32 local selects (LPS), resulting in 1024 unique bit line connections. In the off / idle state, the deselect (PPD, GPD, LPD) will be grounded to each level in the decoding path.

[0087] Considering the remainder of the negative part of the decoder, the negative decoding path mirrors the positive decoding path and is laid out similarly. However, for the selected operation, a choice is now made between ground and the negative voltage neg_MUX, where the negative voltage is selected via an NMOS device and deselected by connecting to ground via a PMOS device. More specifically, the pane level selection is based on the local control signal 1991, which connects the neg_pane to ground via NPD 1993 or to neg_MUX via NPS 1995. When selected, the global decoding used to provide the neg_global signal is then performed by the NMOS switch GNS. <0> 1985-0 to GNS <31> 1985-31 is executed based on the control signal neg_global_en from the level offset 1981, and when deselected, it is controlled by the PMOS switch GND. <0> 1983-0 to GND <31> 1983-31 is executed based on the local control signal 1987. For local decoding of local bit lines, deselection is performed as described above for the positive decoding side. To decode the selected local bit line, the control signal neg_local_enb is provided by the level offset 1961 through a set of drivers / inverters, where additional associated drivers / inverters are included because the switch is now NMOS. The neg_local_en signal is then generated by the driver / inverter 1963, which is positioned closer to the decoding switch. Next, a negative local enable signal is supplied to the switch LNS. <0> 1965-0 to LNS <31> The control gate of 1965-31 was used for GNS <0> 1985-0 local switch, supply to switch LNS <0> 1967-0 to LNS <31> The control gate of 1967-31 was used for GNS <0> The local switch fed by 1985-31, and similarly for other switches not shown.

[0088] Figure 20 illustrates an embodiment of a triple-well transistor, such as that which can be used in the decoder switches of Figures 19A and 19B. A triple-well transistor is used because a negative voltage (e.g., -2.5V) is transmitted on the negative decoding path side. In Figure 20, a PMOS 2030 is situated between a pair of triple-well NMOS 2010 and 2050 above a deep N-well 2003 within a P-substrate 2001. The PMOS switch 2030 includes a control gate 2031, with the p+ region on either side above the N-well 2033, and the n+ tap on either side of the p+ region. The N-well 2033 of the PMOS 2030 and the deep N-well 2003 of the triple-well NMOS are short-circuited. The triple-well NMOS 2010 / 2050 have respective control gates 2011 / 2051 above the isolated P-well regions 2013 / 2053. The n+ region is on either side of the NMOS control gate, and the p+ tap is on either side of the NMOS control gate. Individual N-type wells 2080 and 2090 with individual n+ taps are within the P-substrate 2001 and above a deep N-type well 2003 on the outside of the triple-well NMOS 2010 and triple-well NMOS 2080. This configuration can be used in both the bit-line decoding circuit systems of Figures 19A and 19B, as well as in word-line selection circuit systems that may have a similar structure.

[0089] Figure 21 illustrates an embodiment of the decoder layout of Figures 19A and 19B. This example depicts a bit-line decoder, but as explained below with reference to Figure 23, a similar configuration can be used for a word-line decoder or decoder layer. In this example, the decoder drives 1024 lines, with 512 lines driven from the left and another 512 lines driven from the right. As illustrated in Figure 20, different device types have been separated by a wiring strategy to accommodate an exemplary embodiment of the array, rather than grouping all NMOS and PMOS devices together.

[0090] More specifically, as configured in the diagram, the global selection decoder is located in the center, with half of the local selection decoders on either side. Each of these decoder groups is then divided into NMOS (Negative Selection Region, dotted area) and PMOS (Positive Selection Region). In this example, half of the NMOS local negative select (LNS) switches are located in the center and are again divided into a left portion 2101A of 256 switches and a right portion 2101B of 256 switches, with a corresponding set of 16 global negative select (GNS) 2121 located between the two sides. On either side of the LNS arrays 2101A and 2101B at the edges of the switch array are corresponding local drivers / inverters 2141A and 2141B for the eight elements in element 1923 of Figure 19A, allowing for clearly defined control signal levels.

[0091] Half of the PMOS local positive select (LPS) switches are above the central LNS region, and the other half are below. They are also divided into two halves: the upper half consists of 256 switches in the left portion 2107A and 256 switches in the right portion 2107B; the lower half consists of 256 switches in the left portion 2109A and 256 switches in the right portion 2109B. A corresponding set of 16 global positive selects (GPS) 2127 and 2129 are located between these two sides. On either side of the LPS arrays 2107A / 2107B and 2109A / 2109B at the edge of the switch array, there are corresponding local drivers / inverters 2147A / 2147B and 2149A / 2149B for the eight elements in element 1963 of Figure 19A.

[0092] The remaining half of the NMOS LNS switches is further divided into two halves, and then into left and right halves. 128 NMOS LNS switches 2115A / 2115B are located at the top, with the corresponding GNS switches 2135 positioned in between, and the corresponding edge drivers / inverters 2155A / 2155B on either side. Similarly, 128 NMOS LNS switches 2117A / 2117B are located at the top, with the corresponding GNS switches 2137 positioned in between, and the corresponding edge drivers / inverters 2157A / 2157B on either side. Next, the PMOS local positive deselect (LPD) is divided into four groups, further subdivided into left and right sections, and located between the LNS block and the LPS block. The corresponding edge positioning drivers are on either side: 2103A / B and 2143A / B above the central LNS block; 2105A / B and 2145A / B below the central LNS block; 2111A / B and 2151A / B above the upper LPS block; and 2113A / B and 2153A / B below the lower LPS block. Figure 21 and the following related diagrams are an example, but other embodiments may vary the placement of the NMOS LNS block and PMOS LPS block (along with the corresponding GNS / GPS and driver blocks), as well as the number of drivers in each block, where there is a trade-off between block layout size and routing optimization.

[0093] Figures 22 and 23 illustrate an embodiment of the wiring for the array vias of word lines and bit lines connecting the decoder circuitry and the associated crosspoint array (or pane). Figures 22 and 23 are for a two-layer crosspoint array, as in the embodiment shown in Figure 7D. In Figure 22, word line layer WL1 2203 is above bit line layer 2205, which in turn is above word line layer 2201 in layer 0. Figure 22 is oriented such that the bit lines of layer 2205 travel into the page and the word lines of layers 2201 and 2203 travel from left to right. Three memory cells are shown in each layer; the leftmost memory cell is labeled as memory cell 1 2111 and selector OTS 1 in layer 1, and as memory cell 0 2117 and selector OTS0 in layer 0. The bit lines of layer BL 2205 and the word lines of layers WL0 2201 and WL1 2203 will each need to be connected to a corresponding set of decoders, such as the decoders for the bit lines and similar sets of decoders for the word line layers shown in Figures 19A, 19B, and 20. Because of the different orientations of the bit lines and word lines, the corresponding decoders will also need to be oriented differently. A corresponding set of vias connects the bit line and word line layers to a set of metal layer contacts m5, which are connected to the decoder circuit shown in Figure 24 to provide bias levels for the word lines and bit lines.

[0094] Figure 23 illustrates one embodiment of the orientation of the three decoders for word line layer 0 2301, bit line layer 2305, and word line layer 1 2303. Figure 23 shows these decoders side-by-side, but in an exemplary embodiment, the decoders are positioned one above the other. For example, in one set of embodiments, the decoders are below the array, represented by broken-line blocks 2323, and the vias of Figure 22 connect to the decoders below. In embodiments such as Figure 4, the decoder layers are on control die 611, which is then connected at the m5 contact. Depending on the embodiment, decoder layers 2301, 2305, and 2303 can be stacked in the same order as the word line and bit line layers, with bit line layer 2303 in the middle, or stacked in other ways. In word line layer decoders 2301 and 2303, the word lines (WL) are oriented from left to right, as shown in Figure 22, where the decoder is connected in the central dotted area (represented by a black dot) of the m5 connector. In bit line layer decoder 2305, the bit lines (BL) are oriented vertically, corresponding to the top view in Figure 22, where the decoder is connected in the central dotted area (represented by a black dot) of the m5 connector.

[0095] To provide all the bias conditions for memory operation, each bit line and word line needs to be connected to the positive local select (LPS), negative local select (LNS), and local deselect (LPD) from the corresponding decoder. Minimum design rules do not allow for a single interconnect layer, so two layers (metal layers 4 and 5, m4 and m5) are used to connect the select transistor to the array vias. To accommodate this, NMOS and PMOS transistor systems are separate. Figure 24 is a side view of these connections.

[0096] Figure 24 is a side view of an embodiment of different decoder blocks of Figure 21 and how these decoder blocks are connected to the m5 metal layer of Figure 22. Similar to Figure 21, Figure 24 is oriented from top to bottom, but is a side view. NMOS LNS block 2401 may correspond to blocks 2115A and 2115B of Figure 21; PMOS LPD block 2403 may correspond to blocks 2111A and 2111B; PMOS LPS block 2405 may correspond to blocks 2107A and 2107B; and PMOS LPD block 2407 may correspond to blocks 2103A and 2103B. NMOS LNS blocks 2409 and 2411 together may correspond to 2101A and 2101B, wherein, as illustrated below with reference to Figure 25, NMOS LNS selection blocks 2101A and 2101B are located below the wiring area and their routes travel in different directions. Similarly, PMOS LPD block 2413 can correspond to blocks 2105A and 2105B; PMOS LPS block 2415 can correspond to blocks 2109A and 2109B; PMOS LPD block 2417 can correspond to blocks 2113A and 2113B; and NMOS LNS block 2419 can correspond to blocks 2117A and 2117B.

[0097] In Figure 24, the upper half of the block may correspond to an even number of bit lines, and the lower half of the block may correspond to an odd number of bit lines. Each of the decoder blocks is routed to the m4 metal layer via a connection with lighter dots, and then to the m5 metal layer via a connection with heavier dots. The m5 metal layer is then connected to the array vias, as illustrated in Figures 22 and 23. (Regarding the naming of m4 and m5, in one set of embodiments, a lower number of metal layers are used to form the decoder, where the routing layers are here labeled m4 and m5.) For routing, decoder blocks are grouped at different layers, where half of blocks 2401, 2403, and 2405 are grouped in segment 2421 of layer m5, and then to the upper group of array vias; the other half of 2405, 2407, and 2409 are grouped in segment 2425 of layer m4, and then to the second group of array vias; half of 2411, 2413, and 2415 are grouped in segment 2417 of layer m4, and then to the third group of array vias; and the other half of 2415, 2417, and 2419 are grouped in segment 2423 of layer m5, and then to the lower part of the array vias. A top view of this routing is given in Figure 25.

[0098] Figure 25 repeats the decoder of Figure 21, but adds a portion of the routing from Figure 24 shown in a top view. Wiring areas 2501A and 2501B correspond to the wiring areas of bitline layer 2305 in Figure 23. Wiring areas 2501A and 2501B span the width of the respective NMOS LNS regions 2101A and 2101B, with a gap above the GNS region 2121 because these switches are powered locally, not directly connected to memory array vias. Sections of the m4 and m5 metal layers are shown at 2503, where these metal layers cover the entire local selection decoder switch, but only a portion is shown at 2503 for clarity. By placing wiring areas 2501A and 2501B in the center, the routing volume is minimized, which simplifies the structure and reduces RC delay along the lines, as the lines are shorter compared to those with wiring at the edges.

[0099] Figure 26 illustrates the details of the lower left quadrant of Figure 25, showing only the lower (as shown in the figure) portions of local selection blocks 2117A, 2113A, 2109A, 2105A, and 2101A. In the wiring area, array vias are positioned to allow layer m5 to be attached to the array vias illustrated in Figure 24. Lines m4 and m5 then extend downwards across local selection blocks 2117A, 2113A, 2109A, and 2105A. In Figure 25, and more clearly in Figure 26, the black rectangle along line 2503 connects along m4 (as shown in Figure 24) and then connects to one of the m5 connection areas and to the array vias connecting local selection blocks 2109A (for the upper half), 2105A, and 2101A. The dotted rectangles along line 2503 are connected along m5 (as shown in Figure 24) and then connected to the local selection blocks 2109A (for the lower half), 2113A, and 2117A of the array via.

[0100] Figure 27 is a flowchart of an embodiment of a memory device comprising the decoder structure of Figures 19A to 26. The process begins at step 2701, forming a bipolar decoder circuit for a first set of control lines (i.e., a first of bit lines or word lines) for a crosspoint memory array, wherein memory cells are connected between the first set of control lines and a second set of control lines (i.e., the other of bit lines and word lines). Examples of crosspoint array structures can be described above with respect to Figures 7A to 7D. The bipolar decoder will have positive voltage selection switches and negative voltage selection switches, including local positive selection switches and local negative selection switches that can be arranged as in the embodiment of Figure 21. Both the local positive selection switches and the local negative selection switches can be formed as part of the same CMOS manufacturing process at steps 2703 and 2705, wherein these will generally be formed as part of the same manufacturing process.

[0101] At step 2703, the positive voltage selection switches are configured to supply a positive voltage level to the first set of control lines, as discussed in Figures 19A and 19B for the bitline decoder example. As formed on the die and illustrated in Figure 21, the positive voltage selection switches have a first subgroup of PMOS LPS switches 2107A and 2107B and a second subgroup of PMOS LPS switches 2109A and 2109B. Subgroups of negative selection switches are located between and on either side of the subgroups of LPS switches. These are formed in step 2705, which can be performed simultaneously with step 2703, to supply a negative voltage level to the first set of control lines. Although not included in the flow of Figure 27, the example embodiment also forms separate sets of PMOS LPD deselect switches between the positive and negative selection switches, as shown in the embodiment of Figure 21.

[0102] At step 2707, routing for connecting the switches is performed. In the embodiments of Figures 22 to 26, this involves connecting each of the local select switches to metal wire layers m4 and m5 connected to the m5 layer in wiring areas 2501A and 2501B. At step 2711, the connections in the wiring areas are then connected to the cross-point array, specifically to the array vias in the above examples. Depending on the embodiment, step 2711 may include forming an array over the decoder structure, or in embodiments such as Figure 4, bonding memory chips thereon to form the control chip for the decoder.

[0103] According to a first configuration sample, a non-volatile memory device includes a control circuit configured to be connected to an array comprising a first plurality of non-volatile memory cells having a crosspoint structure in which each of the first plurality of memory cells is connected between one of a plurality of bit lines and one of a plurality of first word lines, the control circuit including a first bipolar decoder configured to be connected to the memory array to selectively bias one of the first bit lines or one of the first word lines to one of a positive voltage level, a ground voltage level, or a negative voltage level. The first bipolar decoder includes: a plurality of local negative selection switches, each configured to supply the negative voltage level to one of the first bit lines or the first word lines; a plurality of local positive selection switches, each configured to supply the positive voltage level to one of the first bit lines or the first word lines; a first subgroup of a plurality of the local positive selection switches and the local negative selection switches is located on a die and is located between the local positive selection switches and the local negative selection switches. Between a first subgroup and a second subgroup of the other of the plurality of; a plurality of connection points, each configured to connect one corresponding to one of the first of the bit lines or the first word lines, the connection points being centrally located in a wiring area above the first subgroup of one of the local positive selector switches and the local negative selector switches; and a plurality of metal wires, each connecting one corresponding to one of the local negative selector switches and the local positive selector switches to one corresponding to one of the connection points.

[0104] According to another configuration, one method includes a bipolar decoder circuit forming a first set of control lines for a crosspoint memory array of non-volatile memory cells on a first die, wherein each of the non-volatile memory cells is connected between one of the first set of control lines and one of the second set of control lines. The bipolar decoder circuit comprises: forming a plurality of positive voltage selector switches, each configured to supply a positive voltage level to a corresponding one of the first set of control lines, including forming a first subgroup and a second subgroup of the plurality of positive voltage selector switches on the first die; forming a plurality of negative voltage selector switches, each configured to supply a negative voltage level to a corresponding one of the first set of control lines, including forming a first subgroup of the plurality of negative voltage selector switches on the first die between the first subgroup and the second subgroup of the plurality of positive voltage selector switches; and forming a plurality of metal lines traveling above the positive voltage selector switches and the negative voltage selector switches, each of the metal lines connecting a corresponding one of the positive voltage selector switches or the negative voltage switches to a connection in the first set of control lines, the connections being located above a central region of the die.

[0105] In another configuration, a memory device includes: a non-volatile memory cell structure comprising non-volatile memory cells arranged at an intersection, each memory cell having a programmable resistive element and connected between one of a plurality of first control lines and one of a plurality of second control lines; and one or more control circuits connected to the memory cell structure. The one or more control circuits include: a plurality of first decoding switches, each configured to bias one corresponding to one of the first control lines to a positive voltage level; a plurality of second decoding switches, each configured to bias one corresponding to one of the first control lines to a negative voltage level, a first subgroup of the plurality of second decoding switches being located on a die and between a first subgroup of the plurality of first decoding switches and a second subgroup of the plurality of first decoding switches; and a plurality of routing lines, each connecting one corresponding to one of the first decoding switches or the second decoding switches to a corresponding connection point of one of the first control lines, the connection points being located above the first subgroup of the second decoding switches.

[0106] For the purposes of this document, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in this specification may be used to describe different or the same embodiments.

[0107] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as a connection or coupling to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is referred to as being directly connected to another element, there is no intermediary element between the element and the other element. If two devices are directly or indirectly connected such that they can transmit electronic signals between them, the devices are "in communication".

[0108] For the purposes of this document, the term "based on" can be interpreted as "based at least in part on".

[0109] For the purposes of this document, without additional context, the use of numerical terms (such as "first" object, "second" object, and "third" object) may not imply the order of objects, but may instead be used for identification purposes to distinguish different objects.

[0110] For the purposes of this document, the term "set" of objects may refer to a group of one or more objects.

[0111] The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or limited to the precise forms disclosed. In view of the foregoing teachings, many modifications and variations are possible. The described embodiments have been selected to best explain the principles and practical application of the proposed technology, thereby enabling those skilled in the art to best utilize it in various embodiments and to contemplate various modifications suitable for that particular purpose. It is intended that this scope be defined by the appended claims.

[0112] 100: Memory System 102: Controller; Memory Controller 104: Non-volatile memory; memory packaging 106: Local Memory; DRAM / ReRAM / MRAM 110: Front-end processor (FEP) circuit; FEP circuit; FEP 112: Back-end Processor (BEP) circuit; BEP circuit; BEP 120: Host 122: Host Processor 124: Host Memory 126: PCIe Interface 128: Busbar 130: Interface 292: Memory chip 294: Memory Bus 296: Dual-state thixotropic mode interface; TM interface 500: Memory System 502: Memory array; array; structure 506: Input / Output 508: Line; Input / Output Line 510: Line control circuit system 512: Line Decoder 514: Bit Line (BL) Driver; BL Driver 516: Read / Write (R / W) circuit; R / W circuit 520: Train control circuit system 522: Column Decoder 524: Word Line (WL) Driver; WL Driver 542: Word line driver 560: System Control Logic 570: Sensing Amplifier 572: Sensing Node 574: Current Mirror 576: Comparator 578: Reference voltage source; Vref source 580: Data latch 600: Integrated Memory Assembly 601: Memory chip 602: Memory structure; memory array; array; structure 606: Electrical Path 608: Electrical Path 610: Line control circuit system 611: Controlling grain size 612: Line Decoder 614: Driver circuitry; BL driver 616: R / W circuit; read / write circuit 620: Train control circuit system 622: Column Decoder 624: Array driver; WL driver 626: Block Selection 660: System Control Logic 680: Selected memory unit 682: Word Line 684: Bitline 701: Memory Unit 718: First Floor 720: Second Layer 801: Bottom Electrode 803: Reference Layer 805: Magnesium oxide (MgO) 807: Free Layer 809: Spacers 811: Top Electrode 813: Voltage source V app 901: Word Line 902: Conductive spacer 903: Reference Layer 905:MgO barrier 907: Free Layer 908: MgO cap 909: Conductive spacer 911: Bitline 921: Padding 923: Padding 925: Filler material 927: Filler material 1000: STT switching MRAM memory unit; memory unit 1002: Magnetic tunneling interface 1006: Electrical conductor; conductor; top conductor 1008: Electrical conductor; conductor; bottom conductor; lower conductor 1010: Upper ferromagnetic layer; Free layer FL; Free layer 1012: Lower ferromagnetic layer; Reference layer RL; Reference layer 1014: Tunneling Barrier 1050: Electron writing current 1052: Electron Writing Current 1100: Character line 1; First character line 1101: Free Layer 1102: MRAM device; MRAM 1103: Tunneling Energy Barrier 1105: Reference Layer 1109: Perimeter Switching Selector 1110: Bit line 1111: Free Layer 1112: MRAM device; MRAM 1113: Tunneling Barrier 1115: Reference Layer 1119: Limit Switching Selector 1120: Word Line 2 1220: Non-volatile memory unit 1222: MRAM cell 1224: Selector 1470: Switch 1472: Non-volatile memory unit 1474: Switch 1478: Low voltage sense amplifier; sense amplifier 1480: Switch 1482: Non-volatile memory unit 1483: High-voltage sensing amplifier; sensing amplifier 1484: Switch 1552: Non-volatile memory unit; First non-volatile memory unit 1554: Bit line switch 1556: Word line switch; WL switch 1558: First group of switches; First switch 1560: Second group of switches; Second switch; Switch 1562: Third group of switches; Third switch; Switch 1564: Fourth group of switches; Fourth switch 1566: Library control circuit; library control 1568: Module control circuit; module control; module logic 1592: Second non-volatile memory unit 1600: Memory chip 1602: Common control circuit; common circuit 1604: Common sensing amplifier 1606: Common Driver 1665: Word Line Switch 1780: Digital Media Control Circuit 1782: Address 1786: Location Information 1792: Signal 1820: Steps 1822: Steps 1824: Steps 1826: Steps 1828: Steps 1830: Steps 1840: Steps 1842: Steps 1844: Steps 1846: Steps 1900: Terminal circuit; terminal circuit system; terminal 1901: Level offset; LS 1903: Global Selection Switch GPS 1903-0~1903-31: Global positive selection switch GPS 1905: Global Deselection Switch GPD 1905-0~1905-31: Global positive / negative selection switch GPD 1907: Local Control Signals 1911: Local Control Signals 1913: Positive pane selection PMOS switch PPS 1915: Deselect NMOS switch PPD in positive pane. 1921: Level offset; LS 1923: Additional driver / inverter; component 1925-0~1925-31: Local positive selection switch LPS 1927-0~1927-31: Local positive selection switch LPS 1941: Level Offset 1943: Level Offset 1945: Driver / Inverter 1947-0~1947-31: PMOS LPD 1949-0~1949-31: PMOS LPD 1961: Level Offset 1963: Driver / Inverter; Component 1965-0~1965-31: Switch LNS 1967-0~1967-31: Switch LNS 1981: Level Offset 1983-0~1983-31: PMOS switch GND 1985-0~1985-31: NMOS switch GNS 1987: Local Control Signals 1991: Local Control Signals 1993: NPD 1995: NPS 2001:P substrate 2003: Deep N-type well 2010: Mijui NMOS 2011: Control gate 2013: Isolation of P-type well areas 2030: PMOS; PMOS switch 2031: Control Gate 2033: N-type well 2050: Triple Well NMOS 2051: Control Gate 2053: Isolate P-type well area 2080: N-type well; Triple-well NMOS 2090: N-type well 2101A: Left section; LNS array; NMOS LNS selection block; Local selection block 2101B: Right section; LNS array; NMOS LNS selection block 2103A: Block 2103B: Block 2105A: Block; Local block selection 2105B: Block 2107A: Left section; LPS array; Block; PMOS LPS switch 2107B: Right section; LPS array; Block; PMOS LPS switch 2109A: Left section; LPS array; Local selection block; PMOS LPS switch 2109B: Right section; LPS array; PMOS LPS switch 2111: Memory Unit 1; Unit 1 2111A: Block 2111B: Block 2113:OTS 1 2113A: Block; Local selection of block 2113B: Block 2115:BL 2115A: NMOS LNS switch; block 2115B: NMOS LNS switch; block 2117: Memory cell 0; Cell 0 2117A: NMOS LNS switch; Block; Local selection block 2117B: NMOS LNS switch; block 2119:OTS 0 2121: Global Negative Selection (GNS); GNS Region 2127: Global Positive Selection (GPS) 2129: Global Positive Selection (GPS) 2135: GNS switch 2137: GNS switch 2141A: Local Drive / Inverter 2141B: Local Drive / Inverter 2143A: Block 2143B: Block 2145A: Block 2145B: Block 2147A: Local Drive / Inverter 2147B: Local Drive / Inverter 2149A: Local Drive / Inverter 2149B: Local Drive / Inverter 2151A: Block 2151B: Block 2153A: Block 2153B: Block 2155A: Edge Driver / Inverter 2155B: Edge Driver / Inverter 2157A: Edge Driver / Inverter 2157B: Edge Driver / Inverter 2201: Layer 0 (character line); Layer; Layer WL0; WL0 2203: Wordline layer WL1; layer; WL1 2205: Bit line layer; layer; layer BL; BL 2301: Word Line Layer 0; Decoder Layer; Word Line Layer 0 Decoder 2303: Word line layer 1; Decoder layer; Bit line layer; Layer 2305: Bitline layer; decoder layer; bitline layer decoder 2323: Broken Wire Block 2401: NMOS LNS block; block 2403: PMOS LPD block; block 2405: PMOS LPS block; block 2407: PMOS LPD block; block 2409: NMOS LNS block; block 2411: NMOS LNS block; block 2413: PMOS LPD block; block 2415: PMOS LPS block; block 2417: PMOS LPD block; block; segment 2419: NMOS LNS block; block 2421: Section 2423: Section 2425: Section 2501A: Connection Area 2501B: Connection Area 2503: Line 2701: Steps 2703: Steps 2705: Steps 2707: Steps 2711: Steps VNN: Supply voltage; Second supply voltage; Negative voltage; Second voltage; First voltage VPP: First supply voltage; positive voltage; first voltage BL 1~BL N: Bit lines; top conductors WL 1~WL M: Word lines; bottom guide lines WL 1,1~WL 1,4: Word lines WL 2,1~WL 2,4: Second group of letter lines Vth: Threshold voltage Iread: constant current; current; reading current RP, RAP: Resistor Voffset: Constant voltage difference Vref: Reference voltage R WL, R BL: Variable resistors

Claims

1. A non-volatile memory device comprising: a control circuit configured to be connected to an array including a first plurality of non-volatile memory cells, the array having a crosspoint structure in which each of the first plurality of memory cells in the crosspoint structure is connected between one of a plurality of bit lines and one of a plurality of first word lines, the control circuit including a first bipolar decoder configured to be connected to the array to selectively bias one of the first bit lines or one of the first word lines to one of a positive voltage level, a ground voltage level, or a negative voltage level, the first bipolar decoder including: a plurality of local negative selection switches, each configured to supply the negative voltage level to one of the first bit lines or the first word lines corresponding to one of the first ones; A plurality of local positive selector switches, each configured to supply the positive voltage level to a corresponding one of the first word lines or the first bit lines; a first subgroup of a plurality of local positive selector switches and local negative selector switches is located on a die and between a first subgroup and a second subgroup of another plurality of local positive selector switches and local negative selector switches; a plurality of connection points, each configured to connect a corresponding one of the first word lines or the first bit lines, the connection points being centrally located in a wiring area above the first subgroup of the local positive selector switches and local negative selector switches; and a plurality of metal wires, each connecting a corresponding one of the local negative selector switches or the local positive selector switches to a corresponding one of the connection points.

2. The non-volatile memory device as claimed in claim 1, wherein the locally positive select-on PMOS devices and the locally negative select-on NMOS devices.

3. The non-volatile memory device of claim 1, wherein the first bipolar decoder further comprises: a plurality of local ground selection switches, each configured to set one of the first bit lines or the first word lines to ground, a first subgroup of the local ground selection switches located on the die and between the first subgroups of a plurality of the local positive selection switches and the local negative selection switches, located on the die and between the first subgroups of the other of the local positive selection switches and the local negative selection switches, and a second subgroup of the local ground selection switches located on the die and between the first subgroups of a plurality of the local positive selection switches and the local negative selection switches, located on the die and between the second subgroups of the other of the local positive selection switches and the local negative selection switches.

4. The non-volatile memory device as claimed in claim 1, wherein one of the local positive selection switches and the local negative selection switches is the local negative selection switch.

5. The non-volatile memory device as claimed in claim 1, wherein: The first subgroup of the plurality of local positive selectors and local negative selectors is located on the die and between the first subgroup of the local positive selectors and local negative selectors and a second subgroup of the plurality of the local positive selectors and local negative selectors, and the second subgroup of the plurality of the local positive selectors and local negative selectors is located on the die and between the first subgroup of the local positive selectors and local negative selectors and a third subgroup of the plurality of the local positive selectors and local negative selectors.

6. The non-volatile memory device of claim 1, wherein the first bipolar decoder is configured to be connected to the array to selectively bias the equivalent bit lines, the control circuitry further comprising: a second bipolar decoder configured to be connected to the memory array to selectively bias the equivalent first word lines, wherein the second bipolar decoder and the first bipolar decoder are mounted on the die, one on top of the other.

7. The non-volatile memory device of claim 6, wherein the array further comprises a second plurality of non-volatile memory cells, wherein each of the second plurality of memory cells is connected between one of the plurality of bit lines and one of the plurality of second word lines, the control circuitry further comprising: a third bipolar decoder configured to be connected to the array to selectively bias the second word lines, wherein the third bipolar decoder, the second bipolar decoder, and the first bipolar decoder are positioned on the die, one above the other.

8. The non-volatile memory device of claim 1, further comprising the array, wherein the array is located on the die and above the first bipolar decoder.

9. The non-volatile memory device of claim 1, wherein the control circuitry is formed on a control die, the non-volatile memory device further comprising: a memory die including the array, the memory die being separate from and bonded to the control die.

10. The non-volatile memory device of claim 1, further comprising the array wherein the memory cells are magnetoresistive random access memory (MRAM) cells.

11. The non-volatile memory device of claim 1, further comprising the array wherein the memory cells are phase change memory (PCM) memory cells.

12. The non-volatile memory device of claim 1, further comprising the array, wherein the first bipolar decoder further comprises: a plurality of global negative selection switches, each configured to receive a corresponding global negative selection signal and provide the corresponding global negative selection signal to a plurality of the local negative selection switches; and a plurality of global positive selection switches, each configured to receive a corresponding global positive selection signal and provide the corresponding global positive selection signal to a plurality of the local positive selection switches.

13. The non-volatile memory device as claimed in claim 12, wherein: The global negative selector switches are located on the die and among a plurality of the local negative selector switches, and the global positive selector switches are located on the die and among a plurality of the local positive selector switches.

14. A method for operating non-volatile memory cells, comprising: forming a bipolar decoder circuit on a first die for a first set of control lines for a crosspoint memory array of non-volatile memory cells, each of the non-volatile memory cells being connected between one of the first set of control lines and one of the second set of control lines, comprising: forming a plurality of positive voltage selection switches, each configured to supply a positive voltage level to one corresponding to one of the first set of control lines, including forming a first subgroup and a second subgroup of the plurality of positive voltage selection switches on the first die; A plurality of negative voltage selector switches are formed, each configured to supply a negative voltage level to a corresponding one of the first group of control lines. This includes forming a first subgroup of the plurality of negative voltage selector switches on the first die between the first subgroup and the second subgroup of the plurality of positive voltage selector switches; and a plurality of metal lines are formed above the positive voltage selector switches and the negative voltage selector switches, each of the metal lines connecting a corresponding one of the positive voltage selector switches or the negative voltage switches to a connection in the first group of control lines, the connections being located above a central region of the first die.

15. The method of claim 14, further comprising: forming the crosspoint memory array above the bipolar decoder circuit on the first die.

16. The method of claim 14, further comprising: forming the crossover memory array on a second die; and bonding the first die and the second die together.

17. The method of claim 14, wherein the positive select-on PMOS devices and the negative select-on NMOS devices.

18. A memory device comprising: a non-volatile memory cell structure including non-volatile memory cells arranged at an intersection, each memory cell having a programmable resistive element and connected between one of a plurality of first control lines and one of a plurality of second control lines; and one or more control circuits connected to the memory cell structure, comprising: a plurality of first decoding switches, each configured to bias one of the first control lines to a positive voltage level corresponding to the first control line; A plurality of second decoding switches, each configured to bias one of the first control lines to a negative voltage level, a first subgroup of the plurality of second decoding switches located on a die and between a first subgroup of the plurality of first decoding switches and a second subgroup of the plurality of first decoding switches; and a plurality of routing lines, each connecting one of the first or second decoding switches to a corresponding connection point of one of the first control lines, the connection points being located above the first subgroup of the second decoding switches.

19. The memory device of claim 18, wherein the non-volatile memory cell structure is located on the die and above the first decoding switch, the second decoding switches, and the routing lines, the non-volatile memory cell structure further comprising: A plurality of through holes, each connecting one of the first control lines to the corresponding connection point.

20. The memory device of claim 18, wherein the one or more control circuits further comprises: a plurality of third decoding switches, each configured to bias one of the first control lines to ground, a first subgroup of the plurality of third decoding switches located on the die and between the first subgroups of the second decoding switches and the first subgroups of the first decoding switches, and a second subgroup of the plurality of third decoding switches located on the die and between the first subgroups of the second decoding switches and the second subgroups of the first decoding switches.

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