Semiconductor device and methods of formation

Abstract

A high-voltage transistor includes an asymmetric gate dielectric layer and / or a gate structure including one or more asymmetric work function metal layers. The gate dielectric layer and / or the work function metal layer are asymmetric because the heights of the gate dielectric layer and / or the work function metal layer on opposite sides of the gate structure are different. Specifically, the height of the gate dielectric layer and / or the height of the work function metal layer on the gate structure facing the drain region of the high-voltage transistor is lower than the height of the gate dielectric layer and / or the work function metal layer on the gate structure facing the source region of the high-voltage transistor.

Description

Technical Field

[0001] none Prior Technology

[0002] A high-voltage transistor includes a transistor configured to operate at a higher voltage (e.g., high gate voltage and high drain voltage) compared to a medium-voltage transistor and a low-voltage transistor, and a medium-voltage transistor includes a transistor configured to operate at a higher voltage (e.g., high gate voltage and high drain voltage) compared to a low-voltage transistor. The maximum voltage that a medium-voltage transistor can withstand (without damage) may be lower than the maximum voltage that a high-voltage transistor can withstand (without damage), and the maximum voltage that a low-voltage transistor can withstand (without damage) is lower than the maximum voltage that a medium-voltage transistor can withstand (without damage). Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. [] Figure 1 is a partial schematic diagram of an example of a semiconductor device described in this article. Figures 2A and 2B are schematic diagrams of an embodiment in which a fin structure for a high voltage transistor is formed in the device layer of the semiconductor element described herein. Figure 3 is a schematic diagram of an embodiment in which a dummy gate structure for a high voltage transistor is formed in the device layer of the semiconductor element described herein. Figures 4A to 4D are schematic diagrams of embodiments in which source / drain regions for high voltage transistors are formed in the device layer of the semiconductor device described herein. Figures 5A to 5R are schematic diagrams of embodiments of alternative gate processes for high-voltage transistors in the device layer of the semiconductor device described herein. Figures 6A to 6F are schematic diagrams of embodiments of the gate trimming process of a high-voltage transistor in the device layer of the semiconductor device described herein. Figure 7 is a schematic diagram of an embodiment of the contact formation process of a high voltage transistor in the device layer of the semiconductor device described herein. Figure 8 is a schematic diagram of an embodiment of the depletion region of the high voltage transistor of the semiconductor device described herein. Figure 9 is a flowchart of a process embodiment 900 related to the formation of the semiconductor element described herein. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0007] In other examples, high-voltage and medium-voltage transistors can be used in many applications, such as integrated circuit (IC) drivers, power integrated circuits, shift registers, image sensors, power management, radio frequency (RF) power amplifiers, display driver ICs (DDICs), bipolar complementary metal-oxide-semiconductor (CMOS) diffused metal-oxide-semiconductor (DMOS) ICs (BCD ICs) and / or image signal processor (ISP) ICs.

[0008] In some cases, high-voltage transistors may be susceptible to performance defects such as leakage current and / or parasitic capacitance. Gate-induced drain leakage current (GIDL) may occur in high-voltage transistors. GIDL is a form of subcritical leakage current below the critical voltage of the high-voltage transistor that occurs between the source and drain due to electron tunneling. High-voltage transistors may be particularly susceptible to GIDL because the overlap between the depletion region in the transistor channel and the drain region can occur due to the high voltage applied to the drain region. Since GIDL occurs at the subcritical voltage, it increases the transistor's off-current (Ioff), thereby increasing the transistor's power consumption.

[0009] In other examples, parasitic capacitance may occur in various regions of the high-voltage transistor, such as between the gate structure and the source / drain contacts, or via the gate dielectric layer between the gate structure and the channel region, and / or due to the overlap between the gate structure and the drain region. Parasitic capacitance reduces the switching speed of the high-voltage transistor, thus increasing its resistance-capacitance delay (RC delay).

[0010] In some embodiments described herein, a high-voltage transistor includes an asymmetric gate dielectric layer and a gate structure having one or more asymmetric work function metal layers. The gate dielectric layer and the work function metal layer are asymmetric because the heights of the gate dielectric layer and the work function metal layer on opposite sides of the gate structure differ. Specifically, the height of the gate dielectric layer and the height of the work function metal layer on the drain side of the gate structure facing the drain region of the high-voltage transistor are lower than the heights of the gate dielectric layer and the work function metal layer on the source side of the gate structure facing the source region of the high-voltage transistor. The lower height of the gate dielectric layer and the work function metal layer on the drain side of the gate structure reduces (or prevents) the overlap between the depletion region and the drain region, which reduces the electron tunneling effect (and the amount of GIDL in the high-voltage transistor) and the amount of parasitic capacitance (Cov) of gate-to-drain overlap in the high-voltage transistor. Therefore, the lower height of the gate dielectric layer and work function metal layer on the drain side of the gate structure enables high voltage transistors to achieve low off-state current leakage and faster switching speeds (e.g., due to lower RC delay).

[0011] Figure 1 is a partial schematic diagram of a semiconductor element 100 according to an embodiment described herein. The semiconductor element 100 includes a system-on-a-chip (SoC) device, logic devices such as a central processing unit (CPU) or a graphics processing unit (GPU), memory devices (e.g., high bandwidth memory (HBM) devices), panel driver devices, integrated circuit (IC) drivers, radio frequency (RF) power amplifiers, display driver ICs (DDICs), and / or other types of semiconductor elements.

[0012] As shown in Figure 1, the semiconductor device 100 includes a device layer 102 and an interconnect layer 104 above the device layer 102 in the z-direction of the semiconductor device 100. The device layer 102 includes a substrate layer 106. The substrate layer 106 corresponds to a portion of a semiconductor wafer on which the semiconductor device 100 is formed. The substrate layer 106 includes a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. The substrate layer 106 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0013] A dielectric layer 108 is contained above a substrate layer 106. The dielectric layer 108 includes an interlayer dielectric (ILD) layer (e.g., an ILD0 layer), an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 108 contains a dielectric material that allows portions of the substrate layer 106 to be selectively etched or prevented from being etched, and / or may electrically isolate integrated circuit elements 110 in the device layer 102. The dielectric layer 108 contains silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or another type of dielectric material. The dielectric layer 108 may extend in the x-direction and / or y-direction of the semiconductor element 100.

[0014] Integrated circuit element 110 is contained within and / or on the substrate layer 106 of semiconductor element 100, and / or contained within the dielectric layer 108 of the device layer 102 of semiconductor element 100. Integrated circuit element 110 includes transistors (such as planar transistors, finFETs, gate-all-around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of semiconductor elements.

[0015] The integrated circuit element 110 includes a plurality of source / drain regions 112, which are grown and / or otherwise formed on and around portions of the substrate layer 106. "Source / drain region" may refer individually or collectively to a source or drain, depending on the context. The source / drain regions 112 may be formed by epitaxial growth of doped semiconductor regions and / or by another semiconductor process. In some embodiments, the source / drain regions 112 are formed in recessed portions in the substrate layer 106. These recessed portions are formed by strained source / drain (SSD) etching and / or another type of etching operation on the substrate layer 106.

[0016] The integrated circuit element 110 further includes a gate dielectric layer 114 between the gate structure 116 and the substrate layer 106. In some embodiments, the gate dielectric layer 114 comprises a low-k dielectric material, such as silicon oxide (SiO₂x). In some embodiments, the gate dielectric layer 114 comprises a high-k dielectric material, such as hafnium oxide (HfO₂x). The gate structure 116 is laterally located between the source / drain regions 112. In some embodiments, the gate structure 116 is formed of polycrystalline silicon. In these embodiments, the polycrystalline silicon material may be doped with one or more types of dopants (e.g., p-type dopants, n-type dopants) to adjust the work function of the gate structure 116. In some embodiments, the gate structure 116 is made of one or more metallic materials (e.g., tungsten (W), titanium (T), cobalt (Co), and / or another metal). In some embodiments, the gate structure 116 may include one or more types of metal (e.g., p-type metal, n-type metal) to adjust the work function of the gate structure 116.

[0017] In other examples, sidewall spacers 118 are included on the sidewalls of the gate structure 116 to provide electrical isolation for the gate structure 116. The sidewall spacers 118 comprise silicon oxide (SiOx), silicon nitride (SixNy), silicon oxide (SiOC), silicon carbonitride (SiOCN), and / or other suitable materials.

[0018] The source / drain region 112 is electrically and / or physically coupled to the source / drain contact 120. The source / drain contact 120 includes contact vias, contact plugs, and / or another type of contact structure electrically connecting the source / drain region 112 of the integrated circuit element 110 to the interconnect layer 104 of the semiconductor element 100. The source / drain contact 120 contains cobalt (Co), ruthenium (Ru), and / or another conductive material or metallic material. One or more pad layers 122 are included on the sidewalls of the source / drain contact 120. The pad layer 122 includes a barrier layer, an adhesion layer, or an adhesive layer. The barrier layer is coated to prevent or minimize material diffusion from the source / drain contact 120 to the surrounding dielectric layer, and the adhesion layer or adhesive layer is included to promote adhesion between the source / drain contact 120 and the surrounding dielectric layer and / or another type of pad. Examples of materials used for the liner layer 122 include titanium nitride (TiN), tantalum nitride (TaN), and / or another suitable liner material.

[0019] Gate structure 116 is electrically and / or physically coupled to gate contact 124. Gate contact 124 includes contact vias, contact plugs, and / or another type of contact structure electrically connecting gate structure 116 of integrated circuit element 110 to interconnect layer 104 of semiconductor element 100. Alternatively, gate structure 116 may be directly electrically and / or physically coupled to interconnect layer 104. Gate contact 124 includes cobalt (Co), ruthenium (Ru), and / or another conductive material or metallic material. One or more pad layers 126 are included on the sidewalls of gate contact 124. Pad layer 126 includes a barrier layer, an adhesion layer, or an adhesive layer. The barrier layer is included to prevent or minimize the diffusion of material from gate contact 124 to the surrounding dielectric layer, and the adhesion layer or adhesive layer is included to promote adhesion between gate contact 124 and the surrounding dielectric layer and / or another type of pad. Examples of materials used for the liner layer 126 include titanium nitride (TiN), tantalum nitride (TaN), and / or another suitable liner material.

[0020] In some embodiments, one or more integrated circuit elements 110 include a high-voltage transistor (or a medium-voltage transistor). "High-voltage transistor" refers to a transistor configured to operate at a higher supply voltage (e.g., a higher gate voltage, a higher source / drain voltage) than a low-voltage transistor. As an example, a high-voltage transistor may be configured to operate in a drain voltage range of about 9 volts to about 36 volts, while a low-voltage transistor may be configured to operate in a drain voltage range of about 0 volts to about 1.8 volts. However, other values ​​within these ranges are also within the scope of this disclosure.

[0021] In some embodiments, a high-voltage transistor can be a high-voltage planar transistor structure comprising one or more planar channels. In some embodiments, a high-voltage transistor can be a high-voltage fin field-effect transistor structure comprising one or more fin channels. In some embodiments, a high-voltage transistor can be a high-voltage all-around gate transistor structure comprising one or more nanostructured channels. Figures 2A to 2B, 3, 4A to 4D, 5A to 5R, 6A to 6F, and 7 illustrate embodiments of various process operations for forming a high-voltage transistor (e.g., a high-voltage transistor comprising one or more fin channels).

[0022] The interconnect layer 104 of the semiconductor device 100 is contained above the substrate layer 106 in the z-direction of the semiconductor device 100 and above the integrated circuit element 110. The interconnect layer 104 includes a plurality of dielectric layers arranged along a direction generally perpendicular to the substrate layer 106 (such as the z-direction). The dielectric layers may include dielectric layers 128 and etch stop layers 130 arranged alternately along the z-direction. The dielectric layers 128 and etch stop layers 130 may extend in the semiconductor device 100 along the x-direction and / or the y-direction.

[0023] The dielectric layer 128 may each comprise an oxide (such as silicon oxide (SiOx) and / or another oxide material), undoped silica glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), tetraethyl silicate (TEOS), hydrogen silsesquioxane photoresist (HSQ), and / or another suitable dielectric material. In some embodiments, the dielectric layer 128 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant of less than about 2.5. Other examples of dielectric materials with extremely low dielectric constants include carbon-doped silicon oxide (C-SiOx), fluorinated amorphous carbon (aCxFy), parylene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxide (SiOC) polymers, porous hydrogen silsesquioxane photoresist (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), and / or porous silicon oxide (SiOx), etc.

[0024] The etch stop layer 130 may each comprise silicon nitride (SixNi), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the dielectric layer 128 and the etch stop layer 130 comprise different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 104.

[0025] Interconnect layer 104 includes multiple conductive structures. These conductive structures are electrically and / or physically coupled to one or more integrated circuit elements 110 in device layer 102 and / or one or more integrated circuit elements 110 in interconnect layer 104. The conductive structures enable the supply of signals and / or power to the integrated circuit elements 110 and / or the supply of signals and / or power from the integrated circuit elements 110.

[0026] The conductive structure comprises a combination of a metallization structure 132 and an interconnect structure 134. The metallization structure 132 may include trenches, conductive traces, and / or other types of conductive structures extending primarily in the x-direction and / or y-direction of the interconnect layer 104. The interconnect structure 134 may include vias, conductive plugs, conductive pillars, and / or other types of conductive structures extending primarily in the z-direction of the semiconductor element. In some embodiments, the conductive structure in the interconnect layer 104 comprises a dual damascene structure, which includes a combination of the metallization structure 132 and the interconnect structure 134.

[0027] In other examples, the metallization structure 132 and the interconnect structure 134 may each comprise one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, one or more padding layers are included between the metallization structure 132 and / or the interconnect structure 134 and the surrounding dielectric layer in the interconnect layer 104. The one or more padding layers may comprise barrier pads, adhesion pads, and / or another type of pad. In other examples, examples of materials used for one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0028] In some embodiments, the metallization structure 132 and the interconnect structure 134 of the interconnect layer 104 may be arranged in a vertical manner (e.g., along the z-direction). In other words, multiple stacked metallization structures 132 and interconnect structures 134 may extend between the top of the device layer 102 and the interconnect layer 104 to facilitate the transmission of electrical signals and / or power between the device layer 102 and the connection structure (not shown) of the semiconductor element 100. Multiple stacked metallization structures 132 may be arranged in a layer referred to as the M layer. For example, the metal O (M0) layer may be located at the bottom of the interconnect layer 104 and may be directly coupled to the device layer 102 (e.g., coupled to the source / drain contacts 120 and / or gate contacts 124 of the integrated circuit element 110 in the device layer 102). A via 1 (V1) layer containing one or more interconnect structures 134 may be included above the metal O layer. Metal 1 (M1) layer can be located above via 1 layer in interconnect layer 104, via 2 (V2) layer can be contained above metal 1 layer, metal 2 (M2) layer can be located above via 2 layer, and so on. In addition, via layers can be contained between vertically arranged M layers.

[0029] As described above, Figure 1 is used as an example. Other examples may differ from those shown in Figure 1.

[0030] Figures 2A and 2B are schematic diagrams of Embodiment 200 in which a fin structure for a high-voltage transistor is formed in the device layer 102 of the semiconductor element 100 described herein. As shown in Figure 2A, one or more operations in Embodiment 200 can be performed in conjunction with the substrate layer 106 of the semiconductor element 100. The substrate layer 106 may be provided as a semiconductor wafer or another type of substrate.

[0031] As shown in Figure 2B, the fin structure 202 is formed in the substrate layer 106 of the semiconductor element 100. In some embodiments, each integrated circuit element 110a and 110b may form the fin structure 202. Integrated circuit element 100a may include an n-type transistor structure (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and integrated circuit element 110b may include a p-type transistor structure (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The NMOS and PMOS transistors enable complementary metal-oxide-semiconductor (CMOS) circuitry to be executed in the semiconductor element 100.

[0032] In some embodiments, the pattern in the photoresist layer is used to form the fin structure 202. In these embodiments, a deposition tool can be used to form the photoresist layer on the substrate layer 106 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the substrate layer 106 to form the fin structure 202. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes residual portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). Furthermore and / or alternatively, other patterning and etching techniques can be used to form the fin structure 202, such as multiple imaging techniques including dual imaging techniques (e.g., self-aligned dual imaging (SADP)) and / or quadruple imaging techniques (e.g., self-aligned quadruple imaging (SAQP)).

[0033] Further, as shown in Figure 2B, the fin structure 202 may extend vertically above the substrate layer 106 in the z-direction of the semiconductor element 100. Furthermore, the fin structure 202 may extend laterally along the substrate layer 106 in the x-direction of the semiconductor element 100. The fin structure 202 may be arranged in the y-direction of the semiconductor element 100.

[0034] As described above, Figures 2A and 2B are used as examples. Other examples may differ from those shown in Figures 2A and 2B.

[0035] Figure 3 is a schematic diagram of an embodiment 300 in which a dummy gate structure for a high-voltage transistor is formed in the device layer 102 of the semiconductor element 100 described herein. In some embodiments, one or more of the semiconductor process operations described in Figure 3 may be performed after one or more of the semiconductor process operations described in Figures 2A and / or 2B.

[0036] As shown in Figure 3, one or more dummy gate structures 302 may be formed above the fin structures 202 of integrated circuit elements 110a (e.g., NMOS transistors) and 110b (e.g., PMOS transistors). In some embodiments, integrated circuit elements 110a and 110b form separate dummy gate structures 302. In some embodiments, the same dummy gate structure 302 spans the fin structures 202 of integrated circuit elements 110a and 110b.

[0037] The term "dummy" as used herein refers to a sacrificial structure that is removed later in the process of forming the integrated circuit elements 110a and 110b, and is replaced by another structure such as a metal gate structure (e.g., gate structure 116). The dummy gate structure 302 may comprise a polysilicon structure and / or a structure comprising another suitable material that can be selectively removed in subsequent processing operations. The process of replacing the dummy gate structure 302 is called the replacement gate process. "Replacement gate process" refers to the fabrication of gate structure 116 later in the overall gate process. Figures 5A through 5R illustrate and describe embodiments of the replacement gate process.

[0038] In other examples, deposition tools may be used to deposit the dummy gate structure 302 using physical vapor deposition (PVD), chemical vapor deposition (CVD) techniques (e.g., low-pressure CVD (LPCVD) and / or plasma-enhanced CVD (PECVD)), atomic layer deposition (ALD), and / or another suitable deposition technique. In some embodiments, a polycrystalline silicon material layer is deposited, patterned, and etched to define the dummy gate structure 302. In some embodiments, after depositing the dummy gate structure 302, a planarization tool is used to perform a planarization operation (e.g., chemical mechanical planarization (CMP)) to planarize the dummy gate structure 302.

[0039] Further, as shown in Figure 3, the dummy gate structure 302 can wrap around the fin structures 202 of integrated circuit elements 110a and 110b on at least three sides of the fin structure 202. In some embodiments, a portion of the dummy gate structure 302 is deposited on the substrate layer 106. Alternatively, a shallow trench isolation insulating layer (STI) region can be formed on a portion of the substrate layer 106 adjacent to the fin structure 202, such that the dummy gate structure 302 is deposited on the STI region instead of on the substrate layer 106. The STI region provides electrical isolation for the gate structure 116, which is formed to replace the dummy gate structure 302, thereby reducing gate leakage current through the substrate layer 106.

[0040] In some embodiments, sidewall spacers 118 are formed on the sidewalls of the dummy gate structure 302. Sidewall spacers 118 can be retained in alternative gate processes such that they are included between the gate structure 116 of the integrated circuit element 110a and / or the source / drain region.

[0041] As mentioned above, Figure 3 is used as an example. Other examples may differ from those shown in Figure 3.

[0042] Figures 4A through 4D are schematic diagrams of an embodiment 400 in which a source / drain region for a high-voltage transistor is formed in the device layer 102 of the semiconductor element 100 described herein. In some embodiments, one or more semiconductor process operations described in Figures 4A through 4D may be performed after one or more of the semiconductor process operations described in Figures 2A, 2B, and / or 3.

[0043] As shown in Figure 4A, source / drain regions 112a and 112b can be formed on the fin structure 202 of the integrated circuit element 110a (e.g., an NMOS high-voltage transistor), such that the source / drain regions 112a and 112b are laterally adjacent to the opposite sides of the dummy gate structure 302 in the x-direction. Similarly, source / drain regions 112a and 112b can be formed on the fin structure 202 of the integrated circuit element 110b (e.g., a PMOS high-voltage transistor), such that the source / drain regions 112a and 112b are laterally adjacent to the opposite sides of the dummy gate structure 302 in the x-direction.

[0044] In some embodiments, source / drain region 112a may be referred to as the source region of integrated circuit elements 110a and 110b, and source / drain region 112b may be referred to as the drain region of integrated circuit elements 110a and 110b. In some embodiments, source / drain region 112b may be configured to operate at high voltages of up to about 36 volts or higher.

[0045] Source / drain regions 112a and 112b can be formed in grooves within the fin structure 202. The fin structure 202 can be etched (e.g., using an etching tool) to form the grooves, and the etching operation used to form the grooves can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique.

[0046] The deposition tool can utilize epitaxial growth technology to form source / drain regions 112a and 112b in a groove, wherein epitaxial material layers of source / drain regions 112a and 112b are grown in the groove, such that n-type source / drain material layers (e.g., for integrated circuit element 110a) and / or p-type source / drain material layers (e.g., for integrated circuit element 110b) are formed by epitaxial growth along a specific crystal axis. The material used to form the source / drain regions 112a and 112b of integrated circuit element 110a (e.g., silicon (Si), germanium (Ge), gallium (Ga), or another type of semiconductor material) can be doped with an n-type dopant (e.g., a dopant containing electron-donating atoms and capable of generating mobile electrons in the material). The materials used to form the source / drain regions 112a and 112b of the integrated circuit element 110b (e.g., silicon (Si), germanium (Ge), gallium (Ga), or another type of semiconductor material) can be doped with p-type dopants (e.g., a dopant containing electron acceptor atoms that can generate holes in the material). The materials of the source / drain regions 112a and 112b can be doped by adding impurities (e.g., p-type dopants, n-type dopants) using a gas source used in the epitaxial operation. Other examples of p-type dopants that can be used in the epitaxial operation include boron (B) or gallium (Ga). Other examples of n-type dopants that can be used in the epitaxial operation include phosphorus (P) or arsenic (As).

[0047] Figure 4B illustrates a cross-sectional view along line segment AA (e.g., along the fin structure 202 of integrated circuit element 110a in the x-direction) and along line segment BB (e.g., along the fin structure 202 of integrated circuit element 110b in the x-direction) in Figure 4A. As shown in Figure 4B, source / drain regions 112a and 112b are located on opposite sides of the dummy gate structure 302 of integrated circuit elements 110a and 110b. Source / drain regions 112a and 112b may be included on the fin structure 202 and may extend into the fin structure 202. Furthermore, source / drain regions 112a and 112b may extend above the top of the fin structure 202.

[0048] As shown in Figures 4C and 4D, dielectric layer 108 may be formed on and / or above the source / drain regions 112a and 112b of integrated circuit elements 110a and 110b. Dielectric layer 108 fills the area surrounding the dummy gate structure 302 and the area above the source / drain regions 112a and 112b. Dielectric layer 108 may be formed to define the space created by removing the dummy gate structure 302. Therefore, dielectric layer 108 serves as a self-aligned mask to form gate structure 116 in the area previously occupied by dummy gate structure 302.

[0049] The deposition tool can use PVD, CVD, ALD, oxidation, and / or another suitable deposition technique to deposit the dielectric layer 108. In some embodiments, after depositing the dielectric layer 108, a planarization tool is used to perform a planarization operation (e.g., CMP) to planarize the dielectric layer 108. In some embodiments, the dielectric layer 108 is formed to a certain height (or thickness) such that the dielectric layer 108 covers the dummy gate structure 302. In these embodiments, the CMP operation removes material from the dielectric layer 108 such that the top surface of the dielectric layer 108 is substantially coplanar with the top surface of the dummy gate structure 302.

[0050] As described above, Figures 4A through 4D are used as examples. Other examples may differ from those shown in Figures 4A through 4D.

[0051] Figures 5A through 5R are schematic diagrams of an embodiment 500 of an alternative gate process for a high-voltage transistor in the device layer 102 of the semiconductor element 100 described herein. In some embodiments, one or more semiconductor process operations described in Figures 5A through 5R may be performed after one or more semiconductor process operations described in Figures 2A, 2B, 3, and / or 4A through 4D.

[0052] As shown in Figures 5A and 5B, the alternative gate process includes removing the dummy gate structure 302 from integrated circuit element 110a (e.g., an NMOS transistor) and integrated circuit element 110b (e.g., a PMOS transistor). In some embodiments, an etching tool is used to perform one or more etching operations to remove the dummy gate structure 302. The one or more etching operations may include wet etching operations, dry etching operations (e.g., gas-based etching operations, plasma-based etching operations), and / or another type of etching technique.

[0053] Further, as shown in Figures 5A and 5B, after removing the dummy gate structure 302, a groove 502 is left in the dielectric layer 108 between the source / drain regions 112a and 112b of the integrated circuit elements 110a and 110b.

[0054] As shown in Figures 5C and 5D, a gate dielectric layer 114 is formed in the recess 502 of the n-type gate structure 116a of the integrated circuit element 110a and the p-type gate structure 116b of the integrated circuit element 110b. The gate dielectric layer 114 can be formed on the bottom surface of the recess 502 and on the sidewalls facing the source / drain regions 112a and 112b. The gate dielectric layer 114 can also be formed on the top and sidewalls of the fin structure 202 exposed in the recess 502. In some embodiments, the gate dielectric layer 114 is formed on the top surface of the dielectric layer 108.

[0055] The deposition tool can use PVD, CVD, ALD, and / or another suitable deposition technique to deposit the gate dielectric layer 114. Conformal deposition techniques can be used to deposit the gate dielectric layer 114 so that the gate dielectric layer 114 conforms to the surface and / or contour of the groove 502.

[0056] As shown in Figures 5E and 5F, the p-type work function metal layer 504 is formed in the grooves 502 for the n-type gate structure 116a and the p-type gate structure 116b. The p-type work function metal layer 504 can also be formed along the top surface of the dielectric layer 108. The deposition tools can use PVD, CVD, ALD and / or another suitable deposition technique to deposit the p-type work function metal layer 504.

[0057] A p-type work function metal layer 504 can be deposited on the gate dielectric layer 114 of the groove 502, such that the p-type work function metal layer 504 is formed on the bottom surface of the groove 502 and on the sidewalls of the groove 502 facing the source / drain regions 112a and 112b. The p-type work function metal layer 504 can also be formed on the top and sidewalls of the fin structure 202 exposed in the groove 502.

[0058] In other examples, the p-type work function metal layer 504 may comprise one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or another metal with a work function greater than about 4.7 electron volts (eV). The p-type work function metal layer 504 may be included to modulate the work function of the p-type gate structure 116b, such that the work function is tuned to approach the valence band of the material of the substrate layer 106.

[0059] As shown in Figure 5F, the p-type work function metal layer 504 can be one-dimensional or multi-dimensional. For example, the p-type work function metal layer 504 can have sidewall segments contained in the sidewall of the recess 502, wherein sidewall segment 504a faces the source / drain region 112a of the integrated circuit element 110a, and another sidewall segment 504b faces the source / drain region 112b of the integrated circuit element 110a. Similarly, sidewall segment 504a of the p-type work function metal layer 504 can face the source / drain region 112a of the integrated circuit element 110b, and another sidewall segment 504b of the p-type work function metal layer 504 can face the source / drain region 112a of the integrated circuit element 110b. The bottom segment 504c of the p-type work function metal layer 504 can be contained on the bottom surface of the recess 502, contained on the fin structure 202 exposed through the recess 502.

[0060] After forming the p-type work function metal layer 504, the bottom segment 504c of the p-type work function metal layer 504 may have a vertical thickness (e.g., the z-direction thickness indicated by dimension D1 in Figure 5F). After forming the p-type work function metal layer 504, the sidewall segments 504a and 504b may have a vertical height (e.g., the z-direction height indicated by dimension D2 in Figure 5F) and a lateral thickness (e.g., the x-direction thickness indicated by dimension D3 in Figure 5F). The vertical height of the sidewall segments 504a and 504b may be greater than the sidewall height of the groove 502. The lateral thicknesses of the sidewall segments 504a and 504b may be approximately equal on the sidewalls of the groove 502. Furthermore, the vertical thickness of the bottom segment 504c may be substantially uniform on the bottom surface of the groove 502.

[0061] As shown in Figures 5G to 5J, a portion of the p-type work function metal layer 504 can be removed from the n-type gate structure 116a of the integrated circuit element 110a. The p-type work function metal layer 504 can be removed from the n-type gate structure 116a so that it does not adversely affect the work function regulation of the n-type gate structure 116a.

[0062] As shown in Figures 5G and 5H, a masking layer 508 may be formed over the integrated circuit element 110b, including over the p-type gate structure 116b in the recess 502. In some embodiments, the masking layer 508 is a hard masking layer (e.g., a silicon nitride (SixNy) layer, a silicon oxynitride (SiON) layer) and is deposited using a deposition tool employing PVD, CVD, and / or another suitable deposition technique. In some embodiments, the masking layer 508 is a photoresist layer and is deposited using a deposition tool employing spin coating. In some embodiments, the masking layer 508 is also deposited over the integrated circuit element 110a and subsequently removed from the integrated circuit element 110a (e.g., by etching and / or photolithography), leaving the masking layer 508 on the integrated circuit element 110b.

[0063] As shown in Figures 5I and 5J, the p-type work function metal layer 504 can be etched based on the masking layer 508 to remove the p-type work function metal layer 504 from the n-type gate structure 116a. The masking layer 508 protects the p-type work function metal layer 504 on the p-type gate structure 116b, so that the p-type work function metal layer 504 remains on the p-type gate structure 116b. The etching tool can utilize wet etching techniques, dry etching techniques (e.g., gas-based etching, plasma-based etching), and / or another suitable etching technique to etch the p-type work function metal layer 504.

[0064] After removing a portion of the p-type work function metal layer 504 from the n-type gate structure 116a, the remaining portion of the mask layer 508 can be removed from the semiconductor element 100. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the mask layer 508 (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0065] As shown in Figures 5K and 5L, an n-type work function metal layer 506 is formed in grooves 502 for n-type gate structure 116a and for p-type gate structure 116b. For p-type gate structure 116b, the n-type work function metal layer 506 can be deposited on p-type work function metal layer 504. The n-type work function metal layer 506 can also be formed along the top surface of dielectric layer 108. The n-type work function metal layer 506 can be deposited using deposition tools via PVD, CVD, ALD, and / or another suitable deposition technique.

[0066] An n-type work function metal layer 506 can be deposited in a groove 502, such that the n-type work function metal layer 506 is formed on the bottom surface of the groove 502 and on the sidewalls of the groove 502 facing the source / drain regions 112a and 112b. The n-type work function metal layer 506 can also be formed on the top and sidewalls of the fin structure 202 exposed in the groove 502.

[0067] The n-type work function metal layer 506 may comprise one or more metallic materials that adjust or regulate the work function of the n-type gate structure 116a near the conduction band of the substrate layer 106 of the semiconductor element 100. In some embodiments, the n-type work function metal layer 506 comprises titanium aluminum (TiAl). In some embodiments, the n-type work function metal layer 506 comprises titanium aluminum carbon (TiAlC). In some embodiments, the n-type work function metal layer 506 comprises another aluminum-containing metal. In some embodiments, the n-type work function metal layer 506 comprises another n-type metallic material.

[0068] As shown in Figure 5L, the n-type work function metal layer 506 can be one-dimensional or multi-dimensional. For example, the n-type work function metal layer 506 can have sidewall segments contained in the sidewalls of the recess 502, wherein sidewall segment 506a faces the source / drain region 112a of the integrated circuit element 110a, and another sidewall segment 506b faces the source / drain region 112b of the integrated circuit element 110a. Similarly, the sidewall segments of the n-type work function metal layer 506 can face the source / drain region 112a of the integrated circuit element 110b, and another sidewall segment of the n-type work function metal layer 506 can face the source / drain region 112a of the integrated circuit element 110b. The bottom segment of the n-type work function metal layer 506 can be contained on the bottom surface of the recess 502, including on the fin structure 202 exposed through the recess 502.

[0069] After forming the n-type work function metal layer 506, the bottom section of the n-type work function metal layer 506 may have a vertical thickness (e.g., the z-direction thickness indicated by dimension D4 in Figure 5L). After forming the n-type work function metal layer 506, the sidewall sections may have a vertical height (e.g., the z-direction height indicated by dimension D5 in Figure 5L) and a lateral thickness (e.g., the x-direction thickness indicated by dimension D6 in Figure 5L). The vertical height of the sidewall sections may be greater than the sidewall height of the groove 502. The lateral thickness of the sidewall sections may be approximately equal on the sidewalls of the groove 502. Furthermore, the vertical thickness of the bottom section may be substantially uniform on the bottom surface of the groove 502.

[0070] As shown in Figures 5M and 5N, the masking layer 510 may be formed over a portion of the integrated circuit element 110a and a portion of the integrated circuit element 110b, and may extend into a portion of the recess 502. For example, the masking layer 510 may be formed over a first portion of the n-type work function metal layer 506 of the integrated circuit element 110a, including a portion of the bottom section and the sidewall section of the n-type work function metal layer 506, which is located on the sidewall of the recess 502 facing the source / drain region 112a of the integrated circuit element 110a. In other examples, the masking layer 510 may be formed over a first portion of the n-type work function metal layer 506 of the integrated circuit element 110b, including over a portion of the bottom section of the n-type work function metal layer 506 and over a sidewall section of the n-type work function metal layer 506 located on the sidewall of the recess 502 facing the source / drain region 112a of the integrated circuit element 110b.

[0071] In some embodiments, mask layer 510 is a hard mask layer (e.g., a silicon nitride (SixNy) layer, a silicon oxynitride (SiON) layer) and is deposited using a deposition tool employing PVD, CVD, and / or another suitable deposition technique. In some embodiments, mask layer 508 is a photoresist layer and is deposited using a deposition tool employing spin coating. In some embodiments, mask layer 510 fills the entire area of ​​groove 502 and is subsequently patterned by etching and / or photolithography.

[0072] As shown in Figures 50 and 5P, a second portion of the n-type work function metal layer 506 in the recess 502 between the source / drain regions 112a and 112b of the integrated circuit element 110a can be etched based on the mask layer 510. Similarly, a second portion of the n-type work function metal layer 506 in the recess 502 between the source / drain regions 112a and 112b of the integrated circuit element 110b can be etched based on the mask layer 510. This results in the second portion of the n-type work function metal layer 506 having a smaller thickness than the first portion of the n-type work function metal layer 506 covered by the mask layer 510.

[0073] The masking layer 510 may cover only a portion of the recess 502, allowing etchant to be supplied into the recess 502 to etch the second portion of the n-type work function metal layer 506. The etchant may contain a wet etchant that omnidirectionally (e.g., isotropically) etches the second portion of the n-type work function metal layer 506. This allows the thickness of the second portion of the n-type work function metal layer 506 to be reduced in a substantially uniform manner. However, other etching techniques, including gas-based etching techniques and / or plasma-based etching techniques, are also within the scope of this disclosure.

[0074] As shown in Figure 5P, the bottom segment 506d of the n-type work function metal layer 506 of the n-type gate structure 116a beneath the masking layer 510 maintains an initial vertical thickness (e.g., dimension D4). However, another bottom segment 506e of the n-type work function metal layer 506 of the n-type gate structure 116a exposed through the masking layer 510 has a vertical (z-direction) thickness (indicated as dimension D7 in Figure 5P), which is less than the vertical thickness of the bottom segment 506d. A transition segment 506f of the n-type work function metal layer 506 of the n-type gate structure 116a is located between the bottom segments 506d and 506e. The transition segment 506f may have a non-uniform vertical (z-direction) thickness. In the transition segment 506f, the vertical (z-direction) thickness transitions between the vertical thickness of the bottom segment 506d and the vertical thickness of the bottom segment 506e. In some embodiments, the transition section 506f has an inclined top surface such that the vertical thickness of the transition section 506f gradually and substantially uniformly decreases from the bottom section 506d to the bottom section 506e. Alternatively, the transition section 506f may have a stepped top surface or another top surface profile.

[0075] In some embodiments, the thickness difference between the vertical thickness (dimension D4) of the bottom segment 506d of the n-type work function metal layer 506 and the vertical thickness (dimension D7) of the bottom segment 506e of the n-type work function metal layer 506 can be contained in the range of about 12 angstroms to about 42 angstroms. If the difference is less than about 12 angstroms, the vertical height of the sidewall segment 506b may not be sufficiently reduced in the subsequent gate trimming process described in conjunction with Figures 6A to 6F to achieve a sufficiently low GIDL for the integrated circuit element 110a. If the difference is greater than about 42 angstroms, the vertical height of the sidewall segment 506b may be reduced by too much, which may increase the likelihood of a gate-to-drain short circuit in the integrated circuit element 110a and / or may reduce the breakdown voltage of the integrated circuit element 110a. However, in addition to the range between approximately 12 angstroms and approximately 42 angstroms, other values ​​and ranges between the vertical thickness of the bottom segment 506d and the vertical thickness of the bottom segment 506e of the n-type work function metal layer 506 are also within the scope of this disclosure.

[0076] In some embodiments, the lateral width of the transition section 506f (denoted as dimension D8 in Figure 5P) may be within the range of approximately 12 angstroms to approximately 42 angstroms. If the lateral width of the transition section 506f is less than approximately 12 angstroms, the vertical height of the sidewall section 506b may not be sufficiently reduced in the subsequent gate trimming process described in conjunction with Figures 6A to 6F to achieve a sufficiently low GIDL for the integrated circuit element 110a. If the lateral width of the transition section 506f is greater than approximately 42 angstroms, the vertical height of the sidewall section 506b may be reduced by too much, which may increase the likelihood of a gate-to-drain short circuit in the integrated circuit element 110a and / or may reduce the breakdown voltage of the integrated circuit element 110a. However, other values ​​and ranges of the lateral width of the transition section 506f, in addition to the range between approximately 12 angstroms and approximately 42 angstroms, are also within the scope of this disclosure.

[0077] Further, as shown in Figure 5P, the sidewall segment 506a of the n-type work function metal layer 506 of the n-type gate structure 116a, facing the source / drain region 112a, maintains an initial lateral thickness (e.g., dimension D6). However, the sidewall segment 506b of the n-type work function metal layer 506 of the n-type gate structure 116a, facing the source / drain region 112b, has a smaller lateral thickness than the sidewall segment 506a (represented as dimension D9 in Figure 5P). The smaller lateral thickness of the sidewall segment 506b allows its vertical height to be reduced at a faster rate than that of the sidewall segment 506a in subsequent gate trimming processes described in conjunction with Figures 6A to 6F.

[0078] Further, as shown in Figure 5P, the bottom segment 506d of the n-type work function metal layer 506 of the p-type gate structure 116b beneath the masking layer 510 maintains an initial vertical thickness (e.g., dimension D4). However, another bottom segment 506e of the n-type work function metal layer 506 of the p-type gate structure 116b exposed through the masking layer 510 has a vertical (z-direction) thickness (denoted as dimension D10 in Figure 5P), which is less than the vertical thickness of the bottom segment 506d. A transition segment 506f of the n-type work function metal layer 506 of the p-type gate structure 116b is located between the bottom segments 506d and 506e. The transition segment 506f may have a non-uniform vertical (z-direction) thickness. In the transition segment 506f, the vertical (z-direction) thickness transitions between the vertical thickness of the bottom segment 506d and the vertical thickness of the bottom segment 506e. In some embodiments, the transition section 506f has an inclined top surface such that the vertical thickness of the transition section 506f gradually and substantially uniformly decreases from the bottom section 506d to the bottom section 506e. Alternatively, the transition section 506f may have a stepped top surface or another top surface profile.

[0079] In some embodiments, the thickness difference between the vertical thickness (dimension D4) of the bottom segment 506d of the n-type work function metal layer 506 and the vertical thickness (dimension D10) of the bottom segment 506e of the n-type work function metal layer 506 can be contained in the range of about 12 angstroms to about 42 angstroms. If the difference is less than about 12 angstroms, the vertical height of the sidewall segment 506b may not be sufficiently reduced in the subsequent gate trimming process described in conjunction with Figures 6A to 6F to achieve a sufficiently low GIDL for the integrated circuit element 110b. If the difference is greater than about 42 angstroms, the vertical height of the sidewall segment 506b may be reduced by too much, which may increase the likelihood of a gate-to-drain short circuit in the integrated circuit element 110b and / or may reduce the breakdown voltage of the integrated circuit element 110b. However, in addition to the range between approximately 12 angstroms and approximately 42 angstroms, other values ​​and ranges between the vertical thickness of the bottom segment 506d and the vertical thickness of the bottom segment 506e of the n-type work function metal layer 506 are also within the scope of this disclosure.

[0080] In some embodiments, the lateral width of the transition section 506f (denoted as dimension D11 in Figure 5P) may be within the range of approximately 12 angstroms to approximately 42 angstroms. If the lateral width of the transition section 506f is less than approximately 12 angstroms, the vertical height of the sidewall section 506b may not be sufficiently reduced in the subsequent gate trimming process described in conjunction with Figures 6A to 6F to achieve a sufficiently low GIDL for the integrated circuit element 110b. If the lateral width of the transition section 506f is greater than approximately 42 angstroms, the vertical height of the sidewall section 506b may be reduced by too much, which may increase the likelihood of a gate-to-drain short circuit in the integrated circuit element 110b and / or may reduce the breakdown voltage of the integrated circuit element 110b. However, other values ​​and ranges of the lateral width of the transition section 506f, in addition to the range between approximately 12 angstroms and approximately 42 angstroms, are also within the scope of this disclosure.

[0081] Further, as shown in Figure 5P, the sidewall segment 506a of the n-type work function metal layer 506 of the p-type gate structure 116b, facing the source / drain region 112a, maintains an initial lateral thickness (e.g., dimension D6). However, the sidewall segment 506b of the n-type work function metal layer 506 of the p-type gate structure 116b facing the source / drain region 112b has a smaller lateral thickness than the sidewall segment 506a (represented as dimension D12 in Figure 5P). The smaller lateral thickness of the sidewall segment 506b allows the vertical height of the sidewall segment 506b to be reduced at a faster rate than the vertical height of the sidewall segment 506a in subsequent gate trimming processes described in conjunction with Figures 6A to 6F.

[0082] After removing a portion of the n-type work function metal layer 506 from the n-type gate structure 116a, the remaining portion of the mask layer 510 can be removed from the semiconductor element 100. In some embodiments, a photoresist removal tool is used to remove the remaining portion of the mask layer 508 (e.g., using chemical strippers, plasma ashing, etching, and / or other techniques).

[0083] As shown in Figures 5Q and 5R, the groove 502 can be filled into the gate electrode 512. The gate electrode 512 of the n-type gate structure 116a can be formed on the n-type work function metal layer 506 in the groove 502 between the source / drain regions 112a and 112b of the integrated circuit element 110a. The gate electrode 512 of the p-type gate structure 116b can be formed on the n-type work function metal layer 506 in the groove 502 between the source / drain regions 112a and 112b of the integrated circuit element 110b. The gate electrode 512 can overfill the groove 502 and can be formed above the dielectric layer 108. Therefore, the planarization tool can be used to perform CMP operation or another type of planarization operation to planarize the excess material on the gate electrode 512, p-type work function metal layer 504 and n-type work function metal layer 506 on the dielectric layer, so that the gate electrode 512, p-type work function metal layer 504 and n-type work function metal layer 506 are approximately coplanar with the top surface of the dielectric layer 108.

[0084] In other examples, the gate electrode 512 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). Deposition tools can be used to deposit the gate electrode 512 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The gate electrode 512 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the gate electrode 512 is deposited on the seed layer.

[0085] Further, as shown in Figure 5R, the bottom segment 506d of the n-type work function metal layer 506 is located below the first portion of the gate electrode 512 of the n-type gate structure 116a, the bottom segment 506e of the n-type work function metal layer 506 is located below the second portion of the gate electrode 512 of the n-type gate structure 116a, and the transition segment 506f of the n-type work function metal layer 506 is located below the third portion of the gate electrode 512 of the n-type gate structure 116a. The bottom segment 506d is adjacent to the sidewall segment 506a of the n-type work function metal layer 506 of the n-type gate structure 116a, and the bottom segment 506e is adjacent to the sidewall segment 506b of the n-type work function metal layer 506 of the n-type gate structure 116a.

[0086] The bottom segment 506d of the n-type work function metal layer 506 is located below the first portion of the gate electrode 512 of the p-type gate structure 116b, the bottom segment 506e of the n-type work function metal layer 506 is located below the second portion of the gate electrode 512 of the p-type gate structure 116b, and the transition segment 506f of the n-type work function metal layer 506 is located below the third portion of the gate electrode 512 of the p-type gate structure 116b. The bottom segment 506d is adjacent to the sidewall segment 506a of the n-type work function metal layer 506 of the p-type gate structure 116b, and the bottom segment 506e is adjacent to the sidewall segment 506b of the n-type work function metal layer 506 of the p-type gate structure 116b.

[0087] After planarization, the sidewall segments 506a and 506b of the n-type work function metal layer 506 in the n-type gate structure 116a can each have approximately a height in the z-direction (dimension D13). After planarization, the sidewall segments 506a and 506b of the p-type work function metal layer 504 can each have approximately the same height in the z-direction (dimension D13). After planarization, the sidewall segments 506a and 506b of the n-type work function metal layer 506 in the p-type gate structure 116b can each have approximately a height in the z-direction (dimension D14).

[0088] As described above, Figures 5A through 5R are used as examples. Other examples may differ from those shown in Figures 5A through 5R.

[0089] Figures 6A through 6F are schematic diagrams of an embodiment 600 of a gate trimming process for a high-voltage transistor in the device layer 102 of the semiconductor element 100 described herein. In some embodiments, one or more semiconductor process operations described in conjunction with Figures 6A through 6F may be performed after one or more semiconductor process operations described in conjunction with Figures 2A, 2B, 3, 4A through 4D, and / or 5A through 5R.

[0090] As shown in Figures 6A and 6B, the sidewall segments 506a and 506b of the n-type work function metal layer 506 of the n-type gate structure 116a and the sidewall segments 506a and 506b of the n-type work function metal layer 506 of the p-type gate structure 116b may be etched during the gate trimming process. The p-type work function metal layer 504 of the p-type gate structure 116b can also be etched in a similar manner. In some embodiments, removal operations may be performed to etch, planarize, and / or otherwise remove the surface oxide layer from the n-type gate structure 116a and the p-type gate structure 116b, enabling the gate trimming process to be performed.

[0091] In some embodiments, in the gate trimming process, an etching tool is used to perform wet etching to etch sidewall segments 506a and 506b. A wet etchant can be used on sidewall segments 506a and 506b, and the wet etchant can selectively etch sidewall segments 506a and 506b while minimizing or not etching gate electrodes 512 and gate dielectric layer 114 of n-type gate structure 116a and p-type gate structure 116b. However, other etching techniques including gas-based etching techniques and / or plasma-based etching techniques are also within the scope of the present disclosure.

[0092] As shown in FIG. 6B, this results in a reduction in the vertical (z-direction) height of sidewall segments 506a and 506b of the n-type work function metal layer 506 of n-type gate structure 116a (e.g., from dimension D13 to dimension D15). Since the lateral thickness of sidewall segment 506b is less than the lateral thickness of sidewall segment 506a, the vertical height of sidewall segment 506b decreases at a faster rate than the vertical height of sidewall segment 506a during the gate trimming process (because less material needs to be removed from sidewall segment 506b). The faster reduction in the vertical height of sidewall segment 506b results in the vertical height of sidewall segment 506b (indicated as dimension D16 in FIG. 6B) being less than the vertical height of sidewall segment 506a (e.g., D16 < D15). The lower height of sidewall segment 506b of the n-type work function metal layer 506 on the sidewall of n-type gate structure 116a facing source / drain region 112b enables source / drain region 112b to achieve less erosion of the depletion region in substrate layer 106, which reduces the amount and / or likelihood of electron tunneling effects (and thus off-state current leakage) that may occur due to GIDL in integrated circuit element 110a, and enables integrated circuit element 110a to achieve a low gate-drain parasitic capacitance (Cgd).

[0093] In some embodiments, after the gate and trimming process, the vertical height (dimension D15) of sidewall segment 506a of the n-type work function metal layer 506 can be in the range between approximately 86 angstroms and approximately 186 angstroms. A vertical height value of sidewall segment 506a less than about 86 angstroms may result in a high gate resistance (Rg) of n-type gate structure 116a. A vertical height value of sidewall segment 506a greater than about 186 angstroms may result in an increased high gate-drain parasitic capacitance (Cgd) and / or an increased likelihood of shorting of n-type gate structure 116a to source / drain contact 120. However, other values and ranges for the vertical height of sidewall segment 506a other than about 86 angstroms to about 186 angstroms are also within the scope of the present disclosure.

[0094] In some embodiments, after the gate trimming process, the vertical height (dimension D16) of the sidewall segment 506b of the n-type work function metal layer 506 can be included in the range of approximately 46 angstroms to approximately 146 angstroms. A vertical height value of less than approximately 46 angstroms may result in a high gate resistance (Rg) of the n-type gate structure 116a. A vertical height value of more than approximately 146 angstroms may result in a high gate-drain parasitic capacitance (Cgd) and / or an increased likelihood of a short circuit between the n-type gate structure 116a and the source / drain contact 120. However, other values ​​and ranges of the vertical height of the sidewall segment 506b besides approximately 46 angstroms to approximately 146 angstroms are also within the scope of this disclosure.

[0095] In some embodiments, the height difference (indicated as dimension D17 in Figure 6B) between the height of the top surface of sidewall segment 506a and the height of the top surface of sidewall segment 506b may be in the range of about 40 angstroms to about 140 angstroms. If the difference between the height of the top surface of sidewall segment 506a and the height of the top surface of sidewall segment 506b is less than about 40 angstroms, the height of the top surface of sidewall segment 506b may not be low enough to achieve a sufficiently low GIDL in integrated circuit element 110a. If the difference between the height of the top surface of sidewall segment 506a and the height of the top surface of sidewall segment 506b is greater than about 140 angstroms, the likelihood of a gate-drain short circuit in integrated circuit element 110a may increase, and / or the breakdown voltage of integrated circuit element 110a may decrease. However, in addition to the range of approximately 40 angstroms to approximately 140 angstroms, other values ​​and ranges of the height difference between the top surface of sidewall section 506a and the top surface of sidewall section 506b are also within the scope of this disclosure.

[0096] Further, as shown in Figure 6B, the vertical (z-direction) height of the sidewall segments 506a and 506b of the n-type work function metal layer 506 of the p-type gate structure 116b can be reduced (e.g., from dimension D14 to dimension D18). The vertical height of the segment of the p-type work function metal layer 504 between the sidewall segment 506a and the gate dielectric layer 114 of the p-type gate structure 116b can also be reduced (e.g., from dimension D13 to dimension D19).

[0097] Because the lateral thickness of the sidewall section 506b is less than that of the sidewall section 506a, the vertical height of the sidewall section 506b decreases at a faster rate than the vertical height of the sidewall section 506a during the gate trimming process (e.g., because less material needs to be removed from the sidewall section 506b). The faster decrease in the vertical height of the sidewall section 506b results in the vertical height of the sidewall section 506b (indicated as dimension D20 in FIG. 6B) being less than the vertical height of the sidewall section 506a (e.g., D20 < D18). The lower height of the sidewall section 506b of the n-type work function metal layer 506 on the sidewall of the p-type gate structure 116b facing the source / drain region 112b enables the source / drain region 112b to achieve less erosion of the depletion region in the substrate layer 106, which reduces the amount and / or likelihood of electron tunneling effect (and thus off-state current leakage) that may occur due to GIDL in the integrated circuit element 110b, and enables the integrated circuit element 110b to achieve a low gate-drain parasitic capacitance (Cgd). The vertical height of the section of the p-type work function metal layer 504 between the sidewall section 506b of the p-type gate structure 116b and the gate dielectric layer 114 can also be reduced (e.g., from dimension D14 to dimension D21).

[0098] In some embodiments, after the gate trimming process, the vertical height (dimension D18) of the sidewall section 506a of the n-type work function metal layer 506 can be in the range between approximately 86 angstroms and approximately 186 angstroms. A vertical height value of the sidewall section 506a less than about 86 angstroms may result in a high gate resistance (Rg) of the p-type gate structure 116b. A vertical height value of the sidewall section 506a greater than about 186 angstroms may result in an increased high gate-drain parasitic capacitance (Cgd) and / or an increased likelihood of short-circuiting between the p-type gate structure 116b and the source / drain contact 120. However, other values and ranges of the vertical height of the sidewall section 506a other than about 86 angstroms to about 186 angstroms are also within the scope of this disclosure.

[0099] In some embodiments, after the gate trimming process, the vertical height (dimension D20) of the sidewall section 506b of the n-type work function metal layer 506 can be in the range between approximately 46 angstroms and approximately 146 angstroms. A vertical height value of the sidewall section 506b less than about 46 angstroms may result in a high gate resistance (Rg) of the p-type gate structure 116b. A vertical height value of the sidewall section 506b greater than about 146 angstroms may result in an increased high gate-drain parasitic capacitance (Cgd) and / or an increased likelihood of short-circuiting between the p-type gate structure 116b and the source / drain contact 120. However, other values and ranges of the vertical height of the sidewall section 506b other than about 46 angstroms to about 146 angstroms are also within the scope of this disclosure.

[0100] In some embodiments, the height difference (indicated as dimension D22 in Figure 6B) between the height of the top surface of sidewall section 506a and the height of the top surface of sidewall section 506b may be in the range of about 40 angstroms to about 140 angstroms. If the difference between the height of the top surface of sidewall section 506a and the height of the top surface of sidewall section 506b is less than about 40 angstroms, the height of the top surface of sidewall section 506b may not be low enough to achieve a sufficiently low GIDL in integrated circuit element 110b. If the difference between the height of the top surface of sidewall section 506a and the height of the top surface of sidewall section 506b is greater than about 140 angstroms, the likelihood of a gate-drain short circuit in integrated circuit element 110b may increase, and / or the breakdown voltage of integrated circuit element 110b may decrease. However, in addition to the range of approximately 40 angstroms to approximately 140 angstroms, other values ​​and ranges of the height difference between the top surface of sidewall section 506a and the top surface of sidewall section 506b are also within the scope of this disclosure.

[0101] As shown in Figures 6C and 6D, the gate trimming process may include trimming portions of the gate dielectric layer 114 on the sidewalls of the n-type gate structure 116a and the p-type gate structure 116b. In some embodiments, wet etching is performed using an etching tool to etch the portions of the gate dielectric layer 114 on the sidewalls of the n-type gate structure 116a and the p-type gate structure 116b. A wet etchant may be applied to the portions of the gate dielectric layer 114 on the sidewalls of the n-type gate structure 116a and the p-type gate structure 116b. The wet etchant may selectively etch the gate dielectric layer 114 while minimally etching or not etching the p-type work function metal layer 504, the n-type work function metal layer 506, and the gate electrode 512. However, other etching techniques, including gas-based etching techniques and / or plasma-based etching techniques, are also within the scope of this disclosure.

[0102] As shown in Figure 6D, the vertical height of a portion of the gate dielectric layer 114 on the sidewall of the n-type gate structure 116a is reduced. The top surface of the portion of the gate dielectric layer 114 between the dielectric layer 108 and the sidewall segment 506a, and the top surface of the sidewall segment 506a, can be approximately coplanar. The top surface of the portion of the gate dielectric layer 114 between the dielectric layer 108 and the sidewall segment 506b, and the top surface of the sidewall segment 506b, can also be approximately coplanar. Therefore, the vertical height of a portion of the gate dielectric layer 114 on the sidewall of the n-type gate structure 116a is also non-uniform, because the vertical height of the portion of the gate dielectric layer 114 facing the source / drain region 112b (indicated as dimension D23 in Figure 6D) is smaller than the vertical height of the portion of the gate dielectric layer 114 facing the source / drain region 112a (indicated as dimension D24 in Figure 6D). In some embodiments, the ratio of dimension D24 to dimension D23 is contained in the range of about 1.9:1 to about 4:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0103] Further, as shown in Figure 6D, the vertical height of the portion of the gate dielectric layer 114 located on the sidewall of the p-type gate structure 116b is reduced. The top surface of the portion of the gate dielectric layer 114 between the dielectric layer 108 and the sidewall segment 506a, and the top surface of the sidewall segment 506a, can be approximately coplanar. Therefore, the vertical height of the portion of the gate dielectric layer 114 on the sidewall of the p-type gate structure 116b is also non-uniform, because the vertical height of the portion of the gate dielectric layer 114 facing the source / drain region 112b (indicated by dimension D25 in Figure 6D) is smaller than the vertical height of the portion of the gate dielectric layer 114 facing the source / drain region 112a (indicated by dimension D26 in Figure 6D).

[0104] In some embodiments, the height difference (indicated as dimension D27 in Figure 6D) between the top surface of the portion of the gate dielectric layer 114 on the sidewall of the n-type gate structure 116a facing the source / drain region 112a of the integrated circuit element 110a and the top surface of the portion of the gate dielectric layer 114 on the sidewall of the n-type gate structure 116a facing the source / drain region 112b of the integrated circuit element 110a can be in the range of about 40 angstroms to about 140 angstroms. If the height difference is less than about 40 angstroms, the height of the portion of the gate dielectric layer 114 facing the source / drain region 112b may not be low enough to achieve a sufficiently low GIDL in the integrated circuit element 110a. If the height difference is greater than about 140 angstroms, the likelihood of a gate-drain short circuit in the integrated circuit element 110a may increase, and / or the breakdown voltage of the integrated circuit element 110a may decrease. However, apart from the range of approximately 40 angstroms to approximately 140 angstroms, other values ​​and ranges of this height difference are also within the scope of this disclosure.

[0105] In some embodiments, the height difference (indicated as dimension D28 in Figure 6D) between the top surface of the portion of the gate dielectric layer 114 on the sidewall of the p-type gate structure 116b facing the source / drain region 112a of the integrated circuit element 110b and the top surface of the portion of the gate dielectric layer 114 on the sidewall of the p-type gate structure 116b facing the source / drain region 112b of the integrated circuit element 110b can be contained in the range of about 40 angstroms to about 140 angstroms. If the height difference is less than about 40 angstroms, the height of the portion of the gate dielectric layer 114 facing the source / drain region 112b may not be low enough to achieve a sufficiently low GIDL in the integrated circuit element 110b. If the height difference is greater than about 140 angstroms, the likelihood of a gate-drain short circuit in the integrated circuit element 110b may increase, and / or the breakdown voltage of the integrated circuit element 110b may decrease. However, apart from the range of approximately 40 angstroms to approximately 140 angstroms, other values ​​and ranges of this height difference are also within the scope of this disclosure.

[0106] As shown in Figures 6E and 6F, the gate trimming process may include trimming the gate electrodes 512 of the n-type gate structure 116a and the p-type gate structure 116b. In some embodiments, wet etching is performed using an etching tool to etch the gate electrodes 512. A wet etchant may be used on the gate electrodes 512, and the wet etchant may selectively etch the gate electrodes 512 while minimally etching or not etching the p-type work function metal layer 504, the n-type work function metal layer 506, and the gate dielectric layer 114. However, other etching techniques, including gas-based etching techniques and / or plasma-based etching techniques, are also within the scope of this disclosure.

[0107] Further, as shown in Figure 6F, the top surface of the gate electrode 512 of the n-type gate structure 116a can be approximately coplanar with the top surface of the sidewall section 506a of the n-type work function metal layer 506. The top surface of the gate electrode 512 of the n-type gate structure 116a can be higher than the top surface of the sidewall section 506b of the n-type work function metal layer 506. The top surface of the gate electrode 512 of the p-type gate structure 116b can be approximately coplanar with the top surface of the sidewall section 504a of the p-type work function metal layer 504. The top surface of the gate electrode 512 of the p-type gate structure 116b can be higher than the top surface of the sidewall section 504b of the p-type work function metal layer 504.

[0108] As described above, Figures 6A through 6F are used as examples. Other examples may differ from those shown in Figures 6A through 6F.

[0109] Figure 7 is a schematic diagram of an embodiment 700 of the contact formation process of a high-voltage transistor in the device layer 102 of the semiconductor element 100 described herein. In some embodiments, one or more semiconductor process operations described in conjunction with Figure 7 may be performed after one or more semiconductor process operations described in conjunction with Figures 2A, 2B, 3, 4A to 4D, 5A to 5R, and / or 6A to 6F.

[0110] As shown in Figure 7, the capping layer 702 can be formed over the n-type gate structure 116a of the integrated circuit element 110a (e.g., an NMOS transistor) and the p-type gate structure 116b of the integrated circuit element 110b (e.g., a PMOS transistor). The deposition tool can use CVD, PVD, ALD, oxidation, and / or another suitable deposition technique to deposit the capping layer 702. In some embodiments, after depositing the capping layer 702, a planarization tool is used to perform a planarization operation (e.g., a CMP operation) to planarize the capping layer 702.

[0111] Further, as shown in Figure 7, the source / drain contact 120 can pass through the dielectric layer 108 and be formed on the source / drain regions 112a and 112b of the integrated circuit elements 110a and 110b. The source / drain regions 112a and 112b can be formed in a groove in the dielectric layer 108. For example, the groove can be formed above the source / drain regions 112a and 112b, and the source / drain contact 120 can be formed in the groove so that the source / drain contact 120 rests on the source / drain regions 112a and 112b.

[0112] In some embodiments, the pattern in the photoresist layer is used to form grooves in the dielectric layer 108. In these embodiments, a deposition tool can be used to form the photoresist layer over the dielectric layer 108. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through the dielectric layer 108 to form grooves. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based groove formation.

[0113] Deposition tools can be used to deposit the source / drain contacts 120 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The source / drain contacts 120 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the source / drain contacts 120 are deposited on the seed layer. In some embodiments, a liner layer 122 is deposited in a recess, and the source / drain contacts 120 are deposited on the liner layer 122 in the recess. The liner layer 122 may include barrier liner, adhesion liner, and / or other suitable liner. Examples of liner materials include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials. In some embodiments, after depositing the source / drain contacts 120, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the source / drain contacts 120.

[0114] As mentioned above, Figure 7 is used as an example. Other examples may differ from those shown in Figure 7.

[0115] Figure 8 is a schematic diagram of an embodiment 800 of the depletion region of the high voltage transistor of the semiconductor element 100 described herein. Specifically, embodiment 800 includes an embodiment of a depletion region 802 of an integrated circuit element 110a (e.g., an NMOS high voltage transistor), which is caused by the lower height of the gate dielectric layer 114 and the lower height of the n-type work function metal layer 506 on the sidewall of the n-type gate structure 116a facing the source / drain region 112b.

[0116] As shown in Figure 8, the depletion region 802 does not intrude into or overlap with the source / drain region 112b. The spacing between the depletion region 802 and the source / drain region 112b reduces the amount and / or likelihood of electron tunneling (and therefore off-state current leakage), which could otherwise occur due to GIDL in the integrated circuit element 110a. Therefore, the lower height of the gate dielectric layer 114 and the lower height of the n-type work function metal layer 506 on the sidewall of the n-type gate structure 116a facing the source / drain region 112b increase the operating efficiency of the integrated circuit element 110a and reduce its power consumption.

[0117] Furthermore and / or alternatively, the spacing between the depletion region 802 and the source / drain region 112b enables the integrated circuit element 110a to achieve a low gate-drain parasitic capacitance (Cgd), because the spacing between the depletion region 802 and the source / drain region 112b provides a small amount of parasitic capacitance due to gate-drain overlap (Cov). Therefore, the lower height of the gate dielectric layer 114 and the lower height of the n-type work function metal layer 506 on the sidewall of the n-type gate structure 116a facing the source / drain region 112b reduce the RC delay of the n-type gate structure 116a, enabling the n-type gate structure 116a to switch more quickly.

[0118] As mentioned above, Figure 8 is used as an example. Other examples may differ from those shown in Figure 8.

[0119] Figure 9 is a flowchart of a process embodiment 900 associated with the formation of the semiconductor device described herein. In some embodiments, one or more semiconductor process tools are used to perform one or more process blocks of Figure 9, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor process tools.

[0120] As shown in Figure 9, process embodiment 900 may include forming a first source / drain region and a second source / drain region (block 910) of a transistor structure in a substrate layer of a semiconductor device. For example, as described herein, one or more semiconductor process tools may be used to form a first source / drain region (e.g., source / drain region 112a) and a second source / drain region (e.g., source / drain region 112b) of a transistor structure (e.g., integrated circuit element 110, integrated circuit element 110a, integrated circuit element 110b) in a substrate layer (e.g., substrate layer 106) of a semiconductor device (e.g., semiconductor element 100).

[0121] Further, as shown in Figure 9, process embodiment 900 may include forming a dielectric layer (block 920) over the first source / drain region and the second source / drain region. For example, as described herein, one or more semiconductor process tools may be used to form the dielectric layer (e.g., dielectric layer 108) over the first source / drain region and the second source / drain region.

[0122] Further, as shown in Figure 9, process embodiment 900 may include forming a gate dielectric layer (block 930) of a transistor structure in a groove in a dielectric layer laterally between the first source / drain region and the second source / drain region. For example, as described herein, one or more semiconductor process tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 114) of a transistor structure in a groove (e.g., groove 502) in a dielectric layer laterally between the first source / drain region and the second source / drain region. In some embodiments, the gate dielectric layer is formed on the first sidewall, the second sidewall, and the bottom surface of the groove.

[0123] Further, as shown in Figure 9, process embodiment 900 may include a work function metal layer (block 940) of a gate structure forming a transistor structure on the gate dielectric layer. For example, as described herein, a work function metal layer (e.g., n-type work function metal layer 506, p-type work function metal layer 504) of a gate structure (e.g., gate structure 116, n-type gate structure 116a, p-type gate structure 116b) of a transistor structure may be formed on the gate dielectric layer using one or more semiconductor process tools.

[0124] Further, as shown in Figure 9, process embodiment 900 may include a gate electrode (512) (block 950) forming a gate structure on the work function metal layer. For example, as described herein, the gate electrode (gate electrode 512) forming the gate structure on the work function metal layer may be formed using one or more semiconductor process tools.

[0125] Further, as shown in Figure 9, process embodiment 900 may include performing an etching operation to etch a first portion of the work function metal layer on the first sidewall and a second portion of the work function metal layer on the second sidewall (block 960). For example, as described herein, one or more semiconductor process tools may be used to perform the etching operation to etch the first portion of the work function metal layer on the first sidewall and the second portion of the work function metal layer on the second sidewall. In some embodiments, after the etching operation, a first vertical height (e.g., dimensions D15, D18, D19) of the first portion of the work function metal layer and a second vertical height (e.g., dimensions D16, D20, D21) of the second portion of the work function metal layer have different vertical heights.

[0126] Process embodiment 900 may include other embodiments, any single embodiment or any combination of embodiments described below, and / or one or more other related processes described elsewhere herein.

[0127] In the first embodiment, after the etching operation, the first vertical height of the first portion of the work function metal layer is greater than the second vertical height of the second portion of the work function metal layer.

[0128] In the second embodiment, either alone or in combination with the first embodiment, process embodiment 900 includes performing another etching operation before forming the gate electrode to etch a second portion of the work function metal layer on the second sidewall, wherein after the additional etching operation, the first lateral thickness (e.g., dimension D3, dimension D6) of the first portion of the work function metal layer is greater than the second lateral thickness (e.g., dimension D8, dimension D12) of the second portion of the work function metal layer.

[0129] In the third embodiment, the additional etching operation, performed alone or in combination with one or more of the first and second embodiments, includes performing the additional etching operation to etch a second portion of the work function metal layer on the second sidewall, while a masking layer (e.g., masking layer 510) protects a first portion of the work function metal layer on the first sidewall.

[0130] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, process embodiment 900 includes performing another etching operation to etch a third portion of the gate dielectric layer on the first sidewall and a fourth portion of the gate dielectric layer on the second sidewall, wherein after the additional etching operation, the third vertical height (e.g., dimension D24, dimension D26) of the third portion of the gate dielectric layer and the fourth vertical height (e.g., dimension D26, dimension D25) of the fourth portion of the gate dielectric layer have different vertical heights.

[0131] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, after the additional etching operation, the third vertical height of the third portion of the gate dielectric layer is greater than the fourth vertical height of the fourth portion of the gate dielectric layer.

[0132] While Figure 9 illustrates an example block of process embodiment 900, in some embodiments, process embodiment 900 includes more, fewer, different, or differently arranged blocks than those shown in Figure 9. Furthermore, or alternatively, two or more blocks in process embodiment 900 may be executed in parallel.

[0133] In this way, the high-voltage transistor comprises an asymmetric gate dielectric layer and a gate structure containing one or more asymmetric work function metal layers. The gate dielectric layer and the work function metal layer are asymmetric because the height of the gate dielectric layer differs from the height of the work function metal layer on the opposite side of the gate structure. Specifically, the height of the gate dielectric layer and the height of the work function metal layer on the gate structure side facing the drain region of the high-voltage transistor are lower than the height of the gate dielectric layer and the height of the work function metal layer on the opposite side of the gate structure facing the source region of the high-voltage transistor. The lower height of the gate dielectric layer and the work function metal layer on the drain side of the gate structure reduces (or prevents) the overlap between the depletion and drain regions, thereby reducing the amount of electron tunneling (and thus reducing the amount of GIDL in the high-voltage transistor) and the amount of gate-to-drain overlap parasitic capacitance (Cov) in the high-voltage transistor. Therefore, the lower height of the gate dielectric layer and work function metal layer on the drain side of the gate structure enables the high voltage transistor to achieve low off-state current leakage and faster switching speed (e.g., due to lower RC delay).

[0134] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first source / drain region located in a substrate layer of the semiconductor device. The semiconductor device includes a second source / drain region in the substrate layer. The semiconductor device includes a gate structure laterally located between the first source / drain region and the second source / drain region. The gate structure includes a gate electrode and a work function metal layer located between the gate electrode and the substrate layer. A first segment of the work function metal layer extends along a first side of the gate electrode facing the first source / drain region. A second segment of the work function metal layer extends along a second side of the gate electrode facing the second source / drain region. A first height of the first segment of the work function metal layer is greater than a second height of the second segment of the work function metal layer.

[0135] In some embodiments described herein, a semiconductor device is provided. The semiconductor device includes a third segment located below a first portion of a gate electrode. The third segment is adjacent to the first segment and has a first thickness. The semiconductor device includes a fourth segment located below a second portion of a gate electrode. The fourth segment is adjacent to the second segment and has a second thickness. The first thickness of the third segment and the second thickness of the fourth segment are different thicknesses.

[0136] In some embodiments described herein, a semiconductor device is provided. The semiconductor device includes a third segment located below a first portion of a gate electrode. The third segment is adjacent to the first segment and has a first thickness. The semiconductor device includes a fourth segment located below a second portion of a gate electrode. The fourth segment is adjacent to the second segment and has a second thickness. The second thickness of the fourth segment is less than the first thickness of the third segment.

[0137] In some embodiments described herein, a semiconductor device is provided. The work function metal layer of the semiconductor device includes a transition segment laterally located between a third segment and a fourth segment.

[0138] In some embodiments described herein, a semiconductor device is provided. The work function metal layer of the semiconductor device has a transitional section laterally located between a third segment and a fourth segment, having a non-uniform thickness that transitions between a first thickness of the third segment and a second thickness of the fourth segment.

[0139] In some embodiments described herein, a semiconductor device is provided. A first segment of the work function metal layer of the semiconductor device has a first thickness, and a second segment of the work function metal layer of the semiconductor device has a second thickness. The first thickness of the first segment and the second thickness of the second segment are different thicknesses.

[0140] In some embodiments described herein, a semiconductor device is provided. A first segment of the work function metal layer of the semiconductor device has a first thickness, and a second segment of the work function metal layer of the semiconductor device has a second thickness. The second thickness of the second segment is less than the first thickness of the first segment.

[0141] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first source / drain region located in a substrate layer of the semiconductor device. The semiconductor device includes a second source / drain region in the substrate layer. The semiconductor device includes a gate structure laterally located between the first source / drain region and the second source / drain region. The gate structure includes a gate electrode and a work function metal layer located between the gate electrode and the substrate layer and above the gate electrode and the substrate layer. The semiconductor device includes a gate dielectric layer located between the work function metal layer and the substrate layer and between the work function metal layer and the dielectric layer. A first segment of the gate dielectric layer extends along a first side of the gate electrode facing the first source / drain region. A second segment of the gate dielectric layer extends along a second side of the gate electrode facing the second source / drain region, and a first height of the first segment of the gate dielectric layer is greater than a second height of the second segment of the gate dielectric layer.

[0142] In some embodiments described herein, a semiconductor device is provided. The work function metal layer of the semiconductor device includes a third segment located between a first side of the gate electrode and a first segment of the gate dielectric layer, and a fourth segment located between a second side of the gate electrode and a second segment of the gate dielectric layer. The third segment has a first lateral thickness, and the fourth segment has a second lateral thickness. The first lateral thickness of the third segment and the second lateral thickness of the fourth segment are different thicknesses.

[0143] In some embodiments described herein, a semiconductor device is provided. The second lateral thickness of a fourth segment of the work function metal layer of the semiconductor device is less than the first lateral thickness of a third segment of the work function metal layer of the semiconductor device.

[0144] In some embodiments described herein, a semiconductor device is provided. A third segment of the work function metal layer of the semiconductor device has a third height, and a fourth segment of the work function metal layer of the semiconductor device has a fourth height. The third height of the third segment and the fourth height of the fourth segment are different heights.

[0145] In some embodiments described herein, a semiconductor device is provided. The fourth height of a fourth segment of the work function metal layer of the semiconductor device is smaller than the third height of the third segment.

[0146] In some embodiments described herein, a semiconductor device is provided. The fourth height of a fourth segment of the work function metal layer of the semiconductor device is smaller than the first height of a first segment of the gate dielectric layer.

[0147] In some embodiments described herein, a semiconductor device is provided. The second height of a second segment of the gate dielectric layer of the semiconductor device is less than the third height of a third segment of the work function metal layer.

[0148] As detailed above, some embodiments described herein provide a method for forming a semiconductor device. The method includes forming a first source / drain region and a second source / drain region in a substrate layer of the semiconductor device. The method (800) includes forming a dielectric layer over the first source / drain region and the second source / drain region. The method includes forming a gate dielectric layer of a transistor structure in a groove in the dielectric layer laterally between the first source / drain region and the second source / drain region, wherein the gate dielectric layer is formed on a first sidewall, a second sidewall, and the bottom surface of the groove. The method includes forming a work function metal layer of the gate structure of the transistor structure on the gate dielectric layer. The method includes forming a gate electrode of the gate structure on the work function metal layer. The method includes performing an etching operation to etch a first portion of the work function metal layer on the first sidewall and a second portion of the work function metal layer on the second sidewall, wherein after the etching operation, a first vertical height of the first portion of the work function metal layer and a second vertical height of the second portion of the work function metal layer have different vertical heights.

[0149] In some embodiments, the first vertical height of the first portion of the work function metal layer is greater than the second vertical height of the second portion of the work function metal layer after the etching operation.

[0150] In some embodiments, as described herein, the method further includes performing another etching operation prior to forming the gate electrode to etch a second portion of the work function metal layer on the second sidewall. After the other etching operation, the first lateral thickness of the first portion of the work function metal layer is greater than the second lateral thickness of the second portion of the work function metal layer.

[0151] In some embodiments, as described herein, another etching operation is performed to etch a second portion of the work function metal layer on the second sidewall, while a masking layer protects a first portion of the work function metal layer on the first sidewall.

[0152] In some embodiments, as described herein, the method further includes performing another etching operation to etch a third portion of the gate dielectric layer on the first sidewall and a fourth portion of the gate dielectric layer on the second sidewall. After the other etching operation, the third vertical height of the third portion of the gate dielectric layer and the fourth vertical height of the fourth portion of the gate dielectric layer are different vertical heights.

[0153] In some embodiments, as described herein, the third vertical height of the third portion of the gate dielectric layer is greater than the fourth vertical height of the fourth portion of the gate dielectric layer after another etch operation.

[0154] The terms "approximately" and "substantially" can indicate that a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not limiting. It should be understood that the terms "approximately" and "substantially" can be interpreted as percentages of the given quantity values ​​disclosed herein.

[0155] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0156] 100: Semiconductor components 102: Device Layer 104: Interconnection Layer 106: Substrate layer 108: Dielectric layer 110: Integrated circuit elements 110a: Integrated circuit element 110b: Integrated circuit element 112: Source / Drain Region 112a: Source / Drain Region 112b: Source / Drain Region 114: Gate dielectric layer 116: Gate structure 116a: n-type gate structure 116b: p-type gate structure 118: Sidewall spacers 120: Source / Drain Contact 122: Lining layer 124: Gate contact 126: Lining layer 128: Dielectric layer 130: Etching Stop Layer 132: Metallized structure 134: Interconnection Structure 200: Example 202: Fin Structure 300: Example 302: Dummy gate structure 400: Example 500: Example 502: Groove 504: p-type work function metal layer 504a: Sidewall Section 504b: Sidewall Section 504c: Bottom section 506: n-type work function metal layer 506a: Sidewall Section 506b: Sidewall Section 506c: Bottom section 506d: Bottom section 506e: Bottom section 506f: Transition Section 508: Masking layer 510: Masking layer 512: Gate electrode 600: Example 700: Example 702: Covering layer 800: Example 802: Void Zone 900: Process Implementation Examples 910~960: Square AA: Line segment BB: Line segment D1~D28: Dimensions x, y, z: Direction

[0157] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a first source / drain region located in a substrate layer of the semiconductor device; a second source / drain region located in the substrate layer; and a gate structure laterally located between the first source / drain region and the second source / drain region, comprising: a gate electrode; and a work function metal layer located between the gate electrode and the substrate layer, wherein a first segment of the work function metal layer extends along a first side of the gate electrode, the first side of the gate electrode facing the first source / drain region, wherein a second segment of the work function metal layer extends along a second side of the gate electrode, the second side of the gate electrode facing the second source / drain region, and wherein a first height of the first segment of the work function metal layer is greater than a second height of the second segment of the work function metal layer, and a top surface of the first segment of the work function metal layer is higher than a top surface of the second segment of the work function metal layer.

2. The semiconductor device of claim 1, wherein the work function metal layer comprises: a third segment located below a first portion of the gate electrode, wherein the third segment is adjacent to the first segment, and wherein the third segment has a first thickness; and a fourth segment located below a second portion of the gate electrode, wherein the fourth segment is adjacent to the second segment, wherein the fourth segment has a second thickness, and wherein the first thickness and the second thickness are different thicknesses.

3. The semiconductor element as claimed in claim 2, wherein the second thickness is less than the first thickness.

4. The semiconductor device as claimed in claim 2, wherein the work function metal layer includes a transition section laterally located between the third section and the fourth section.

5. A semiconductor device comprising: a first source / drain region located in a substrate layer of the semiconductor device; a second source / drain region located in the substrate layer; a gate structure laterally located between the first source / drain region and the second source / drain region, comprising: a gate electrode; and a work function metal layer located between the gate electrode and the substrate layer, and between the gate electrode and a dielectric layer above the substrate layer; and a gate dielectric layer located between the work function metal layer and the substrate layer, and between the work function metal layer and the dielectric layer, wherein a first segment of the gate dielectric layer extends along a first side of the gate electrode facing the first source / drain region, wherein a second segment of the gate dielectric layer extends along a second side of the gate electrode facing the second source / drain region, and wherein a first height of the first segment of the gate dielectric layer is greater than a second height of the second segment of the gate dielectric layer.

6. The semiconductor device of claim 5, wherein the work function metal layer comprises: a third segment located between the first side of the gate electrode and the first segment of the gate dielectric layer, wherein the third segment has a first lateral thickness; and a fourth segment located between the second side of the gate electrode and the second segment of the gate dielectric layer, wherein the fourth segment has a second lateral thickness; and wherein the first lateral thickness and the second lateral thickness are different thicknesses.

7. The semiconductor element as claimed in claim 6, wherein the second lateral thickness is less than the first lateral thickness.

8. A method of forming a semiconductor device, comprising: forming a first source / drain region and a second source / drain region of a transistor structure in a substrate layer of a semiconductor device; forming a dielectric layer above the first source / drain region and the second source / drain region; forming a gate dielectric layer of the transistor structure in a groove in the dielectric layer, the groove being laterally located between the first source / drain region and the second source / drain region, wherein the gate dielectric layer is formed on a first sidewall, a second sidewall, and a bottom surface of the groove; forming a work function metal layer of a gate structure of the transistor structure on the gate dielectric layer; forming a gate electrode of the gate structure on the work function metal layer; and performing an etching operation to etch a first portion of the work function metal layer on the first sidewall and a second portion of the work function metal layer on the second sidewall, wherein a first vertical height of the first portion of the work function metal layer and a second vertical height of the second portion of the work function metal layer are different vertical heights after the etching operation.

9. The method of claim 8, wherein the first vertical height of the first portion of the work function metal layer is greater than the second vertical height of the second portion of the work function metal layer after the etching operation.

10. The method of claim 9, further comprising: performing another etching operation to etch the second portion of the work function metal layer on the second sidewall prior to forming the gate electrode, wherein a first lateral thickness of the first portion of the work function metal layer is greater than a second lateral thickness of the second portion of the work function metal layer after the other etching operation.

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