Semiconductor device and method of forming semiconductor device

Abstract

This disclosure relates to an interconnect structure for a semiconductor device and a method for forming the interconnect structure. The interconnect structure includes a first metal line, a second metal line on the first metal line, and a conductive via electrically coupling the first and second metal lines. The conductive via includes protrusions extending laterally and vertically into the first metal line to reduce contact resistance between the conductive via and the first metal line. The method includes forming the first metal line and a dielectric layer on the first metal line, forming an opening in the dielectric layer to expose the first metal line, and laterally recessing the first metal line in the opening. The method further includes depositing a conductive material in the opening to form the conductive via and the second metal line.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than its predecessor. Throughout IC evolution, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower cost has continuously increased. To meet these demands, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased. Consequently, the critical dimensions of interconnect structures have become increasingly smaller to allow for the connection of more devices within a limited space. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] Several aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation and discussion. Figure 1 is a cross-sectional view of a semiconductor device including a multilayer interconnect structure according to some embodiments. Figures 2A to 2C are cross-sectional views of the interconnection structure in the enlarged area of ​​Figure 1 according to some embodiments. Figures 3A to 3C are enlarged cross-sectional views of the areas in Figures 2A to 2C according to some embodiments. Figures 4A and 4B are cross-sectional views of an interconnection structure according to some embodiments. Figures 5A to 5C are flowcharts of methods for forming interconnect structures according to some implementation methods. Figures 6 through 17 are cross-sectional views of an intermediate structure during the fabrication of an interconnect structure according to some embodiments. Several illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote multiple elements that are identical, functionally similar, and / or structurally similar. Implementation

[0005] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and not limiting. For example, in the following description, forming a first feature over a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, the formation of a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is not in itself intended to indicate a relationship between the various implementations and / or configurations discussed.

[0006] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the figures, spatially relative terms may be used herein, such as "below," "lower than," "slightly below," "higher than," "slightly above," or similar terms. In addition to the directions depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] In some implementations, the terms "about" and "substantially" may refer to a given quantity that varies within 5% of a value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of this value). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to percentages of values ​​as interpreted by those skilled in the art based on the teachings herein.

[0008] It should be noted that references to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics; however, each embodiment may not necessarily include this specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0009] It should be understood that the wording or terminology used herein is for descriptive purposes and not restrictive, and therefore the wording or terminology used herein should be interpreted by those skilled in the art based on the teachings herein.

[0010] An integrated circuit includes multiple semiconductor devices electrically connected together via multiple interconnect structures. The interconnect structures include, for example, metal lines that provide wiring between the multiple semiconductor devices in a direction parallel to the top surface of the substrate of the integrated circuit. Metal lines at different layers and levels of the integrated circuit can be electrically connected to each other via conductive vias that extend vertically through a dielectric layer between the multiple metal lines at different layers and levels. Conductive vias can be formed such that the bottom surface of the via is electrically connected to a first metal line at a first interconnect level below the via, and the top surface of the via is electrically connected to a second metal line at a second interconnect level above the via. Barrier layers can be formed on the surface of the conductive vias to prevent conductive material from diffusing or migrating from the vias into the surrounding dielectric layer.

[0011] As semiconductor devices continue to shrink, the critical dimensions of conductive vias are becoming increasingly smaller to enable the connection of more semiconductor devices within a limited space. Consequently, the formation of conductive vias becomes more challenging because the higher aspect ratio (e.g., depth-to-width ratio) of the vias increases their resistance, thus affecting the conductivity of the vias used to achieve effective coupling between multiple metal lines. For example, a barrier layer may include a portion between the conductive via and a metal line below it. Since the barrier layer is made of a material with a higher resistivity than the conductive via, this portion with its reduced size becomes a bottleneck for the conductivity of the conductive via. Even if the barrier layer can be fabricated such that the conductive via and the metal line are in direct contact without a barrier layer between them, the contact resistance of this reduced-size direct contact still limits the conductivity of the conductive via due to structural discontinuities in the conductive material on both sides of the boundary between the conductive via and the metal line (e.g., different grain sizes on one side of the conductive via and the other side of the metal line lead to conductivity mismatch, which enhances charge carrier scattering).

[0012] To overcome the aforementioned challenges, several embodiments described herein relate to interconnect structures for semiconductor devices and methods for forming such interconnect structures. In some embodiments, the interconnect structure may include a first metal line, a second metal line on the first metal line, and a conductive via electrically coupling the first and second metal lines. The conductive via may include a protrusion extending vertically and laterally into the first metal line to increase the contact area between the conductive via and the first metal line, thereby reducing the contact resistance between the conductive via and the first metal line. The method may include forming a first metal line and a dielectric layer on the first metal line, forming an opening in the dielectric layer to expose the first metal line, and laterally recessing the first metal line to extend the opening into the first metal line. The method may also include depositing a conductive material in the opening to form the conductive via and the second metal line.

[0013] According to some embodiments, Figure 1 shows a cross-sectional view of a semiconductor device 100. The semiconductor device 100 may include a substrate 102, a device layer 116 disposed on the substrate 102, and a plurality of interconnect layers disposed on the device layer 116. The semiconductor device 100 may be included in a microprocessor, a memory cell, or other integrated circuit (IC).

[0014] Referring to Figure 1, substrate 102 may be a semiconductor material, such as silicon. In some embodiments, substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 102 may include (i) elemental semiconductors, such as silicon (Si) or germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) alloy semiconductors, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), gallium indium phosphide (InGaP), gallium indium arsenide (InGaAs), gallium indium arsenide phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) combinations thereof. Furthermore, substrate 102 may be doped according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0015] Device layer 116 may include a plurality of transistors disposed on substrate 102. The transistors may include metal-oxide-semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, fin field-effect transistors (FinFETs), complementary fin field-effect transistors (CFETs), gate all-ring field-effect transistors (GAA FETs), and / or vertical fin field-effect transistors (VFETs). Device layer 116 may further include contact structures for the transistors, such as gate contact structures and source / drain contact structures. Device layer 116 may also include other electronic components, such as resistors, capacitors, inductors, and contact structures in contact with these electronic components.

[0016] Referring to Figure 1, the interconnect layers disposed on device layer 116 may include interconnect layers M0, M1, M2, M3, etc. Although four interconnect layers are shown as an embodiment in Figure 1, the number of interconnect layers can be any integer greater than 1. For example, semiconductor device 100 may include 2, 4, 8, 12, 16, 24, or 32 interconnect layers. In some embodiments, the interconnect layers may be formed in a back-to-line (BEOL) process. Each interconnect layer may include an etch stop layer 130 and a dielectric layer 120 on the etch stop layer 130. Each interconnect layer may also include a metal line 140 in the dielectric layer 120 and a conductive via 150 passing through the etch stop layer 130 and the dielectric layer 120. The conductive via 150 may electrically couple the metal line 140 to a plurality of conductive elements below and / or above each interconnect layer. For example, among multiple interconnect layers, interconnect layer M0 is closest to device layer 116, and conductive vias 150 in interconnect layer M0 can electrically couple the metal lines 140 of interconnect layer M0 to the contact structures in device layer 116. In another embodiment, conductive vias 150 in interconnect layer M2 can electrically couple the metal lines 140 of interconnect layer M2 to the metal lines 140 of interconnect layers M1 and / or M3. Etch stop layer 130 and dielectric layer 120 may include low-k dielectric materials, such as silicon oxide (SixOy), silicon nitride (SixNy), silicon oxynitride (SixOyCzNu), silicon oxynitride (SixCyNz), silicon oxynitride (SixOyNz), silicon carbide (SixCy), aluminum nitride (AlxNy), aluminum oxide (AlxOy), or aluminum oxynitride (AlxOyNz). The metal wire 140 and the conductive via 150 may comprise any suitable conductive material, such as titanium, aluminum, copper, tungsten, tantalum, nickel, ruthenium, other suitable metals, and / or combinations thereof.

[0017] Figures 2A through 2C show cross-sectional views of structure 200, which are enlarged portions of the area around the interconnect layer in Figure 1. Unless otherwise stated, the discussion of elements with the same or similar reference numerals in Figure 1 applies to Figures 2A through 2C.

[0018] Referring to Figure 2A, structure 200 may include a dielectric layer 222 and metal lines 242 on the dielectric layer 222. In some embodiments, the dielectric layer 222 and metal lines 242 may be multiple portions of a first interconnect layer (e.g., one of multiple interconnect layers M0, M1, M2, M3, etc., as shown in Figure 1). Structure 200 may also include a dielectric layer 224 and metal lines 244 in the dielectric layer 224. The dielectric layer 224 and metal lines 244 are disposed on the dielectric layer 222 and metal lines 242, and may be multiple portions of a second interconnect layer that is above and adjacent to the first interconnect layer. The boundary between the first and second interconnect layers is indicated by a line along A-A'. Dielectric layers 222 and 224 may be the same as dielectric layer 120 shown in Figure 1. Metal lines 242 and 244 may be the same as metal line 140 shown in Figure 1. In some embodiments, metal lines 242 and 244 may extend along different horizontal directions. For example, as shown in Figure 2A, metal line 242 extends along the x-axis, and metal line 244 extends along the y-axis. In some embodiments, the thickness d1 of metal line 242 may be between about 5 nanometers and about 50 nanometers. In some embodiments, metal lines 242 and 244 may have similar thicknesses. In some embodiments, the top surface of metal line 244 and dielectric layer 224 may be coplanar.

[0019] In some embodiments, structure 200 may further include an etch stop layer 230 disposed on the first interconnect layer. For example, as shown in Figure 2A, the etch stop layer 230 may be disposed on the metal line 242 and below the dielectric layer 224. In some embodiments, the etch stop layer 230 may include one or more sublayers of a low-k dielectric material, such as SixOy, SixNy, SixOyCzNu, SixCyNz, SixOyNz, SixCy, AlxNy, AlxOy, or AlxOyNz. In some embodiments, the thickness of each of the multiple sublayers of the low-k dielectric material may be between about 1 nanometer (nm) and about 10 nanometers. In some embodiments, the thickness of the etch stop layer 230 may be between about 1 nanometer and about 50 nanometers.

[0020] Referring to Figure 2A, structure 200 may further include a conductive via 250 in dielectric layer 224, passing through etch stop layer 230 and electrically coupling metal lines 242 and 244. The conductive via 250 may include the same or similar conductive material as metal lines 242 and 244, such as titanium, cobalt, aluminum, copper, tungsten, tantalum, nickel, ruthenium, other suitable metals, and / or combinations thereof. In some embodiments, the conductive via 250 may include a conductive material different from that in metal line 242. In some embodiments, structure 200 may further include a barrier layer 260 surrounding the conductive via 250. The barrier layer 260 may be disposed between the conductive via 250 and dielectric layer 224. The barrier layer 260 may also be disposed between the conductive via 250 and etch stop layer 230. The barrier layer 260 prevents conductive material from diffusing from the conductive via 250 into dielectric layer 224 and etch stop layer 230. In some embodiments, the barrier layer 260 may also be disposed between the conductive via 250 and the metal line 242. In some embodiments, the barrier layer 260 may include tantalum and / or tantalum nitride. In some embodiments, the barrier layer 260 may have a thickness between about 0.5 nanometers and about 5 nanometers. In some embodiments, the barrier layer 260 may also be disposed between the metal line 244 and the dielectric layer 224.

[0021] Referring to Figure 2A, the conductive via 250 may have a rivet shape and include a first portion 252 (as the head of the rivet shape) and a second portion 254 (as the shaft portion of the rivet shape) on the first portion 252. The first portion 252 may be a protrusion extending into the metal line 242 and below line A-A'. For example, the first portion 252 may extend laterally below the dielectric layer 224 and the etch stop layer 230. The second portion 254 may extend through the etch stop layer 230 and the dielectric layer 224 and contact the metal line 244. In some embodiments, the second portion 254 may have a tapered shape, wherein the side surfaces 254s are inclined, and the width w1 at the lower end of the second portion 254 is smaller than the width w2 at the upper end of the second portion 254. In some embodiments, the side surfaces 254s may be perpendicular to the top surface of the metal line 242, and the widths w1 and w2 are substantially the same. In some embodiments, the widths w1 and w2 may be between about 2 nanometers and about 50 nanometers.

[0022] As shown in Figure 2A, the first portion 252 of the conductive via 250 may extend vertically into the metal line 242. For example, the ratio of the vertical thickness d of the first portion 252 to the thickness d1 of the metal line 242 may be between about 0.2 and about 0.7. The first portion 252 may also extend laterally within the metal line 242. For example, the first portion 252 may have an upper surface 252u having a lateral extension w3 from point 252a to point 252b toward a first horizontal direction, where point 252a is the location where the side surface 254s of the second portion 254 and the upper surface 252u are connected to each other. In some embodiments, the first portion 252 may also extend laterally, with the lateral extension w4 toward a second horizontal direction opposite to the first direction. In some embodiments, the lateral extensions w3 and w4 may be substantially the same. In some embodiments, the lateral extensions w3 and w4 may be different and have a variation of less than about 10%. In some embodiments, the lateral extensions w3 and w4 can be between about 1 nanometer and about 100 nanometers. In some embodiments, the ratio between the lateral extension w3 and the width w1 can be between about 0.1 and about 1. In some embodiments, the ratio between the lateral extension w3 and the vertical thickness d can be between about 0.5 and about 1. In some embodiments, the total width (w1+w3+w4) of the first portion can be greater than the width w2. In some embodiments, the first portion 252 can have a curved lower surface 252d. In some embodiments, the angle α at point 252b can be between about 30° and about 90°, where point 252b is the location where the lower surface 252d and the upper surface 252u are connected to each other. In some embodiments, the angle β between the side surface 254s and the upper surface 252u can be between about 60° and about 90°. In some embodiments, the angle β can be greater than about 90°. In some embodiments, both the lower surface 252d and the upper surface 252u can be covered by the barrier layer 260. In some embodiments, the first portion 252 of the conductive via 250 protruding into the metal wire 242 can increase the contact area between the conductive via 250 and the metal wire 242, thereby sufficiently mitigating the influence of the relatively high-resistance barrier layer 260 between the conductive via 250 and the metal wire 242. In some embodiments, the ratio of the length of the lower surface 252d to the width w1 at the lower end of the second portion 254 can be between about 2 and about 10, corresponding to an enhancement in contact conductivity compared to the case without the first portion 252.

[0023] As described below with reference to the method in Figures 5A to 5C, the rivet shape forming the conductive via 250 forms a cavity below the etch stop layer 230 via a recessed metal line 242, which is then filled with a conductive material to form the first portion 252 of the conductive via 250. Depending on the details of the recess, the first portion 252 may have different shapes. Figure 2B shows another embodiment of the conductive via 250 in which the shape of the first portion 252 differs from that in Figure 2A. Specifically, as shown in Figure 2B, the angle α between the lower surface 252d and the upper surface 252u can be greater than about 90°. For example, the angle α can be between about 90° and about 120°. In some embodiments, having an angle α greater than about 90° can further increase the contact area between the conductive via 250 and the metal line 242. The discussion of other elements with the same reference numerals in Figure 2A applies to Figure 2B and will not be repeated for simplicity.

[0024] In some embodiments, the upper surface 252u of the first portion 252 may contact the bottom surface of the etch stop layer 230 without being covered by the barrier layer 260, and the lower surface 252d of the first portion 252 may directly contact the metal line 242 without the barrier layer 260 between them, as shown in Figure 2C. Unless otherwise stated, the discussion of other elements with the same reference numerals in Figures 2A and 2B applies to Figure 2C.

[0025] Referring to Figure 2C, in some embodiments, even if the conductive via 250 is in direct contact with the metal line 242, the contact resistance can still affect the conductivity of the conductive via 250. This is because the metal line 242 and the conductive via 250 are deposited separately, rather than continuously. Specifically, the presence of defects / impurities on the surface of the metal line 242 after it has been recessed can affect the grain structure of the conductive via 250 deposited on the metal line 242, resulting in different grain structures on opposite sides of the lower surface 252d. For example, on one side of the lower surface 252d having the first portion 252, the average grain size of the conductive material can be smaller than on the other side of the lower surface 252d having the metal line 242. The structural differences between the two sides of the lower surface 252d can lead to conductivity mismatch, which affects the conductivity of the conductive via 250. As the first portion 252 extends laterally, the contact area between the conductive via 250 and the metal line 242 can be increased, mitigating the effects of conductivity mismatch at the lower surface 252d, which serves as the boundary between the conductive via 250 and the metal line 242. Although Figure 2C shows a conductive via 250 with a first portion 252, the shape of which is similar to that in Figure 2A (angle α less than about 90°), it should be understood that the first portion 252 in Figure 2C can also have a shape similar to that in Figure 2B (angle α greater than about 90°).

[0026] As described above, the etch stop layer 230 may include one or more layers of dielectric material. In some embodiments, the first portion 252 and the second portion 254 of the conductive via 250 may be connected to each other using a connection profile finely tuned via the etch stop layer 230. Specifically, for the etch stop layer 230 having multiple layers of dielectric material, the angle β between the side surface 254s and the top surface 252u of the second portion 254 may be adjusted to improve the conductivity of the conductive via 250, as shown in Figures 3A to 3C. Figures 3A to 3C show cross-sectional views of structure 300 (i.e., structures 300A to 300C), which are enlarged portions of Figures 2A to 2C around angle β. Unless otherwise stated, the discussion of elements with the same or similar reference numerals in Figures 2A to 2C applies to Figures 3A to 3C.

[0027] Referring to Figure 3A, in some embodiments, the etch stop layer 230 may include two sublayers 230a and 230b with different dielectric materials, and the angle β may be less than about 90°.

[0028] Referring to Figure 3B, in some embodiments, the two sublayers 230a and 230b of the etch stop layer 230 can have different etch selectivity, such that during the etch process to recess the metal line 242, sublayer 230b can also be recessed, while sublayer 230a can be recessed by a smaller amount. As a result, the angle β can be greater than about 90°, and the barrier layer 260 can include a segment 260b on the side surface of sublayer 230b and is not aligned with the rest of the barrier layer 260 disposed on dielectric layer 224.

[0029] Referring to Figure 3C, in some embodiments, the etch stop layer 230 may include a plurality of sublayers 230a to 230n with different etch selectivity, such that the barrier layer 260 may include a smooth transition of the barrier layer 260 from the side surface 254s of the second portion 254 to the upper surface of the first portion 252. As a result, the angle β becomes less pronounced, and the side surface 254s of the second portion 254 to the upper surface of the first portion 252 can be smoothly connected around the etch stop layer 230 without significant angular structures. In some embodiments, the smooth connection of the surfaces of the first portion 252 and the second portion 254 can improve the mechanical, thermal, and / or electrical performance of the conductive via 250. For example, in the absence of significant angular structures, the first portion 252 and the second portion 254 can have improved mechanical connections and are less susceptible to stress or mechanical deformation under varying conditions during manufacturing processes (e.g., annealing processes). The smooth profile of the conductive via 250 surface can also improve its conductivity by reducing surface scattering or static charge accumulation.

[0030] Although Figures 2A through 3C show that the first portion 252 of the conductive via 250 can extend laterally along the x-axis below the etch stop layer 230, in some embodiments, the first portion 252 can also extend laterally along a different lateral direction (e.g., along the y-axis), as shown in Figures 4A and 4B. Figures 4A and 4B show cross-sectional views of structure 200 corresponding to line A-A' in Figures 2A through 2C. Figures 4A and 4B are from a top perspective view (along the z-axis), and lines 252a and 252b correspond to points 252a and 252b in Figure 2A, respectively. Specifically, line 252a corresponds to the line connecting the side surface 254s of the second portion 254 and the upper surface 252u of the first portion 252 to each other, and line 252a corresponds to the laterally extending perimeter of the first portion 252 (where the first portion 252 and the metal line 242 intersect along line A-A').

[0031] Referring to Figure 4A, in some embodiments, the conductive via 250 may have cylindrical symmetry, and lines 252a and 252b are multiple circles with the same axis. Specifically, the diameter w1 of line 252a is the same as the width w1 shown in Figure 2A, and the radius of line 252b is larger than the radius of line 252a by a length w3 or w4 as shown in Figure 2A.

[0032] Referring to Figure 4B, in some embodiments, the conductive via 250 may have a rectangular cross-section. In some embodiments, the rectangle may have rounded corners. For example, the lower end of the second portion 254, indicated by line 252a, may have a width w1 along the x-axis and a length s1 along the y-axis. Similar to the lateral extension w3 / w4 along the x-axis of the first portion 252 as shown in Figure 2A, the lateral extension y1 along the y-axis of the first portion 252 is between about 1 nanometer and about 100 nanometers. In some embodiments, the lateral extension y1 may be the same as the lateral extension w3 / w4. In some embodiments, the lateral extension y1 may be different from the lateral extension w3 / w4. In some embodiments, the ratio of the lateral extension w3 / w4 or y1 to the width w1 or the length s1 may be between about 0.1 and about 1.

[0033] According to some embodiments, Figures 5A to 5C illustrate flowcharts of manufacturing methods 500, 500', and 500" for forming the structure 200 shown in Figures 2A to 2C. This disclosure is not limited to such operational descriptions, and additional operations may be performed. Other manufacturing operations may be performed between the various operations of methods 500, 500', and 500" and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in a different order than shown in Figures 5A to 5C. In some embodiments, one or more other operations may be performed in addition to or instead of the operations currently described. For illustrative purposes, method 500 is described with reference to the structures shown in Figures 6 to 11, Figures 2A and 2B; method 500' is described with reference to the structures shown in Figures 6 to 10, Figures 12 to 14 and 2C; and method 500' is described with reference to the structures shown in Figures 6 to 9, Figures 14 to 17 and 2C. Unless otherwise stated, the discussion of elements with the same reference numerals in Figures 2A to 2C applies to Figures 6 to 17.

[0034] Referring to Figure 5A, method 500 may begin with operation 505 and the process of forming a first metal line on a substrate. In some embodiments, the substrate may include a dielectric layer 222, as described with reference to Figure 6, and forming the first metal line may include (i) forming trenches in the dielectric layer 222 and extending them in a horizontal direction (e.g., the x-axis), and (ii) depositing a conductive material in the trenches to form the metal line 242. In some embodiments, a device layer (e.g., device layer 116 shown in Figure 1) may be formed below the dielectric layer 222 prior to forming the first metal line 242. In some embodiments, forming the metal line 242 may include depositing a metal, such as titanium, aluminum, copper, tungsten, tantalum, nickel, ruthenium, other suitable metals, and / or combinations thereof. In some embodiments, depositing the metal may include performing a sputtering process, an evaporation process, an electrochemical plating (ECP) process, a chemical vapor deposition (CVD) process, or an atomic vapor deposition (ALD) process. For example, during an electrochemical plating (ECP) process, an electrolyte such as a mixture of copper sulfate and sulfuric acid can be used to deposit copper. The deposition rate and properties of the deposited metal line 242 can be controlled by adjusting the concentration of copper sulfate in the electrolyte, the current density applied during the electrochemical plating process, the plating time, and / or the temperature of the electrolyte. In some embodiments, forming the metal line 242 may include a planarization process, such as a chemical mechanical polishing (CMP) process, to form a flat top surface of the metal line 242.

[0035] Referring to Figure 5A, method 500 can proceed to operation 510 and the process of depositing an etch stop layer and a dielectric layer on the first metal line. For example, etch stop layer 230 can be deposited over metal line 242 and dielectric layer 222, and dielectric layer 224 can be deposited over etch stop layer 230, as described in Figure 7. In some embodiments, depositing etch stop layer 230 may include blanketing a layer of deposited dielectric material. In some embodiments, depositing etch stop layer 230 may include sequentially depositing different dielectric materials for multiple sublayers. In some embodiments, depositing etch stop layer 230 may include selecting the dielectric material for the sublayers based on the etch selectivity of the dielectric material, such that the geometry of the subsequently formed conductive vias can be adjusted as described in Figures 3A to 3C. In some embodiments, depositing etch stop layer 230 may be performed via ALD process, CVD process, plasma-enhanced CVD (PECVD) process, and / or sputtering process.

[0036] In some implementations, the deposited dielectric layer 224 may include a layer of blanket-deposited low-k dielectric material, similar to the process of depositing etch stop layer 230.

[0037] Referring to Figure 5A, method 500 can proceed to operation 515 and the process of forming an opening through the dielectric layer and the etch stop layer. For example, as described with reference to Figure 8, an opening 854 can be formed through the dielectric layer 224 and the etch stop layer 230. In some embodiments, as described below, the opening 854 can then be filled with a conductive material to form a conductive via. In some embodiments, forming the opening 854 can include (i) forming a mask on the dielectric layer 224 with a pattern exposing a portion of the dielectric layer 224, (ii) etching the exposed portion of the dielectric layer 224 to expose the etch stop layer 230, and (iii) etching through the etch stop layer 230 to expose the top surface of the metal line 242. In some embodiments, etching the dielectric layer 224 and the etch stop layer 230 can include a dry etching process using an etchant, such as carbon fluoride (CxFy), nitrogen (N2), carbon dioxide (CO2), argon (Ar), or a combination thereof. In some embodiments, the etchant can be in the form of plasma. In some embodiments, the mask on the dielectric layer 224 can be removed after the opening 854 is formed. In some embodiments, after the opening 854 is formed, a trench 944 can be formed within and above the opening 854 in the dielectric layer 224, as described in Figure 9. In some embodiments, the trench 944 can be formed to extend along a horizontal direction (e.g., the y-axis) and can subsequently be filled with a conductive material to form a metal line 244, as described below, as shown in Figures 2A through 2C.

[0038] Referring to Figure 5A, method 500 can proceed to operation 520 and the process of recessing the first metal wire. For example, a cavity 1052 in the metal wire 242 can be formed by recessing a portion of the metal wire 242 exposed in the opening 854, as described in Figure 10. The cavity 1052 is an extension of the opening 854 into the metal wire 242. The cavity 1052 can be formed in the shape of a rivet head extending laterally and vertically into the metal wire 242. The cavity 1052 can also be formed to extend in the metal wire 242 along different lateral directions (e.g., along the x-axis and y-axis). As described below, the cavity 1052 and the opening 854 can then be filled with a conductive material to form a first portion 252 and a second portion 254 of the conductive via 250, as shown in Figures 2A to 2C.

[0039] In some embodiments, recessing the metal line 242 may include performing a selective isotropic etching operation, such as a wet etching operation, in the opening 854, which may selectively etch the conductive material of the metal line 242 without etching the dielectric layer 224 and / or the dielectric material of the stop layer 230. The wet etching operation may include etching using an etchant capable of isotropically etching metal, such that the cavity 1052 extends laterally and vertically into the metal line 242. In some embodiments, the etchant may include a chemical solution for etching copper, such as ferric chloride, ammonium persulfate, nitric acid, copper dichloride, or combinations thereof. The etchant may oxidize the copper surface and then dissolve in the chemical solution. Etching conditions may be controlled according to the desired geometry of the cavity 1052 and the specific etchant used. In some embodiments, the temperature of the chemical solution may be adjusted to control the etching rate of the metal line 242. For example, the wet etching operation may be performed at room temperature or a high temperature. In some embodiments, the width and / or depth of the cavity 1052 may be controlled via etching time. In some embodiments, the sublayers of the etch stop layer 230 may also be etched in a wet etching operation (at a lower etch rate than that of the metal line 242), and the geometry of the side surface of the etch stop layer 230 may be fine-tuned, as described in Figures 3A through 3C, by selecting an appropriate etchant and controlling the etching time.

[0040] In some embodiments, recessing the metal line 242 may include performing an etching operation that combines wet and dry etching. For example, anisotropic dry etching may be used first to extend the opening 854 deep into the metal line 242 by etching the metal line 242 only in the vertical direction, and then selective isotropic wet etching may be used to form the cavity 1052 by laterally recessing the metal line 242. The anisotropic dry etching may be the same as or similar to the dry etching process that forms the opening 854 in operation 515. In some embodiments, where the metal line 242 has been vertically recessed after anisotropic dry etching, wet etching may begin at a depth below the upper surface of the metal line 242, and in addition to recessing the metal line 242 laterally and vertically downward, wet etching may also recess the metal line 242 vertically upward to form a cavity having a geometry similar to the first portion 252 of the conductive via 250, as shown in Figure 2B (angle α is greater than about 90°).

[0041] Referring to Figure 5A, method 500 can proceed to operation 525 and the process of forming a barrier layer in the opening. For example, barrier layer 260 can be formed above the surfaces of opening 854 and cavity 1052, as described in Figure 11. For example, barrier layer 260 can be formed on multiple side surfaces of dielectric layer 224 and etch stop layer 230. In some embodiments, barrier layer 260 can be formed below dielectric layer 224 and on the bottom surface of etch stop layer 230. In some embodiments, barrier layer 260 can be formed on the curved surface of metal line 242 exposed in cavity 1052. In some embodiments, barrier layer 260 can also be formed above the surface of trench 944. In some embodiments, forming barrier layer 260 can include depositing tantalum and / or tantalum nitride layers via PVD, CVD, or ALD processes. In some embodiments, the deposition of tantalum and / or tantalum nitride layers may be performed by using tantalum chloride (TaCl5) and ammonia (NH3) as precursors. In some embodiments, forming the barrier layer 260 may include a post-deposition annealing operation to improve the adhesion of the tantalum and / or tantalum nitride layers on the plurality of surfaces of the opening 854 and the cavity 1052.

[0042] Referring to Figure 5A, method 500 can proceed to operation 530 and the deposition of a layer of conductive material in the opening. For example, the conductive via 250 can be formed by depositing metal in the opening 854 and cavity 1052, as described in Figure 11, Figures 2A, and 2B. In some embodiments, the deposition of metal in the opening 854 and cavity 1052 can be the same as or similar to the formation of the metal line 242 in operation 505. For example, the deposition of copper in the opening 854 and cavity 1052 can be via an electrochemical plating process. In some embodiments, a barrier layer 260 can be used as a seed layer to facilitate copper deposition during the electrochemical plating process. During the electrochemical plating process, copper deposition can be performed using an electrolyte, such as a mixture of copper sulfate and sulfuric acid. The deposition rate and properties of the conductive via 250 can be controlled by adjusting the concentration of copper sulfate in the electrolyte, the current density applied during the electrochemical plating process, the plating time, and / or the temperature of the electrolyte. In some embodiments, after the conductive via 250 is formed, an electrochemical plating process can be continued to form a metal line 244 on the conductive via 250.

[0043] Referring to Figure 5A, method 500 can proceed to operation 535, performing a planarization operation on metal line 244 and dielectric layer 224, as described in Figures 2A and 2B. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process to form a coplanar top surface of metal line 244 and dielectric layer 224. In some embodiments, planarizing the top surface of metal line 244 and dielectric layer 224 may facilitate the fabrication of subsequent structures on metal line 244 and dielectric layer 224, such as additional conductive vias and metal lines formed in subsequent back-end line (BEOL) processes, which are similar to being electrically connected in parallel to metal lines 242 and 244 and conductive via 250.

[0044] Referring to Figure 5B, method 500' can be used to form structure 200, as described with reference to Figure 2C. Compared to method 500 in Figure 5A, method 500' may include the same operations 505 to 520, 530, and 535 as method 500. However, operation 525 of method 500 is replaced by operations 550 to 560 in method 500'. In the following description of method 500', for the sake of simplicity, the descriptions of operations 505 to 520, 530, and 535, and the corresponding Figures 6 to 10, will not be repeated in detail.

[0045] Referring to Figure 5B, after operation 520, which forms the intermediate structure 200 as described in Figure 10, method 500' can proceed to operation 550 and the process of forming an inhibitor layer on a conductive surface in the opening. For example, inhibitor layer 1270 can be formed on the surface of metal line 242 exposed in cavity 1052, as described in Figure 12. Inhibitor layer 1270 can be selectively deposited on conductive surfaces but not on non-conductive surfaces (e.g., the dielectric surfaces of dielectric layer 224 and etch stop layer 230), and can inhibit the subsequent formation of a barrier layer on the surface of metal line 242. In some embodiments, forming inhibitor layer 1270 may include depositing quaternary ammonium cations, benzotriazole, tolyltriazole, and / or 5,6-dimethylbenzotriazole via physical adsorption processes, chemisorption, and / or electrostatic adsorption processes.

[0046] Referring to Figure 5B, method 500' can proceed to operation 555 and the process of forming a barrier layer on the dielectric surface in the opening. Unless otherwise stated, the description of forming a barrier layer in operation 525 applies to forming a barrier layer in operation 555. For example, barrier layer 260 can be formed on multiple side surfaces of dielectric layer 224 and etch stop layer 230 exposed in opening 854 and / or trench 944, as described in Figure 13. In some embodiments, the presence of inhibitor layer 1270 can prevent the formation of barrier layer 260 on the upper surface of inhibitor layer 1270 exposed in cavity 1052.

[0047] Referring to Figure 5B, method 500' can proceed to operation 560 and the process of removing the inhibitor layer. For example, the inhibitor layer 1270 in Figure 13 can be removed to expose the surface of the metal wire 242 in cavity 1052, as described in Figure 14. In some embodiments, removing the inhibitor layer 1270 may include plasma treatment of the intermediate structure 200 as shown in Figure 13, via exposing the intermediate structure 200 to a plasma gas, such as hydrogen, oxygen, nitrogen, argon, and / or combinations thereof. For example, when exposed to plasma, the inhibitor layer 1270 may be released from the surface of the metal wire 242.

[0048] Referring to Figure 5B, method 500' can continue with operations 530 and 535 to form structure 200 as shown in Figure 2C. For simplicity, the descriptions of operations 530 and 535 provided in the discussion of method 500 will not be repeated.

[0049] Referring to Figure 5C, method 500” can be used to form structure 200, as described with reference to Figure 2C. Compared to method 500 in Figure 5A, method 500’ may include the same operations 505 to 520, 530, and 535 as method 500. However, in method 500”, additional operations 565 to 575 are introduced between operations 515 and 520. In the following description of method 500”, for the sake of simplicity, the descriptions of operations 505 to 520, 530, and 535, and the corresponding Figures 6 to 9 and 14, will not be repeated in detail.

[0050] Referring to Figure 5C, and as described with reference to Figure 9, after operation 515, which forms an opening through the dielectric layer and etch stop layer, method 500” can proceed to operation 565 and the process of forming an inhibitor layer on a conductive surface in the opening. For example, inhibitor layer 1570 can be formed on the surface of metal line 242 exposed in the opening 854, as described with reference to Figure 15. Inhibitor layer 1570 can be selectively deposited on conductive surfaces but not on non-conductive surfaces (e.g., the dielectric surfaces of dielectric layer 224 and etch stop layer 230), and can inhibit the subsequent formation of a barrier layer on the surface of metal line 242. In some embodiments, forming inhibitor layer 1570 may include depositing quaternary ammonium cations, benzotriazole, tolyltriazole, and / or 5,6-dimethylbenzotriazole via physical adsorption processes, chemisorption and / or electrostatic adsorption processes.

[0051] Referring to Figure 5C, method 500 can proceed to operation 570 and the process of forming a barrier layer on the dielectric surface in the opening. Unless otherwise stated, the description of forming the barrier layer in operation 525 applies to forming the barrier layer in operation 570. For example, barrier layer 260 can be formed on multiple side surfaces of dielectric layer 224 and etch stop layer 230 exposed in opening 854 and / or trench 944, as described in Figure 16. In some embodiments, the presence of inhibitor layer 1570 can prevent the formation of barrier layer 260 on the upper surface of inhibitor layer 1570 exposed in opening 854.

[0052] Referring to Figure 5C, method 500 can proceed to operation 575 and the process of removing the inhibitor layer. For example, the inhibitor layer 1570 in Figure 16 can be removed to expose the surface of the metal wire 242 in the opening 854, as described in Figure 17. In some embodiments, removing the inhibitor layer 1570 may include plasma treatment of the intermediate structure 200 as shown in Figure 16, via exposing the intermediate structure 200 to a plasma gas, such as hydrogen, oxygen, nitrogen, argon, and / or combinations thereof. For example, when exposed to plasma, the inhibitor layer 1570 may be released from the surface of the metal wire 242.

[0053] Referring to Figure 5C, method 500' can continue with operation 520 to form structure 200 as shown in Figure 14, and then operations 530 and 535 to form structure 200 as shown in Figure 2C. For simplicity, the descriptions of operations 520, 530, and 535 provided in the discussion of method 500 will not be repeated.

[0054] The various embodiments described herein relate to interconnect structures for semiconductor devices and methods of forming interconnect structures. The interconnect structure includes a first metal line, a second metal line on the first metal line, and a conductive via electrically coupling the first and second metal lines. The conductive via includes a protrusion extending laterally and vertically into the first metal line to reduce contact resistance between the conductive via and the first metal line. The method includes forming a first metal line and a dielectric layer on the first metal line, forming an opening in the dielectric layer to expose the first metal line, and laterally recessing the first metal line in the opening. The method further includes depositing a conductive material in the opening to form the conductive via and the second metal line.

[0055] In some embodiments, a structure includes a substrate, a first metal line above the substrate, a dielectric layer on the first metal line, a second metal line in the dielectric layer, and a conductive via electrically coupling the first and second metal lines. The conductive via includes a protrusion extending laterally into the first metal line and a barrier layer surrounding the protrusion.

[0056] In some embodiments, a structure includes a first metal line on a substrate, an etch stop layer on the first metal line, a dielectric layer on the etch stop layer, a conductive via in the dielectric layer and through the etch stop layer, and a second metal line on the conductive via and electrically coupled to the first metal line. The conductive via includes a first portion in the first metal line and below the etch stop layer, a barrier layer surrounding the first portion, and a second portion on the first portion. The width of the second portion is smaller than the width of the first portion.

[0057] In some embodiments, a method includes forming a first metal line on a substrate, depositing a dielectric layer on the first metal line, forming an opening in the dielectric layer, and recessing the first metal line in the opening in both lateral and vertical directions. The method further includes forming a barrier layer on the surface of the opening, depositing a conductive material in the opening to form a conductive via, and forming a second metal line on the conductive via.

[0058] It should be understood that the detailed description section, rather than the summary of the disclosure section, is intended to explain the claims. The summary of the disclosure section may illustrate one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0059] The foregoing disclosure outlines several features of various embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they may readily use this disclosure as a basis for the design or modification of other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0060] 100: Semiconductor devices 102:Substrate 116: Device Layer 120: Dielectric layer 130: Etching Stop Layer 140: Metal wire 150: Conductive via 200: Structure 222: Dielectric layer 224: Dielectric layer 230: Etching Stop Layer 230a: Sublayer 230b: Sublayer 242: Metal wire 244: Metal wire 250: Conductive via 252: Part One 252a: Point (Line) 252b: Point (Line) 252d: Lower surface 252u: Upper surface 254: Part Two 254s: Side surface 260: Barrier Layer 260b: Section 260c: Section 300: Structure 300A: Structure 300B: Structure 300C: Structure 500: Methods 500': Method 500”: Method 505: Operation 510: Operation 515: Operation 520: Operation 525: Operation 530: Operation 535: Operation 550: Operation 555: Operation 560: Operation 565: Operation 570: Operation 575: Operation 854: Opening 944: Trench 1052: Cavity 1270: Inhibitor layer 1570: Inhibitor Layer A-A': line d: Vertical thickness d1: Thickness M0: Interconnect layer M1: Interconnect layer M2: Interconnect layer M3: Interconnect layer s1: Length w1: width w2: width w3: Lateral extension (length) w4: Lateral extension (length) x: axis y: axis y1: Lateral extension z: axis α: Angle β: Angle

Claims

1. A semiconductor device comprising: a substrate; a first metal line above the substrate; a dielectric layer on the first metal line; a second metal line in the dielectric layer; and a conductive via electrically coupling the first metal line and the second metal line, wherein the conductive via includes a protrusion extending laterally into the first metal line, the protrusion including an upper surface and a lower surface, wherein, in a cross-sectional view, the upper surface extends below the dielectric layer along a first horizontal direction to a position, and the lower surface is curved and connected to the upper surface at the position.

2. The semiconductor device as described in claim 1, wherein, The upper surface of the protrusion extends along the first horizontal direction to a width between approximately 1 nanometer and approximately 100 nanometers at the location.

3. The semiconductor device as claimed in claim 2, wherein the ratio of the extension of the protrusion along the first horizontal direction to the width of a portion of the conductive via in the dielectric layer is between about 0.1 and about 1.

4. The semiconductor device as claimed in claim 1 further includes a barrier layer surrounding the conductive via.

5. A semiconductor device comprising: a first metal line above a substrate; an etch stop layer on the first metal line; a dielectric layer on the etch stop layer; a conductive via in the dielectric layer and through the etch stop layer, wherein the conductive via comprises: a first portion in the first metal line and below the etch stop layer; a barrier layer surrounding the first portion; and a second portion on the first portion and in the dielectric layer, wherein a width of the second portion is smaller than a width of the first portion, the first portion comprising an upper surface and a lower surface, wherein, in a cross-sectional view, the upper surface extends along a first horizontal direction below the dielectric layer to a location, the lower surface is curved and connected to the upper surface at the location; and a second metal line on the conductive via and electrically coupled to the first metal line.

6. The semiconductor device as claimed in claim 5, wherein the barrier layer is contained in a horizontal portion between the first portion and the etch stop layer.

7. The semiconductor device as claimed in claim 5, wherein the etch stop layer comprises a first sublayer and a second sublayer, wherein the first sublayer comprises a first dielectric material, and wherein the second sublayer comprises a second dielectric material different from the first dielectric material.

8. A method of forming a semiconductor device, comprising: forming a first metal line on a substrate; depositing a dielectric layer on the first metal line; forming an opening in the dielectric layer; recessing the first metal line in the opening in a first horizontal direction and a vertical direction; forming a barrier layer on a plurality of surfaces of the opening; depositing a conductive material in the opening to form a conductive via, wherein the conductive via includes a first portion in the first metal line and a second portion in the dielectric layer, the first portion including an upper surface and a lower surface, wherein, in a cross-sectional view, the upper surface extends along the first horizontal direction below the dielectric layer to a position, the lower surface is curved and connected to the upper surface at the position; and forming a second metal line on the conductive via.

9. The method of forming a semiconductor device as claimed in claim 8, wherein recessing the first metal line comprises isotropically etching the first metal line to form a cavity in the first metal line, and wherein the cavity has a rivet head shape.

10. The method of forming a semiconductor device as claimed in claim 8, wherein the first metal line recessing includes etching the first metal line in the first horizontal direction and in a second horizontal direction different from the first horizontal direction.

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