Semiconductor structure and method of forming the same and method of forming pillar within via

Abstract

A semiconductor structure and a method for forming the same. In some embodiments, a method for forming a semiconductor device includes forming a redistribution layer including connecting vias and surface mount pad vias, wherein the top surface width of each via is greater than the bottom surface width. The method includes attaching an element to the redistribution layer through a plurality of microbumps and filling the gap between the element and the redistribution layer with molding and underfill. The method includes etching back the redistribution layer to expose the surface mount pad vias and attaching a surface mount pad to the surface mount pad vias. The surface mount pad is connected to the bottom surface width of the surface mount pad via, and the surface mount pad includes protrusions. The method includes attaching a device to the bottom surface of the surface mount pad. This disclosure further includes a method for forming pillars within the vias.

Description

Technical Field

[0001] This invention relates to packaging technology, and more particularly to a semiconductor structure having a redistribution layer and a method for forming the same. Prior Technology

[0002] The semiconductor industry has undergone continuous development due to the ever-increasing density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, these improvements in density are achieved by continuously shrinking the minimum component size, allowing more components to be integrated into a given area (e.g., coverage area).

[0003] A packaging substrate serves as a structure for attaching semiconductor dies to a printed circuit board. Semiconductor packages can include one or more semiconductor devices (e.g., semiconductor dies, interposer modules, etc.) mounted on the substrate. For example, in wafer-level heterogeneous integration devices, various different semiconductor materials (e.g., processing units) are used on a single carrier (e.g., a wafer) to enable advanced modern computing applications. Wafer-level heterogeneous integration devices provide powerful systems with multiple functions, such as high-performance computing and artificial intelligence.

[0004] While heterogeneous integration devices offer high-speed applications, such as artificial intelligence, several challenges remain. For example, wafer-level heterogeneous integration devices face challenges related to yield and defects, material compatibility, thermal management, and bonding alignment and strength. Summary of the Invention

[0005] A method for forming a semiconductor structure. The method includes forming a redistribution layer, wherein the redistribution layer includes a plurality of vias, wherein the vias include a plurality of connecting vias and at least one surface mount pad via, wherein the width of the top surface of each via is greater than the width of the bottom surface of each via; etching back the redistribution layer to expose at least a portion of the at least one surface mount pad via; and attaching a surface mount pad to each of the surface mount pad vias, wherein the surface mount pad is connected to the bottom surface of the surface mount pad via, and the surface mount pad includes a protrusion.

[0006] A method for forming a columnar structure within a via. The method includes etching a dielectric material layer to form a cavity, forming a columnar structure of conductive material within the cavity, and forming a conductive material within the cavity to form a via.

[0007] A semiconductor structure includes a surface mount pad and a seed layer. The surface mount pad includes a pad layer and a plating layer, and the pad layer contacts the bottom width of a via and has a protrusion. The seed layer is located on the surface mount pad and partially contacts the seed layer of the via. Simple Explanation of the Diagram

[0008] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. Figure 1A is a vertical cross-sectional view of the initial layer forming the redistribution layer and an enlarged view of the surface mounting pad guide holes, according to various embodiments of the present disclosure. Figure 1B is a vertical cross-sectional view of the second layer forming the redistribution layer and an enlarged view of the surface mounting pad guide holes, according to various embodiments of the present disclosure. Figure 1C is a vertical cross-sectional view of the redistribution layer and an enlarged view of the connecting vias, according to various embodiments of the present disclosure. Figure 2A is a vertical cross-sectional view illustrating the bonding of a redistribution layer to a carrier board according to various embodiments of the present disclosure. Figure 2B is a vertical cross-sectional view and an enlarged view of the microbumps used to connect components to a redistribution layer according to various embodiments of the present disclosure. Figure 2C is a vertical cross-sectional view illustrating the formation of the bottom fill layer and the molding layer according to various embodiments disclosed herein. Figure 2D is a vertical cross-sectional view illustrating the peeling and joining of various carrier plates according to various embodiments disclosed herein. Figure 2E is a vertical cross-sectional view of the surface mounting pads forming the surface mounting pads and an enlarged view of the surface mounting pads forming the ball grid array, according to various embodiments disclosed herein. Figure 2F is a vertical cross-sectional view illustrating the application of an abrasive belt to a ball grid array to protect the ball grid array during subsequent abrasive and cleaning processes, according to various embodiments disclosed herein. Figure 2G is a vertical cross-sectional view illustrating the drilling and cleaning processes according to various embodiments disclosed herein. Figure 2H is a vertical cross-sectional view illustrating the connection of the device to the surface mounting pad according to various embodiments of the present disclosure. Figure 2I is a vertical cross-sectional view of the attached thermal module according to various embodiments of the present disclosure. Figure 3 is a top view of a semiconductor device according to various embodiments disclosed herein. Figure 4 is a flowchart illustrating a method for forming a semiconductor device according to various embodiments of the present disclosure. Figure 5 is a flowchart illustrating a method for forming a surface mounting pad according to various embodiments of the present disclosure. Implementation

[0009] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements so that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0010] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0011] Ordinal numbers such as "first," "second," and "third" are not inherent parts of any element name; they are only used to individually identify multiple elements having the same or similar characteristics. Therefore, different ordinal numbers can be used for the same element throughout the specification and in the claims. For example, a second element in the specification can be referred to as a first element in the claims.

[0012] Unless otherwise expressly stated, elements having the same reference numerals are assumed to be the same or similar elements, and are assumed to have the same material composition and provide the same function. As used herein, an element or system is "configured for" functioning or operating or "configured to" provide or perform functioning or operating.

[0013] Wafer-level system integration technologies, such as integrated fan-out systems on wafer (InFO-SoW) devices, combine multiple semiconductor materials onto a single wafer to enable advanced device applications. For example, wafer-level system integration can functionally integrate computer components, memory, input / output devices, passive chiplets, and other components. InFO devices specifically offer high bandwidth density, low latency chip-to-chip communication, and low power transmission network impedance. Wafer-level system integration devices are used in high-performance computing (HPC), electrochemical device integration, self-powered chips, implantable health monitoring systems, fully integrated chemical analysis chips, and artificial intelligence.

[0014] Methods for forming wafer-level integrated devices begin with a pick-and-place process that places a component on a carrier substrate, followed by molding and polishing processes. The component may be inverted, with the connecting pad or microbump face upwards. Next, in these methods, a redistribution layer (RDL) is formed layer by layer over the component. In other words, a dielectric layer is placed on top of the component, and vias are then formed within the dielectric layer. To form vias, cavities are typically formed by etching, and then the cavities are filled with a conductive material. Due to the orientation of the component during RDL formation, the vias are typically formed in a trapezoidal shape, where the top of the via (the side facing away from and away from the pad or microbump) is larger than the bottom of the via (i.e., the side closer to the pad or microbump). In this method, the via has a narrower bottom connected to the component. Another dielectric layer may be placed on top of the via layer, and metal traces may be formed within another dielectric layer placed above the via layer. The RDL formation process continues by building dielectric material layers, each with vias or metal traces. Once the RDL is fully formed, ball grid array (BGA) mounting pads can be formed on top of it. Again, due to the orientation of the components and the RDL during formation, the vias connecting to the BGA mounting pads have a trapezoidal shape, with their wider surfaces or the tops of the vias connecting to the BGA mounting pads. Furthermore, the BGA mounting pads are formed on the redistribution layer, resulting in surface mount pads having a concave shape above the top-layer vias of the RDL.

[0015] While wafer-level system integration (WBI) technology improves device performance and power efficiency, it remains complex and presents numerous challenges. For example, wafer-level heterogeneous integration devices typically suffer from yield and defect issues. More specifically, WBI devices require integrating multiple dies onto a single wafer. Due to the size and complexity of the integrated system, achieving high yields is challenging, or in some cases, impossible. Yield losses can be caused by defects in the transistor layer or high-density underlying metal layer. Furthermore, through the formation of the RDL over components, as mentioned above, defects in the RDL (e.g., misalignment or incorrect connections) can lead to failure of the entire semiconductor device. Distortions or defects occurring during RDL formation not only affect the RDL yield but also the yield of components placed beneath it during the fabrication process.

[0016] Furthermore, wafer-level heterogeneous integration devices face challenges in thermal management. Due to high computational density, wafer-level heterogeneous integration devices generate a significant amount of heat. More specifically, inappropriate thermal management and / or yield losses can lead to defective devices, resulting in efficiency and performance issues, and in some cases, complete unusability. By forming and configuring vias in the RDL (Resource Dependency Layer), the wider side of the via is positioned close to the heat-generating components to limit the thermal conductivity of the heat generated by the components. Therefore, effective thermal management strategies can mitigate overheating and ensure reliable device operation.

[0017] The various embodiments disclosed herein relate to semiconductor devices, such as wafer-level heterogeneous integration devices or system-on-wafer (SoW) structures with organic interposer chip on wafer (CoW-R). These embodiments can improve the thermal management of semiconductor devices and reduce yield losses. By forming an RDL and subsequently attaching components to it, defects in the RDL can be detected before component attachment. Furthermore, by forming components and the RDL individually, components can avoid damage that may occur due to the formation of the RDL. Both of these advantages can improve the overall yield of the semiconductor device. Additionally, by forming and configuring the RDL such that the wider side of the vias of the RDL is close to the heat-generating components, thermal management can be improved. Furthermore, the formation of a ball grid array (BGA), which will be described below, can improve the bonding alignment and connection strength between the semiconductor device and connectors and / or devices. This semiconductor device can provide high bandwidth memory (HBM) components for high performance computing (HPC) applications and methods for forming them.

[0018] In one embodiment, the semiconductor device may include connectors, voltage regulator modules (VRMs), redistribution layers, high bandwidth memory (HBMs), system-on-a-chip (SoCs), input / output (IO) components, μ-bump structures, underfill and molding materials, ball grid arrays (BGAs), and thermal modules. The redistribution layer can distribute contact points between devices and generate heat dissipation, thereby enhancing thermal management. The orientation and shape of surface mount pads can promote vertical heat flow, thereby reducing thermal resistance and enhancing heat dissipation.

[0019] Alternative embodiments relate to a method of forming a semiconductor device, such as an organic interposer chip on wafer (CoW-R) system-on-wafer (SoW) structure. In some embodiments, the method forms a redistribution layer including trapezoidal vias, the angle θ between the bottom and sides of the trapezoidal vias being greater than 90°, which enhances thermal performance by allowing better heat dissipation between components and thus reduces overall thermal resistance. In some embodiments, the redistribution layer further includes a seed layer separating the vias from the dielectric material. In some embodiments, the method forms components, such as high-bandwidth memory components, system-on-wafers, or input / output components, connected to the redistribution layer via microbumps. The embodiment methods may also utilize molding and underfill to fill the space between the components and the redistribution layer. The underfill, with its large surface area, dissipates heat generated by the device. Molding can further encapsulate the components and protect them from damage, such as thermal damage. In some embodiment methods, surface mount pads connected to the redistribution layer may be etched. Surface mount pads may include vias, pillars, seed layers, and protruding pads. In some embodiments, devices such as connectors or VRMs can be connected to surface mount pads via BGAs. Surface mount pads can enhance heat dissipation by facilitating vertical heat flow between the device and the RDL, thereby reducing thermal resistance. Furthermore, surface mount pads, due to their large surface area, can minimize thermal paths to allow for heat dissipation.

[0020] The various embodiments disclosed herein offer various advantages and improvements. For example, the disclosed embodiments provide appropriate integration between the RDL, wafer array, HBM, power module, and thermal module within a semiconductor device. More specifically, the embodiments ensure defect-free connection of HBM components to the RDL, thereby improving yield. Furthermore, the RDL improves heat dissipation between the power module and the HBM module, thereby improving thermal management through the thermal module. In this way, the disclosed embodiments can improve HPC applications while regulating the heat generated by the semiconductor device. Some embodiments may utilize a die-lasting approach, which can increase yield and mitigate yield losses for both HBM and SoC. Additionally, some embodiments may utilize an organic interposer and a die-lasting HBM approach. The organic interposer and die-lasting HBM approach can more effectively dissipate heat through bonding to the HBM die, thereby mitigating HBM thermal issues. Some embodiments can provide thermally regulated and power-efficient semiconductor devices capable of performing HPC applications. For example, an RDL can disperse the heat generated by the device and provide heat dissipation, while a surface mount pad can allow heat to flow vertically between the device and the RDL, thereby reducing thermal resistance and improving heat dissipation. Various embodiments provide advantages and improvements in thermal management and yield loss for semiconductor devices incorporating HBM elements.

[0021] Referring now to the accompanying drawings, Figures 1A through 1C illustrate the various steps involved in forming the redistribution layer (RDL) 103 of the semiconductor structure 100. In some embodiments, the RDL 103 can increase package density by allowing a high pin count and increased functionality within a small device package. The RDL 103 can also provide improved electrical performance, as shorter interconnect lengths help reduce power consumption and increase signal speed. The RDL 103 can be used to integrate multiple types of chips and components within a single semiconductor device by providing multiple electrical connections. Furthermore, the RDL 103 can distribute contact points between the devices connected to it. This distribution of contact points generates heat dissipation, which helps enhance thermal management within the semiconductor structure 100. Enhanced thermal management further optimizes heat transfer throughout the semiconductor device and mitigates overheating, thus improving reliability.

[0022] Figure 1A illustrates an example of forming the first layer of RDL 103. RDL 103 includes a dielectric material layer 104 on top of a carrier plate 102. The dielectric material layer 104 may be formed of a polymeric material, while the carrier plate 102 may be formed of an oxide. Various conductive materials, as well as oxide materials, are also within the scope of this disclosure.

[0023] Figure 1A also shows an enlarged view of the surface mount pad via 106. In some embodiments, the surface mount pad via 106 may be formed in a dielectric material layer. The via 106 may be formed through various processes. For example, the cavity may be formed by etching or patterning the first dielectric material layer of the RDL. Once the cavity is formed, subsequent polishing steps (e.g., chemical mechanical polishing) may be performed to smooth the sides of the cavity. To provide a via of sufficient size to support the subsequently formed BGA, the cavity may be designed to have a corresponding width. In some embodiments, the via 106 has a trapezoidal shape, wherein the width of the top of the via 106 is greater than the width of the bottom of the via 106.

[0024] In one embodiment, pillar 108 may be formed in the cavity. A seed layer 124 may be compliantly deposited in the cavity. The seed layer 124 may be deposited by chemical vapor deposition (CVD), atomic vapor deposition (AVD), or other suitable deposition methods. In some embodiments, the seed layer 124 is formed of titanium, tungsten titanate, titanium nitride, or other suitable materials. Other seed layer materials are also within the scope of this disclosure. The seed layer 124 may facilitate the growth of conductive materials (e.g., copper or other conductive materials). Due to the size and width of the cavity, it may be difficult for conductive materials to grow in the cavity. Pillar 108 may be formed in the central portion of the cavity. Pillar 108 may be etched to leave a pillar core of conductive material in the cavity. Pillar 108 may be formed of conductive materials, such as copper, silver, gold, tungsten, or other suitable conductive materials. Pillar 108 may be grown by electroplating or other processes. After core forming and etching, an additional seed layer 110 can be deposited around and above the column 108 and on the surface of the remaining portion of the cavity. The seed layer 110 can be deposited using chemical vapor deposition (CVD), atomic vapor deposition (AVD), or other suitable deposition methods. In some embodiments, the seed layer 110 can be the same material as seed layer 124 or can be a different seed layer material. The seed layer 110 can serve as a base for additional metal deposition and ensure strong adhesion between film layers, while promoting uniform nucleation of the metal film, thereby improving coverage and reliability. The additional metal deposition helps fill the cavity and provides vias with improved strength characteristics, reducing potential damage during subsequent pressure placement of the semiconductor structure 100 to attach connectors and VRMs. Furthermore, the seed layer 110 can serve as a conductive path to improve electron flow between RDL layers. The seed layer 110 can also serve as a barrier layer to prevent diffusion between the metal traces 118 and vias 106 and the dielectric material layer 104.

[0025] In one embodiment, conductive material is grown in the cavity to form via 106. In some embodiments, pillars 108 reduce the amount of conductive material required to fill the cavity. Since the dielectric material layer 104 is formed of an organic material (e.g., a polymer), there is a significant difference in the coefficient of thermal expansion between the dielectric material layer 104 and the conductive material in via 106. Therefore, by first forming pillars 108 surrounded by seed layer 110 and then filling the cavity to form via 106, the amount of conductive material filling the cavity can be reduced, thereby improving thermal mitigation due to the influence of the coefficient of thermal expansion. Because pillars 108 are formed first, compliant formation of conductive material may create a divot 116 above the portion surrounding pillars 108.

[0026] Figure 1B illustrates an example of forming a second metal trace layer in RDL 103 and an enlarged view of the surface mount pad via 106 and metal trace 118. In one embodiment, an additional dielectric material layer is added to dielectric material layer 104. Dielectric material layer 104 can be etched to pattern cavities in which metal trace 118 can be formed. Conductive material can be conformally deposited in the patterned cavities in the additional dielectric material layer to form metal trace 118. Metal trace 118 can be located above via 106. In some embodiments, metal trace 118 is formed of a conductive material, such as copper, silver, gold, tungsten, or other suitable material. Metal trace 118 can be conformally formed above via 106 and therefore includes formation above notch 116. Polishing processes (e.g., chemical mechanical polishing (CMP) processes or grinding processes) can be used to form a single top surface plane and remove the notch 116 present in the first metal trace layer of the RDL.

[0027] Figure 1C illustrates an example of via layers and metal trace layers 118 forming an additional dielectric material layer 104 and RDL 103. Figure 1C also shows an enlarged view of the connecting via 120. In one embodiment, RDL 103 comprises six layers (alternating layers of vias 106, vias 120, and metal traces 118 formed in the dielectric material layer 104). In alternative embodiments, RDL 103 comprises four, five, six, seven, ten, or more than ten layers. Each layer may include the dielectric material layer 104 and vias (e.g., surface mount pad vias 106 or connecting vias 120) or metal traces 118.

[0028] In some embodiments, the connecting via 120 can be formed through various processes. For example, the cavity can be formed by etching or patterning in a corresponding dielectric material layer 104. Patterning can continue for a specified time or until the metal trace 118 is identified. Once the cavity is formed, subsequent polishing steps, such as chemical mechanical polishing, can be performed to smooth the sides of the cavity.

[0029] After the cavity is formed, a seed layer 124 can be deposited on the surface of the cavity using CVD, AVD, or other suitable deposition methods. In some embodiments, the seed layer 124 is formed of titanium, tungsten titanate, titanium nitride, or other suitable materials. The cavity can be filled with a conductive material, such as copper, tungsten, silver, gold, or other suitable materials, to form the connecting via 120 (or metal trace 118). Other seed layer materials are also within the scope of this disclosure. The seed layer 124 can serve as a base for metal deposition and ensure strong adhesion between film layers, while promoting uniform nucleation of the metal film, thereby improving coverage and reliability. Furthermore, the seed layer 124 can serve as a conductive path to improve electron flow between the various RDL layers. The seed layer 110 can serve as a barrier layer to prevent diffusion between the metal trace 118 and the via 120 and the dielectric material layer 104.

[0030] After depositing the seed layer 124, the cavity is filled with a conductive material or a conductive material is grown in the cavity. Similar to the surface-mounted pad via 106, the connecting via 120 can be formed in a trapezoidal shape, with the width of its top surface greater than the width of its bottom surface. In other words, the angle θ between the side of the via 120 and the width of its bottom surface is greater than 90°.

[0031] When via 120 is formed in an intermediate layer of RDL 103, metal trace 118 may be formed on top of via 120. When via 120 is the last layer in RDL 103, no metal trace 118 is added above via 120. In some embodiments, surface mount pad via 106 is larger than connecting via 120. Therefore, connecting via 120 does not include pillars, but is filled with conductive material in a single step.

[0032] In one embodiment, RDL 103 can be tested after its formation to ensure that RDL 103 is reliable before being used in the final semiconductor structure 100. By testing RDL 103 at this stage, embodiments of the invention can stabilize RDL 103, thereby improving overall yield.

[0033] In some embodiments, the network of fine metal traces 118 and vias (e.g., surface mount pad vias 106 and connection vias 120) within the RDL 103 optimizes signal paths by providing contact when components and devices are attached to or connected to the RDL 103. Furthermore, the RDL 103 reduces the overall size of the semiconductor structure 100 by allowing multiple components and devices to be connected to a single RDL 103 and incorporated into a single semiconductor structure 100. Moreover, components are subsequently picked up and placed on the top surface of the RDL 103, allowing components to be placed and connected to the wider top surface of the via 120. This connection to the top surface of the via 120 facilitates the vertical flow of heat from heat-generating components away from the components through the RDL 103.

[0034] Figures 2A through 2H illustrate examples of forming the semiconductor structure 100 after forming the RDL 103. In some embodiments, the semiconductor structure 100 is a chip-on-wafer (CoW) structure for a system-on-chip (SoC) architecture. In one embodiment, the CoW structure includes an organic interposer (CoW-R).

[0035] Figure 2A illustrates an example of an intermediate semiconductor structure having a redistribution layer (RDL) 103 temporarily bonded (e.g., via an adhesive layer 126) on a first carrier wafer 128. The first carrier wafer 128 may comprise a circular wafer or a polygonal wafer, such as a rectangular wafer. When the first carrier wafer 128 is circular, its diameter may be, for example, 100 mm, 300 mm, 450 mm, etc. Generally, the first carrier wafer 128 may comprise a semiconductor wafer, an insulating wafer, a conductive wafer, or a composite wafer with sufficient mechanical strength to support additional wafers subsequently attached thereto. The thickness of the first carrier wafer 128 may range from 500 micrometers to 2 millimeters, but smaller and larger thicknesses may also be used. In one embodiment, the first carrier wafer 128 may comprise a commercially available silicon wafer.

[0036] The first adhesive layer 126 may be applied to the surface of the first carrier wafer 128. In one embodiment, the first adhesive layer 126 may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which may cause the material of the LTHC layer to lose its adhesiveness. Alternatively, the first adhesive layer 126 may include a thermally decomposable adhesive material. For example, the first adhesive layer 126 may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peel temperature of the thermally decomposable adhesive material may be from 100 to 150 degrees Celsius.

[0037] Figure 2B illustrates an example of another intermediate semiconductor structure 100, which includes microbumps 130 for connecting elements (e.g., I / O elements 132, HBM elements 134, and SoC elements 136) to RDL 103. As shown in Figure 2B, various elements can be placed (e.g., using a pick-and-place (PNP) device) and connected to RDL 103 via the microbumps 130. In some embodiments, these elements include system-on-a-chip (SoC) elements 136, multiple high-bandwidth memory (HBM) elements 134, and multiple input / output (I / O) elements 132. Although only one SoC element 136 is shown in the cross-section, in some embodiments, more than one SoC element 136 may be present. Similarly, in some embodiments, one, two, three, or more than three HBM elements 134 and / or I / O elements 132 may be present. Although only SoC element 136, HBM element 134, and I / O element 132 are shown and described, those skilled in the art will understand that other types of elements may exist in various quantities and configurations.

[0038] In some embodiments, the microbumps 130 can be formed using photomasks, deposition, electroplating, and reflow processes. First, a photoresist mask can be applied to define the area where the microbumps 130 are to be formed. A metal seed layer can be deposited first. In some embodiments, the seed layer can be formed of titanium or copper. In some embodiments, the electroplating process includes electroplating a conductive material such as copper onto a predefined seed layer typically formed of titanium or titanium-tungsten. Other conductive materials and seed layer materials are also within the scope of this disclosure. The photoresist layer can be stripped away, leaving the microbumps 130. Finally, the microbumps 130 can undergo a reflow process to form the shape of the microbumps 130.

[0039] In some embodiments, the microbumps 130 may be formed of copper, tungsten, gold, silver, platinum, or other conductive materials. A pitch may exist between the microbumps 130, referring to the distance between adjacent microbumps 130. In some embodiments, the pitch of the microbumps 130 beneath each element may be from about 30 micrometers (μm) to about 160 micrometers, from about 40 micrometers to about 150 micrometers, or from about 80 micrometers to 120 micrometers. The pitch of the microbumps 130 can define the size and density of connectors for the corresponding elements (e.g., SoC element 136, HBM element 134, and I / O element 132), which can then be connected to the semiconductor structure 100 via the microbumps 130. In some embodiments, the microbumps 130 may have dimensions of from about 20 micrometers to 90 micrometers, from about 25 micrometers to about 80 micrometers, or from about 30 micrometers to about 50 micrometers. The microbumps 130 may have a substantially uniform spacing between adjacent microbumps 130. In an alternative embodiment, the microbumps 130 may have substantially inconsistent spacing between adjacent microbumps 130.

[0040] The placement of microbumps 130 can enhance heat dissipation and overcome electromigration challenges. For example, microbumps 130 can provide an interlayer between components (e.g., SoC component 136, HBM component 134, and I / O component 132) and RDL 103 to provide a path for conducting heat generated by the components from the components to RDL 103. Furthermore, microbumps 130 can enhance thermal performance by acting as solid-state heat pumps. Additionally, microbumps 130 provide mechanical support between RDL 103 and the components. Overall, the microbump design provides improved heat dissipation, as well as improved reliability and performance for the semiconductor structure 100.

[0041] Microbumps 130 electrically connect components (e.g., SoC component 136, HBM component 134, and I / O component 132) to RDL 103. In some embodiments, components may be connected via multiple microbumps. Each microbump 130 is associated with a connection via 120. Different components may be connected via microbumps 130 of different shapes, sizes, or numbers. In other embodiments, the shape, size, and number of microbumps 130 may be consistent for each component. In some embodiments, microbumps 130 can enable high-density and low-latency communication between architectures, structures, or components.

[0042] The SoC element 136 is an integrated circuit that combines multiple components onto a single chip. In some embodiments, the SoC element 136 may include one or more of the following: a central processing unit (CPU), a microcontroller, a memory interface, an I / O interface, a secondary storage device, a graphics processing unit (GPU), a radio modem, a coprocessor, and / or other suitable components. In some embodiments, the SoC element 136 may include analog, mixed-signal, and radio-frequency signal processing components. In some embodiments, the SoC element 136 may be a microcontroller-based SoC with various external devices, a microcontroller-based SoC including a microprocessor, a special-purpose SoC designed for a specific application, or other suitable SoC devices. In some embodiments, the incorporation of multiple components (e.g., CPU, GPU, coprocessor) in the SoC element 136 reduces power consumption. Additionally, incorporating multiple components into a single SoC element 136 reduces the wafer area of ​​the semiconductor device and provides tighter component integration.

[0043] In some embodiments, SoC element 136 may reduce power consumption by integrating multiple components into a single element, thus resulting in higher power dissipation. Because SoC element 136 integrates multiple elements, its functionality and performance can be customized. SoC element 136 also reduces die area by integrating multiple dies into a single element, thus providing improved component integration. Additionally, SoC element 136 may improve performance by reducing latency due to placing critical components very close together. SoC element 136 may be located between two other elements, such as between two HBM elements 134.

[0044] HBM element 134 is a dedicated computer memory interface. In some embodiments, HBM element 134 can be used as a 3D stacked synchronous dynamic random-access memory (DRAM). HBM element 134 achieves high bandwidth by vertically stacking multiple DRAM dies. In some embodiments, HBM element 134 can stack multiple channels to provide a wide memory bus. In some embodiments, HBM element 134 utilizes thru-silicon vias (TSVs) to vertically interconnect different memory dies. Other suitable conductive materials are also within the scope of this disclosure. Additionally, in some embodiments, microbumps (e.g., copper microbumps) can be formed on top of the die to establish appropriate electrical connections with other components. HBM element 134 is a memory architecture designed for HPC applications, providing higher bandwidth compared to related memory technologies. In some embodiments, HBM element 134 includes a stacking design that vertically stacks multiple memory dies to create a 3D structure. In some embodiments, the HBM element 134 may have a thickness of about 300 micrometers, about 400 micrometers, about 500 micrometers, about 700 micrometers, about 800 micrometers, or about 900 micrometers.

[0045] In some embodiments, the semiconductor structure 100 includes a plurality of HBM elements 134, resulting in increased heat generation. While a plurality of HBM elements 134 can provide higher memory bandwidth, it also concentrates heat in a smaller space and increases the likelihood of overheating. RDL 103 can improve heat dissipation from the HBM elements 134 and can improve overall thermal management. Because the HBM elements 134 contain multiple memory dies, in some embodiments, the HBM elements 134 can achieve high bandwidth by allowing simultaneous data access processing across multiple memory dies. The HBM elements 134 can also use wide data buses to allow the HBM elements 134 to transfer data between different components (e.g., GPU or CPU and memory), and thus achieve high bandwidth.

[0046] I / O element 132 provides circuitry that allows the exchange of data and signals between external devices (e.g., monitors, speakers, microcontrollers). In some embodiments, I / O element 132 may include input ports for receiving data and signals and output ports for transmitting data and signals. I / O element 132 may be a GPIO element that includes general-purpose input / output (GPIO) pins. In some embodiments, a user may dynamically change the function of I / O element 132 during its operation. In some embodiments, I / O element 132 has a thickness of approximately 300 micrometers, approximately 400 micrometers, approximately 500 micrometers, approximately 700 micrometers, approximately 800 micrometers, or approximately 900 micrometers. In some embodiments, I / O element 132 may be located at the outer edge of semiconductor structure 100, forming a sidewall adjacent to HBM element 134.

[0047] In some embodiments, post-die fabrication methods are used to attach components (e.g., HBM component 134, SoC component 136, and I / O component 132) to RDL 103. In the post-die fabrication method, RDL 103 is formed on a carrier wafer (e.g., RDL 103 is formed on carrier wafer 128) and a logic die is placed on RDL 103. The logic die can be a CPU or a GPU. Subsequently, components (e.g., SoC component 136, HBM component 134, and I / O component 132) are bonded to the top of the logic die. The post-die fabrication method can improve thermal management by dissipating heat generated by the components through the logic die and further through RDL 103. Furthermore, by forming HBM component 134 using the post-die fabrication method, RDL 103 can be inspected before component formation. In this way, since components such as HBM element 134 are not added to the defective RDL 103, defects in the overall semiconductor structure 100 are prevented, thus improving yield. In addition, by using a post-die fabrication method to form HBM element 134, appropriate thermal analysis can be performed on the semiconductor structure 100, thereby mitigating thermal challenges during manufacturing.

[0048] RDL 103 provides connections to and from multiple components (e.g., HBM component 134, SoC component 136, and I / O component 132), thus increasing the package density of semiconductor structure 100 and reducing the overall footprint. RDL 103 also provides efficient signal routing and power distribution between multiple components, improving functional integration. Furthermore, due to the direct connections between microbumps 130, RDL 103 provides efficient heat transfer. Such direct connections allow for efficient heat dissipation through RDL 103, reducing thermal resistance and improving overall thermal management. RDL 103 also provides design flexibility, allowing components and devices to be placed in optimal locations (e.g., placing high-heat-generating components next to low-heat-generating components) to ensure effective heating strategies.

[0049] The trapezoidal shape of via 120 provides improved wiring capabilities between microbumps 130. The trapezoidal profile of via 120 also enhances thermal performance by allowing better heat dissipation between components and thus reducing overall thermal resistance. The trapezoidal profile of via 120 (with a top surface wider than the bottom surface) allows more heat generated from heat-generating components and elements (e.g., HBM element 134, SoC element 136, and I / O element 132) mounted on the top surface to be transferred downwards through via 120, thereby dissipating heat through RDL 103. Additionally, the trapezoidal shape of via 120 provides improved alignment between components, thus ensuring reliable bonding between film layers.

[0050] Turning to Figure 2C, an underfill 142 may be formed on top of the RDL 103, and a mold 146 may subsequently be formed around the underfill 142 and on top of the RDL 103. The mold 146 forms a film layer on top of the RDL 103, while the underfill 142 is formed in a portion of the mold 146. In some embodiments, the underfill 142 may typically have a rectangular, trapezoidal, triangular, or other cross-sectional shape.

[0051] Underfill 142 may be formed around the array of bonded microbumps 130. Underfill 142 may be formed by injecting underfill material around the array of microbumps 130 and between components (e.g., SoC component 136, HBM component 134, and I / O component 132). In some embodiments, underfill 142 may be formed from a combination of epoxy polymer and silica filler or other materials. In some embodiments, underfill 142 may provide thermal expansion matching, mechanical strength, and may fill gaps 144 within the semiconductor structure 100 during the assembly process.

[0052] In some embodiments, the underfill 142 may be a capillary underfill, a non-flowing underfill, a molding underfill, or a wafer-level underfill. Capillary underfill utilizes the capillary flow of a mixture of liquid organic resin binder and inorganic filler (e.g., silicon dioxide) to aid in material curing and reduce the coefficient of thermal expansion. Non-flowing underfill is applied directly to the semiconductor structure 100 without flowing. Non-flowing underfill allows for better control of the underfill process and reduces the risk of voids or incomplete coverage. Molded underfill is pre-molded into a specific shape. Molded underfill undergoes a curing process to ensure proper bonding after placement on the semiconductor device. Wafer-level underfill is applied to the entire semiconductor device before dicing using specialized equipment and processes. Any known underfill material application method can be used, such as a capillary underfill method, a molding underfill method, or a printed underfill method.

[0053] In one embodiment, multiple components (e.g., SoC component 136, HBM component 134, and I / O component 132) may be attached to a dielectric portion (e.g., dielectric material layer 104) within the RDL 103. An underfill 142 may extend continuously beneath the multiple components and surround the microbumps 130. Alternatively, the underfill 142 may be formed in the gaps 144 between the components.

[0054] In some embodiments, the underfill 142 may be formed of an epoxy polymer or other suitable composite material. The underfill 142 can provide mechanical support and structural reinforcement for the semiconductor 100, thereby protecting the microbumps 130. In some embodiments, the underfill 142 can also dissipate heat generated by the device 100 due to its large surface area. The underfill 142 also mitigates stress by providing a compliant layer that reduces mechanical stress as components (e.g., SoC component 136, HBM component 134, and I / O component 132) or microbumps 130 expand or contract during temperature cycling. The underfill 142 can also prevent moisture ingress by encapsulating the microbumps 130 and protect connectors from moisture and contamination, thereby providing long-term reliability. Additionally, the underfill 142 can improve stability and prevent component detachment by providing a protective layer around the component, thus enhancing the durability of the semiconductor structure 100.

[0055] Molding 146 may be applied over the top of RDL 103. In some embodiments, molding 146 surrounds underfill 142. In some embodiments, molding 146 is formed from an organic resin such as epoxy resin, fillers, catalysts, and other suitable materials. Molding 146 is located near underfill 142 to form an outer wall. Molding 146 can encapsulate the component and underfill 142, thus protecting the semiconductor device from external factors such as shock, pressure, moisture, heat, and UV light. Molding 146 can also maintain the electrical insulation properties of the semiconductor device by preventing contact between the component and the environment. For example, molding 146 can prevent short circuits due to undesirable interactions. Additionally, molding 146 can provide a suitable and easy mounting for the device.

[0056] Molding compound 146 may include an epoxy resin compound that can be cured (i.e., cured) to provide a dielectric material portion with sufficient rigidity and mechanical strength. Molding compound 146 may include epoxy resin, a hardener, silica (as a filler), and other additives. Depending on viscosity and flowability, molding compound 146 may be provided in liquid or solid form. Liquid molding compounds provide better workability, good flowability, fewer voids, better filling, and fewer flow marks. Solid molding compounds provide less curing shrinkage, better isolation, and less molding drift. A high filler content (e.g., 85% by weight) in the molding compound can shorten molding time, reduce molding shrinkage, and reduce molding warpage. A uniform filler size distribution in the molding compound can reduce flow marks and enhance flowability. The curing temperature of the molding compound can be from 125°C to 150°C.

[0057] Molding compound 146 can be cured at a curing temperature to form a matrix of portions of a two-dimensional array of components (e.g., SoC component 136, HBM component 134, and I / O component 132) laterally surrounding the underfill 142 and semiconductor grains. The molding compound matrix comprises a plurality of interconnected molding compound grain frameworks. The Young's coefficient of pure epoxy resin is approximately 3.35 GPa, and by adding additives, the Young's coefficient of molding compound 146 can be higher than that of pure epoxy resin. The Young's coefficient of molding compound 146 can be greater than 3.5 GPa. The Young's coefficient of molding compound 146 provides sufficient stiffness to mitigate cracking and stress caused by thermal expansion. In some embodiments, suitable alternative molding materials can be used for molding compound 146.

[0058] Molding 146 can also encapsulate components to protect them from damage. For example, molding 146 can protect the device from mechanical deformation, moisture migration, chemical damage, ultraviolet radiation, and the effects of heat. In other words, molding 146 protects the components within the device from external damage. Additionally, molding 146 can dissipate heat generated by the components, further providing thermal management.

[0059] Figure 2D illustrates a semiconductor structure 100 undergoing bonding and peeling processes with different carrier wafers (first carrier wafer 128 and second carrier wafer 150). In some embodiments, the first carrier wafer 128 is peeled off and removed, and the second carrier wafer 150 is bonded to a mold 146 over the component using an adhesive 148. In some embodiments, the second carrier wafer 150 is temporarily bonded to the semiconductor structure 100 via the adhesive 148 and can provide mechanical stability during processes such as thinning, film deposition, and device integration. In some embodiments, the first carrier wafer 128 and the second carrier wafer 150 may be formed of ceramic materials, metallic materials, plastic materials, aluminum alloys, epoxy fiberglass, glass materials, seamless steel, or other suitable carrier materials.

[0060] The first carrier wafer 128 can be bonded to the RDL 103 through the adhesive layer 126. The first carrier wafer 128 can be an optically transparent material, such as glass or sapphire. In this embodiment, the first adhesive layer 126 may include a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which can cause the material of the LTHC layer to lose its adhesiveness. Alternatively, the first adhesive layer 126 may include a thermally decomposable adhesive material. For example, the adhesive layer 126 may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peel temperature of the thermally decomposable adhesive material can be from 150°C to 400°C. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0061] In other embodiments, the first adhesive layer 126 can be decomposed by ultraviolet radiation or by thermal annealing at a peel temperature. In embodiments where the first carrier wafer 128 comprises an optically transparent material and the first adhesive layer 126 comprises an LTHC layer, the first adhesive layer 126 can be decomposed by irradiating the transparent carrier substrate with ultraviolet light. The LTHC layer can absorb ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and causes the transparent first carrier wafer 128 to separate from the RDL 103. In embodiments where the first adhesive layer 126 comprises thermally decomposable adhesive material, a thermal annealing process can be performed at a peel temperature to separate the first carrier wafer 128 from the RDL 103.

[0062] Figure 2E illustrates another example of an intermediate semiconductor structure 100 that has undergone etching and pad formation processes, as well as an enlarged view of the surface mount pad 158. In some embodiments, the surface mount pad 158 can increase density by allowing more interconnects between components, lower thermal resistance and more efficient heat dissipation, and lower inductance.

[0063] In some embodiments, the dielectric material layer of RDL 103 may undergo an etch-back process to selectively remove portions of the dielectric material layer 104 and expose portions of the via 106. The dielectric material layer 104 may be etched up to a height of 1 micrometer, 2 micrometers, 5 micrometers, 7 micrometers, 8 micrometers, 10 micrometers, or 15 micrometers to expose a portion of the via 106. In some embodiments, the etch-back process is a forward etch-back process or a plasma etching process. In a forward etch-back process, material is mechanically removed. In a plasma etching process, plasma etching is applied to carefully remove the dielectric portion of RDL 103 and expose a portion of the via 106.

[0064] Once a portion of the via 106 is exposed, a seed layer can be deposited using a CVD process, an AVD process, or other suitable deposition process. In one embodiment, the seed layer 156 is formed of titanium, tungsten titanate, or titanium nitride. After depositing the seed layer 156, a pad layer 152 can be compliantly formed beneath the seed layer 156. In some embodiments, the pad layer 152 is formed of a conductive material such as copper, silver, tungsten, or other suitable materials. The pad layer 152 is compliantly formed on the bottom surface, so that the protrusion 153 can be formed beneath the via 106. In one embodiment, a plating layer 154 is formed beneath the pad layer 152. The plating layer 154 can be formed of an alloy such as a tin alloy or other suitable materials.

[0065] In some embodiments, the surface mounting pad 158 is a ball grid array (BGA), a quad flat no-lead (QFN), a land grid array (LGA), a plastic over-molded ball grid array (PBGA), or other suitable surface mounting pad 158.

[0066] In embodiments where the surface mount pad 158 is a BGA, the BGA 158 can be used to subsequently mount devices (e.g., connectors and voltage regulator modules) by utilizing interconnect pins along the entire bottom surface of the device. The BGA 158 provides high density by accommodating multiple pins within a single surface mount pad. Additionally, the BGA 158 provides low thermal resistance due to its overall design. For example, the BGA 158 is directly connected to the RDL 103. This direct contact allows for efficient heat transfer between the BGA 158 and the RDL 103. This direct contact also minimizes the thermal path, thereby reducing thermal resistance. The BGA 158 also has a large surface area to allow for heat dissipation. Vias located in the BGA 158 allow heat to flow vertically, further reducing thermal resistance. The BGA 158 includes a pad layer that connects to the metal trace 118 in the RDL 103 and enhances heat dissipation and improves high-speed performance. Additionally, the via 106 containing the column 108 has increased and improved strength, providing extra strength and support when the BGA 158 is pressurized and applied to the connector 162 and the voltage regulator module (VRM) 164, as described below.

[0067] In other cases, the surface mount pad 158 is a QFN with a flat package and exposed metal pads (not shown) on its bottom surface. In these embodiments, the QFN 158 improves thermal performance due to the large exposed pads, which provide a heat transfer path across the device and reduce thermal resistance. In other words, the large exposed pads act as heat sinks, dissipating heat by carrying most of the generated heat and dissipating it to other parts of the device. In another case, the surface mount pad 158 is a BGA-like LGA; however, the LGA 158 comprises pads or an array of pads on the bottom surface instead of solder balls. In yet another case, the surface mount pad 158 is a PBGA, which combines a plastic-coated body, a glass-mixture laminated substrate, and etched metal traces.

[0068] In one embodiment, the pad 152 may be formed of copper, tungsten, silver, gold, or other suitable conductive materials. The protrusion 153 is an access point for connection to devices (e.g., connector 162 and VRM 164). The protrusion 153 aids in alignment when connecting devices (e.g., connector 162 and VRM 164). Furthermore, the protrusion 153 promotes stable solder formation, resulting in good electrical and mechanical connections. The protrusion 153 improves mechanical stability and prevents component displacement or tilting after connection. Additionally, the protrusion 153 increases the surface area of ​​the surface mount pad 158, leading to improved heat transfer between the devices (e.g., connector 162 and VRM 164) and the RDL 103.

[0069] Figure 2F illustrates an example of another intermediate semiconductor structure 100 that has undergone a second peeling process, a back-grinding taping process, and a grinding process. In some embodiments, the second carrier 150 is removed and a back-grinding (BG) tape 160 is added to mount a pad 158 around the surface.

[0070] The second carrier wafer 150 may be bonded to the mold 146 via adhesive 148. The second carrier wafer 150 may be an optically transparent material, such as glass or sapphire. In this embodiment, adhesive 148 may include a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which may cause the material of the LTHC layer to lose its adhesiveness. Alternatively, adhesive 148 may include a thermally degradable adhesive material. For example, adhesive 148 may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peel temperature of the thermally degradable adhesive material may be from 150°C to 400°C. Other suitable thermally degradable adhesive materials that decompose at other temperatures are also within the scope of this disclosure.

[0071] In other embodiments, the adhesive 148 can be decomposed by ultraviolet radiation or by thermal annealing at a peel temperature. In embodiments where the second carrier wafer 150 comprises an optically transparent material and the adhesive 148 comprises an LTHC layer, the adhesive 148 can be decomposed by irradiating the transparent carrier substrate with ultraviolet light. The LTHC layer can absorb ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and causes the transparent second carrier wafer 150 to separate from the mold 146. In embodiments where the adhesive 148 comprises a thermally decomposable adhesive material, a thermal annealing process can be performed at a peel temperature to separate the second carrier wafer 150 from the mold 146.

[0072] In some embodiments, BG tape 160 may be an ultraviolet (UV) curing tape, a non-UV tape, or other suitable BG tape. UV curing tapes undergo a UV curing reaction in response to exposure to UV irradiation. Under UV irradiation, UV curing tapes undergo a polymerization reaction, hardening the tape and causing it to lose adhesive strength, making it easier to peel off. In contrast, non-UV tapes provide reliable protection without undergoing a UV curing process.

[0073] In some embodiments, BG tape 160 is applied to the surface on which surface mount pads 158 are formed. Once BG tape 160 is applied to the surface, a polishing process removes mold 146 to expose portions of components (e.g., SoC component 136, HBM component 134, and I / O component 132). After polishing, BG tape 160 is removed. BG tape 160 can protect surface mount pads 158 during polishing and / or thinning processes. For example, BG tape 160 can prevent wafer surface contamination caused by the penetration of polishing fluid or other debris.

[0074] Optionally, the semiconductor structure 100 may also undergo other processes and cleaning processes, such as sawing and laser drilling. Referring to Figure 2G, in one embodiment, the processes include mold sawing and laser drilling of the sides of the semiconductor structure 100. Additionally, after sawing and drilling, the semiconductor structure 100 undergoes a laser drilling cleaning process. The sawing, laser drilling, and laser drilling cleaning processes are used to remove portions of the mold 146 and RDL 103 to match the form factor of the semiconductor structure 100. The form factor defines the desired dimensions of the final semiconductor structure 100.

[0075] Figure 2H illustrates an example of a semiconductor structure 100 with connection devices. As shown, the BG tape 160 can be removed, and devices such as connector 162 and voltage regulator module (VRM) 164 can be connected to the surface mount pad 158.

[0076] Connector 162 provides connectivity and communication between semiconductor structure 100 and other devices. In some embodiments, connector 162 may be a board-to-board connector, orthogonal connector, printed circuit board (PCB) connector, circular connector, D-subminiature (D-sub) connector, fiber optic connector, universal serial bus (USB) connector, or other suitable connector. Other connectors are also contemplated within the scope of this disclosure. As shown, semiconductor structure 100 includes two connectors 162. Fewer or more connectors 162 may be used in semiconductor structure 100. In some embodiments, connectors may be of the same or different types. In some embodiments, connector 162 may include intrusion protection to further prevent the ingress of dust, water, or other environmental factors.

[0077] In some embodiments, the semiconductor structure 100 includes one or more VRMs 164. As shown, the semiconductor structure 100 includes two VRMs 164. In alternative embodiments, the semiconductor structure 100 may include a single VRM, two VRMs, three VRMs, or more than three VRMs. The VRMs 164 can regulate the voltage from the power supply to the integrated device. In some embodiments, the VRMs 164 can be used as switching regulators that utilize a buck converter to improve efficiency.

[0078] RDL 103 provides connections to and from multiple components (e.g., connector 162 and VRM 164), thus increasing the package density of semiconductor structure 100 and reducing the overall footprint. RDL 103 also provides efficient signal routing and power distribution among multiple components, improving functional integration. Furthermore, due to the direct connections between surface mount pads 158, RDL 103 provides efficient heat transfer. Direct connections allow for efficient heat dissipation through RDL 103, reducing thermal resistance and improving overall thermal management. RDL 103 also offers design flexibility, allowing components and devices to be placed in optimal locations (e.g., placing high-heat-generating components next to low-heat-generating components) to ensure effective heating strategies.

[0079] The trapezoidal shape of via 106 provides improved wiring capabilities between devices (e.g., connector 162 and VRM 164). The trapezoidal profile of via 106 also enhances thermal performance by allowing better heat dissipation between components and thus reducing overall thermal resistance. The trapezoidal profile of via 106 (with a top surface wider than the bottom surface) allows more heat generated by heat-generating components mounted on the surface mount pad 158 to be transferred through via 106 towards RDL 103 for dissipation. Additionally, the trapezoidal shape of via 106 provides improved alignment between RDL 103 and the surface mount pad 158, thus ensuring reliable bonding between film layers.

[0080] Figure 2I illustrates an example of a semiconductor structure 100 having an attached thermal module 166. In some embodiments, the thermal module 166 may provide a mechanism for removing heat from the semiconductor structure 100. In some embodiments, the thermal module 166 may be a heat pipe thermal module or other suitable thermal module for cooling the semiconductor structure 100. In some embodiments, the thermal module 166 may include a cold plate positioned on top of the component. The cold plate may include, for example, a cold plate substrate (e.g., a copper plate) and a cold plate covering the cold plate substrate. The thermal module 166 may also include, for example, one or more heat pipes located on the cold plate substrate.

[0081] In some embodiments, thermal module 166 may include a distal heat pipe radiator and be part of a distal heat pipe radiator design. In some embodiments, heat generated from HBM 134 or other components may be dissipated through a cold plate substrate. Heat pipes attached to the cold plate substrate may transfer heat removed from HBM 134 or other components to the radiator.

[0082] In some embodiments, the cold plate substrate may include protrusions (e.g., protrusions, bases, etc.) located on an interposer module (e.g., a chip-on-wafer (CoW) die) for cooling. In some embodiments, the thermal module 166 may be used, for example, in a high-performance computing (HPC) fan-out package. The thermal module 166 may include a cavity design located in the protrusion of the cold plate substrate, wherein one or more heat pipes may be bent into a U-shape and soldered into the cavity. In some embodiments, the thermal module 166 helps to improve the thermal performance of a semiconductor package (e.g., a ring-shaped semiconductor package).

[0083] Referring now to Figure 3, which shows a top view of semiconductor structure 100, cut lines A-A' indicate the locations of the cross-sectional views shown in Figures 1A to 1C and Figures 2A to 2H. As shown, semiconductor structure 100 includes a plurality of SoC elements 136 in a two-dimensional (2D) array, each SoC element 136 being surrounded by eight HBM elements 134. Additionally, as shown, I / O elements 132 form the outer perimeter, with each I / O element 132 adjacent to two HBM elements 134.

[0084] As shown in Figure 3, the arrangement of the outer periphery of I / O element 132 adjacent to the HBM element 134 surrounding SoC element 136 allows for the integration of HBM element 134 while mitigating thermal issues. More specifically, by separating HBM element 134, RDL 103, underfill 142, molding 146, and microbumps 130, the heat generated by HBM element 134 can be effectively dissipated. Those skilled in the art will appreciate that various configurations of various elements are possible, including but not limited to the integration of HBM elements.

[0085] The following discussion involves various methods and their steps. Although the methods and steps are discussed in a specific order, or shown in a specific order in the flowchart, a specific execution order does not need to be followed unless explicitly stated or because one action can only be performed after another action has been completed.

[0086] Embodiments will now be described with reference to Figure 4, which is a flowchart illustrating an exemplary method 400 for forming a semiconductor structure 100 according to embodiments of the present disclosure. In some embodiments, step 402 includes forming a redistribution layer 103, wherein the redistribution layer 103 includes a plurality of connection vias 120 and at least one surface mount via 106, wherein the top surface width of each surface mount via 106 / connection via 120 is greater than the bottom surface width of each surface mount via 106 / connection via 120. Referring to Figures 1A to 1C, in step 402 of method 400, the redistribution layer 103 is formed. The redistribution layer 103 includes metal traces 118, surface mount vias 106, connection vias 120, and a dielectric material layer 104.

[0087] In some embodiments, the first layer of RDL 103 is formed by etching cavities in the dielectric material layer 104. Step 402 may optionally include forming conductive pillars 108 in the surface mount pad via 106, forming a seed layer 110 surrounding the conductive pillars 108 and the surface mount pad via 106, and filling the surface mount pad via 106 with a conductive material. Additionally, step 402 may include forming metal traces 118 over the surface mount pad via 106.

[0088] In some embodiments, step 402 includes forming at least six film layers in RDL 103, wherein each film layer includes at least one of a metal trace 118 or a via (e.g., a surface mount pad via 106 or a connection via 120). Step 402 may also include forming the metal trace 118 below and above the connection via 120. Optionally, step 402 includes forming a seed layer 124 around the connection via 120.

[0089] In some embodiments, step 404 includes connecting components (e.g., I / O components 132, HBM components 134, or SoC components 136) to the redistribution layer 103 via a plurality of microbumps 130, wherein each microbump 130 is connected to the top surface width of a connection via 120. The wider top surface of the connection via 120 improves the alignment of the microbumps 130 and can facilitate improved thermal mitigation by allowing more heat energy to flow vertically away from the heat-generating component. Referring to Figure 2B, in step 404 of method 400, the components may include HBM components 134, SoC components 136, or I / O components 132. In some embodiments, the SoC components 136 may be placed in a two-dimensional array in a first horizontal direction hd1 and a second horizontal direction hd2. The SoC components 136 may be placed on RDL 103 such that all sides are surrounded by HBM components 134 in a top view. Additionally, I / O components 132 can be placed on RDL 103 and connected via microbumps 130, such that I / O components 132 surround a two-dimensional array of SoC components 136 and HBM components 134 in a top view. In other words, SoC components 136 and HBM components 134 can be positioned such that I / O components 132 surround the outer periphery of semiconductor structure 100, as shown in Figure 3. In some embodiments, the components are connected to redistribution layer 103 via microbumps 130. In some embodiments, microbumps 130 can have a pitch of at least 150 micrometers. Additionally, in some embodiments, microbumps 130 can have a critical dimension of at least 80 micrometers. In some embodiments, microbumps 130 can be formed of solder material.

[0090] In some embodiments, step 406 includes filling the gap 144 between an element (e.g., I / O element 132, HBM element 134, or SoC element 136) and the redistribution layer 103 with a molding 146 and an underfill 142, wherein the molding 146 forms an outer edge and the underfill 142 is located between the element (e.g., I / O element 132, HBM element 134, or SoC element 136) and the redistribution layer 103. Referring to Figure 2C, in step 406 of method 400, the molding 146 and the underfill 142 form a film layer over RDL 103. In some embodiments, the molding 146 forms a sidewall of the semiconductor structure 100. The underfill 142 may surround the microbumps 130 and a portion of the element, while the molding 146 may surround the underfill 142.

[0091] In some embodiments, step 408 includes etching back the redistribution layer 103 to expose at least a portion of the surface mount pad via 106, and step 410 includes forming a surface mount pad 158 on the surface mount pad via 106, wherein the surface mount pad 158 is connected to the bottom surface width of the surface mount pad via 106, and the surface mount pad 158 includes a protrusion 153. Referring to Figure 2E, in step 408 of method 400, a portion of the RDL 103 may be etched back to expose at least a portion of the surface mount pad via 106. In some embodiments, step 408 includes depositing a seed layer 156 in contact with the dielectric material layer 104 and the via 106. A pad layer 152 is formed to contact the etched portion and is formed of a conductive material such as copper, tungsten, silver, gold, or other suitable material. Because the pad layer 152 is compliantly formed, a protrusion 153 is also formed below the via 106. In one embodiment, a plating layer 154 may be formed below the pad layer 152. In some embodiments, the plating 154 may be formed of an alloy such as a tin alloy.

[0092] In some embodiments, step 412 includes attaching a device (e.g., connector 162 or VRM 164) to the bottom surface of surface mounting pad 158. Referring to Figure 2G, in step 412 of method 400, the device may be hybrid-engaged to surface mounting pad 158. In some embodiments, method 400 may further include attaching a thermal module 166 above the element. In some embodiments, the thermal module 166 can dissipate heat from the element, such as HBM 134, and mitigate thermal issues.

[0093] The embodiments will now be described with reference to Figure 5, which is a flowchart illustrating an exemplary method 500 for forming a surface mount pad 158 according to an embodiment of the present disclosure. In some embodiments, step 502 includes etching back at least a portion of the dielectric material layer 104 in the redistribution layer 103. As shown in Figure 2E, in step 408 of method 400, at least a portion of the RDL 103 is etched back to expose at least a portion of the via 106. In one embodiment, a portion of the dielectric material layer 104 is etched back to remove a height of up to 10 micrometers of the dielectric material layer 104.

[0094] In some embodiments, step 504 includes depositing a seed layer 156 on the bottom surface of the redistribution layer 103 and over the exposed portion of the surface mount pad via 106. The seed layer 156 may be deposited using CVD, AVD, or other suitable deposition methods. The seed layer 156 may be formed of titanium, tungsten titanate, titanium nitride, or other suitable materials.

[0095] In some embodiments, step 506 includes forming a pad 152 beneath the bottom surface, wherein the pad 152 includes a protrusion 153, and step 508 includes forming a plating layer 154 beneath the pad 152. In one embodiment, the pad 152 is compliantly formed beneath the etched RDL 103 and thus includes a protrusion 153 located beneath the via 106. The pad 152 may be formed of a conductive material such as copper, tungsten, silver, gold, or other suitable materials. The plating layer 154 may be formed of an alloy such as a tin alloy.

[0096] Referring to all the accompanying drawings and various embodiments of the present disclosure, a method of forming a semiconductor structure 100 includes forming an RDL 103, wherein the RDL 103 includes a plurality of vias (connecting vias 120, surface mount vias 106), wherein the plurality of vias includes connecting vias 120 and at least one surface mount via 106, wherein the top surface width of each via (connecting via 120, surface mount via 106) is greater than the bottom surface width of each via (connecting via 120, surface mount via 106); etching back the RDL 103 to expose at least a portion of at least one surface mount via 106; and attaching a surface mount pad 158 to the surface mount via 106, wherein the surface mount pad 158 is connected to the bottom surface of the surface mount via 106, and the surface mount pad includes a protrusion 153.

[0097] In some embodiments, forming RDL 103 further includes: etching a dielectric material layer to form a surface mount pad cavity; forming a columnar structure 108 of conductive material in the surface mount pad cavity; depositing a seed layer 110 surrounding the columnar structure 108 and the surface of the surface mount pad cavity; and forming a conductive material in the surface mount pad cavity to form a surface mount pad via 106. In some embodiments, forming RDL 103 further includes forming a metal trace 118 over the surface mount pad via 106. In some embodiments, forming RDL 103 further includes etching in a dielectric material layer to form a connection via cavity; depositing a seed layer 124 on the surface of the connection via cavity; and forming a conductive material in the connection via cavity to form a connection via 120. In some embodiments, forming RDL 103 further includes forming a metal trace 118 over the connection via 120. In some embodiments, the method further includes attaching a thermal module 166 onto multiple components (e.g., I / O component 132, HBM component 134, or SoC component 136). In some embodiments, forming the RDL 103 further includes forming at least six film layers, wherein each film layer includes at least a metal trace 118 or a via (connection via 120, surface mount pad via 106). In some embodiments, the dielectric material layer 104 is etched back to expose a portion of the surface mount pad via 106, wherein the surface mount pad via 106 has a top surface width greater than the bottom surface width. In some embodiments, the method further includes depositing a surface mount pad seed layer 156, the surface mount pad seed layer 156 partially contacting the surface mount pad via seed layer 124. In some embodiments, the dielectric material layer 104 is etched back to remove up to 10 micrometers of the dielectric layer.

[0098] In another embodiment, the method of forming a pillar in a via includes etching a dielectric material layer (e.g., redistribution layer 103) to form a cavity; forming a pillar 108 made of a conductive material in the cavity; and forming a conductive material in the cavity to form a via 106.

[0099] In some embodiments, the method further includes depositing a seed layer surrounding the surface of the column 108 and the cavity 124.

[0100] In another embodiment, the semiconductor structure 100 includes a surface mount pad 158, wherein the surface mount pad 158 includes a pad layer 152 and a plating layer 154, wherein the pad layer 152 contacts the bottom width of the via 106 and has a protrusion 153; and a seed layer 156, which is located on the surface mount pad 158 and partially contacts the via seed layer 124.

[0101] In some embodiments, the semiconductor structure 100 further includes an RDL 103, which includes vias 106 and metal traces 118 located within a dielectric material layer 104. The vias 106 are formed beneath the metal traces 118, the top surface width of the vias 106 is greater than the bottom surface width of the vias 106, pillars 108 are located within the vias 106 and surrounded by a seed layer 110, and the vias 106 are filled with a conductive material. In some embodiments, the RDL 103 further includes a connection via 120, wherein the connection via 120 has a top surface width greater than the bottom surface width. In some embodiments, a plurality of microbumps 130 are provided, each connecting one of a plurality of elements (e.g., I / O element 132, HBM element 134, or SoC element 136) to the connection via 120 in the RDL 103, and the microbumps 130 have a pitch of up to 150 micrometers. In some embodiments, the conductive material is copper. In some embodiments, the pad 152 is formed of copper, and the plating 154 is formed of a tin alloy. In some embodiments, the dielectric material layer 104 includes a plurality of dielectric layers, and each dielectric layer includes at least one connection via 120, at least one surface mount pad via 106, or at least one metal trace 118. In some embodiments, the semiconductor structure 100 further includes a plurality of elements (e.g., I / O element 132, HBM element 134, or SoC element 136), including at least one high-bandwidth memory element 134; a plurality of microbumps 130, wherein each microbump connects one of the plurality of elements (e.g., I / O element 132, HBM element 134, or SoC element 136) to a connection via 120 in the RDL 103, and the microbumps 130 have a pitch of up to 150 micrometers; an underfill 142, wherein the underfill 142 is located between the element (e.g., I / O element 132, HBM element 134, or SoC element 136) and the RDL 103 and surrounds the microbumps 130; and a molding layer 146, wherein the molding layer 146 surrounds each side and top of the underfill 142 and forms a sidewall; at least one device (e.g., connector 162 or VRM 164), wherein the device (e.g., connector 162 or VRM) 164) Attached to the bottom surface of the surface mounting pad 158; and a thermal module 166 located on top of the components (e.g., I / O component 132, HBM component 134, or SoC component 136).

[0102] The various embodiments disclosed herein offer various advantages and improvements. For example, the disclosed embodiments provide suitable integration between various components in a semiconductor device, such as wafer-level heterogeneous integration devices or CoW-R SoW devices. In this way, the disclosed embodiments can improve complex applications, such as HPC applications, while addressing thermal challenges. The various embodiments disclosed herein can utilize HBM post-die methods during the formation of semiconductor devices. In this way, the disclosed embodiments improve yield and avoid yield losses due to HBM and SoC issues. Furthermore, the embodiments disclosed herein disclose HBM post-die methods combined with organic interposers to prevent thermal problems. Overall, the embodiments can provide thermal conditioning and reduce yield losses in semiconductor devices with HBM components while maintaining HPC application capabilities.

[0103] The components of several embodiments are summarized above to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0104] 100: Semiconductor Structure 102: Carrier board 103: Rewire Layer (RDL) 104: Dielectric material layer 106: Surface mounting pad guide hole / guide hole 108: Columnar material 110: Seed layer 116: Notch 118: Metallic traces 120: Connecting guide hole / guide hole 124: Seed layer 126: Adhesive layer 128: Carrier wafer 130: Microbumps 132: Input / Output (I / O) Elements 134: High-bandwidth memory (HBM) device 136: System-on-a-Chip (SoC) Component 142: Bottom filler 144: Gap 146: Molding 148: Adhesive 150: Carrier wafer 152: Subbase 153: Protrusion 154: Coating 156: Seed layer 158: Surface support pad 160: Back-Grinding (BG) Tape 162: Connector 164: Voltage Regulator Module (VRM) 166: Thermal Module 400, 500: Method 402, 404, 406, 408, 410, 412, 502, 504, 506, 508: Steps hd1: First horizontal direction hd2: Second horizontal direction θ: angle

Claims

1. A method for forming a semiconductor structure, comprising: A redistribution layer is formed, wherein the redistribution layer includes a plurality of vias, wherein the vias include a plurality of connecting vias and at least one surface mount pad via, wherein the width of a top surface of each of the vias is greater than the width of a bottom surface of each of the vias; the redistribution layer is etched back to expose at least a portion of the at least one surface mount pad via; and a surface mount pad is attached to each of the surface mount pad vias, wherein the surface mount pad is connected to a bottom surface of the surface mount pad via, and the surface mount pad includes a protrusion.

2. The method for forming a semiconductor structure as described in claim 1 further includes: Etch a dielectric material layer to form a surface mount pad cavity. A pillar made of a conductive material is formed in the surface-supported pad cavity; a seed layer is deposited around the pillar and a surface of the surface-supported pad cavity. The conductive material is formed in the cavity of the surface mounting pad to form the guide hole of the surface mounting pad.

3. The method for forming a semiconductor structure as described in claim 1, wherein forming the redistribution layer further comprises: Etching in a dielectric material layer to form a connecting via cavity. A seed layer is deposited on one surface of the connecting via cavity; and a conductive material is formed in the connecting via cavity to form the connecting vias.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein a dielectric layer is etched back to expose the portion of the surface mount pad via, wherein the surface mount pad via has a top surface width and a bottom surface width, the top surface width being greater than the bottom surface width.

5. A method for forming a columnar object in a guide hole, comprising: Etch a dielectric material layer to form a cavity; A columnar object made of a conductive material is formed in the cavity, wherein the columnar object partially fills the cavity; And the conductive material is formed in the cavity to form a via.

6. The method of forming a column in a via as described in claim 5 further includes depositing a seed layer surrounding the column and a surface of the cavity.

7. A semiconductor structure comprising: A surface mount pad includes a pad and a plating, wherein the pad contacts a bottom width of a via and has a protrusion; and a seed layer is located on the surface mount pad and partially contacts the seed layer of the via.

8. The semiconductor structure as claimed in claim 7 further includes a redistribution layer comprising a via and a metal trace located in a dielectric material, wherein the via is formed below the metal trace, a top surface width of the via is greater than a bottom surface width of the via, a pillar is located in the via and surrounded by a pillar seed layer, and the via is lined with the pillar seed layer and filled with a conductive material.

9. The semiconductor structure as described in claim 7 or 8 further includes a plurality of microbumps, wherein each of the microbumps connects one of the plurality of elements to a connection via in the redistribution layer, and the microbumps have a pitch of up to 150 micrometers.

10. The semiconductor structure as claimed in claim 7, wherein the pad is formed of copper and the plating is formed of a tin alloy.

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