Ferroelectric memory devices with a three-dimensional topography structure

Abstract

According to some embodiments of the present invention, a storage device is provided. The storage device may include: a three-dimensional (3D) feature structure fabricated on a bonding pad comprising a conductive material, a first electrode fabricated on the 3D feature structure, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer may include at least one ferroelectric material, such as HfO2, ZrO2, Hf1-xZrxO2, Al1-xScxN, BaTiO3, LiNbO3, NaTaO3, etc. The 3D feature structure may be a pillar, a fin structure, a trench, a via, etc.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to a storage and computing device, and more specifically, to a ferroelectric storage device having a three-dimensional (3D) topology. Prior Technology

[0002] Ferroelectric materials are materials that exhibit spontaneous polarization, and whose polarization direction can be reversed by applying a suitable electric field. Examples include hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2), scandium-doped aluminum nitride (Al1-xScxN), titanates (BaTiO3), niobates (LiNbO3), and tantalates (NaTaO3). Even when the electric field is removed, ferroelectric materials retain their polarization state. Therefore, ferroelectric materials can store data when power is off. This makes ferroelectric materials a strong candidate for realizing non-volatile memory, which retains stored data even when the external power source is disconnected. Summary of the Invention

[0003] The following is a simplified overview of the invention to provide a basic understanding of certain aspects of it. This overview is not a comprehensive summary of the invention. Its purpose is neither to identify key or essential elements of the invention, nor to define any scope of particular embodiments of the invention or the scope of any patent application. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to a more detailed description thereafter.

[0004] According to one or more aspects of the present invention, a storage device is provided. The storage device includes: a three-dimensional (3D) feature structure fabricated on connection pads comprising a conductive material; a first electrode; a ferroelectric layer fabricated on the first electrode; and a second electrode fabricated on the ferroelectric layer. At least a portion of the first electrode is fabricated on the surface of the 3D feature structure. The ferroelectric layer comprises a ferroelectric material.

[0005] In some embodiments, the three-dimensional feature includes at least one of a column, fin, groove, or through hole.

[0006] In some embodiments, the three-dimensional feature includes an opening formed in a dielectric layer, wherein the dielectric layer is formed on the connection pad.

[0007] In some embodiments, the three-dimensional feature exposes at least a portion of the connection pad, and at least a portion of the first electrode is formed on the exposed portion of the connection pad.

[0008] In some embodiments, at least a portion of the first electrode is fabricated on the top surface of the dielectric layer and on the sidewalls of the three-dimensional feature.

[0009] In some embodiments, the connection pads are fabricated on a substrate, and the three-dimensional feature extends outward from a two-dimensional plane on the top surface of the substrate.

[0010] In some embodiments, at least a portion of the first electrode is fabricated on the top surface of the three-dimensional feature and on the top surface of the connection pad.

[0011] In some embodiments, the ferroelectric material comprises a metal oxide, wherein the metal oxide comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2, where x ranges from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN, where x>0.3), titanate (BaTiO3), niobate (LiNbO3), or tantalate (NaTaO3).

[0012] In some embodiments, the ferroelectric material is interstitially doped with at least one interstitial dopant, wherein the at least one interstitial dopant includes at least one of H, N, C, B or F.

[0013] In some embodiments, the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium.

[0014] In some embodiments, the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium.

[0015] According to one or more aspects of the present invention, a method for manufacturing a storage device is provided. The method includes: fabricating a three-dimensional (3D) feature structure on interconnect pads comprising a conductive material, wherein the interconnect pads are fabricated on a substrate; fabricating a first electrode layer on the substrate, the interconnect pads, and the three-dimensional feature; fabricating a ferroelectric layer comprising a ferroelectric material on the first electrode layer; and fabricating a second electrode layer on the ferroelectric layer.

[0016] In some embodiments, the three-dimensional feature includes at least one of a column, fin, groove, or through hole.

[0017] In some embodiments, fabricating the three-dimensional feature on the connection pad includes fabricating a dielectric layer with openings on the connection pad.

[0018] In some embodiments, the three-dimensional feature exposes at least a portion of the connection pad, and at least a portion of the first electrode is formed on the exposed portion of the connection pad.

[0019] In some embodiments, at least a portion of the first electrode is formed on the top surface of the dielectric layer and the sidewalls of the openings in the dielectric layer.

[0020] In some embodiments, the connection pads are fabricated on a substrate, and the three-dimensional feature extends outward from a two-dimensional plane on the top surface of the substrate.

[0021] In some embodiments, at least a portion of the first electrode is fabricated on the top surface of the three-dimensional feature and the top surface of the connecting pad.

[0022] In some embodiments, the ferroelectric material comprises a metal oxide, and the metal oxide comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2, where x ranges from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN, where x>0.3), titanate (BaTiO3), niobate (LiNbO3), or tantalate (NaTaO3).

[0023] In some embodiments, the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium, and the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium. Simple Explanation of the Diagram

[0024] The invention will be more fully understood through the following detailed description and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting the invention to the specific embodiments, and are for explanation and understanding only.

[0025] Figures 1A and 1B show cross-sectional views of exemplary storage devices according to some embodiments of the present invention;

[0026] Figures 2A, 2B, 2C, 2D, 2E, and 2F illustrate structures related to the manufacturing process of storage devices according to some embodiments of the present invention;

[0027] Figures 3A, 3B, 3C, 3D, 3E, and 3F illustrate structures related to the manufacturing process of storage devices according to some embodiments of the present invention;

[0028] Figure 4 is a flowchart illustrating an exemplary process for manufacturing a storage device according to some embodiments of the present invention;

[0029] Figure 5A is a flowchart illustrating an exemplary process for fabricating an interconnect structure including metal vias and metal pads;

[0030] Figures 5B-5G show cross-sectional views of structures for manufacturing interconnect structures according to some embodiments of the present invention. Implementation

[0031] Various aspects of the present invention provide ferroelectric storage devices and methods for manufacturing the same. The ferroelectric storage device may be a portion of ferroelectric random access memory (Fe-RAM), such as a capacitor (e.g., a ferroelectric capacitor (FeCAP)), a transistor (e.g., a ferroelectric field-effect transistor (FeFET)), a ferroelectric tunnel junction (FTJ), or ferroelectric random access memory (FeRAM).

[0032] Ferroelectric materials can be polarized in response to the application of an external electric field and retain their polarization even after the external electric field is removed. This reversible spontaneous polarization originates from the non-centrosymmetric arrangement of ions in the ferroelectric material, which generates a permanent electric dipole moment. Adjacent dipoles tend to align in the same direction, thus forming regions known as ferroelectric domains.

[0033] A single material can possess multiple polymorphs with varying ferroelectric properties. For example, hafnium oxide (HfO2) can exist as a monoclinic phase (m phase) between room temperature and 1670°C. With increasing temperature, HfO2 may undergo phase transitions from the monoclinic (m phase) to the tetragonal (t phase) and then to the cubic (c phase). HfO2 does not exhibit ferroelectricity in the m, t, or c phases, but it does in the orthorhombic polar phase (o phase). Although the m-HfO2 phase is thermodynamically the most stable phase near ambient temperature, the o-HfO2 phase exhibits unique properties due to its inherent non-centrosymmetric polarity and ferroelectric behavior. Ferroelectricity in a material is related to the permanent polarization of the crystalline dielectric under an electric field. Ferroelectric materials exhibit two-state polarization behavior, enabling them to store binary information ("0" and "1") in a non-volatile manner, making them suitable for storage devices.

[0034] FeRAM devices typically consist of a planar MIM (metal-insulator-metal) capacitor structure, where "M" represents metal and "I" typically represents insulator. In FeRAM, "I" is replaced by ferroelectric material. While scaling down the size of FeRAM devices can reduce their volume, it may lead to a reduction in the amount of ferroelectric material within the device, thus decreasing the ferroelectric signal measurable from the device. Therefore, optimizing the MIM size while maintaining a small silicon wafer footprint holds promise for improving FeRAM performance at a lower cost.

[0035] This invention provides a ferroelectric memory device and a method for manufacturing the same. The memory device may include a stack of ferroelectric devices fabricated on a three-dimensional (3D) feature structure. The three-dimensional feature may extend outward from a two-dimensional plane containing the top surface of the substrate supporting the ferroelectric device stack, or may be etched into the substrate and / or fabricated within the substrate. For example, the ferroelectric device stack may be fabricated on pillars, fin structures, etc.; or, for example, within vias, trenches, etc. Because the ferroelectric device stack is fabricated on a three-dimensional feature, it can be considered a 3DFeRAM device. Compared to a planar ferroelectric device stack with a planar ferroelectric thin film, the three-dimensional ferroelectric device of this invention can have an increased total surface area, thereby accommodating more ferroelectric material without increasing the overall device footprint. This ultimately enhances the ferroelectric signal without sacrificing size or cost efficiency.

[0036] Figures 1A and 1B show cross-sectional views of exemplary storage devices 100a and 100b according to some embodiments of the present invention.

[0037] As shown in FIG1A, the storage device 100a may include a substrate 110a, a three-dimensional feature 120a, a first connection pad 115a, a ferroelectric device stack layer 130a, and a second connection pad 140a. In some embodiments, the second connection pad 140a may include a connection via (e.g., a metal via) and a connection pad (e.g., a metal pad). The storage device 100a may also include a dielectric layer 150a surrounding the second connection pad 140a and the ferroelectric device stack layer 130a. The storage device 100a may be a non-volatile storage device that retains stored data even when no power is applied.

[0038] Substrate 110a may include any suitable material for providing a substrate for the fabrication of storage devices, such as silicon, sapphire, silicon carbide, etc. In some embodiments, substrate 110a may include driving circuitry comprising one or more individually controllable circuits (e.g., circuit arrays). In some embodiments, driving circuitry may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.

[0039] The first connection pad 115a may be fabricated on the substrate 110a. In one implementation, the top surface of the first connection pad 115a is higher than the top surface of the substrate 110a. The first connection pad 115a may include any suitable conductive material, such as a metal, metal nitride, alloy, etc., for providing ohmic contacts for devices fabricated on the first connection pad 115a. In some embodiments, the substrate 110a may be a CMOS substrate, and the first connection pad 115a may include interconnect structures of the CMOS substrate (e.g., metal pads, metal vias, etc.).

[0040] The three-dimensional feature 120a can be a pillar, a fin structure (i.e., a thin-walled structure), or any other suitable structure fabricated on the first connection pad 115a and extending outward from a two-dimensional plane on the top surface of the substrate 110a. The three-dimensional feature 120a may cover a portion of the top surface of the first connection pad 115a, rather than the entire top surface of the first connection pad 115a. The three-dimensional feature 120a may include one or more dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0041] The ferroelectric device stack 130a can be conformally fabricated on the top surface of the substrate 110a, the top surface of the first connection pad 115a, and the sidewalls of the three-dimensional feature 120a.

[0042] The ferroelectric device stack 130a may include a first electrode 131a, a ferroelectric layer 133a, and a second electrode 135a. The first electrode 131a may include any suitable conductive material. For example, the first electrode 131a may include metals such as tungsten (W), ruthenium (Ru), molybdenum (Mo), platinum (Pt), palladium (Pd), iridium (Ir), etc. Alternatively, the first electrode 131a may include nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc. As shown in FIG1A, the first electrode 131a may be conformally fabricated on the top surface of the substrate 110a, the first connection pad 115a, and the three-dimensional feature 120a, and extends along the sidewalls of the three-dimensional feature 120a. In some embodiments, one or more portions of the first electrode 131a may directly contact the top surface of the first connection pad 115a.

[0043] The ferroelectric layer 133a may comprise one or more ferroelectric thin films conformally fabricated on the first electrode 131a. Each ferroelectric thin film may contain a ferroelectric material. The ferroelectric material may include metal oxides, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2, where x ranges from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN) with a scandium doping concentration x>0.3, titanate (BaTiO3), niobate (LiNbO3), tantalate (NaTaO3), etc. In some embodiments, the metal oxide may be doped with one or more alternative and / or interstitial dopants, which may occupy vacancies between atoms of the ferroelectric material. Interstitial dopants may include elements with atomic radii no greater than the atomic radius of the metal element in the metal oxide. The metal oxide may contain at least one of hafnium and zirconium. Interstitial dopants may include non-metallic elements, such as H, N, C, B, F, etc. Interstitial dopants can be introduced into ferroelectric thin films using ion implantation, co-sputtering, alternating sputtering, thermal diffusion, chemisorption, and / or any other suitable techniques. In some embodiments, the doping concentration of the interstitial dopant may be about 10% or less. As shown in FIG1A, the ferroelectric layer 133a can be conformally fabricated on the first electrode 131a, and thus fabricated on the top surface of the first connection pad 115a, the top surface of the three-dimensional feature 120a, and the sidewalls of the three-dimensional feature 120a.

[0044] The second electrode 135a may comprise any suitable conductive material conformally fabricated on the ferroelectric layer 133a. For example, the second electrode 135a may comprise metals (such as tungsten, ruthenium, molybdenum, platinum, palladium, iridium, etc.) and / or nitrides (such as titanium nitride, tantalum nitride, tungsten nitride, etc.). The second electrode 135a may comprise the same material as the first electrode 131a or may comprise different materials. As shown in FIG1A, the second electrode 135a may be conformally fabricated on the ferroelectric layer 133a, and thus fabricated on the top surface of the first connection pad 115a, the top surface of the three-dimensional feature 120a, and the sidewalls of the three-dimensional feature 120a.

[0045] The second connection pad 140a may contain any suitable conductive material, such as a metal, metal nitride, alloy, etc., for providing ohmic contact for the ferroelectric device stack layer 130a. In some embodiments, the second connection pad 140a may include one or more interconnect structures (such as metal pads, metal vias, etc.). As shown, the second connection pad 140a may be fabricated in a dielectric layer 150a. The dielectric layer 150a may include one or more suitable dielectric materials fabricated on the first connection pad 115a. The dielectric layer 150a may cover the ferroelectric device stack layer 130a.

[0046] Referring to FIG1B, the storage device 100b may include a substrate 110b, a dielectric layer 120b, a first connection pad 115b, a ferroelectric device stack layer 130b, and a second connection pad 140b. In some embodiments, the second connection pad 140b may include a via and a connection pad. The storage device 100b may be a non-volatile storage device that retains stored data even when no power is applied. The substrate 110b may be the same as the substrate 110a. The first connection pad 115b may be the same as the first connection pad 115a.

[0047] The dielectric layer 120b may comprise one or more layers of dielectric material (e.g., SiO2, Si3N4, etc.) having three-dimensional features (e.g., vias, trenches, etc.) etched into and / or fabricated within the substrate 110b, said three-dimensional features exposing at least a portion of the top surface of the first connection pad 115b. Therefore, the dielectric layer 120b does not cover at least a portion of the first connection pad 115b. A ferroelectric device stack layer 130b may be fabricated within the three-dimensional features and on the top surface of the dielectric layer 120b.

[0048] The ferroelectric device stack 130b may include a first electrode 131b, a ferroelectric layer 133b, and a second electrode 135b. The first electrode 131b may contain the same material as the first electrode 131a. As shown in FIG1B, the first electrode 131b may be conformally fabricated within a three-dimensional feature of the dielectric layer 120b and on the top surface of the dielectric layer 120b. Specifically, a portion of the first electrode 131b is fabricated on the exposed portion of the first connection pad 115b (i.e., the portion not covered by the dielectric layer 120b and exposed by the three-dimensional feature), and extends above the top of the three-dimensional feature and along its sidewalls.

[0049] Ferroelectric layer 133b may be fabricated on the first electrode 131b. Therefore, a portion of ferroelectric layer 133b is fabricated within the three-dimensional feature. One or more portions of the ferroelectric layer 133b may be fabricated on the top surface of dielectric layer 120b. Ferroelectric layer 133b and ferroelectric layer 133a may contain the same or substantially the same material.

[0050] The second electrode 135b may be fabricated on the ferroelectric layer 133b. One or more portions of the second electrode 135b may be fabricated within a three-dimensional feature of the dielectric layer 120b. One or more portions of the second electrode 135b may be fabricated on the top surface of the dielectric layer 120b.

[0051] The second connection pad 140b may comprise any suitable conductive material to provide an ohmic contact for the ferroelectric device stack 130b. In some embodiments, a portion of the second connection pad 140b is fabricated within a three-dimensional feature of the dielectric layer 120b. The dielectric layer 150b may surround one or more portions of the second connection pad 140b and the ferroelectric device stack 130b. The dielectric layer 150b may comprise one or more layers of one or more dielectric materials (e.g., SiO2, Si3N4).

[0052] Figures 2A, 2B, 2C, 2D, 2E and 2F illustrate structures related to the manufacturing process of storage devices according to some embodiments of the present invention.

[0053] As shown in Figure 2A, a substrate 110a with a first connection pad 115a can be provided. The first connection pad 115a may include any suitable conductive material, such as a metal (e.g., tungsten (W)). In some embodiments, the first connection pad 115a may be an interconnect structure of a CMOS substrate (e.g., a metal pad, a metal via, etc.).

[0054] As shown in Figure 2B, the three-dimensional feature 120a can be fabricated on the first connection pad 115a and the substrate 110a. The three-dimensional feature 120a can be a pillar, a fin structure (i.e., a thin-walled structure), or any other structure fabricated on the top surface of the first connection pad 115a. The three-dimensional feature 120a can cover a portion of the top surface of the first connection pad 115a. At least a portion of the top surface of the first connection pad 115a is not covered by the three-dimensional feature 120a.

[0055] As shown in Figure 2C, a first electrode layer 231 can be fabricated on a substrate 110a, a first connection pad 115a, and a three-dimensional feature 120a. The first electrode layer 231 may comprise one or more layers of a suitable conductive material (e.g., tungsten, ruthenium, molybdenum, platinum, palladium, iridium, titanium nitride, tantalum nitride, tungsten nitride, etc.) deposited on the substrate 110a, the first connection pad 115a, and the three-dimensional feature 120a. At least a portion of the first electrode layer 231 directly contacts the first connection pad 115a. The first electrode layer 231 also covers the three-dimensional feature 120a, including its top surface and sidewalls.

[0056] As shown in Figure 2D, a ferroelectric layer 233 can be fabricated on the first electrode layer 231. The ferroelectric layer 233 may include one or more ferroelectric thin films, each containing a ferroelectric material. The ferroelectric material may include metal oxides (HfO2, ZrO2, Hf1xZrxO2 with x values ​​ranging from 0 to 1, Al1-xScxN with x values ​​greater than 0.3, BaTiO3, LiNbO3, NaTaO3, etc.). In some embodiments, the metal oxide may be doped with one or more alternative and / or interstitial dopants, which may occupy vacancies between ferroelectric material atoms. Interstitial dopants may include non-metallic elements, such as H, N, C, B, F, etc. The ferroelectric layer 233 can be conformally fabricated on the first electrode layer 231. Therefore, at least a portion of the ferroelectric layer 233 can be fabricated on top of the three-dimensional feature 120a and extending along its sidewalls, and a portion of the ferroelectric layer 233 can be fabricated on the first connection pad 115a and the substrate 110a.

[0057] As shown in Figure 2E, a second electrode layer 235 can be fabricated on the ferroelectric layer 233. The second electrode layer 235 may comprise one or more layers of one or more conductive materials (e.g., tungsten, ruthenium, molybdenum, platinum, palladium, iridium, titanium nitride, tantalum nitride, tungsten nitride, etc.). The second electrode layer 235 may be conformally fabricated on the ferroelectric layer 233; therefore, at least a portion of the second electrode layer 235 may be fabricated on top of the three-dimensional feature 120a and extend along its sidewalls. A portion of the second electrode layer 235 may be fabricated on the first connection pad 115a and the substrate 110a.

[0058] As shown in Figure 2F, one or more portions of the first electrode layer 231, the ferroelectric layer 233, and the second electrode layer 235 can be selectively removed to fabricate a ferroelectric device stack layer 130a. Specifically, the first electrode 131a, the ferroelectric layer 133a, and the second electrode 135a can be fabricated by patterning and etching the first electrode layer 231, the ferroelectric layer 233, and the second electrode layer 235, respectively.

[0059] Returning to Figure 1A, the second connection pad 140a may be fabricated on the second electrode 135a. The second connection pad 140a may include metal vias, metal pads, etc., fabricated within the dielectric layer 150a. The dielectric layer 150a is fabricated on the substrate 110a and encapsulates the surface of the ferroelectric device stack layer 130a that conformally covers the three-dimensional feature 120a and the first connection pad 115a. In some embodiments, the second connection pad 140a may include an interconnect structure fabricated using a dual damascene fabrication process (e.g., process 500 of Figure 5A).

[0060] Figures 3A, 3B, 3C, 3D, 3E and 3F illustrate structures related to the manufacturing process of storage devices according to some embodiments of the present invention.

[0061] As shown in Figure 3A, the first connection pad 115b can be fabricated on the substrate 110b. The first connection pad 115b can include any suitable conductive material, such as a metal (e.g., tungsten (W)). In some embodiments, the first connection pad 115b can be an interconnect structure of the CMOS substrate (e.g., a metal pad, a metal via, etc.).

[0062] As shown in Figure 3B, a dielectric layer 120b having a three-dimensional feature 125 can be fabricated on the first connection pad 115b and the substrate 110b. The three-dimensional feature 125 can be an opening (e.g., a trench, a via, etc.) and / or any other suitable structure that can expose a portion of the top surface 315 of the first connection pad 115b.

[0063] As shown in Figure 3C, the first electrode layer 331 can be conformally fabricated on the entire surface of the dielectric layer 120b and the three-dimensional feature 125. Specifically, the first electrode layer 331 can be fabricated on the top surface of the dielectric layer 120b, along the sidewalls of the three-dimensional feature 125, and on the exposed portion 315 of the first bonding pad 115b. The first electrode layer 331 can fill a portion of the three-dimensional feature 125, and the unfilled portion of the three-dimensional feature 125 is referred to as the three-dimensional feature 125a.

[0064] As shown in Figure 3D, a ferroelectric layer 333 can be fabricated on the first electrode layer 331. One or more portions of the ferroelectric layer 333 (e.g., portion 333a of the ferroelectric layer 333) can be fabricated on portion 331a of the first electrode layer 331, and one or more portions of the ferroelectric layer 333 can be fabricated within the three-dimensional feature 125a. The unfilled portion of the three-dimensional feature 125a can be referred to as the three-dimensional feature 125b.

[0065] As shown in Figure 3E, a second electrode layer 335 can be fabricated on the ferroelectric layer 333. One or more portions of the second electrode layer 335 can be fabricated within the three-dimensional feature 125b, and the unfilled portion of the three-dimensional feature 125 can be referred to as the three-dimensional feature 125c. Specifically, a portion 335a of the second electrode layer 335 can be fabricated on a portion 331a of the first electrode layer 331.

[0066] As shown in Figure 3F, one or more portions of the first electrode layer 331, the ferroelectric layer 333, and the second electrode layer 335 can be selectively removed to fabricate a ferroelectric device stack layer 130b. Specifically, the first electrode 131b, the ferroelectric layer 133b, and the second electrode 135b can be fabricated by patterning and etching the first electrode layer 331, the ferroelectric layer 333, and the second electrode layer 335, respectively.

[0067] Returning to Figure 1B, a second connection pad 140b may be fabricated on the second electrode 135b. A portion of the second connection pad 140b may fill the three-dimensional feature 125c. The second connection pad 140b may include metal vias, metal pads, etc. The second connection pad 140b may be fabricated in a dielectric layer 150b. The dielectric layer 150b is fabricated on the dielectric layer 120b and encapsulates the surface of the ferroelectric device stack layer 130b that conformally covers the three-dimensional feature 125c and the dielectric layer 120b. In some embodiments, the second connection pad 140b may include an interconnect structure fabricated using a dual damascene fabrication process (e.g., process 500 of Figure 5A).

[0068] Figure 4 is a flowchart illustrating an exemplary process 400 for manufacturing a storage device according to some embodiments of the present invention.

[0069] In step 410, a substrate having a first connection pad is provided. The substrate may be substrate 110a in FIG. 1A and / or substrate 110b in FIG. 1B. The first connection pad may be first connection pad 115a in FIG. 1A and / or first connection pad 115b in FIG. 1B.

[0070] In 420, a three-dimensional feature can be fabricated on the first connection pad. In one implementation, the three-dimensional feature may cover one or more portions of the first connection pad and extend outward from a two-dimensional plane on the top surface of the substrate, such as a pillar, fin structure, etc. For example, the three-dimensional feature may be three-dimensional feature 120a in FIG. 1A. Fabricating the three-dimensional feature may include depositing a dielectric material (e.g., SiO2, Si3N4, etc.) on the first connection pad to form a vertical structure (e.g., a pillar, fin structure, etc.). For example, the top surfaces of the first connection pad and the substrate may be pretreated (e.g., cleaned); then, a dielectric material may be deposited and patterned using a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., followed by etching processes such as reactive ion etching (RIE), sputtering etching, etc., to fabricate the three-dimensional feature. The patterning of the three-dimensional feature (e.g., the size and geometry of the pillar, fin structure) may be defined by photolithography, wherein a photoresist layer may be coated on the dielectric layer forming the three-dimensional feature 120a. Photoresist is exposed to ultraviolet light through a mask, thereby forming the size and geometry of a three-dimensional feature on the first bonding pad. After developing the photoresist to reveal the pattern, etching processes such as reactive ion etching (RIE) or sputtering etching can be used to remove the exposed dielectric material, thereby forming a three-dimensional feature in the dielectric layer (three-dimensional feature 120a in Figure 2B).

[0071] In another implementation, fabricating the three-dimensional feature may include fabricating a dielectric layer (e.g., dielectric layer 120b in FIG. 3B) on the first bonding pad and the substrate, and fabricating openings within the dielectric layer. For example, the dielectric layer may be patterned using photolithography to define the size and geometry of the three-dimensional feature. After developing the photoresist to expose the pattern, an etching process, such as reactive ion etching (RIE), may be used to remove the exposed dielectric material, thereby forming a three-dimensional feature (e.g., three-dimensional feature 125 in FIG. 3B) within the dielectric layer (dielectric layer 120b in FIG. 3B).

[0072] In 430, a first electrode layer can be fabricated on a substrate, a first connection pad, and a three-dimensional feature. The first electrode layer can be fabricated by conformally depositing a layer comprising a conductive material over the entire surface of the substrate, the first connection pad, and the three-dimensional feature. In some embodiments where the three-dimensional feature is a pillar, fin structure, etc., the layer of conductive material can be deposited on the top surface of the substrate, the top surface of the first connection pad, and the top surface of the three-dimensional feature, extending along the sidewalls of the three-dimensional feature. In some embodiments where the three-dimensional feature is a via, trench, etc., fabricated in a dielectric layer, the layer of conductive material can be deposited on the exposed portion of the first electrode layer and the top surface of the dielectric layer, filling the three-dimensional feature.

[0073] Conductive materials can be deposited using methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), and molecular beam epitaxy (MBE). The conductive materials may include, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), platinum (Pt), palladium (Pd), and iridium (Ir).

[0074] In 440, a ferroelectric layer may be fabricated on the first electrode layer. Fabricating the ferroelectric layer may include alternatingly fabricating one or more ferroelectric thin films using atomic layer deposition (ALD) or other suitable deposition techniques. Each ferroelectric thin film may contain at least one ferroelectric material (e.g., hafnium oxide (HfO2, HfO), zirconium oxide (ZrO2, ZO), zirconium hafnium oxide (HZO, Hf0.5Zr0.5O2), Hf1-xZxO (Hf1-xZrxO2) with x values ​​ranging from 0 to 1, etc.). In some embodiments, the ferroelectric layer may include a multilayer structure formed by alternating stacking of multiple ferroelectric thin films and interface layers. For example, fabrication of the ferroelectric layer may involve a fabrication process in which a thin film of ferroelectric material (e.g., HfO or HZO) is deposited on the first electrode, and an alumina thin layer (e.g., Al2O3) is deposited on top of the ferroelectric thin film. The process may be repeated an appropriate number of times to form a layered structure of desired thickness. In some embodiments, the top ferroelectric layer (e.g., HfO layer, HZO layer, etc.) may be fabricated on the multilayer structure. In some embodiments, the ferroelectric layer may be manufactured using the technology described in U.S. Patent Application No. 18 / 539,202, the entire contents of which are incorporated herein by reference.

[0075] In 450, a second electrode layer can be fabricated on the ferroelectric layer. For example, suitable deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), and molecular beam epitaxy (MBE) can be used to deposit layers of suitable conductive materials (such as tungsten, ruthenium, molybdenum, platinum, palladium, iridium, titanium nitride, tantalum nitride, tungsten nitride, etc.).

[0076] In step 460, the first electrode layer, the ferroelectric layer, and the second electrode layer can be patterned to form a ferroelectric device stack. The patterning process may include defining the geometry of the ferroelectric device stack (as shown in ferroelectric device stack 130a in Figure 1A or ferroelectric device stack 130b in Figure 1B), and selectively removing one or more portions of the first electrode layer, the ferroelectric layer, and the second electrode layer using suitable etching methods such as reactive ion etching (RIE), plasma etching, sputtering etching, etc.

[0077] In 470, the storage device and / or ferroelectric device stack can be subjected to a heat treatment including controlled heating and cooling to achieve the desired ferroelectric o-HfO2 phase. For example, the heat treatment may include heating and then cooling a first electrode, the ferroelectric layer, and / or a second electrode at a controlled rate. More specifically, for example, the storage device may be heated for the crystallization of the t-HfO2 phase, and then rapidly cooled to form the ferroelectric o-HfO2 phase. As a more specific example, amorphous zirconium hafnium oxide (HZO) may be transformed into the t phase during heating and then into the o phase during subsequent cooling. This process can be achieved by a rapid thermal annealing (RTA) at a temperature of 450°C (ranging from 400°C to 500°C) for 30 seconds (possibly ranging from 15 to 60 seconds). After the heating process, the storage device can be rapidly cooled. Alternatively, 470 may be performed at the end of manufacturing after the device has completed its entire thermal budget.

[0078] Figure 5A is a flowchart illustrating an exemplary process 500 for fabricating an interconnect structure including metal vias and metal pads in a single process. Figures 5B-5G show cross-sectional views of the structure of the interconnect structure 590 shown in Figure 5G fabricated by implementing process 500 according to some embodiments of the present invention.

[0079] As shown in the figure, process 500 can begin at 505 to fabricate a dielectric layer on a substrate. The substrate may be and / or include one or more transistors, interconnect layers, etc. Depositing the dielectric layer may include depositing one or more interlayer dielectrics (ILDs), such as SiO2, Si3N4, Al2O3, etc. For example, as shown in Figure 5B, dielectric layer 563 may be fabricated on substrate 561. In some embodiments, photoresist 565 may be fabricated on dielectric layer 563.

[0080] In step 510, the dielectric layer can be patterned and partially etched, meaning the dielectric layer is partially etched in the depth direction. For example, as shown in Figure 5C, via 571 can be fabricated by partially etching the dielectric layer 563 and the resist 565.

[0081] In step 515, the partially etched dielectric layer is completely etched to form vias and / or trenches. Due to conformal etching, the etch profiles of the vias and trenches are maintained while the dielectric layer is completely etched in the depth direction. For example, as shown in FIG5D, vias 573 and trenches 575 can be formed by etching a partially etched dielectric layer 563 and resist 565.

[0082] In 520, a barrier layer can be fabricated. For example, as shown in FIG5E, a barrier layer 567 (e.g., a layer containing tantalum (Ta) or tantalum nitride (TaN)) can be deposited on the fully etched dielectric layer and on the sidewalls of via 573 and trench 575.

[0083] In 525, metal can be deposited to form metal vias and metal pads. For example, a thin copper seed layer can be deposited by physical vapor deposition (PVD), followed by copper electroplating to fill the vias and trenches. Metal deposition can also form one or more metal lines. Metal layers can be deposited (e.g., by electroplating) in vias 573 and trenches 575 to form metal vias 581 and metal pads 583, respectively.

[0084] In step 530, a chemical mechanical polishing (CMP) process is performed. For example, as shown in Figure 5F, metal vias 581, metal pads 583, and metal lines (not shown) may be patterned and processed using a CMP process to remove excess copper and planarize the surface. In some embodiments, as shown in Figure 5G, a capping layer 569 (such as tantalum, tantalum nitride, or silicon nitride) may be deposited.

[0085] In 535, metal vias and metal pads can be annealed. For example, the interconnect structure 590 in Figure 5G can be annealed at an annealing temperature (e.g., 350-450°C) in a gas stream (e.g., a mixture of N2 and H2) for an appropriate time (e.g., 15-30 minutes).

[0086] For ease of explanation, the method of the present invention is depicted and described as a series of actions. However, the actions according to the invention can occur in various orders and / or simultaneously, and can occur in combination with other actions not presented and described in the invention. Furthermore, not all actions shown are necessary for implementing the method according to the subject matter of the invention. Additionally, those skilled in the art will understand and recognize that the method can alternatively be represented by a state diagram or events as a series of interrelated states.

[0087] The terms “approximately,” “approximately,” and “substantially” may mean within ±20% of the target size in some embodiments, within ±10% in some embodiments, within ±5% in some embodiments, and even within ±2% in some embodiments. The terms “approximately” and “approximately” may include the target size.

[0088] Many details have been set forth in the foregoing description. However, it will be apparent that the invention can be practiced without these specific details. In some cases, to avoid obscuring the invention, well-known structures and apparatuses are shown in block diagram form rather than in detail.

[0089] The terms “first,” “second,” “third,” and “fourth” used in this article are intended as labels to distinguish different components and do not necessarily have an ordering meaning based on their numerical designations.

[0090] In this invention, the term "example" or "exemplary" is used to indicate something as an example, instance, or illustration. Any aspect or design of the invention described as an "example" or "exemplary" is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the term "example" or "exemplary" is intended to present concepts in a specific manner. As used in this application, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clearly understood from the context, "X includes A or B" is intended to indicate any natural inclusive arrangement. In other words, "X includes A or B" holds true if X includes A; X includes B; or X includes both A and B. Furthermore, the articles "a" and "an" used in this application and the appended claims should generally be interpreted as "one or more," unless otherwise stated or clearly indicated from the context as a singular form. In this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment.

[0091] As described in this invention, when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly on" another element or layer, there are no intermediate elements or layers.

[0092] While many modifications and variations of the invention will undoubtedly become apparent to those skilled in the art after reading the foregoing description, it should be understood that any particular embodiment shown and described by way of example is in no way intended to be limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which themselves merely enumerate those features considered to be part of the invention.

[0093] 100a: Storage device 100b: Storage device 110a: Substrate 110b: Substrate 115a: First connection pad 115b: First connection pad 120a: Three-dimensional features 120b: Dielectric layer 130a: Ferroelectric device stacking layer 130b: Ferroelectric device stack layer 131a: First electrode 131b: First electrode 133a: Ferroelectric layer 133b: Ferroelectric layer 135a: Second electrode 135b: Second electrode 140a: Second connection pad 140b: Second connection pad 150a: Dielectric layer 150b: Dielectric layer 231: First electrode layer 233: Ferroelectric layer 235: Second electrode layer 125: Three-dimensional features 315: Top surface 125a: Three-dimensional features 331: First electrode layer 331a: Part of the first electrode layer 125b: Three-dimensional features 333: Ferroelectric layer 333a: Part of the ferroelectric layer 125c: Three-dimensional features 335: Second electrode layer 335a: Part of the second electrode layer 561: Substrate 563: Corrosion resist 565: Dielectric layer 571: Through hole 573: Through hole 575: Trench 567: Barrier Layer 581: Metal through hole 583: Metal pad 590: Interconnection Structure

Claims

1. A storage device, characterized in that it comprises: Fabricating three-dimensional (3D) feature structures on connection pads including conductive material; A first electrode, wherein at least a portion of the first electrode is formed on the surface of the 3D feature structure; a ferroelectric layer formed on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material; and to fabricate a second electrode on the ferroelectric layer.

2. The storage device as claimed in claim 1, wherein, The 3D feature structure includes at least one of the following: column, fin structure, groove or through hole.

3. The storage device as claimed in claim 1, wherein, The 3D feature structure includes openings fabricated in a dielectric layer, wherein the dielectric layer is fabricated on the connection pads.

4. The storage device as claimed in claim 3, wherein, The 3D feature structure exposes at least a portion of the connection pad, and at least a portion of the first electrode is formed on the exposed portion of the connection pad.

5. The storage device as claimed in claim 4, wherein, At least a portion of the first electrode is fabricated on the top surface of the dielectric layer and the side surface of the 3D feature mechanism.

6. The storage device as claimed in claim 1, wherein, The connection pads are fabricated on the substrate, and the 3D feature structure extends outward from a two-dimensional plane on the top surface of the substrate.

7. The storage device as claimed in claim 6, wherein, At least a portion of the first electrode is fabricated on the top surface of the 3D feature structure and the top surface of the connecting pad.

8. The storage device as claimed in claim 1, wherein, The ferroelectric material comprises a metal oxide, wherein the metal oxide comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2, where x ranges from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN, where x > 0.3), titanate (BaTiO3), niobate (LiNbO3), or tantalate (NaTaO3).

9. The storage device as claimed in claim 1, wherein, The ferroelectric material is interstitially doped with at least one interstitial dopant, wherein the at least one interstitial dopant includes at least one of H, N, C, B or F.

10. The storage device as claimed in claim 1, wherein, The first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium.

11. The storage device as claimed in claim 1, wherein, The second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium.

12. A method for manufacturing a storage device, characterized in that the method comprises: A three-dimensional (3D) feature structure is fabricated on a bonding pad comprising a conductive material, wherein the bonding pad is fabricated on a substrate; A first electrode layer is fabricated on the substrate, the bonding pads, and the 3D feature structure; a ferroelectric layer comprising a ferroelectric material is fabricated on the first electrode layer; and a second electrode layer is fabricated on the ferroelectric layer.

13. The method as described in claim 12, wherein, The 3D feature structure includes at least one of the following: column, fin structure, groove or through hole.

14. The method as described in claim 12, wherein, Fabricating the 3D feature structure on the connection pad includes fabricating a dielectric layer with openings on the connection pad.

15. The method as described in claim 14, wherein, The 3D feature structure exposes at least a portion of the connection pad, and at least a portion of the first electrode layer is formed on the exposed portion of the connection pad.

16. The method as described in claim 15, wherein, At least a portion of the first electrode layer is formed on the top surface of the dielectric layer and the side surface of the opening of the dielectric layer.

17. The method as described in claim 12, wherein, The connection pads are fabricated on a substrate, wherein the 3D feature structure extends outward from a two-dimensional plane on the top surface of the substrate.

18. The method as described in claim 17, wherein, At least a portion of the first electrode layer is formed on the top surface of the 3D feature structure and the top surface of the connection pad.

19. The method as described in claim 12, wherein, The ferroelectric material includes metal oxides, which include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2, where x ranges from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN, where x > 0.3), titanate (BaTiO3), niobate (LiNbO3), or tantalate (NaTaO3).

20. The method as described in claim 12, wherein, The first electrode layer comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium, and the second electrode layer comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium.

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