Semiconductor device and methods of forming the same

Abstract

An apparatus includes a substrate having a first side and a second side; a first transistor and a second transistor formed in a first layer on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second layer on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, wherein the first interconnect structure and the second interconnect structure are each configured to carry a supply voltage, and the third and fourth interconnect structures are each configured to carry a ground voltage; and a power supply structure extending vertically through the first layer and the second layer, and configured to electrically couple the source / drain terminals of the third transistor and the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in minimum feature size, allowing more components to be integrated into a given area. For example, based on this scaling trend, various advanced transistor structures have been proposed, such as complementary field-effect transistors (CFETs). Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates an example circuit diagram of a memory cell according to some embodiments. Figures 2 and 3 illustrate common layouts for forming the memory cells of Figure 1 in a CFET structure with an embedded power supply structure, according to some embodiments. Figures 4 and 5 respectively illustrate perspective views of a portion of a memory cell formed based on the layout of Figures 2 and 3 according to some embodiments. Figures 6 and 7 illustrate common layouts for forming the memory cells of Figure 1 in a CFET structure with an embedded power supply structure, according to some embodiments. Figures 8 and 9 respectively illustrate perspective views of a portion of a memory cell formed based on the layout of Figures 6 and 7 according to some embodiments. Figures 10 and 11 respectively illustrate cross-sectional views of the memory cells shown in Figures 4 and 5 according to some embodiments. Figures 12 and 13 respectively illustrate cross-sectional views of the memory cells shown in Figures 8 and 9 according to some embodiments. Figures 14 and 15 respectively illustrate top views of the memory cell shown in Figures 4 and 5 or Figures 8 and 9 according to some embodiments. Figures 16 and 17 respectively illustrate top / bottom views of the memory cell shown in Figures 4 and 5 or Figures 8 and 9 according to some embodiments. Figure 18 illustrates an example flowchart of a method for forming a semiconductor device including memory cells configured with a CFET structure, according to some embodiments. Figures 19 through 28 illustrate cross-sectional views of example semiconductor devices manufactured according to some embodiments using the method of Figure 18 during various manufacturing processes. Figures 29A to 29B illustrate example flowcharts of methods for forming a semiconductor device including memory cells configured with CFET structures, according to some embodiments. Figures 30 to 41 illustrate cross-sectional views of example semiconductor devices manufactured according to some embodiments using the method of Figure 35 during various manufacturing stages. Figures 42 and 43 illustrate a common layout of memory cells in one of Figures 1 within a CFET structure having an embedded power supply structure, according to some embodiments. Figures 44 and 45 respectively illustrate the layout of the front and rear metal tracks for forming a memory cell based on the layout of Figures 42 and 43, according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0007] A complementary field-effect transistor (CFET) is a gate-all-around (GAA) field-effect transistor. Generally, a GAA FET comprises multiple nanostructures, such as nanosheets or nanowires stacked vertically on top of each other. P-type and n-type GAA FETs are formed on the same horizontal plane above the substrate and separated by an isolation structure. In contrast, CFETs are typically fabricated by vertically stacking p-type and n-type GAA FETs on top of each other. This configuration of stacking n-type and p-type transistors in a single structure eliminates the need for n-to-p separation, reduces the active area footprint, and increases the transistor density within the chip. This stacking concept is not limited to GAA FETs; for example, a CFET can be formed with a FinFET device or a combination of GAA-FETs and FinFETs.

[0008] Some researchers have proposed using CFET structures to form static random access memory (SRAM) cells. For example, to form an SRAM cell with six transistors (6T) (generally referred to as a 6T SRAM cell), a first layer including a first pull-up transistor and a second pull-up transistor is first formed on the front side of the substrate. Then, a second layer including a first pull-down transistor, a second pull-down transistor, a first channel gate transistor, and a second channel gate transistor is formed above the first layer (on the front side of the substrate). Generally, the pull-up transistors are typically p-type conductive, while the pull-down and channel gate transistors are typically n-type conductive.

[0009] When using a backside power grid (BPG) / buried power rail (BPR) configuration, with the formation of an n-type pull-down transistor above the p-type transistor, tap cells or fill cells are typically required to form via structures extending from the second layer through the substrate to the rear side of the substrate. In the BPG / BPR configuration, numerous interconnect structures for carrying reference voltages or ground voltages (e.g., VSS) are formed on the rear side of the substrate. Tap cells (or the via structures they include) are used to electrically couple the pull-down transistors at the second layer to the interconnect structures carrying the ground voltage. Such additional tap cells disadvantageously occupy a relatively large area. For example, multiple of these tap cells are typically formed around or away from the array including memory cells. In other words, additional area is required to form these tap cells. Therefore, existing CFET structures for forming memory cells are not entirely satisfactory in some configurations.

[0010] This disclosure provides various embodiments of semiconductor devices (e.g., memory cells) formed in a CFET structure having a first front layer and a second front layer for forming individual transistors of different conductivity types, wherein power supply structures are embedded within or along the boundaries of the memory cells. According to some embodiments, the memory device may include at least one SRAM cell having a plurality of (e.g., six) transistors. As disclosed herein, the SRAM cell may include a first p-type pull-up transistor and a second p-type pull-up transistor formed at the first front layer, a first n-type channel gate transistor and a second n-type channel gate transistor formed at the second front layer, and a first n-type pull-down transistor and a second n-type pull-down transistor. With the power supply structures embedded within or along the boundaries of the SRAM cell (e.g., cell), additional tap configurations for carrying ground voltage are no longer required. For example, at the first layer, the first pull-up transistor and the second pull-up transistor may be disposed around one pair of opposite corners of the boundary. Furthermore, at the first level, the first dummy transistor can be disposed next to the first pull-up transistor along the first lateral direction, and the second dummy transistor can be disposed next to the second pull-up transistor along the first lateral direction (i.e., the first dummy transistor and the second dummy transistor are respectively disposed around other diagonals of the boundary). At the second level, the first pull-down transistor can be perpendicularly aligned with the first pull-up transistor, the second pull-down transistor can be perpendicularly aligned with the second pull-up transistor, the first channel gate transistor can be perpendicularly aligned with the first dummy transistor, and the second channel gate transistor can be perpendicularly aligned with the second dummy transistor.

[0011] A power supply structure, which can be formed as one or more vertical structures extending from the first level to the second level, can be formed along the midline of the boundary (extending along the first lateral direction). For example, the power supply structure can be inserted between the first pull-up transistor and the second dummy transistor along a second lateral direction perpendicular to the first lateral direction, between the second pull-up transistor and the first dummy transistor along the second lateral direction, between the first channel gate transistor and the second pull-down transistor along the second lateral direction, and between the first pull-down transistor and the second channel gate transistor along the second lateral direction. Through the power supply structure, the first pull-down transistor and the second pull-down transistor at the second level can each be electrically coupled to interconnect structures formed on the back side level of the substrate, which are used to carry the ground voltage. In this way, the disclosed SRAM cell no longer needs to be provided with additional tap units around it to provide the ground voltage.

[0012] Figure 1 illustrates an example circuit diagram of a memory cell 100 according to some embodiments. As shown, the memory cell 100 includes six transistors operatively forming a 6T SRAM cell. In various embodiments, the six transistors may be formed using a CFET structure, as will be discussed below. The memory cell 100 includes six transistors: a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first channel gate transistor PG1, and a second channel gate transistor PG2.

[0013] Transistors PU1 and PD1 form a first inverter, and transistors PU2 and PD2 form a second inverter, wherein the first and second inverters are cross-coupled to each other. Specifically, both the first and second inverters are coupled between a first reference voltage 101 and a second reference voltage 103. In some embodiments, the first reference voltage 101 is the supply voltage applied to the memory cell 100, sometimes referred to as "VDD," and the second reference voltage 103 is the ground voltage, sometimes referred to as "VSS." The first inverter (formed by transistors PU1 and PD1) is coupled to transistor PG1, and the second inverter (formed by transistors PU2 and PD2) is coupled to transistor PG2. In addition to being coupled to the first and second inverters, transistors PG1 and PG2 are each coupled to a word line (WL) and, respectively, to a bit line (BL) and a bit line bar (BLB).

[0014] In some embodiments, transistors PU1 and PU2 each comprise a p-type metal-oxide-semiconductor (PMOS) transistor, and transistors PD1, PD2, PG1, and PG2 each comprise an n-type metal-oxide-semiconductor (NMOS) transistor. Although the embodiment shown in Figure 1 indicates that the transistors in memory cell 100 are NMOS or PMOS transistors, various transistors suitable for use in memory devices or any of the devices may be implemented as at least one transistor in memory cell 100, such as, for example, a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc. Furthermore, as will be discussed below, p-type transistors PU1 and PU2 are each formed as GAA FETs disposed on the first layer on the front side of the substrate, and n-type transistors PG1, PG2, PD1, and PD2 are each formed as GAA-FETs on the second layer above the first layer.

[0015] Transistors PG1 and PG2 each have a gate terminal coupled to WL. The gate terminals of PG1 and PG2 are used to receive pulse signals via WL to accordingly enable or block access to memory cell 100 (e.g., read operations, write operations). Transistors PD1 and PU1 are coupled between VDD and VSS and are coupled to each other at internal node 110. For example, transistor PU1 has a first source / drain terminal connected to VDD, and transistor PD1 has a first source / drain terminal connected to VSS, wherein transistors PU1 and PD1 have their second source / drain terminals connected to each other at internal node 110. Transistor PG1 has a first source / drain terminal connected to BL and a second source / drain terminal connected to internal node 110, which is further coupled to the gate terminals of transistors PU2 and PD2. Similarly, transistors PD2 and PU2 are coupled between VDD and VSS and are coupled to each other at internal node 112. For example, transistor PU2 has a first source / drain terminal connected to VDD, and transistor PD2 has a first source / drain terminal connected to VSS, wherein the second source / drain terminals of transistors PU2 and PD2 are connected to each other at internal node 112. Transistor PG2 has a first source / drain terminal connected to BLB and a second source / drain terminal connected to internal node 112, which is further coupled to the gate terminals of transistors PU1 and PD1.

[0016] Figures 2 and 3 illustrate layouts 200 and 300 of a memory cell 100 (Figure 1) configured as a CFET structure with an embedded power structure, which can be jointly utilized according to some embodiments. The CFET structure may include a plurality of first transistors disposed at a first layer on the front side of the substrate and a plurality of second transistors disposed at a second upper layer on the front side of the substrate. In some embodiments, each of these first and second transistors is configured as a GAA FET, wherein the first and second transistors have opposite conductivity types. In some other embodiments, each of the first and second transistors may be formed as other types of transistor structures, while still within the scope of this disclosure.

[0017] As depicted in Figures 2 and 3, each of layouts 200 and 300 may include a cell boundary 201 defining a physical region of the memory cell 100. The embedded power structure may be formed as an integral wall structure extending vertically from a first level to a second level. Further, when viewed from above, this embedded wall structure may be disposed within the cell boundary 201 of the memory cell 100. For example, the wall structure may extend laterally along the centerline of the cell boundary 201, with transistors respectively disposed on opposite sides of the centerline. The centerline may pass through the cell boundary in a first lateral direction, with the edges of the cell boundary extending in a second lateral direction perpendicular to the first lateral direction respectively disposed at the longitudinal ends of the centerline.

[0018] Generally, layouts 200 and 300 may include a number of patterns configured to form individual structures; therefore, in the following discussion, such patterns in the disclosed layouts are referred to herein as structures to be formed. For example, layout 200 includes a pattern for forming a structure in a first transistor at a first layer on the front side; layout 300 includes a pattern for forming a structure in a second transistor at a second layer on the front side. Further, layout 200 includes a pattern for forming contact / via / interconnect structures disposed on the rear side of the substrate (e.g., at a first layer on the rear side); layout 300 includes a pattern for forming via / interconnect structures at a third layer on the front side (e.g., above a second layer). It should be understood that layouts 200 and 300 have been simplified for illustrative purposes and may therefore include any of a variety of other patterns while still within the scope of this disclosure.

[0019] Referring first to Figure 2, layout 200 may include patterns for forming active regions 210 and 220, and gate structures 230 and 240, respectively. Active regions 210 and 220 may extend in the X direction (e.g., a first lateral direction); gate structures 230 and 240 may extend in the Y direction (e.g., a second lateral direction). Each of active regions 210 and 220 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 230 and 240 may be formed as extending in the Y direction across active regions 210 and 220.

[0020] The layout 200 may further include a plurality of cutting patterns (e.g., 242), each cutting pattern extending along the X direction and traversing one or more of the gate structures 230 to 240. As shown, the cutting pattern 242 extending along the X direction to traverse the gate structures 230 to 240 can be used to define the footprint of the dielectric structure (hereinafter referred to as "dielectric structure 242"). The dielectric structure 242 may be formed along the centerline of the boundary 201, thereby dividing each of the gate structures 230 to 240 into separate gate portions, such as gate portions 230A and 230B and gate portions 240A and 240B. The power supply structure, implemented as a vertically extending integral wall structure 244, may be formed to extend through the dielectric structure 242.

[0021] Referring next to Figure 3, layout 300 may include patterns for forming active regions 310 and 320, and gate structures 330 and 340, respectively. Active regions 310 and 320 may extend in the X direction; gate structures 330 and 340 may extend in the Y direction. Each of active regions 310 and 320 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 330 and 340 may be formed as extending in the Y direction across active regions 310 and 320.

[0022] The layout 300 may further include a plurality of cutting patterns (e.g., 342), each cutting pattern extending along the X direction and traversing one or more of the gate structures 330 to 340. As shown, the cutting pattern 342 extending along the X direction to traverse the gate structures 330 to 340 can be used to define the footprint of the dielectric structure (hereinafter referred to as "dielectric structure 342"). The dielectric structure 342 may be formed along the centerline of the boundary 201, thereby dividing each of the gate structures 330 to 340 into separate gate portions, such as gate portions 330A and 330B and gate portions 340A and 340B. The power supply structure, implemented as a vertically extending integral wall structure 344, may be formed to extend through the dielectric structure 342.

[0023] In some embodiments, active regions 210 and 310 are perpendicularly aligned to each other, active regions 220 and 320 are perpendicularly aligned to each other, gate structures 230 and 330 are perpendicularly aligned to each other, and gate structures 240 and 340 are perpendicularly aligned to each other. Active regions 210 and 310 may be solidly formed into a single structure (sometimes referred to as "active region 210 / active region 310"), active regions 220 and 320 may be solidly formed into a single structure (sometimes referred to as "active region 220 / active region 320"), gate structures 230 and 330 may be solidly formed into a single structure (sometimes referred to as "active region 230 / active region 330"), and gate structures 240 and 340 may be solidly formed into a single structure (sometimes referred to as "active region 240 / active region 340").

[0024] Furthermore, in some embodiments, dielectric structure 242 and dielectric structure 342 are perpendicularly aligned to each other, and wall structures 244 and 344 respectively disposed in dielectric structure 242 and dielectric structure 342 are perpendicularly aligned to each other. Dielectric structure 242 and dielectric structure 342 may be solidly formed as a single structure (sometimes referred to as "dielectric structure 242 / dielectric structure 342"), and wall structures 244 and 344 may be solidly formed as a single structure (sometimes referred to as "wall structure 244 / wall structure 344"). Thus, dielectric structure 242 / dielectric structure 342 and wall structure 244 / wall structure 344 can extend vertically from the first level to the second level, so that dielectric structure 242 / dielectric structure 342 can cut gate structure 230 into gate portion 230A and gate portion 230B, gate structure 330 into gate portion 330A and gate portion 330B, gate structure 240 into gate portion 240A and gate portion 240B, and gate structure 340 into gate portion 340A and gate portion 340B. In some embodiments, gate portion 230A and gate portion 330A may be coupled to each other (sometimes referred to as "gate portion 230A / gate portion 330A"), gate portion 230B and gate portion 330B may be coupled to each other (sometimes referred to as "gate portion 230B / gate portion 330B"), gate portion 240A and gate portion 340A may be coupled to each other (sometimes referred to as "gate portion 240A / gate portion 340A"), and gate portion 240B and gate portion 340B may be coupled to each other (sometimes referred to as "gate portion 240B / gate portion 340B").

[0025] For example, active regions 210 / 310 and 220 / 320 may each initially be formed as a stacked structure protruding from the front side surface of the substrate. The stack may include a plurality of first semiconductor nanostructures (e.g., first nanosheets) extending along the X direction and perpendicularly separated from each other, and a plurality of second semiconductor nanostructures (e.g., second nanosheets) extending along the X direction and perpendicularly separated from each other. The first nanosheets are positioned at a first level, and the second nanosheets are positioned at a second level. According to some embodiments of this disclosure, the first nanosheets formed based on the lower portion of active regions 210 / 310 or the lower portion of active regions 220 / 320 may partially form a first transistor at the first level; the second nanosheets formed based on the upper portion of active regions 210 / 310 or the upper portion of active regions 220 / 320 may partially form a second transistor at the second level. Further, the first and second nanosheets may be perpendicularly aligned but separated from each other, with at least one dielectric layer inserted between them.

[0026] Next, individual portions of the first and second nanosheets in the stack can be retained, these portions being respectively covered by gate structures 230 / 330 and 240 / 340, which were initially formed as a plurality of dummy (e.g., polysilicon) gate structures. Other portions of the first nanosheet are replaced by a plurality of first epitaxial structures, and other portions of the second nanosheet are replaced by a plurality of second epitaxial structures. According to some embodiments of this disclosure, the first epitaxial structure (at the first layer) can be formed with p-type conductivity, and the second epitaxial structure (at the second layer) can be formed with n-type conductivity. The first epitaxial structure can operably form individual source / drain terminals of the first transistor at the first layer, and the second epitaxial structure can operably form individual source / drain terminals of the second transistor at the second layer.

[0027] Next, each of the dummy gate structures 230 / 330 and 240 / 340 can be replaced by a corresponding active (e.g., metallic) gate structure to form the first transistor and the second transistor. According to some embodiments disclosed herein, each of the active gate structures may include a lower portion and an upper portion corresponding to the first level and the second level, respectively. For example, the lower portion of the active gate structure (e.g., corresponding to gate portion 230A, gate portion 230B, gate portion 240A, or gate portion 240B) may include one or more first work function metals configured to form the gate terminal of one of the first transistors having p-type conductivity, and the upper portion of the active gate structure (e.g., corresponding to gate portion 330A, gate portion 330B, gate portion 340A, or gate portion 340B) may include one or more second work function metals configured to form the gate terminal of one of the second transistors having n-type conductivity. Details of a series of manufacturing processes for forming a semiconductor device comprising a first transistor at a first layer and a second transistor at a second layer will be described with reference to Figures 18 through 41.

[0028] As a brief overview, transistors PU1 and PU2 in memory cell 100 (Figure 1) can be formed at a first level based on layout 200 (as shown in Figure 2), and transistors PG1, PG2, PD1, and PD2 in memory cell 100 (Figure 1) can be formed at a second level based on layout 300 (as shown in Figure 3). In some embodiments, transistors PU1 and PU2 at the first level can have p-type conductivity, and transistors PG1, PG2, PD1, and PD2 at the second level can have n-type conductivity. Further, a first dummy transistor DMY1 and a second dummy transistor DMY2 can be formed at the first level, and one of the first epitaxial structures (e.g., source / drain terminals) of each dummy transistor is replaced by an isolation structure.

[0029] For example, in Figure 2, transistor PU1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 210, gate portion 240A, and a subset of the first epitaxial structure formed by active region 210 and disposed on the opposite side of gate portion 240A. Transistor PU2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 220, gate portion 230B, and a subset of the first epitaxial structure formed by active region 220 and disposed on the opposite side of gate portion 230B. Transistor DMY1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 210, gate portion 230A, and a subset of the first epitaxial structure formed by active region 210 and disposed on the opposite side of gate portion 230A. In some embodiments, one of the source / drain terminals of transistor DMY1 (e.g., the first epitaxial structure disposed opposite to gate portion 230A relative to gate portion 240A) can be replaced by isolation structure 246. Transistor DMY2 may include its channel, gate terminal, and source / drain terminals, which are respectively formed by a subset of the first nanosheets in active region 220, gate portion 240B, and a subset of the first epitaxial structure formed by active region 220 and disposed on the opposite side of gate portion 240B. In some embodiments, one of the source / drain terminals of transistor DMY2 (e.g., the first epitaxial structure disposed opposite to gate portion 240B relative to gate portion 230B) can be replaced by isolation structure 248.

[0030] In another example, in Figure 3, transistor PD1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 310, gate portion 340A, and a subset of the second epitaxial structure formed by active region 310 and disposed on the opposite side of gate portion 340A. Transistor PG1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 310, gate portion 330A, and a subset of the second epitaxial structure formed by active region 310 and disposed on the opposite side of gate portion 330A. Transistor PD2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 320, gate portion 330B, and a subset of the second epitaxial structure formed by active region 320 and disposed on the opposite side of gate portion 330B. The transistor PG2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in the active region 320, the gate portion 340B, and a subset of the second epitaxial structure formed by the active region 320 and disposed on the opposite side of the gate portion 340B.

[0031] Referring again to Figure 2, layout 200 may further include patterns for forming source / drain contact structures 250, 252, 254, 256, 258, and 260, respectively. Each of these source / drain contact structures 250 to 260 is sometimes referred to as an MD. Generally, each of these MDs 250 to MD 260 is used to electrically connect the source / drain terminals of the corresponding transistor to an upper or lower interconnect structure. However, according to some embodiments of this disclosure, some of the MDs 250 to MD 260 (e.g., 250, 260) may be physically coupled to corresponding isolation structures that replace the epitaxial structures (e.g., 246, 248). Each of MD 250 to MD 260 may be physically coupled to or surrounded by a corresponding epitaxial structure or isolation structure. In some embodiments, each of MD 250 to MD 260 may extend laterally in the same direction (e.g., the Y direction) as gate structures 230 to 240.

[0032] For example, in Figure 2, MD 250 is coupled to the bottom surface of isolation structure 246; MD 260 is coupled to the bottom surface of isolation structure 248; MD 254 is coupled to the bottom surface of one of the source / drain terminals of transistor PU1, while MD 252 is coupled to the bottom surface of the other source / drain terminal of transistor PU1; MD 256 is coupled to the bottom surface of one of the source / drain terminals of transistor PU2, while MD 258 is coupled to the bottom surface of the other source / drain terminal of transistor PU2.

[0033] The layout 200 may further include patterns for forming internal contact structures 270 and 274, respectively; patterns for forming interconnect structures 272, 276, 280, 282, 284, and 286, respectively, in a first layer on the rear side; and patterns for forming via structures 273, 277, 287, 289, 291, and 293, respectively. In some embodiments, each of the internal contact structures 270 and 274 may be formed below and coupled to the MD. Further, each of the internal contact structures 270 and 274 may extend along the X direction to connect to the interconnect structure (e.g., BMO track) formed below it, as will be discussed below. In some embodiments, each of the internal contact structures 270 and 274 may be vertically disposed between the MD and the BMO track. For example, internal contact structures 270 and 274 can be vertically inserted between the back side of the substrate and the BMO layer. Each of via structures 273 and 277 is typically formed below or extends downwards from the gate structure (sometimes referred to as BVG). Each of BVG 273 and BVG 277 is coupled to its corresponding gate structure. Each of via structures 287 to 293 is typically formed below or extends downwards from the MD (sometimes referred to as BVD). Each of BVD 287 to BVD 293 is coupled to its corresponding MD.

[0034] The first layer disposed on the back side is sometimes referred to as the bottom of a plurality of back metallization layers, such as the BMO layer, and the interconnect structures 272, 276, 280, 282, 284, and 286 disposed therein are sometimes referred to as BMO orbitals. The back metallization layer typically comprises one or more dielectric materials (e.g., silicon, oxide, low-k dielectric, or the like) embedded with corresponding metal orbitals formed of, for example, copper. These BMO orbitals 272, 276, 280, 282, 284, and 286 (including internal contact structures 270 and 274) may extend along the X or Y direction, as shown in Figure 2.

[0035] In some embodiments, BM0 rails 272 and 276 may each be coupled via BVG to a corresponding overlying gate structure (or gate portion) in the first layer on the front side, and BM0 rails 280 to 286 may each be coupled via BVD to a corresponding overlying MD in the first layer on the front side. For example, BM0 rail 280 is coupled to MD 250 via BVD 287; BM0 rail 282 is coupled to MD 260 via BVD 293; BM0 rail 284 is coupled to MD 254 via BVD 289; and BM0 rail 286 is coupled to MD 256 via BVD 291. BM0 rails 280 and 282 may each be operably used as part of a power rail carrying ground voltage VSS, and BM0 rails 284 and 286 may each be operably used as another power rail carrying supply voltage VDD.

[0036] In some embodiments, these power rails (e.g., 280 to 286) may be respectively positioned at the corners of boundary 201, with BMO rails (VSS) 280 and 282 diagonally opposite each other, and BMO rails (VDD) 284 and 286 diagonally opposite each other. Along with MD 250 and MD 260 positioned along the Y direction, wall structure 244 / wall structure 344 positioned along the centerline of boundary 201 may be coupled to BMO rails (VSS) 280 and 282 extending along the X direction. For example, MD 250 and MD 260 may be coupled to wall structure 244 / wall structure 344 (or overlap with it when viewed from the top / bottom), as shown in Figure 2. Along their respective longitudinal directions (e.g., the Y direction), MD 250 and MD 260 can couple wall structure 244 / wall structure 344 to BM0 track (VSS) 280 and BM0 track (VSS) 282, respectively.

[0037] Furthermore, the internal contact structure 270 can be coupled to a BMO track 272 coupled to the gate terminal of transistor PU2, and the internal contact structure 274 can be coupled to a BMO track 276 coupled to the gate terminal of transistor PU1. As the internal contact structure 270 extends in the X direction and the BMO track 272 extends in the Y direction, the internal contact structure 270 and the BMO track 272 can together form an L-shaped profile when viewed from the top or bottom. Similarly, when viewed from the top or bottom, the internal contact structure 274 and the BMO track 276 can together form another L-shaped profile. In some other embodiments, the internal contact structure 270 and the BMO track 272 can be formed in the same layer, for example, in an intermediate layer vertically between the substrate rear side and the BMO layer. Similarly, the internal contact structure 274 and the BMO track 276 can be formed in the same intermediate layer.

[0038] Thus, the connection between one of the source / drain terminals of transistor PU1 and the gate terminal of transistor PU2 (or the internal node 110 in Figure 1) can be operably formed by at least MD 252 (connected to the source / drain terminal of transistor PU1), internal contact structure 270, BMO track 272, and BVG 273 (connected to the gate terminal of transistor PU2); and the connection between one of the source / drain terminals of transistor PU2 and the gate terminal of transistor PU1 (or the internal node 112 in Figure 1) can be operably formed by at least MD 258 (connected to the source / drain terminal of transistor PU1), internal contact structure 274, BMO track 276, and BVG 277 (connected to the gate terminal of transistor PU1).

[0039] Referring again to Figure 3, layout 300 may further include patterns for forming source / drain contact structures 350, 352, 354, 356, 358, and 360, respectively. Each of these source / drain contact structures 350 to 360 is sometimes referred to as an MD. Generally, each of these MDs 350 to 360 is used to electrically connect the source / drain terminals of the corresponding transistor to an upper or lower interconnect structure. Each of the MDs 350 to 360 may be physically coupled to or surround a corresponding epitaxial structure. In some embodiments, each of the MDs 350 to 360 may extend laterally along the same direction (e.g., the Y direction) as the gate structures 330 to 340.

[0040] For example, in Figure 3, MD 350 is coupled to the top surface of one of the source / drain terminals of transistor PG1, while MD 352 is coupled to the top surface of the other source / drain terminal of transistor PG1 (which is also one of the source / drain terminals of transistor PD1); MD 354 is coupled to the top surface of the other source / drain terminal of transistor PD1; MD 360 is coupled to the top surface of one of the source / drain terminals of transistor PG2, while MD 358 is coupled to the top surface of the other source / drain terminal of transistor PG2 (which is also one of the source / drain terminals of transistor PD2); MD 356 is coupled to the top surface of the other source / drain terminal of transistor PD2.

[0041] The layout 300 may further include patterns for forming internal contact structures 362 and 364, respectively; patterns for forming interconnect structures 370, 372, 374, and 376 in a third layer on the front side, respectively; and patterns for forming via structures 377, 379, 381, and 383, respectively. In some embodiments, on the front side, each of the internal contact structures 362 and 364 may extend vertically from the first layer to the second layer (sometimes referred to as MDLI). Each of the via structures 377 and 379 is typically formed on or extends upward from the gate structure (sometimes referred to as VG). Each of VG 377 and VG 379 is coupled to a corresponding gate structure. Each of the via structures 381 and 383 is typically formed on or extends upward from the MD (sometimes referred to as VD). VD 381 and VD 383 are each coupled to their respective MDs.

[0042] The third layer, situated above the second layer on the front side, is sometimes referred to as the bottom of a plurality of front metallization layers, such as the M0 layer, and the interconnect structures 370 to 376 disposed therein are sometimes referred to as M0 orbitals. The front metallization layer typically comprises one or more dielectric materials (e.g., silicon, oxide, low-k dielectric materials, or the like) embedded with corresponding metal orbitals formed of, for example, copper. These M0 orbitals 370 to 376 may extend along the X direction, as shown in Figure 3.

[0043] In some embodiments, M0 rails 370 and 376 may each be coupled via VG to a corresponding overlying gate structure (or gate portion) in the second layer on the front side, and M0 rails 372 and 374 may each be coupled via VD to a corresponding overlying MD in the second layer on the front side. For example, M0 rail 370 is coupled to gate portion 330A via VG 377; M0 rail 376 is coupled to gate portion 340B via VG 379; M0 rail 372 is coupled to MD 350 via VD 381; and M0 rail 374 is coupled to MD 360 via VD 383. M0 rails 370 and 376 may each be operably used as part of WL (Figure 1), M0 rail 372 may be operably used as part of BL (Figure 1), and M0 rail 374 may be operably used as part of BLB (Figure 1).

[0044] The internal contact structure 362 extends downward from the second level to the first level, thereby coupling the MD 352 at the second level (which is coupled to the common source / drain terminal of transistors PD1 and PG1) to the source / drain terminal of transistor PU1 at the first level. As described above, the source / drain terminal of transistor PU1 (the first epitaxial structure formed by the active region 210 and above the MD 252) is coupled to the gate terminal (gate portion 230B) of transistor PU2 via the MD 252, the internal contact structure 270, and the BMO track 272; and the gate terminal (gate portion 230B) of transistor PU2 is coupled to the gate terminal (gate portion 330B) of transistor PD2. In this way, an internal node 110 connecting the common source / drain terminal of transistors PU1, PD1, and PG1 to the gate terminals of transistors PU2 and PD2 can be operably formed.

[0045] Similarly, the internal contact structure 364 can extend downwards from the second level to the first level, thereby coupling the MD 358 at the second level (which is coupled to the common source / drain terminal of transistors PD2 and PG2) to the source / drain terminal of transistor PU2 at the first level. As described above, the source / drain terminal of transistor PU2 (the first epitaxial structure formed by the active region 220 and above MD 252) is coupled to the gate terminal (gate portion 230B) of transistor PU2 via MD 258, internal contact structure 274, and BMO track 276; and the gate terminal (gate portion 240A) of transistor PU1 is coupled to the gate terminal (gate portion 340A) of transistor PD1. In this way, an internal node 112 can be operably formed that couples the common source / drain terminal of transistors PU2, PD2, and PG2 to the gate terminals of transistors PU1 and PD1.

[0046] Figures 4 and 5 illustrate perspective views of a semiconductor device 400 including memory cells configured with CFET structures according to some embodiments of the present disclosure. For example, the semiconductor device 400 may include memory cells 100 formed based on layouts 200 to 300 (Figures 2 and 3), therefore, some of the reference numerals in Figures 2 and 3 may be used again. Specifically, the perspective view of Figure 4 is viewed from the front side of the substrate (where the transistors of the memory cells 100 are formed), and the perspective view of Figure 5 is viewed from the rear side of the substrate. It should be understood that the semiconductor device 400 in Figures 4 and 5 has been simplified; therefore, some of the above structures have been omitted for clarity.

[0047] As shown in the figure, wall structure 244 / wall structure 344 extends vertically, connecting MD 354 and MD 356 at the second front layer to MD 250 (not shown in Figure 5) and MD 260 (not shown in Figure 4) at the first layer. MD 356 is connected to one of the source / drain terminals of transistor PD2, and MD 354 is connected to one of the source / drain terminals of transistor PD1. MD 250 is coupled to BMO track 280 carrying ground voltage VSS, and MD 260 is coupled to BMO track 282 carrying ground voltage VSS. Thus, the source / drain terminals of transistors PD1 and PD2 can be electrically connected to ground voltage VSS via wall structure 244 / wall structure 344. Further, it should be noted that the top surface of MD 250 is connected to isolation structure 246 (as shown in Figure 4), and the top surface of MD 260 is connected to isolation structure 248 (as shown in Figure 5). Specifically, in Figure 5, the internal contact structure 270, BM0 track 272, and BVG 273 can form part of the connection between one of the source / drain terminals of transistor PU1 and the gate terminal of transistor PU2; the internal contact structure 274, BM0 track 276, and BVG 277 can form part of the connection between one of the source / drain terminals of transistor PU2 and the gate terminal of transistor PU1.

[0048] Figures 6 and 7 illustrate layouts 700 and 800, respectively, of a memory cell 100 (Figure 1) configured as a CFET structure with an embedded power structure, which can be jointly utilized according to some embodiments. The CFET structure may include a plurality of first transistors disposed at a first layer on the front side of the substrate, and a plurality of second transistors disposed at a second upper layer on the front side of the substrate. In some embodiments, each of these first and second transistors is configured as a GAA FET, wherein the first and second transistors have opposite conductivity types. In some other embodiments, each of the first and second transistors may be formed as other types of transistor structures, while still within the scope of this disclosure.

[0049] As depicted in Figures 6 and 7, each of layouts 600 and 700 may include a cell boundary 601 defining a physical region of the memory cell 100. An embedded power structure may be formed as a pair of via structures extending vertically from a first level to a second level. Further, when viewed from above, this pair of via structures may be disposed within the cell boundary 601 of the memory cell 100. For example, the via structures may extend laterally along the centerline of the cell boundary 601, with transistors respectively disposed on opposite sides of the centerline. The centerline may pass through the cell boundary in a first lateral direction, with edges of the cell boundary extending in a second lateral direction perpendicular to the first lateral direction respectively disposed at the longitudinal ends of the centerline. The pair of via structures may be disposed around these edges respectively.

[0050] Generally, layouts 600 and 700 may include a number of patterns configured to form individual structures; therefore, in the following discussion, such patterns of the disclosed layouts are referred to herein as structures to be formed. For example, layout 600 includes a pattern for forming a structure in a first transistor at a first layer on the front side; layout 700 includes a pattern for forming a structure in a second transistor at a second layer on the front side. Further, layout 600 includes a pattern for forming contact / via / interconnect structures disposed on the rear side of the substrate (e.g., at a first layer on the rear side); layout 700 includes a pattern for forming via / interconnect structures at a third layer on the front side (e.g., above a second layer). It should be understood that layouts 600 and 700 have been simplified for illustrative purposes and may therefore include any of a variety of other patterns while still within the scope of this disclosure.

[0051] Referring first to Figure 6, layout 600 may include patterns for forming active regions 610 and 620, and gate structures 630 and 640, respectively. Active regions 610 and 620 may extend in the X direction (e.g., a first lateral direction); gate structures 630 and 640 may extend in the Y direction (e.g., a second lateral direction). Each of active regions 610 and 620 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 630 and 640 may be formed to extend in the Y direction across active regions 610 and 620.

[0052] The layout 600 may further include a plurality of cut patterns (e.g., 642), each cut pattern extending along the X direction and traversing one or more of the gate structures 630 to 640. As shown, the cut pattern 642 extending along the X direction to traverse the gate structures 630 to 640 can be used to define the footprint of the dielectric structure (hereinafter referred to as "dielectric structure 642"). The dielectric structure 642 may be formed along the centerline of the boundary 601, thereby dividing each of the gate structures 630 to 640 into separate gate portions, such as gate portions 630A and 630B and gate portions 640A and 640B. Power structures implemented as vertically extending first via structures 644A and 644B may be formed extending through the dielectric structure 642.

[0053] Referring next to Figure 7, layout 700 may include patterns for forming active regions 710 and 720, and gate structures 730 and 740, respectively. Active regions 710 and 720 may extend in the X direction; gate structures 730 and 740 may extend in the Y direction. Each of active regions 710 and 720 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 730 and 740 may be formed as extending in the Y direction across active regions 710 and 720.

[0054] The layout 700 may further include a plurality of cut patterns (e.g., 742), each cut pattern extending along the X direction and traversing one or more of the gate structures 730 to 740. As shown, the cut pattern 742 extending along the X direction to traverse the gate structures 730 to 740 can be used to define the footprint of the dielectric structure (hereinafter referred to as "dielectric structure 742"). The dielectric structure 742 may be formed along the centerline of the boundary 601, thereby dividing each of the gate structures 730 to 740 into separate gate portions, such as gate portions 730A and 730B and gate portions 740A and 740B. Power structures implemented as vertically extending first via structures 744A and second via structures 744B may be formed to extend through the dielectric structure 742.

[0055] In some embodiments, active regions 610 and 710 are perpendicularly aligned to each other, active regions 620 and 720 are perpendicularly aligned to each other, gate structures 630 and 730 are perpendicularly aligned to each other, and gate structures 640 and 740 are perpendicularly aligned to each other. Active regions 610 and 710 may be solidly formed into a single structure (sometimes referred to as "active region 610 / active region 710"), active regions 620 and 720 may be solidly formed into a single structure (sometimes referred to as "active region 620 / active region 720"), gate structures 630 and 730 may be solidly formed into a single structure (sometimes referred to as "gate structure 630 / gate structure 730"), and gate structures 640 and 740 may be solidly formed into a single structure (sometimes referred to as "gate structure 640 / gate structure 740").

[0056] Furthermore, in some embodiments, dielectric structure 642 and dielectric structure 742 are perpendicularly aligned to each other, and through-hole structures 644A to 644B and 744A to 744B respectively disposed in dielectric structure 642 and dielectric structure 742 are perpendicularly aligned to each other. For example, through-hole structures 644A and 744A are perpendicularly aligned to each other, and through-hole structures 644B and 744B are perpendicularly aligned to each other. Dielectric structure 642 and dielectric structure 742 may be solidly formed as a single structure (sometimes referred to as "dielectric structure 642 / dielectric structure 742"), through-hole structure 644A and through-hole structure 744A may be solidly formed as a single structure (sometimes referred to as "through-hole structure 644A / through-hole structure 744A"), and through-hole structures 644B and 744B may be solidly formed as a single structure (sometimes referred to as "through-hole structure 644B / through-hole structure 744B").

[0057] Thus, dielectric structure 642 / dielectric structure 742, via structure 644A / via structure 744A, and via structure 644B / via structure 744B can extend vertically from the first level to the second level, so that dielectric structure 642 / dielectric structure 742 can cut gate structure 630 into gate portion 630A and gate portion 630B, cut gate structure 730 into gate portion 730A and gate portion 730B, cut gate structure 640 into gate portion 640A and gate portion 640B, and cut gate structure 740 into gate portion 740A and gate portion 740B. In some embodiments, gate portion 630A and gate portion 730A may be coupled to each other (sometimes referred to as "gate portion 630A / gate portion 630A / 730A730A"), gate portion 630B and gate portion 730B may be coupled to each other (sometimes referred to as "gate portion 630B / gate portion 730B"), gate portion 640A and gate portion 740A may be coupled to each other (sometimes referred to as "gate portion 640A / gate portion 740A"), and gate portions 640B and 740B may be coupled to each other (sometimes referred to as "gate portion 640B / gate portion 740B").

[0058] For example, active regions 610 / 710 and 620 / 720 may each initially be formed as a stacked structure protruding from the front side surface of the substrate. The stack may include a plurality of first semiconductor nanostructures (e.g., first nanosheets) extending along the X direction and perpendicularly separated from each other, and a plurality of second semiconductor nanostructures (e.g., second nanosheets) extending along the X direction and perpendicularly separated from each other. The first nanosheets are positioned at a first level, and the second nanosheets are positioned at a second level. According to some embodiments of this disclosure, the first nanosheets formed based on the lower portion of active regions 610 / 710 or the lower portion of active regions 620 / 720 may partially form a first transistor at the first level; the second nanosheets formed based on the upper portion of active regions 610 / 710 or the upper portion of active regions 620 / 720 may partially form a second transistor at the second level. Further, the first and second nanosheets may be perpendicularly aligned but separated from each other, with at least one dielectric layer inserted between them.

[0059] Next, individual portions of the first and second nanosheets in the stack can be retained. These portions are respectively covered by gate structures 630 / 730 and 640 / 740, which were initially formed as a plurality of dummy (e.g., polysilicon) gate structures. Other portions of the first nanosheet are replaced by a plurality of first epitaxial structures, and other portions of the second nanosheet are replaced by a plurality of second epitaxial structures. According to some embodiments of the present disclosure, the first epitaxial structure (at the first layer) can be formed to have p-type conductivity, and the second epitaxial structure (at the second layer) can be formed to have n-type conductivity. The first epitaxial structure can operably form individual source / drain terminals of the first transistor at the first layer, and the second epitaxial structure can operably form individual source / drain terminals of the second transistor at the second layer.

[0060] Next, each of the dummy gate structures 630 / 730 and 640 / 740 can be replaced by a corresponding active (e.g., metallic) gate structure to form the first transistor and the second transistor. According to some embodiments of this disclosure, each of the active gate structures may include a lower portion and an upper portion corresponding to the first level and the second level, respectively. For example, the lower portion of the active gate structure (e.g., corresponding to gate portion 630A, gate portion 630B, gate portion 640A, or gate portion 640B) may include one or more first work function metals configured to form the gate terminal of one of the first transistors having p-type conductivity, and the upper portion of the active gate structure (e.g., corresponding to gate portion 730A, gate portion 730B, gate portion 740A, or gate portion 740B) may include one or more second work function metals configured to form the gate terminal of one of the second transistors having n-type conductivity. The details of a series of manufacturing processes for forming a semiconductor device, including a first transistor at a first layer and a second transistor at a second layer, will be described with reference to Figures 6 and 7.

[0061] As a brief overview, transistors PU1 and PU2 in memory cell 100 (Figure 1) can be formed at a first level based on layout 600 (as shown in Figure 6), and transistors PG1, PG2, PD1, and PD2 in memory cell 100 (Figure 1) can be formed at a second level based on layout 700 (as shown in Figure 7). In some embodiments, transistors PU1 and PU2 at the first level can have p-type conductivity, and transistors PG1, PG2, PD1, and PD2 at the second level can have n-type conductivity. Further, a first dummy transistor DMY1 and a second dummy transistor DMY2 can be formed at the first level, and one of the first epitaxial structures (e.g., source / drain terminals) of each dummy transistor is replaced by an isolation structure.

[0062] For example, in Figure 6, transistor PU1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 610, gate portion 640A, and a subset of the first epitaxial structure formed by active region 610 and disposed on the opposite side of gate portion 640A. Transistor PU2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 620, gate portion 630B, and a subset of the first epitaxial structure formed by active region 620 and disposed on the opposite side of gate portion 630B. Transistor DMY1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in active region 610, gate portion 630A, and a subset of the first epitaxial structure formed by active region 610 and disposed on the opposite side of gate portion 630A. In some embodiments, one of the source / drain terminals of transistor DMY1 (e.g., the first epitaxial structure disposed opposite to gate portion 630A relative to gate portion 640A) can be replaced by isolation structure 646. Transistor DMY2 may include its channel, gate terminal, and source / drain terminals, which are respectively formed by a subset of the first nanosheets in active region 620, gate portion 640B, and a subset of the first epitaxial structure formed by active region 620 and disposed on the opposite side of gate portion 640B. In some embodiments, one of the source / drain terminals of transistor DMY2 (e.g., the first epitaxial structure disposed opposite to gate portion 640B relative to gate portion 630B) can be replaced by isolation structure 648.

[0063] In another example, in Figure 7, transistor PD1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 710, gate portion 740A, and a subset of the second epitaxial structure formed by active region 710 and disposed on the opposite side of gate portion 740A. Transistor PG1 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 710, gate portion 730A, and a subset of the second epitaxial structure formed by active region 710 and disposed on the opposite side of gate portion 730A. Transistor PD2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in active region 720, gate portion 730B, and a subset of the second epitaxial structure formed by active region 720 and disposed on the opposite side of gate portion 730B. The transistor PG2 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in the active region 720, the gate portion 740B, and a subset of the second epitaxial structure formed by the active region 720 and disposed on the opposite side of the gate portion 740B.

[0064] Referring again to Figure 6, layout 600 may further include patterns for forming source / drain contact structures 650, 652, 654, 656, 658, and 660, respectively. Each of these source / drain contact structures 650 to 660 is sometimes referred to as an MD. Generally, each of these MDs 650 to 660 is used to electrically connect the source / drain terminals of the corresponding transistor to an upper or lower interconnect structure. However, according to some embodiments of this disclosure, some of the MDs 650 to 660 (e.g., 650, 660) may be physically coupled to corresponding isolation structures that replace the epitaxial structures (e.g., 646, 648). Each of MD 650 to MD 660 may be physically coupled to or surrounded by a corresponding epitaxial structure or isolation structure. In some embodiments, each of MD 650 to MD 660 may extend laterally in the same direction (e.g., the Y direction) as gate structures 630 to 640.

[0065] For example, in Figure 6, MD 650 is coupled to the bottom surface of isolation structure 646; MD 660 is coupled to the bottom surface of isolation structure 648; MD 654 is coupled to the bottom surface of one of the source / drain terminals of transistor PU1, while MD 652 is coupled to the bottom surface of the other source / drain terminal of transistor PU1; MD 656 is coupled to the bottom surface of one of the source / drain terminals of transistor PU2, while MD 658 is coupled to the bottom surface of the other source / drain terminal of transistor PU2.

[0066] The layout 600 may further include patterns for forming internal contact structures 670 and 674, respectively; patterns for forming interconnect structures 672, 676, 680, 682, 684, and 686, respectively, in a first layer on the rear side; and patterns for forming via structures 673, 677, 687, 689, 691, and 693, respectively. In some embodiments, each of the internal contact structures 670 and 674 may be formed below and coupled to the MD. Further, each of the internal contact structures 670 and 674 may extend along the X direction to connect to the interconnect structure (e.g., a BMO track) formed below it, as will be discussed below. In some embodiments, each of the internal contact structures 670 and 674 may be vertically disposed between the MD and the BMO track. For example, internal contact structures 670 and 674 can be vertically inserted between the back side of the substrate and the BMO layer. Each of via structures 673 and 677 is typically formed below or extends downwards from the gate structure (sometimes referred to as BVG). BVG 673 and BVG 677 are each coupled to their respective gate structures. Each of via structures 687 to 693 is typically formed below or extends downwards from the MD (sometimes referred to as BVD). BVD 687 to BVD 693 are each coupled to their respective MD.

[0067] The first layer disposed on the back side is sometimes referred to as the bottom of a plurality of back metallization layers, such as the BMO layer, and the interconnect structures 672, 676, 680, 682, 684, and 686 disposed therein are sometimes referred to as BMO orbitals. The back metallization layer typically comprises one or more dielectric materials (e.g., silicon, oxide, low-k dielectric, or the like) embedded with corresponding metal orbitals formed of, for example, copper. These BMO orbitals 672, 676, 680, 682, 684, and 686 (including internal contact structures 670 and 674) may extend along the X or Y direction, as shown in Figure 6.

[0068] In some embodiments, BM0 rails 672 and 676 may each be coupled via BVG to a corresponding overlying gate structure (or gate portion) in the first layer on the front side, and BM0 rails 680 to 686 may each be coupled via BVD to a corresponding overlying MD in the first layer on the front side. For example, BM0 rail 680 is coupled to MD 650 via BVD 687; BM0 rail 682 is coupled to MD 660 via BVD 693; BM0 rail 684 is coupled to MD 654 via BVD 689; and BM0 rail 686 is coupled to MD 656 via BVD 691. BM0 rails 680 and 682 may each be operably used as part of a power rail carrying ground voltage VSS, and BM0 rails 684 and 686 may each be operably used as another power rail carrying supply voltage VDD.

[0069] In some embodiments, these power rails (e.g., 680 to 686) may be respectively disposed at the corners of boundary 601, with BMO rails (VSS) 680 and 682 arranged diagonally opposite each other, and BMO rails (VDD) 684 and 686 arranged diagonally opposite each other. As MD 650 and MD 660 are disposed along the Y direction, through-hole structures 644A / 744A disposed along the centerline of boundary 601 may be coupled to BMO rails (VSS) 680 extending along the X direction, and through-hole structures 644B / 744B disposed along the centerline of boundary 601 may be coupled to BMO rails (VSS) 682 extending along the X direction. For example, MD 650 and MD 660 may be coupled to via structures 644A / 744A and 644B / 744B (or overlap them when viewed from the top / bottom), as shown in Figures 6 and 7. MD 650 and MD 660 may couple via structures 644A / 744A to BMO track (VSS) 680 and via structures 644B / 744B to BMO track (VSS) 682 along each of their longitudinal directions (e.g., the Y direction).

[0070] Furthermore, the internal contact structure 670 can be coupled to a BMO track 672 coupled to the gate terminal of transistor PU2, and the internal contact structure 674 can be coupled to a BMO track 676 coupled to the gate terminal of transistor PU1. As the internal contact structure 670 extends in the X direction and the BMO track 672 extends in the Y direction, when viewed from the top or bottom, the internal contact structure 670 and the BMO track 672 can together form an L-shaped profile. Similarly, when viewed from the top or bottom, the internal contact structure 674 and the BMO track 676 can together form another L-shaped profile. In some other embodiments, the internal contact structure 670 and the BMO track 672 can be formed in the same layer, for example, in an intermediate layer vertically between the substrate and the BMO layer. Similarly, the internal contact structure 674 and the BMO track 676 can be formed in the same intermediate layer.

[0071] Thus, the connection between one of the source / drain terminals of transistor PU1 and the gate terminal of transistor PU2 (or the internal node 110 in Figure 1) can be operably formed by at least MD 652 (connected to the source / drain terminal of transistor PU1), internal contact structure 670, BMO track 672, and BVG 673 (connected to the gate terminal of transistor PU2); and the connection between one of the source / drain terminals of transistor PU2 and the gate terminal of transistor PU1 (or the internal node 112 in Figure 1) can be operably formed by at least MD 658 (connected to the source / drain terminal of transistor PU2), internal contact structure 674, BMO track 676, and BVG 677 (connected to the gate terminal of transistor PU1).

[0072] Referring again to Figure 7, layout 700 may further include patterns for forming source / drain contact structures 750, 752, 754, 756, 758, and 760, respectively. Each of these source / drain contact structures 750 to 760 is sometimes referred to as an MD. Generally, each of these MDs 750 to MD 760 is used to electrically connect the source / drain terminals of the corresponding transistor to an upper or lower interconnect structure. Each of the MDs 750 to MD 760 may be physically coupled to or surround a corresponding epitaxial structure. In some embodiments, each of the MDs 750 to MD 760 may extend laterally along the same direction (e.g., the Y direction) as the gate structures 730 to 740.

[0073] For example, in Figure 7, MD 750 is coupled to the top surface of one of the source / drain terminals of transistor PG1, while MD 752 is coupled to the top surface of the other source / drain terminal of transistor PG1 (which is also the source / drain terminal of transistor PD1); MD 754 is coupled to the top surface of the other source / drain terminal of transistor PD1; MD 760 is coupled to the top surface of one of the source / drain terminals of transistor PG2, while MD 758 is coupled to the top surface of the other source / drain terminal of transistor PG2 (which is also the source / drain terminal of transistor PD2); MD 756 is coupled to the top surface of the other source / drain terminal of transistor PD2.

[0074] The layout 700 may further include patterns for forming internal contact structures 762 and 764, respectively; patterns for forming interconnect structures 770, 772, 774, and 776 in the third layer on the front side, respectively; and patterns for forming via structures 777, 779, 781, and 783, respectively. In some embodiments, on the front side, each of the internal contact structures 762 and 764 may extend vertically from the first layer to the second layer (sometimes referred to as MDLI). Each of the via structures 777 and 779 is typically formed on or extends upward from the gate structure (sometimes referred to as VG). Each of VG 777 and VG 779 is coupled to a corresponding gate structure. Each of the via structures 781 and 783 is typically formed on or extends upward from the MD (sometimes referred to as VD). VD 781 and VD 783 are each coupled to their respective MDs.

[0075] The third layer, situated above the second layer on the front side, is sometimes referred to as the bottom of a plurality of front metallization layers, such as the M0 layer, and the interconnect structures 770 to 776 disposed therein are sometimes referred to as M0 orbitals. The front metallization layer typically comprises one or more dielectric materials (e.g., silicon, oxide, low-k dielectric materials, or the like) embedded with corresponding metal orbitals formed of, for example, copper. These M0 orbitals 770 to 776 may extend along the X direction, as shown in Figure 7.

[0076] In some embodiments, each of M0 rails 770 and 776 may be coupled via VG to a corresponding overlying gate structure (or gate portion) in the second layer on the front side, and each of M0 rails 772 and 774 may be coupled via VD to a corresponding overlying MD in the first layer on the front side. For example, M0 rail 770 is coupled to gate portion 730A via VG 777; M0 rail 776 is coupled to gate portion 740B via VG 779; M0 rail 772 is coupled to MD 750 via VD 781; and M0 rail 774 is coupled to MD 760 via VD 783. M0 orbitals 770 and 776 can each be operably used as part of WL (Figure 1), M0 orbital 772 can be operably used as part of BL (Figure 1), and M0 orbital 774 can be operably used as part of BLB (Figure 1).

[0077] The internal contact structure 762 extends downward from the second level to the first level, thereby coupling the MD 752 at the second level (which is coupled to the common source / drain terminal of transistors PD1 and PG1) to the source / drain terminal of transistor PU1 at the first level. As described above, the source / drain terminal of transistor PU1 (the first epitaxial structure formed by the active region 610 and above the MD 652) is coupled to the gate terminal (gate portion 630B) of transistor PU2 via the MD 652, the internal contact structure 670, and the BMO track 672; and the gate terminal (gate portion 630B) of transistor PU2 is coupled to the gate terminal (gate portion 730B) of transistor PD2. In this way, an internal node 110 connecting the common source / drain terminal of transistors PU1, PD1, and PG1 to the gate terminals of transistors PU2 and PD2 can be operably formed.

[0078] Similarly, the internal contact structure 764 can extend downwards from the second level to the first level, thereby coupling the MD 758 at the second level (which is coupled to the common source / drain terminal of transistors PD2 and PG2) to the source / drain terminal of transistor PU2 at the first level. As described above, the source / drain terminal of transistor PU2 (the first epitaxial structure formed by the active region 620 and above MD 652) is coupled to the gate terminal (gate portion 630B) of transistor PU2 via MD 658, internal contact structure 674, and BMO track 676; and the gate terminal (gate portion 640A) of transistor PU1 is coupled to the gate terminal (gate portion 740A) of transistor PD1. In this way, an internal node 112 connecting the common source / drain terminal of transistors PU2, PD2, and PG2 to the gate terminals of transistors PU1 and PD1 can be operably formed.

[0079] Figures 8 and 9 illustrate perspective views of a semiconductor device 800 including memory cells configured with CFET structures according to some embodiments of the present disclosure. For example, the semiconductor device 800 may include memory cells 100 formed based on layouts 600 to 700 (Figures 6 and 7), and therefore, some of the reference numerals in Figures 6 and 7 may be used again. Specifically, the perspective view of Figure 8 is viewed from the front side of the substrate (where the transistors of the memory cells 100 are formed), and the perspective view of Figure 9 is viewed from the rear side of the substrate. It should be understood that the semiconductor device 800 in Figures 8 and 9 has been simplified; therefore, some of the structures described above have been omitted for clarity.

[0080] As shown in the figure, via structures 644A / 744A extend vertically to connect MD 756 at the second front layer to MD 650 at the first layer (not shown in Figure 9), and via structures 644B / 744B extend vertically to connect MD 754 at the second front layer to MD 660 at the first layer (not shown in Figure 8). MD 756 is connected to one of the source / drain terminals of transistor PD2, and MD 650 is coupled to BMO track 680 carrying the ground voltage VSS. MD 754 is connected to one of the source / drain terminals of transistor PD1, and MD 660 is coupled to BMO track 682 carrying the ground voltage VSS. Thus, the source / drain terminals of transistors PD1 and PD2 can be electrically connected to the ground voltage VSS via via structures 644A / 744A and 644B / 744B, respectively. Furthermore, it should be noted that the top surface of MD 650 is connected to isolation structure 646 (as shown in Figure 8), and the top surface of MD 660 is connected to isolation structure 648 (as shown in Figure 9). Specifically, in Figure 9, the internal contact structure 670, BMO track 672, and BVG 673 can form part of the connection between one of the source / drain terminals of transistor PU1 and the gate terminal of transistor PU2; the internal contact structure 674, BMO track 676, and BVG 677 can form part of the connection between one of the source / drain terminals of transistor PU2 and the gate terminal of transistor PU1.

[0081] Figures 10 and 11 respectively illustrate cross-sectional views of the semiconductor device 400 shown in Figures 4 and 5 according to some embodiments. For example, the cross-sectional view of Figure 10 is cut along line AA (e.g., the X direction) shown in Figure 4, and the cross-sectional view of Figure 11 is cut along line BB (e.g., the Y direction) shown in Figure 4.

[0082] In Figure 10, wall structures 244 / 344 extend vertically (e.g., through the first and second front layers) to connect MD 250 and MD 260 to MD 356 and MD 354. In some embodiments, MD 250 and MD 260 may extend laterally in opposite directions, and MD 356 and MD 354 may extend laterally in opposite directions, as better understood in Figures 4 and 5. In Figure 11, wall structures 244 / 344 extend vertically (e.g., through the first and second front layers) to connect MD 250 to MD 356. In some embodiments, MD 250 may be coupled to isolation structure 246, and MD 356 may be coupled to one of the source / drain terminals of transistor PD2. As further depicted in Figure 11, at the first level, MD 256 and MD 250, which are coupled to one of the source / drain terminals of transistor PU2, are laterally separated; at the second level, MD 350 and MD 356, which are coupled to one of the source / drain terminals of transistor PG1, are laterally separated.

[0083] Figures 12 and 13 respectively illustrate cross-sectional views of the semiconductor device 800 shown in Figures 8 to 9 according to some embodiments. For example, the cross-sectional view of Figure 12 is cut along line AA (e.g., the X direction) shown in Figure 8, and the cross-sectional view of Figure 13 is cut along line BB (e.g., the Y direction) shown in Figure 8.

[0084] In Figure 12, via structures 644A / 744A extend vertically (e.g., through the first and second front layers) to connect MD 650 to MD 756; via structures 644B / 744B extend vertically (e.g., through the first and second front layers) to connect MD 660 to MD 754. In some embodiments, MD 650 and MD 756 may extend laterally in opposite directions, and MD 660 and MD 754 may extend laterally in opposite directions, as better understood in Figures 8 to 9. In Figure 13, via structures 644A / 744A extend vertically (e.g., through the first and second front layers) to connect MD 650 to MD 756. In some embodiments, MD 650 may be coupled to isolation structure 646, and MD 756 may be coupled to one of the source / drain terminals of transistor PD2. As further depicted in Figure 13, at a first level, MD 656 coupled to one of the source / drain terminals of transistor PU2 is laterally separated from MD 650; at a second level, MD 750 coupled to one of the source / drain terminals of transistor PG1 is laterally separated from MD 756.

[0085] Figures 14 and 15 illustrate top views of a semiconductor device 400 (Figures 4-5) or a semiconductor device 800 (Figures 8-9) according to some embodiments. Each of the top views in Figures 14 and 15 includes a plurality of front metal tracks disposed above the memory cells. It should be understood that the top views in Figures 14 and 15 are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0086] The top view of Figure 14 refers to the configuration of a plurality of M0 tracks 1402, M0 track 1404, M0 track 1406, and M0 track 1408 relative to the corresponding unit boundary, and these M0 tracks 1402 to M0 track 1408 are respectively configured as a first WL, BL, BLB, and a second WL. In some embodiments, from the leftmost edge to the rightmost edge of the unit boundary, the first WL (1402), BL (1404), BLB (1406), and second WL (1408) are configured in the order shown. For example, as shown in Figures 4 and 5, the first WL, BL, BLB, and second WL in Figure 14 may correspond to M0 tracks 370, 372, 374, and 376, respectively. In another example, the first WL, BL, BLB, and second WL in Figure 14 may correspond to M0 orbitals 770, 772, 774, and 776, respectively, as shown in Figures 8 and 9. In some embodiments, these M0 orbitals may extend along the X direction. Further, the semiconductor device 400 or semiconductor device 800 may further include at least one M1 orbital 1410 extending along the Y direction above the first WL, BL, BLB, and second WL, and coupled to the first WL and second WL via individual via structures 1420. This M1 orbital is disposed in the next bottommost (front) metallization layer, commonly referred to as the M1 layer.

[0087] The top view of Figure 15 refers to another configuration of the plurality of M0 tracks 1502, M0 track 1504, M0 track 1506, and M0 track 1508 relative to the corresponding unit boundary, and these M0 tracks 1502 to M0 track 1508 are respectively configured as a first WL, BL, a second WL, and BLB. In some embodiments, from the leftmost edge to the rightmost edge of the unit boundary, the first WL (1502), BL (1504), second WL (1506), and BLB (1508) are configured in the order shown. For example, the first WL, BL, second WL, and BLB in Figure 15 may correspond to M0 tracks 370, 372, 374, and 376, respectively, as shown in Figures 4 and 5. In another example, the first WL, BL, second WL, and BLB in Figure 15 may correspond to M0 orbitals 770, 772, 774, and 776, respectively, as shown in Figures 8 and 9. In some embodiments, these M0 orbitals may extend along the X direction. Further, the semiconductor device 400 or semiconductor device 800 may further include at least one M1 orbital 1510 extending in the Y direction above the first WL, BL, BLB, and second WL, and coupled to the first WL and second WL via individual via structures 1520. This M1 orbital is disposed in the next bottommost (front) metallization layer, commonly referred to as the M1 layer.

[0088] Figures 16 and 17 illustrate top (or bottom) views of a semiconductor device 400 (Figures 4-5) or a semiconductor device 800 (Figures 8-9) according to some embodiments. Each of the top / bottom views in Figures 16 and 17 includes a plurality of rear metal tracks disposed beneath one or more memory cells. It should be understood that the top views in Figures 16 and 17 are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0089] The top / bottom view of Figure 16 refers to the configuration of the plurality of BM0 rails 1602, BM0 rails 1604, BM0 rails 1606, and BM0 rails 1608 relative to the corresponding cell boundary. BM0 rail 1602 is configured as part of a first power rail carrying VSS, BM0 rail 1604 is configured as part of a second power rail carrying VDD, BM0 rail 1606 is configured as part of a third power rail carrying VDD, and BM0 rail 1608 is configured as a fourth power rail carrying VSS. In some embodiments, the first power rail 1602 and the fourth power rail 1608 are respectively disposed around a pair of corners of the cell boundary, and the second power rail 1604 and the third power rail 1606 are respectively disposed around another pair of corners of the cell boundary.

[0090] For example, the first power rail 1602, the second power rail 1604, the third power rail 1606, and the fourth power rail 1608 in Figure 16 may correspond to BM0 rails 280, BM0 rail 284, BM0 rail 286, and BM0 rail 282, respectively, as shown in Figures 4 and 5. In another example, the first power rail 1602, the second power rail 1604, the third power rail 1606, and the fourth power rail 1608 in Figure 16 may correspond to BM0 rails 680, BM0 rail 684, BM0 rail 686, and BM0 rail 682, respectively, as shown in Figures 8 and 9. In some embodiments, these BM0 rails may extend along the X direction. Furthermore, semiconductor device 400 or semiconductor device 800 may further include at least one BM1 track (not shown in Figure 16) extending in the Y direction and coupled to the first power rail 1602 and the fourth power rail 1608 via individual via structures, and at least another BM1 track (not shown in Figure 16) extending in the Y direction and coupled to the second power rail 1604 and the third power rail 1606 via individual via structures. Such BM1 tracks are disposed in the next bottommost (backside) metallization layer, commonly referred to as the BM1 layer.

[0091] The top / bottom view of Figure 17 refers to the configuration of multiple BM0 rails 1702, BM0 rail 1704, BM0 rail 1706, BM0 rail 1708, BM0 rail 1710, and BM0 rail 1712 relative to the boundaries of two corresponding elements. BM0 rail 1702 is configured as part of the first power rail carrying VDD, BM0 rail 1704 is configured as part of the second power rail carrying VSS, BM0 rail 1706 is configured as part of the third power rail carrying VDD, BM0 rail 1708 is configured as the fourth power rail carrying VSS, BM0 rail 1710 is configured as part of the fifth power rail carrying VDD, and BM0 rail 1712 is configured as the sixth power rail carrying VSS. In some embodiments, the first power rail 1702 and the fifth power rail 1710 are respectively disposed around a pair of corners of the first unit boundary, the second power rail 1704 and the fourth power rail 1708 are respectively disposed around another pair of corners of the first unit boundary, the second power rail 1704 and the sixth power rail 1712 are respectively disposed around a pair of corners of the second unit boundary, and the third power rail 1706 and the fifth power rail 1710 are respectively disposed around another pair of corners of the second unit boundary. Further, the second power rail 1704 and the fifth power rail 1710 may be shared by the first and second unit boundaries, or shared by corresponding memory units.

[0092] For example, the first power rail 1702, the second power rail 1704, the fourth power rail 1708, and the fifth power rail 1710 in Figure 17 may correspond to BM0 rails 284, BM0 rail 280, BM0 rail 282, and BM0 rail 286, respectively, as shown in Figures 4 and 5. In another example, the first power rail 1702, the second power rail 1704, the fourth power rail 1708, and the fifth power rail 1710 in Figure 17 may correspond to BM0 rails 684, BM0 rail 680, BM0 rail 682, and BM0 rail 686, respectively, as shown in Figures 8 and 9. In some embodiments, these BM0 rails may extend along the X direction. Furthermore, semiconductor device 400 or semiconductor device 800 may further include at least one BM1 track 1720 extending in the Y direction and coupled to the second power rail 1704 and the fourth power rail 1708 via individual via structures, and at least another BM1 track 1730 extending in the Y direction and coupled to the third power rail 1706 and the fifth power rail 1710 via individual via structures. Such BM1 tracks are disposed in the next bottommost (backside) metallization layer, commonly referred to as the BM1 layer.

[0093] Figure 18 illustrates a flowchart of an example method 1800 for forming a memory cell configured with a CFET structure according to some embodiments of the present disclosure. At least some of the operations (or steps) of method 1800 can be used to form a memory cell 100 (Figure 1) in a CFET structure having an embedded power structure. For example, the CFET structure includes a plurality of p-type transistors disposed at a first layer on the front side of the substrate, a plurality of n-type transistors disposed at a second upper layer on the front side of the substrate, and a power structure extending vertically through the first and second layers and laterally inserted between the p-type transistors and the n-type transistors. In one embodiment, the power structure may be formed as a monolithic wall structure. In another embodiment, the power structure may be formed as a pair of through-hole structures.

[0094] It should be understood that method 1800 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that additional operations may be provided before, during, and after method 1800 of Figure 18, and only a few other operations may be briefly described herein. In some embodiments, the operations in method 1800 may be associated with cross-sectional views of the CFET structure 1900 (similar to semiconductor device 400 of Figures 4-5 or semiconductor device 800 of Figures 8-9) at various manufacturing stages, as shown in Figures 19, 20, 21, 22, 23, 24, 25, 26, 27, and 28, respectively, which will be discussed in further detail below.

[0095] In brief, method 1800 begins at operation 1802, forming a plurality of dummy gate structures over a stack comprising a lower portion and an upper portion. The lower portion comprises a plurality of first nanostructures and a plurality of second nanostructures stacked alternately on top of each other, and the upper portion comprises a plurality of third nanostructures and a plurality of fourth nanostructures stacked alternately on top of each other. The first and third nanostructures may be formed of a first semiconductor material, and the second and fourth nanostructures may be formed of a second semiconductor material. Further, the lower and upper portions may be separated from each other by a fifth nanostructure formed of a third semiconductor material. Method 1800 continues to operation 1804, etching the stack to form source / drain recesses. 1800 continues to operation 1806, laterally recessing the second and fourth nanostructures. Method 1800 continues to operation 1808, forming a plurality of internal spacers. Method 1800 continues to operation 1810, selectively removing the fifth nanostructure. Method 1800 continues to operation 1812, forming a dielectric layer between the lower and upper portions. Method 1800 continues to operation 1814, forming a plurality of p-type epitaxial structures in the lower portion and a plurality of n-type epitaxial structures in the upper portion. Method 1800 continues to operation 1816, forming a first active gate structure in the lower portion and a second active gate structure in the upper portion. Method 1800 continues to operation 1818, forming a power supply structure. Method 1800 continues to operation 1820, forming a plurality of contact structures.

[0096] Corresponding to operation 1802 in Figure 18, Figure 19 is a cross-sectional view of a CFET structure 1900 including a plurality of dummy gate structures 1902 above a stack 1904 at one of the various manufacturing stages. The cross-sectional view of Figure 19 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0097] In some embodiments, a stack 1904 may be formed over a semiconductor substrate 1901, followed by a dummy gate structure 1902 formed over the stack 1904. The stack 1904 may extend along the X direction, and the dummy gate structure 1902 may extend along the Y direction to cross or otherwise traverse the stack 1904. The stack 1904 includes a lower portion 1904-1 and an upper portion 1904-2, which may correspond to a first level and a second level on the front side of the substrate, respectively (e.g., Figures 4-5, 8-9). The lower portion 1904-1 includes a plurality of first nanostructures 1906 and a plurality of second nanostructures 1908 alternately stacked on top of each other, and the upper portion 1904-2 includes a plurality of third nanostructures 1910 and a plurality of fourth nanostructures 1912 alternately stacked on top of each other.

[0098] The substrate 1901, the first nanostructure 1906, and the third nanostructure 1910 may be formed of a first semiconductor material (e.g., silicon (Si)), while the second nanostructure 1908 and the fourth nanostructure 1912 may be formed of a second semiconductor material (e.g., silicon germanium (Si1-xGex)). Further, the lower portion 1904-1 and the upper portion 1904-2 are separated from each other by a fifth nanostructure 1914 formed of a third semiconductor material (e.g., silicon germanium (Si1-yGey)). In some embodiments, the molar ratio "x" of the second semiconductor material may be less than 0.5, and the molar ratio "y" of the third semiconductor material may be greater than 0.5.

[0099] Nanostructures 1906 to 1912 can be epitaxially grown from a semiconductor substrate 1901. For example, each of nanostructures 1906 to 1912 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD, MOCVD), and / or other suitable epitaxial growth processes. After growing nanostructures 1906 to 1912 on the substrate 1901 as a blanket stack, the blanket stack can be patterned to form the stack 1904 shown in Figure 19 (e.g., having a longitudinal direction in the X direction and a relatively narrow width in the Y direction). After the stack 1904 is formed, a dummy gate structure 1902 is formed across the stack 1904, including a dummy gate dielectric (e.g., silicon oxide) and a dummy gate material (e.g., polysilicon).

[0100] Corresponding to operation 1804 in Figure 18, Figure 20 is a cross-sectional view of the CFET structure 1900, in which source / drain recesses 1920 are formed at one of the various manufacturing stages. The cross-sectional view of Figure 20 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0101] To form the source / drain recess 1920, a pair of gate spacers 1916 can be formed on opposite sidewalls of the dummy gate structure 1902. Next, using the dummy gate structure 1902 and the gate spacers 1916 as a mask, an anisotropic etching process is used to pattern the stack 1904 again to form the source / drain recess 1920. This anisotropic etching process may include reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof.

[0102] Corresponding to operation 1806 in Figure 18, Figure 21 is a cross-sectional view of the CFET structure 1900, wherein the second nanostructure 1908 and the fourth nanostructure 1912 are laterally recessed at one of the various manufacturing stages. The cross-sectional view of Figure 21 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0103] As shown in the figure, a "pull-back" process is used to remove (e.g., etch) individual end portions of each of the second nanostructure 1908 and the fourth nanostructure 1912 (formed from Si1-xGex), thereby pulling back each of the nanostructures 1908 and 1912 by a pull-back distance. For example, the pull-back process may include an isotropic etching process using hydrogen chloride (HCl) gas, which etches SiGe with a lower Ge content (e.g., Si1-xGex) without attacking Si or SiGe with a higher Ge content (e.g., Si1-yGey). Thus, during this process, nanostructures 1906 (Si), 1910 (Si), and 1914 (Si1-yGey) remain substantially intact, and a plurality of grooves 1924 can be formed, each groove extending inward from the source / drain groove 1920.

[0104] Corresponding to operation 1808 in Figure 18, Figure 22 is a cross-sectional view of a CFET structure 1900 including a number of internal spacers 1926 at one of the various manufacturing stages. The cross-sectional view in Figure 22 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0105] The internal spacer 1926 can be formed by filling the groove 1924 with a dielectric material. For example, the internal spacer 1926 can be deposited using, for example, a conformal deposition process and subsequent isotropic or anisotropic etch-back to remove excess spacer material on the sidewalls of the stack 1904. The dielectric material used to form the internal spacer 1926 includes silicon nitride, boron silicon carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers of transistors (e.g., a dielectric material having a dielectric constant k less than about 5).

[0106] Corresponding to operation 1810 in Figure 18, Figure 23 is a cross-sectional view of the CFET structure 1900 with the fifth nanometer structure 1914 removed at one of the various manufacturing stages. The cross-sectional view in Figure 23 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0107] After the internal spacers 1926 are formed, the fifth nanostructure 1914 can be selectively removed using an isotropic etching process that etches Si1-yGey without damaging Si. Thus, the first nanostructure 1906 (Si) and the third nanostructure 1910 (Si) remain substantially intact, the fifth nanostructure 1914 (Si1-yGey) can be completely removed, and the remaining portions of the second nanostructure 1908 (Si1-xGex) and the fourth nanostructure 1912 (Si1-xGex) can be preserved under the protection of the internal spacers 1926.

[0108] Corresponding to operation 1812 in Figure 18, Figure 24 is a cross-sectional view of the CFET structure 1900 including the dielectric layer 1930 at one of the various manufacturing stages. The cross-sectional view in Figure 24 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0109] After the fifth nanostructure 1914 is removed, a space is formed between the lower portion 1904-1 and the upper portion 1904-2. A dielectric layer 1930 can be formed by filling this space with a dielectric material. Dielectric materials used to form the dielectric layer 1930 include silicon nitride, boron silicon carbonitride, silicon carbon nitride, silicon oxycarbonitride, or any other type of dielectric material suitable for forming an insulating structure of a transistor (e.g., a dielectric material having a dielectric constant k less than about 5).

[0110] Corresponding to operation 1814 in Figure 18, Figure 25 is a cross-sectional view of a CFET structure 1900 comprising a plurality of first epitaxial structures 1932 and a plurality of second epitaxial structures 1934 at one of the various manufacturing stages. The cross-sectional view in Figure 25 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0111] As shown in the figure, a pair of first epitaxial structures 1932 are respectively coupled to the ends of each of the first nanostructures 1906; a pair of second epitaxial structures 1934 are respectively coupled to the ends of each of the third nanostructures 1910. The first epitaxial structures 1932 can be formed via a first epitaxial growth process, followed by a second epitaxial growth process for forming the second epitaxial structures 1934. Further, one or more dielectric layers 1936 can be formed between the first and second epitaxial growth processes to electrically isolate the first epitaxial structures 1932 and the second epitaxial structures 1934. Each of the first and second epitaxial growth processes may include selective epitaxial growth (SEG) processes, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. Specifically, the first epitaxial structure 1932 can be grown from the first nanostructure 1906, and the second epitaxial structure 1934 can be grown from the third nanostructure 1910.

[0112] The first epitaxial structure 1932 and the second epitaxial structure 1934 may each include silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material, or combinations thereof. Furthermore, in-situ doping (ISD) may be applied during the formation of each of the first epitaxial structure 1932 and the second epitaxial structure 1934. For example, the first epitaxial structure 1932 may be doped by implanting a p-type dopant (e.g., boron (B)); the second epitaxial structure 1934 may be doped by implanting an n-type dopant (e.g., arsenic (As), phosphorus (P)). In some embodiments, the first epitaxial structure 1932 may be coupled to each of the first nanostructures 1906 via a lightly doped region 1933 (e.g., SiGeB); the second epitaxial structure 1934 may be coupled to each of the third nanostructures 1910 via a lightly doped region 1935 (e.g., SiP).

[0113] Corresponding to operation 1816 in Figure 18, Figure 26 is a cross-sectional view of the CFET structure 1900, including the first active gate structure 1942 and the second active gate structure 1944, at one of the various manufacturing stages. The cross-sectional view in Figure 26 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0114] As shown in the figure, a first active gate structure 1942 surrounds each of the first nanostructures 1906; a second active gate structure 1944 surrounds each of the third nanostructures 1910. To form the first active gate structure 1942 and the second active gate structure 1944, the remaining portions of the dummy gate structure 1902, the second nanostructure 1908, and the fourth nanostructure 1912 are removed. Thus, a first gate trench exposing each of the first nanostructures 1906 can be formed in the lower portion 1904-1 (e.g., the first layer); and a second gate trench exposing each of the third nanostructures 1910 can be formed in the upper portion 1904-2 (e.g., the second layer). Next, a first active gate structure 1942 can be formed in the first gate trench to cover each of the first nanostructures 1906; a second active gate structure 1944 can be formed in the second gate trench to cover each of the third nanostructures 1910.

[0115] In some embodiments, the first active gate structure 1942 may include a first gate dielectric and a first gate metal; the second active gate structure 1944 may include a second gate dielectric and a second gate metal. The first gate dielectric / second gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Examples of high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb, and combinations thereof. The first gate dielectric / second gate dielectric may include a stack of multiple high-k dielectric materials. The first gate metal may include one or more p-type work function metals, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof; the second gate metal may include one or more n-type work function metals, which may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0116] Corresponding to operation 1818 in Figure 18, Figure 27 is a cross-sectional view of the CFET structure 1900, including the power supply structure 1950, at one of the various manufacturing stages. The cross-sectional view in Figure 27 is cut along the longitudinal direction (e.g., the Y direction mentioned above) of the gate structure of the CFET structure 1900.

[0117] As shown in the figure, the power supply structure 1950 is used to divide the first active gate structure 1942 into gate portion 1942A and gate portion 1942B, and the second active gate structure 1944 into gate portion 1944A and gate portion 1944B. Gate portion 1942A and gate portion 1942B are separated from each other along the Y direction, and gate portion 1944A and gate portion 1944B are also separated from each other along the Y direction. Further, the power supply structure 1950 is electrically isolated from the separated gate portions, such as gate portion 1942A and gate portion 1942B, and gate portion 1944A and gate portion 1944B, by a dielectric structure 1952.

[0118] In some embodiments, power structure 1950 may correspond to wall structure 244 / wall structure 344, and dielectric structure 1952 may correspond to dielectric structure 242 / dielectric structure 342 (Figures 2 to 5). Thus, gate portion 1942A and gate portion 1942B may correspond to gate portion 230A and gate portion 230B or gate portion 240A and gate portion 240B, respectively, and gate portion 1944A and gate portion 1944B may correspond to gate portion 330A and gate portion 330B or gate portion 340A and gate portion 340B, respectively. In some other embodiments, power structure 1950 may correspond to via structure 644A / via structure 744A or via structure 644B / via structure 744B, and dielectric structure 1952 may correspond to dielectric structure 642 / dielectric structure 742 (Figures 6 to 9). Thus, gate portion 1942A and gate portion 1942B can correspond to gate portion 630A and gate portion 630B or gate portion 640A and gate portion 640B, respectively, and gate portion 1944A and gate portion 1944B can correspond to gate portion 730A and gate portion 730B or gate portion 740A and gate portion 740B, respectively.

[0119] To form the power supply structure 1950, the intermediate portions of the first active gate structure 1942 and the second active gate structure 1944 can be removed following the aforementioned cutting patterns (e.g., cutting patterns 242 / 342, 642 / 742). For example, this intermediate portion of the first and second active gate structures is removed via at least one anisotropic etching process, thereby forming a vertical trench extending from the first layer to the second layer. Next, a dielectric material (e.g., silicon nitride) can be deposited to fill the vertical trench, followed by the deposition of a metallic material (e.g., copper) to form the power supply structure 1950. The integral wall structure (e.g., wall structure 244 / wall structure 344) can be self-aligned with the vertical trench (i.e., without further lithography). The dual via structure (e.g., via structure 644A / 744A and via structure 644B / 744B) can be formed via another lithography process. For example, after depositing dielectric material into vertical trenches, a lithography process can be performed to form a pair of vertical trenches extending through the dielectric material, followed by the deposition of metallic material.

[0120] After forming the power supply structure 1950, at least two p-type transistors can be formed at the first level and on opposite sides of the power supply structure 1950, and at least two n-type transistors can be formed at the second level and on opposite sides of the power supply structure 1950. The p-type transistors can be operably formed based on a first nanostructure 1906, a gate portion 1942A or a gate portion 1942B, and a pair of first epitaxial structures 1932. The n-type transistors can be operably formed based on a third nanostructure 1910, a gate portion 1944A or a gate portion 1944B, and a pair of second epitaxial structures 1934.

[0121] Corresponding to operation 1818 in Figure 18, Figure 28 is a cross-sectional view of the CFET structure 1900, including the first contact structure 1960 and the second contact structure 1970, at one of the various manufacturing stages. The cross-sectional view of Figure 28 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 1900.

[0122] As shown in the figure, the first contact structure 1960 is coupled to a corresponding one of the first epitaxial structures 1932; the second contact structure 1970 is coupled to a corresponding one of the second epitaxial structures 1934. For example, the first contact structure 1960 may be formed under the first epitaxial structure 1932; the second contact structure 1970 may be formed on the second epitaxial structure 1934. In another example, the first contact structure 1960 may surround the first epitaxial structure 1932; the second contact structure 1970 may surround the second epitaxial structure 1934. In some embodiments, the first contact structure 1960 and the second contact structure 1970 may each be configured as MD, and as described above, they may include titanium, aluminum, nickel, tungsten, tantalum, or other suitable metallic materials.

[0123] Figures 29A and 29B illustrate flowcharts of another example method 2900 for forming a memory cell configured with a CFET structure according to some embodiments of the present disclosure. At least some operations (or steps) in method 2900 can be used to form a memory cell 100 (Figure 1) in a CFET structure having an embedded power structure. For example, the CFET structure includes a plurality of p-type transistors disposed at a first layer on the front side of the substrate, a plurality of n-type transistors disposed at a second upper layer on the front side of the substrate, and a power structure extending vertically through the first and second layers and laterally inserted between the p-type transistors and the n-type transistors. In one embodiment, the power structure may be formed as a monolithic wall structure. In another embodiment, the power structure may be formed as a pair of through-hole structures.

[0124] It should be understood that method 2900 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that additional operations may be provided before, during, and after method 2900 of Figures 29A to 29B, and only a few other operations may be briefly described herein. In some embodiments, the operations in method 2900 may be associated with cross-sectional views of the CFET structure 3000 (similar to semiconductor device 400 of Figures 4 to 5 or semiconductor device 800 of Figures 8 to 9) at various manufacturing stages, as shown in Figures 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, and 41, respectively, which will be discussed in further detail below.

[0125] In brief, method 2900 begins at operation 2902, forming a plurality of dummy gate structures over a stack including a lower portion and an upper portion. The lower portion includes a plurality of first nanostructures and a plurality of second nanostructures stacked alternately, and the upper portion includes a plurality of third nanostructures and a plurality of fourth nanostructures stacked alternately. The first and third nanostructures may be formed of a first semiconductor material, and the second and fourth nanostructures may be formed of a second semiconductor material. Further, the lower and upper portions may be separated from each other by a fifth nanostructure formed of a third semiconductor material. Method 2900 continues to operation 2904, etching the stack to form source / drain recesses. 2900 continues to operation 2906, removing the second and fourth nanostructures. Method 2900 continues to operation 2908, forming a plurality of sacrificial oxide layers, each sacrificial oxide layer inserted between adjacent first nanostructures or between adjacent third nanostructures. Method 2900 continues to operation 2910, causing the sacrificial oxide layers to be laterally recessed. Method 2900 continues to operation 2912, forming a plurality of internal spacers. Method 2900 continues to operation 2914, selectively removing the fifth nanostructure. Method 2900 continues to operation 2916, forming a dielectric layer between the lower and upper portions. Method 2900 continues to operation 2918, forming a plurality of p-type epitaxial structures in the lower portion and a plurality of n-type epitaxial structures in the upper portion. Method 2900 continues to operation 2920, forming a first active gate structure in the lower portion and a second active gate structure in the upper portion. Method 2900 continues to operation 2922, forming a power supply structure. Method 2900 continues to operation 2924, forming a plurality of contact structures.

[0126] Corresponding to operation 2902 in Figures 29A to 29B, Figure 30 is a cross-sectional view of the CFET structure 3000, including a plurality of dummy gate structures 3002 above the stack 3004, at one of the various manufacturing stages. The cross-sectional view of Figure 30 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0127] In some embodiments, a stack 3004 may be formed over a semiconductor substrate 3001, followed by a dummy gate structure 3002 formed over the stack 3004. The stack 3004 may extend along the X direction, and the dummy gate structure 3002 may extend along the Y direction to cross or otherwise traverse the stack 3004. The stack 3004 includes a lower portion 3004-1 and an upper portion 3004-2, which may correspond to a first level and a second level on the front side of the substrate, respectively (e.g., Figures 4-5, 8-9). The lower portion 3004-1 includes a plurality of first nanostructures 3006 and a plurality of second nanostructures 3008 alternately stacked on top of each other, and the upper portion 3004-2 includes a plurality of third nanostructures 3010 and a plurality of fourth nanostructures 3012 alternately stacked on top of each other.

[0128] The substrate 3001, the first nanostructure 3006, and the third nanostructure 3010 may be formed of a first semiconductor material (e.g., silicon (Si)), while the second nanostructure 3008 and the fourth nanostructure 3012 may be formed of a second semiconductor material (e.g., silicon germanium (Si1-xGex)). Further, the lower portion 3004-1 and the upper portion 3004-2 are separated from each other by a fifth nanostructure 3014 formed of a third semiconductor material (e.g., silicon germanium (Si1-yGey)). In some embodiments, the molar ratio "x" of the second semiconductor material may be less than 0.5, and the molar ratio "y" of the third semiconductor material may be greater than 0.5.

[0129] Nanostructures 3006 to 3012 can be epitaxially grown from a semiconductor substrate 3001. For example, each of nanostructures 3006 to 3012 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD, MOCVD), and / or other suitable epitaxial growth processes. After growing nanostructures 3006 to 3012 on the substrate 3001 as a blanket stack, the blanket stack can be patterned to form the stack 3004 shown in Figure 30 (e.g., having a longitudinal direction in the X direction and a relatively narrow width in the Y direction). After the stack 3004 is formed, a dummy gate structure 3002 is formed across the stack 3004, including a dummy gate dielectric (e.g., silicon oxide) and a dummy gate material (e.g., polysilicon).

[0130] Corresponding to operation 2904 in Figures 29A to 29B, Figure 31 is a cross-sectional view of the CFET structure 3000 in which the source / drain recess 3020 is formed at one of the various manufacturing stages. The cross-sectional view of Figure 31 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0131] To form the source / drain recess 3020, a pair of gate spacers 3016 can be formed on opposite sidewalls of the dummy gate structure 3002. Next, with the dummy gate structure 3002 and gate spacers 3016 acting as a mask, the stack 3004 is patterned again using an anisotropic etching process to form the source / drain recess 3020. This anisotropic etching process may include reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof.

[0132] Corresponding to operation 2906 in Figures 29A to 29B, Figure 32 is a cross-sectional view of the CFET structure 3000 in one of the various manufacturing stages, in which the second nanostructure 3008 and the fourth nanostructure 3012 have been removed. The cross-sectional view of Figure 32 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0133] In some embodiments, the second nanostructure 3008 and the fourth nanostructure 3012 may be selectively removed (e.g., etched), while the first nanostructure 3006, the third nanostructure 3010, and the fifth nanostructure 3014 remain substantially intact. The second nanostructure 3008 and the fourth nanostructure 3012 can be completely removed using an isotropic etching process with hydrogen chloride (HCl) gas, which etches SiGe with a lower Ge content (e.g., Si1-xGex) without attacking Si or SiGe with a higher Ge content (e.g., Si1-yGey). Thus, a plurality of spaces 3023 can be formed. As shown in Figure 32, each of the elements in space 3023 can be vertically inserted between substrate 3001 and the bottommost element of the first nanostructure 3006, between adjacent elements of the first nanostructure 3006, between the topmost element of the first nanostructure 3006 and the fifth nanostructure 3014, between the fifth nanostructure 3014 and the bottommost element of the third nanostructure 3010, or between adjacent elements of the third nanostructure 3010.

[0134] Corresponding to operation 2908 in Figures 29A to 29B, Figure 33 is a cross-sectional view of a CFET structure 3000 including a plurality of sacrificial oxide layers 3024 at one of the various manufacturing stages. The cross-sectional view of Figure 33 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0135] As shown in the figure, sacrificial oxide layers 3024 are formed at least in spaces 3023. In some embodiments, the sacrificial oxide layers 3024 may be deposited using, for example, a conformal deposition process to deposit oxide material, and one or more subsequent isotropic or anisotropic etching processes may be used to remove excess oxide material on the sidewalls of the stack 3004. Thus, as shown in Figure 33, the sacrificial oxide layers 3024 may be vertically inserted between the substrate 3001 and the lowest of the first nanostructures 3006, between adjacent first nanostructures 3006, between the top of the first nanostructure 3006 and the fifth nanostructure 3014, between the fifth nanostructure 3014 and the bottom of the third nanostructure 3010, or between adjacent third nanostructures 3010.

[0136] Corresponding to operation 2910 in Figures 29A to 29B, Figure 34 is a cross-sectional view of the CFET structure 3000 in which the sacrificial oxide layer 3024 is laterally recessed at one of the various manufacturing stages. The cross-sectional view of Figure 34 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0137] As shown in the figure, a "pull-back" process is used to remove (e.g., etch) individual end portions of each element in the sacrificial oxide layer 3024, thereby pulling each element back from the sacrificial oxide layer 3024 by a pull-back distance. For example, the pull-back process may include an isotropic etching process using hydrofluoric acid (HF) gas, which etches silicon oxide without attacking Si or SiGe with a higher Ge content (e.g., Si1-yGey). Thus, nanostructures 3006 (Si), 3010 (Si), and 3014 (Si1-yGey) remain substantially intact during this process, and a plurality of grooves 3025 can be formed, each groove extending inward from the source / drain groove 3020.

[0138] Corresponding to operation 2912 in Figures 29A to 29B, Figure 35 is a cross-sectional view of the CFET structure 3000 including multiple internal spacers 3026 at one of the different manufacturing stages. The cross-sectional view of Figure 35 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0139] The internal spacer 3026 can be formed by filling the groove 3025 with a dielectric material. For example, the internal spacer 3026 can be deposited using, for example, a conformal deposition process and subsequent isotropic or anisotropic etching back to remove excess spacer material on the sidewalls of the stack 3004. The dielectric material used to form the internal spacer 3026 includes silicon nitride, boron silicon carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers of transistors (e.g., a dielectric material having a dielectric constant k less than about 5).

[0140] Corresponding to operation 2914 in Figures 29A to 29B, Figure 36 is a cross-sectional view of the CFET structure 3000 in one of the various manufacturing stages, in which the fifth nanometer structure 3014 has been removed. The cross-sectional view of Figure 36 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0141] After the internal spacer 3026 is formed, the fifth nanostructure 3014 can be selectively removed using an isotropic etching process that etches Si1-yGey without attacking Si. In this way, the first nanostructure 3006 (Si) and the third nanostructure 3010 (Si) remain substantially intact, the fifth nanostructure 3014 (Si1-yGey) can be completely removed, and the remainder of the sacrificial oxide layer 3024 can be retained under the protection of the internal spacer 3026.

[0142] Corresponding to operation 2916 in Figures 29A to 29B, Figure 37 is a cross-sectional view of the CFET structure 3000 including the dielectric layer 3030 at one of the various manufacturing stages. The cross-sectional view in Figure 37 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0143] After the fifth nanostructure 3014 is removed, a space is formed between the lower portion 3004-1 and the upper portion 3004-2. A dielectric layer 3030 can be formed by filling this space with a dielectric material. The dielectric material used to form the dielectric layer 3030 includes silicon nitride, boron silicon carbonitride, silicon carbonitride, silicon oxynitride, or any other type of dielectric material suitable for forming an insulating structure of a transistor (e.g., a dielectric material having a dielectric constant k less than about 5).

[0144] Corresponding to operation 2918 in Figure 35, Figure 38 is a cross-sectional view of the CFET structure 3000, which includes a plurality of first epitaxial structures 3032 and a plurality of second epitaxial structures 3034, at one of the various manufacturing stages. The cross-sectional view of Figure 38 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0145] As shown in the figure, a pair of first epitaxial structures 3032 are respectively coupled to the ends of each of the first nanostructures 3006; a pair of second epitaxial structures 3034 are respectively coupled to the ends of each of the third nanostructures 3010. The first epitaxial structures 3032 can be formed via a first epitaxial growth process, followed by a second epitaxial growth process for forming the second epitaxial structures 3034. Further, one or more dielectric layers 3030 can be formed between the first epitaxial growth process and the second epitaxial growth process to electrically isolate the first epitaxial structure 3032 and the second epitaxial structure 3034. Each of the first and second epitaxial growth processes may include selective epitaxial growth (SEG), CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. Specifically, the first epitaxial structure 3032 may be grown from the first nanostructure 3006, and the second epitaxial structure 3034 may be grown from the third nanostructure 3010.

[0146] The first epitaxial structure 3032 and the second epitaxial structure 3034 may each include silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material, or combinations thereof. Furthermore, in-situ doping (ISD) may be applied during the formation of each of the first epitaxial structure 3032 and the second epitaxial structure 3034. For example, the first epitaxial structure 3032 may be doped by implanting a p-type dopant (e.g., boron (B)); the second epitaxial structure 3034 may be doped by implanting an n-type dopant (e.g., arsenic (As), phosphorus (P)). In some embodiments, the first epitaxial structure 3032 may be coupled to each of the first nanostructures 3006 via a lightly doped region 3033 (e.g., SiGeB); the second epitaxial structure 3034 may be coupled to each of the third nanostructures 3010 via a lightly doped region 3035 (e.g., SiP).

[0147] Corresponding to operation 2920 in Figures 29A to 29B, Figure 39 is a cross-sectional view of the CFET structure 3000, including the first active gate structure 3042 and the second active gate structure 3044, at one of the various manufacturing stages. The cross-sectional view of Figure 39 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0148] As shown in the figure, a first active gate structure 3042 surrounds each of the first nanostructures 3006; a second active gate structure 3044 surrounds each of the third nanostructures 3010. To form the first active gate structure 3042 and the second active gate structure 3044, the remaining portions of the dummy gate structure 3002 and the sacrificial oxide layer 3024 are removed. Thus, a first gate trench exposing each of the first nanostructures 3006 can be formed in the lower portion 3004-1 (e.g., the first layer); and a second gate trench exposing each of the third nanostructures 3010 can be formed in the upper portion 3004-2 (e.g., the second layer). Next, a first active gate structure 3042 can be formed in the first gate trench to cover each of the first nanostructures 3006; a second active gate structure 3044 can be formed in the second gate trench to cover each of the third nanostructures 3010.

[0149] In some embodiments, the first active gate structure 3042 may include a first gate dielectric and a first gate metal; the second active gate structure 3044 may include a second gate dielectric and a second gate metal. The first / second gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Examples of high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb, and combinations thereof. The first / second gate dielectric may include a stack of multiple high-k dielectric materials. The first gate metal may include one or more p-type work function metals, which may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof; the second gate metal may include one or more n-type work function metals, which may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0150] Corresponding to operation 2922 in Figures 29A to 29B, Figure 40 is a cross-sectional view of the CFET structure 3000, including the power supply structure 3050, at one of the various manufacturing stages. The cross-sectional view in Figure 40 is cut along the longitudinal direction (e.g., the Y direction mentioned above) of the gate structure of the CFET structure 3000.

[0151] As shown in the figure, the power supply structure 3050 is used to divide the first active gate structure 3042 into gate portion 3042A and gate portion 3042B, and the second active gate structure 3044 into gate portion 3044A and gate portion 3044B. Gate portion 3042A and gate portion 3042B are separated from each other along the Y direction, and gate portion 3044A and gate portion 3044B are also separated from each other along the Y direction. Further, the power supply structure 3050 is electrically isolated from the separated gate portions, such as gate portion 3042A and gate portion 3042B, and gate portion 3044A and gate portion 3044B, by a dielectric structure 3052.

[0152] In some embodiments, power supply structure 3050 may correspond to wall structure 244 / wall structure 344, and dielectric structure 3052 may correspond to dielectric structure 242 / dielectric structure 342 (Figures 2 to 5). Thus, gate portion 3042A and gate portion 3042B may correspond to gate portion 230A and gate portion 230B or gate portion 240A and gate portion 240B, respectively, and gate portion 3044A and gate portion 3044B may correspond to gate portion 330A and gate portion 330B or gate portion 340A and gate portion 340B, respectively. In some other embodiments, power supply structure 3050 may correspond to via structure 644A / via structure 744A or via structure 644B / via structure 744B, and dielectric structure 3052 may correspond to dielectric structure 642 / dielectric structure 742 (Figures 6 to 9). Thus, gate portions 3042A and 3042B can correspond to gate portions 630A and 630B or gate portions 640A and 640B, respectively, and gate portions 3044A and 3044B can correspond to gate portions 730A and 730B or gate portions 740A and 740B, respectively.

[0153] To form the power supply structure 3050, the intermediate portions of the first active gate structure 3042 and the second active gate structure 3044 can be removed following the aforementioned cutting patterns (e.g., cutting pattern 242 / cutting pattern 342, cutting pattern 642 / cutting pattern 742). For example, this intermediate portion of the first and second active gate structures is removed via at least one anisotropic etching process, thereby forming a vertical trench extending from the first layer to the second layer. Next, a dielectric material (e.g., silicon nitride) can be deposited to fill the vertical trench, followed by the deposition of a metallic material (e.g., copper) to form the power supply structure 3050. The monolithic wall structure (e.g., 244 / 344) can be self-aligned with the vertical trench (i.e., without further lithography). Dual via structures (e.g., via structure 644A / via structure 744A and via structure 644B / via structure 744B) can be formed via another lithography process. For example, after depositing dielectric material into vertical trenches, a lithography process can be performed to form a pair of vertical trenches extending through the dielectric material, followed by the deposition of metallic material.

[0154] After forming the power supply structure 3050, at least two p-type transistors can be formed at the first level and on opposite sides of the power supply structure 3050, and at least two n-type transistors can be formed at the second level and on opposite sides of the power supply structure 3050. The p-type transistors can be operably formed based on a first nanostructure 3006, a gate portion 3042A or a gate portion 3042B, and a pair of first epitaxial structures 3032. The n-type transistors can be operably formed based on a third nanostructure 3010, a gate portion 3044A or a gate portion 3044B, and a pair of second epitaxial structures 3034.

[0155] Corresponding to operation 2924 in Figures 29A to 29B, Figure 41 is a cross-sectional view of the CFET structure 3000, including the first contact structure 3060 and the second contact structure 3070, at one of the various manufacturing stages. The cross-sectional view of Figure 41 is cut along the longitudinal direction (e.g., the X direction mentioned above) of the active region of the CFET structure 3000.

[0156] As shown in the figure, the first contact structure 3060 is coupled to a corresponding one of the first epitaxial structures 3032; the second contact structure 3070 is coupled to a corresponding one of the second epitaxial structures 3034. For example, the first contact structure 3060 may be formed under the first epitaxial structure 3032; the second contact structure 3070 may be formed on the second epitaxial structure 3034. In another example, the first contact structure 3060 may surround the first epitaxial structure 3032; the second contact structure 3070 may surround the second epitaxial structure 3034. In some embodiments, the first contact structure 3060 and the second contact structure 3070 may each be configured as MD, and as described above, they may include titanium, aluminum, nickel, tungsten, tantalum, or other suitable metallic materials.

[0157] Figures 42 and 43 illustrate layouts 4200 and 4300, respectively, according to some embodiments, which can be used together to form a pair of memory cells 100 configured with a CFET structure having an embedded power structure (Figure 1). The CFET structure may include a plurality of first transistors disposed at a first layer on the front side of the substrate and a plurality of second transistors disposed at a second upper layer on the front side of the substrate. In some embodiments, each of these first and second transistors is configured as a GAA FET, wherein the first and second transistors have opposite conductivity types. In some other embodiments, each of the first and second transistors may be formed as other types of transistor structures, while still within the scope of this disclosure.

[0158] As shown in Figures 42 and 43, each of layouts 4200 and 4300 may include a cell boundary 4201 defining a physical region of the memory cell 100. The embedded power structure may be formed as an integral wall structure extending vertically from a first level to a second level. Further, when viewed from above, this embedded wall structure may be disposed along the cell boundary 201 of the memory cell 100. For example, the wall structure may extend laterally along one of the edges of the cell boundary 201, wherein a transistor is disposed on one (inner) side of that edge.

[0159] Generally, layouts 4200 and 4300 may include a number of patterns configured to form individual structures; therefore, in the following discussion, such patterns in the disclosed layouts are referred to herein as structures to be formed. For example, layout 4200 includes a pattern for forming a structure in a first transistor at a first layer on the front side; layout 4300 includes a pattern for forming a structure in a second transistor at a second layer on the front side. Further, layout 4200 includes a pattern for forming contact / via / interconnect structures disposed on the rear side of the substrate (e.g., at a first layer on the rear side); layout 4300 includes a pattern for forming via / interconnect structures at a third layer on the front side (e.g., above a second layer). It should be understood that layouts 4200 and 4300 have been simplified for illustrative purposes and may therefore include any of a variety of other patterns while still within the scope of this disclosure.

[0160] Referring first to Figure 42, layout 4200 may include patterns for forming active regions 4210 and 4220, and gate structures 4230, 4232, 4234, and 4236, respectively. Active regions 4210 and 4220 may extend in the X direction; gate structures 4230 to 4236 may extend in the Y direction. Each of active regions 4210 and 4220 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 4230 to 4236 may be formed as extending in the Y direction across active regions 4210 and 4220. Layout 4200 may further include a plurality of cutting patterns, such as cutting pattern 4261, cutting pattern 4262, and cutting pattern 4263, each cutting pattern extending along the X direction across gate structures 4230 to 4236. Cutting patterns 4261 to 4263 can each be used to form a dielectric structure, thereby dividing gate structures 4230 to 4236 into separate gate portions. For example, as shown in Figure 42, cutting patterns 4261 to 4263 can divide gate structures 4230, 4232, 4234, and 4236 into gate portions 4230A and 4230B, gate portions 4232A and 4232B, gate portions 4234A and 4234B, and gate portions 4236A and 4236B, respectively.

[0161] Referring now to Figure 43, layout 4300 may include patterns for forming active regions 4310 and 4320, and gate structures 4330, 4332, 4334, and 4336, respectively. Active regions 4310 and 4320 may extend in the X direction; gate structures 4330 to 4336 may extend in the Y direction. Each of active regions 4310 and 4320 may be formed as a fin structure or a stacked structure extending along the X direction, and each of gate structures 4330 to 4336 may be formed as extending in the Y direction across active regions 4310 and 4320. Layout 4300 may further include a plurality of cutting patterns, such as cutting pattern 4361, cutting pattern 4362, and cutting pattern 4363, each cutting pattern extending along the X direction across gate structures 4330 to 4336. Cutting patterns 4361 to 4363 can each be used to form a dielectric structure, thereby dividing gate structures 4330 to 4336 into separate gate portions. For example, as shown in Figure 43, cutting patterns 4361 to 4363 can divide gate structures 4330, 4332, 4334, and 4336 into gate portions 4330A and 4330B, gate portions 4332A and 4332B, gate portions 4334A and 4334B, and gate portions 4336A and 4336B, respectively.

[0162] In some embodiments, active regions 4210 and 4310 are perpendicularly aligned to each other, active regions 4220 and 4320 are perpendicularly aligned to each other, gate structures 4230 and 4330 are perpendicularly aligned to each other, gate structures 4232 and 4332 are perpendicularly aligned to each other, gate structures 4234 and 4334 are perpendicularly aligned to each other, gate structures 4236 and 4336 are perpendicularly aligned to each other, cutting patterns 4261 and 4361 are perpendicularly aligned to each other, cutting patterns 4262 and 4362 are perpendicularly aligned to each other, and cutting patterns 4263 and 4363 are perpendicularly aligned to each other. Furthermore, active regions 4210 and 4310 can form a single structure of solid terrain (sometimes referred to as "active region 4210 / active region 4310"), active regions 4220 and 4320 can form a single structure of solid terrain (sometimes referred to as "active region 4220 / active region 4320"), and gate structures 4230 and 4330 can form a single structure of solid terrain (sometimes referred to as "gate structure 4230 / gate structure 4330"). Structure 4232 and gate structure 4332 can be solidified into a single structure (sometimes referred to as "gate structure 4232 / gate structure 4332"), gate structure 4234 and gate structure 4334 can be solidified into a single structure (sometimes referred to as "gate structure 4234 / gate structure 4334"), and gate structure 4236 and gate structure 4336 can be solidified into a single structure (sometimes referred to as "gate structure 4236 / gate structure 4336").

[0163] Based on the manufacturing process described in Figures 18 to 41, layouts 4200 and 4300 can be used together to form a plurality of first transistors at a first layer on the front side of the substrate and a plurality of second transistors at a second upper layer on the front side, wherein the first transistors are operably formed based on a plurality of first nanosheets and a plurality of first epitaxial structures, and the second transistors are operably formed based on a plurality of second nanosheets and a plurality of second epitaxial structures.

[0164] For example, based on layout 4200 (as shown in Figure 42), transistors PU1 and PU2 in the first memory cell 100 and transistors PU1 and PU2 in the second memory cell 100 can be formed at the first level. Based on layout 4300 (as shown in Figure 43), transistors PD1, PD2, PG1, and PG2 in the first memory cell 100 and transistors PD1, PD2, PG1, and PG2 in the second memory cell 100 can be formed at the second level. Furthermore, based on layout 4200 (Figure 42), a first dummy transistor DMY1 and a second dummy transistor DMY2 can be formed in each of the first and second memory cells 100. In some embodiments, transistors PU1 and PU2 (including transistors DMY1 and DMY2) in the first memory cell and the second memory cell 100 at the first level may have p-type conductivity, and transistors PD1, PD2, PG1 and PG2 in the first and second memory cells 100 at the second level may have n-type conductivity.

[0165] As a representative example, in Figure 42, the transistor PU1 of the first memory cell 100 (e.g., between dicing patterns 4261 and 4262) may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the first nanosheet in the active region 4210, the gate portion 4232A, and a subset of the first epitaxial structure formed by the active region 4210 and disposed on the opposite side of the gate structure 4232. The transistor PU2 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the first nanosheet in the active region 4210, the gate portion 4234A, and another subset of the first epitaxial structure formed by the active region 4210 and disposed on the opposite side of the gate structure 4234. The transistor DMY1 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the first nanosheet in the active region 4210, the gate portion 4230A, and another subset of the first epitaxial structure formed by the active region 4210 and disposed on the opposite side of the gate structure 4230. The transistor DMY2 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the first nanosheet in the active region 4210, the gate portion 4236A, and another subset of the first epitaxial structure formed by the active region 4210 and disposed on the opposite side of the gate structure 4236.

[0166] As another representative example, in Figure 43, the transistor PD1 of the first memory cell 100 (e.g., between dicing patterns 4361 and 4362) may include its channel, gate terminal, and source / drain terminal, which are respectively formed by a subset of the second nanosheet in the active region 4310, the gate portion 4332A, and a subset of the second epitaxial structure formed by the active region 4310 and disposed on the opposite side of the gate structure 4332. The transistor PG1 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the second nanosheet in the active region 4310, the gate portion 4330A, and another subset of the second epitaxial structure formed by the active region 4310 and disposed on the opposite side of the gate structure 4330. The transistor PD2 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the second nanosheet in the active region 4310, the gate portion 4334A, and another subset of the second epitaxial structure formed by the active region 4310 and disposed on the opposite side of the gate structure 4334. The transistor PG2 of the first memory cell 100 may include its channel, gate terminal, and source / drain terminal, which are respectively formed by another subset of the second nanosheet in the active region 4310, the gate portion 4336A, and another subset of the second epitaxial structure formed by the active region 4310 and disposed on the opposite side of the gate structure 4336.

[0167] Referring again to Figure 42, layout 4200 may further include patterns for forming source / drain contact structures (MD) 4240, 4242, 4244, 4246, 4248, 4250, and 4252, respectively. Similarly, in Figure 43, layout 4300 may further include patterns for forming source / drain contact structures (MDs) 4340, 4342, 4344, 4346, 4348, 4350, and 4352, respectively. Each of these MDs is used to electrically connect to the source / drain terminals of the corresponding transistor.

[0168] For example, in Figure 42, MD 4240 is connected to the first source / drain terminal of transistor DMY1 of the first memory cell 100 and the first source / drain terminal of transistor DMY2 of the second memory cell 100; MD 4242 is connected to the second source / drain terminal of transistor DMY1 of the first memory cell 100 and the first source / drain terminal of transistor PU1; MD 4244 is connected to the second source / drain terminal of transistor DMY1 of the second memory cell 100 and the first source / drain terminal of transistor PU1; MD 4246 is connected to the second source / drain terminal of transistor PU1 of the first memory cell 100 and the first source / drain terminal of transistor PU2, and the second source / drain terminal of transistor PU1 of the second memory cell 100 and the first source / drain terminal of transistor PU2; MD MD 4248 is connected to the second source / drain terminal of transistor PU2 and the first source / drain terminal of transistor DMY2 in the first memory unit 100; MD 4250 is connected to the second source / drain terminal of transistor PU2 and the first source / drain terminal of transistor DMY2 in the second memory unit 100; MD 4252 is connected to the second source / drain terminal of transistor DMY2 and the second source / drain terminal of transistor DMY1 in the second memory unit 100.

[0169] In Figure 43, MD 4340 is connected to the first source / drain terminal of transistor PG1 in the first memory cell 100 and the first source / drain terminal of transistor PG1 in the second memory cell 100; MD 4342 is connected to the second source / drain terminal of transistor PG1 in the first memory cell 100 and the first source / drain terminal of transistor PD1; MD 4344 is connected to the second source / drain terminal of transistor PG1 in the second memory cell 100 and the first source / drain terminal of transistor PD1; MD 4346 is connected to the second source / drain terminal of transistor PD1 in the first memory cell 100 and the first source / drain terminal of transistor PD2, and the second source / drain terminal of transistor PD1 in the second memory cell 100 and the first source / drain terminal of transistor PD2; MD MD 4348 is connected to the second source / drain terminal of transistor PD2 and the first source / drain terminal of transistor PG2 in the first memory cell 100; MD 4350 is connected to the second source / drain terminal of transistor PD2 and the first source / drain terminal of transistor PG2 in the second memory cell 100; MD 4352 is connected to the second source / drain terminal of transistor PG2 in the first memory cell 100 and the second source / drain terminal of transistor PG2 in the second memory cell 100.

[0170] In some embodiments, layouts 4200 and 4300 each include a pair of patterns for forming power supply structures 4280 and 4282, respectively. Power supply structure 4280 may extend along one of the edges of cell boundary 4201 in the X direction, and power supply structure 4282 may extend along the other edge of cell boundary 4201 in the X direction. Power supply structures 4282 and 4283 may extend vertically through the first and second layers and be used to carry the ground voltage VSS. For example, power supply structures 4280 and 4282 may be formed at the second layer below (coupled to) MD 4346, extending downward to the first layer, and formed above (coupled to) MD 4240 and MD 4252. As shown in Figures 44 and 45 below, a plurality of MO tracks formed above the second front layer can be used to carry the ground voltage VSS. Thus, the ground voltage VSS can be carried "within" the cell boundary, or without additional tap units.

[0171] Figure 44 illustrates a layout 4400 (as shown in Figures 42 and 43) that can be used to form a plurality of front metal tracks disposed above the first memory cell and the second memory cell 100 according to some embodiments, and Figure 45 illustrates a layout 4500 (as shown in Figures 42 and 43) that can be used to form a plurality of rear metal tracks disposed below the first and third memory cells 100. It should be understood that the layouts in Figures 44 and 45 are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0172] Layout 4400 refers to the arrangement of a plurality of M0 tracks 4402, M0 track 4404, M0 track 4406, M0 track 4408, and M0 track 4410 relative to the cell boundary 4201, wherein M0 tracks 4402, M0 track 4406, and M0 track 4410 are used together to carry the ground voltage VSS of the first memory cell and the second memory cell 100, M0 track 4404 is configured as the BL of the first memory cell and the second memory cell 100, and M0 track 4408 is configured as the BLB of the first memory cell and the second memory cell 100. In some embodiments, these M0 tracks may extend along the X direction. M0 rails 4402, 4406, and 4410 can be coupled to MD 4436 via VD 4411, VD 4413, and VD 4415 (also shown in Figure 43), respectively; M0 rail 4402 can be coupled to MD 4340 via VD 4417 (as shown in Figure 43); and M0 rail 4408 can be coupled to MD 4352 via VD 4419 (also shown in Figure 43).

[0173] Layout 4500 refers to the arrangement of a plurality of BM0 tracks 4502, BM0 track 4504, BM0 track 4506, BM0 track 4508, BM0 track 4510, BM0 track 4512, BM0 track 4514 relative to cell boundary 4201. BM0 track 4502 is used to carry the supply voltage VDD of the first memory cell and the second memory cell 100. BM0 track 4504 is configured as the WL of the first memory cell 100, BM0 track 4506 is configured as the WL of the second memory cell 100, BM0 tracks 4508 to BM0 track 4510 are configured as the internal contact structure of the first memory cell 100, and BM0 tracks 4512 to BM0 track 4514 are configured as the internal contact structure of the second memory cell 100. In some embodiments, these BM0 tracks may extend along the X direction. BM0 track 4502 can be coupled to MD 4246 via BVD 4515 (as shown in Figure 42); BM0 track 4504 can be coupled to gate portion 4230A and gate portion 4236A via BVG 4517 and 4519 (also shown in Figure 42), respectively; BM0 track 4506 can be coupled to gate portion 4230B and gate portion 4236B via BVG 4521 and BVG 4523 (also shown in Figure 42), respectively. BM0 track 4508 can be coupled to MD 4242 and gate portion 4234A via BVD 4525 and BVG 4527 (also shown in Figure 42); BM0 track 4510 can be coupled to MD 4248 and gate portion 4232A via BVD 4531 and BVG 4529 (also shown in Figure 42); BM0 track 4514 can be coupled to MD 4244 and gate portion 4234B via BVD 4535 and BVG 4537 (also shown in Figure 42); BM0 track 4512 can be coupled to MD 4520 and gate portion 4232B via BVD 4541 and BVG 4539 (also shown in Figure 42).

[0174] In one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a substrate having a first side and a second side opposite to each other; a first transistor and a second transistor having first conductivity at a first layer on the first side of the substrate; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor having second conductivity at a second layer on the first side of the substrate and above the first layer; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side of the substrate, wherein the first interconnect structure and the second interconnect structure are each used to carry a supply voltage, and the third interconnect structure and the fourth interconnect structure are each used to carry a ground voltage; and a power supply structure extending vertically through the first layer and the second layer, and used to electrically couple the source / drain terminals of the third transistor and the source / drain terminals of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively. When viewed from above, the power supply structure is inserted between the fifth and fourth transistors along the first lateral direction, and between the third and sixth transistors along the first lateral direction.

[0175] In some embodiments, the device further includes: a first dummy transistor disposed next to the first transistor along a second lateral direction perpendicular to the first lateral direction, and having source / drain terminals replaced by a first isolation structure; and a second dummy transistor disposed next to the second transistor along a second lateral direction, and having source / drain terminals replaced by a second isolation structure.

[0176] In some embodiments, the first dummy transistor and the second dummy transistor each have a first conductivity.

[0177] In some embodiments, the device further includes: a first contact structure electrically connected to the source / drain terminal of a third transistor; a second contact structure electrically connected to the source / drain terminal of a fourth transistor; a third contact structure vertically disposed below the first isolation structure and electrically connected to the third interconnect structure; and a fourth contact structure vertically disposed below the second isolation structure and electrically connected to the fourth interconnect structure.

[0178] In some embodiments, the power supply structure is formed as an integral wall structure, which is used to connect the first contact structure and the second contact structure to the third contact structure and the fourth contact structure.

[0179] In some embodiments, the power supply structure is formed as a first through-hole structure and a second through-hole structure, the first through-hole structure being used to connect the first contact structure to the third contact structure, and the second through-hole structure being used to connect the second contact structure to the fourth contact structure.

[0180] In some embodiments, each of the first to fourth interconnect structures extends along a second lateral direction perpendicular to the first lateral direction.

[0181] In some embodiments, the first interconnect structure and the third interconnect structure are aligned along a second lateral direction, and the second interconnect structure and the fourth interconnect structure are aligned along a second lateral direction.

[0182] In some embodiments, the first interconnect structure and the third interconnect structure are disposed opposite to the power supply structure and the first transistor along a first lateral direction, and the second interconnect structure and the fourth interconnect structure are disposed opposite to the power supply structure and the second transistor along a first lateral direction.

[0183] In some embodiments, the first to sixth transistors are operatively formed into static random access memory (SRAM) cells.

[0184] In another embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first active region formed on a first layer on a first side of a substrate and extending along a first lateral direction; a second active region formed on the first layer and extending along the first lateral direction; a first gate structure formed on the first layer, extending in a second lateral direction and traversing the first and second active regions; a second gate structure formed on the first layer, extending in the second lateral direction and traversing the first and second active regions; and a third active region formed on a second layer above the first layer on the first side, extending in the first lateral direction, perpendicular to and opposite the first active region. The first active region is formed at the second level, extending in the first lateral direction, perpendicularly above and aligned with the second active region; the second gate structure is formed at the second level, extending in the second lateral direction, perpendicularly above and aligned with the third active region; the third gate structure is formed at the second level, extending in the second lateral direction, perpendicularly above and aligned with the fourth active region; and the power supply structure extends perpendicularly from the first level to the second level, inserted between the first and second active regions along the second lateral direction, and inserted between the third and first active regions along the second lateral direction. The first active region and the second gate structure are operable to form a first transistor with first conductivity of the memory cell; the second active region and the first gate structure are operable to form a second transistor with second conductivity of the memory cell; the third active region and the third gate structure are operable to form a third transistor with second conductivity of the memory cell; the third active region and the fourth gate structure are operable to form a fourth transistor with second conductivity of the memory cell; the fourth active region and the third gate structure are operable to form a fifth transistor with third conductivity of the memory cell; and the fourth active region and the fourth gate structure are operable to form a sixth transistor with the fourth conductivity of the memory cell.

[0185] In some embodiments, the memory cell is a static random access memory (SRAM) cell.

[0186] In some embodiments, wherein: a first active region and a first gate structure are operably configured to form a first dummy first transistor, the source / drain terminals of the first dummy first transistor being replaced by a first isolation structure; and a second active region and a second gate structure are operably configured to form a second dummy first transistor, the source / drain terminals of the second dummy first transistor being replaced by a second isolation structure.

[0187] In some embodiments, the semiconductor device further includes: a first contact structure having at least a portion vertically disposed above and electrically connected to the source / drain terminal of a fourth transistor; a second contact structure having at least a portion vertically disposed above and electrically connected to the source / drain terminal of a fifth transistor; a third contact structure vertically disposed below the first isolation structure; and a fourth contact structure vertically disposed below the second isolation structure.

[0188] In some embodiments, the semiconductor device further includes: a first interconnect structure formed on a second side of a substrate, extending along a first lateral direction and used to carry a ground voltage, and a third contact structure coupled to the first interconnect structure; and a second interconnect structure formed on a second side of a substrate, extending along a first lateral direction and used to carry a ground voltage, and a fourth contact structure coupled to the second interconnect structure.

[0189] In some embodiments, the power supply structure is formed as an integral wall structure, which is used to connect the first contact structure and the second contact structure to the third contact structure and the fourth contact structure.

[0190] In some embodiments, the power supply structure is formed as a first through-hole structure and a second through-hole structure, the first through-hole structure being used to connect the first contact structure to the third contact structure, and the second through-hole structure being used to connect the second contact structure to the fourth contact structure.

[0191] In another embodiment disclosed herein, a method for forming a memory device is disclosed. The method includes forming a first active region extending in a first lateral direction at a first layer on a first side of a substrate; forming a second active region extending in the first lateral direction at the first layer; forming a first gate structure extending in a second lateral direction and traversing the first and second active regions at the first layer; forming a second gate structure extending in the second lateral direction and traversing the first and second active regions at the first layer; forming a third active region extending in the first lateral direction at a second layer above the first layer on the first side; forming a fourth active region extending in the first lateral direction at the second layer; forming a third gate structure extending in the second lateral direction at the second layer; forming a fourth gate structure extending in the second lateral direction at the second layer; and forming a power supply structure extending vertically from the first layer to the second layer, the power supply structure being inserted between the first and second active regions in the second lateral direction, and also inserted between the third and first active regions in the second lateral direction. The first active region and the second gate structure are operable to form a first transistor with first conductivity of the memory cell; the second active region and the first gate structure are operable to form a second transistor with second conductivity of the memory cell; the third active region and the third gate structure are operable to form a third transistor with second conductivity of the memory cell; the third active region and the fourth gate structure are operable to form a fourth transistor with second conductivity of the memory cell; the fourth active region and its third gate structure are operable to form a fifth transistor with third conductivity of the memory cell; and the fourth active region and the fourth gate structure are operable to form a sixth transistor with fourth conductivity of the memory cell.

[0192] In some embodiments, the method further includes: forming a first interconnect structure on a second side of a substrate for carrying a ground voltage; and forming a second interconnect structure on a second side of a substrate for carrying a ground voltage; wherein the power supply structure is used to electrically couple a plurality of individual source / drain terminals of a fourth transistor and a fifth transistor to the ground voltage.

[0193] In some embodiments, the power supply structure is formed as an integral wall structure or a pair of through-hole structures.

[0194] As used herein, the terms "about" and "approximately" generally refer to a given quantity of value that may vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term "about" may refer to a given quantity of value, for example, varying within a range of 10% to 30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0195] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0196] 100: Memory Unit 101: First reference voltage 103: Second reference voltage 110: Internal node 112: Internal node 200: Layout 201: Boundary 210~220: Active Zone 230: Gate structure 230A~230B: Gate section 240: Gate structure 240A~240B: Gate section 242: Dielectric structure (cut pattern) 244: Wall Structure 246: Isolation Structure 248: Isolation Structure 250~260:MD (Source / Drain Contact Structure) 270: Internal contact structure 272: BM0 track (interconnection structure) 273: BVG (through-hole structure) 274: Internal contact structure 276: BM0 track (interconnection structure) 277: BVG (through-hole structure) 280~286: BM0 track (interconnection structure) 287~289: BVD (through-hole structure) 291~293: BVD (through-hole structure) 300: Layout 310~320: Active Zone 330: Gate structure 330A~330B: Gate section 340: Gate structure 340A~340B: Gate section 342: Dielectric structure (cut pattern) 344: Wall Structure 350~360:MD (Source / Drain Contact Structure) 362~364: MDLI (Internal Contact Structure) 370~376: M0 track (interconnection structure) 377~379: VG (through-hole structure) 381~383: VD (through-hole structure) 400: Semiconductor Device 600: Layout 601: Boundary 610~620: Active Zone 630: Gate structure 630A~630B: Gate section 640: Gate structure 640A~640B: Gate section 642: Dielectric structure (cut pattern) 644A~644B: Through-hole structure 646~648: Isolation Structure 650~660: MD (Source / Drain Contact Structure) 670: Internal contact structure 672: BM0 track (interconnection structure) 673: BVG (through-hole structure) 674: Internal contact structure 676: BM0 track (interconnection structure) 677: BVG (through-hole structure) 680~686: BM0 track (interconnection structure) 687~693: BVD (through-hole structure) 700: Layout 710: Active Zone 720: Active Zone 730: Gate structure 730A~730B: Gate section 740: Gate structure 740A~740B: Gate section 742: Dielectric structure (cut pattern) 744A: Through-hole structure 744B: Through-hole structure 750~760:MD (Source / Drain Contact Structure) 762~764: MDLI (Internal Contact Structure) 770~776: M0 track (interconnection structure) 777~779: VG (through-hole structure) 781~783: VD (through-hole structure) 800: Semiconductor Device 1402: M0 orbit (first WL) 1404: M0 orbital (BL) 1406: M0 orbital (BLB) 1408: M0 orbit (second WL) 1410: M1 orbit 1420: Through-hole structure 1502: M0 orbit (first WL) 1504: M0 orbital (BL) 1506: M0 orbit (first WL) 1508: M0 orbital (BLB) 1510: M1 orbit 1520: Through-hole structure 1602: BM0 rail (first power rail) 1604: BM0 rail (second power rail) 1606: BM0 rail (third power supply rail) 1608: BM0 rail (fourth power rail) 1702: BM0 rail (first power rail) 1704: BM0 rail (second power rail) 1706: BM0 rail (third power supply rail) 1708: BM0 rail (fourth power rail) 1710: BM0 rail (fifth power rail) 1712: BM0 rail (sixth power rail) 1720: BM1 orbit 1730: BM1 orbit 1800: Method 1802~1820: Operations 1900: CFET structure 1901:Substrate 1902: Virtual gate structure 1904: Stacking 1904-1: Lower Part 1904-2: Upper Part 1906: Nanostructure 1908: Nanostructure 1910: Nanostructure 1912: Nanostructure 1914: Nanostructure 1916: Gate spacer 1920: Source / Drain Groove 1924: Groove 1926: Internal spacers 1930: Dielectric layer 1932: Epitaxial Structure 1933: Lightly Doped Region 1934: Epitaxial Structure 1935: Lightly Doped Region 1936: Dielectric layer 1942: Active gate structure 1942A~1942B: Gate section 1944: Active gate structure 1944A~1944B: Gate section 1950: Power Supply Structure 1952: Dielectric Structure 1960: Contact Structure 1970: Contact Structure 2900: Method 2902~2924: Operations 3000: CFET structure 3001:Substrate 3002: Virtual gate structure 3004: Stacking 3004-1: Lower Part 3004-2: Upper Part 3006: Nanostructure 3008: Nanostructure 3010: Nanostructure 3012: Nanostructure 3014: Nanostructure 3016: Gate spacer 3020: Source / Drain Groove 3023: Space 3024: Sacrificial oxide layer 3025: Groove 3026: Internal spacers 3030: Dielectric layer 3032: Epitaxial structure 3033: Lightly Doped Region 3034: Epitaxial structure 3035: Lightly Doped Region 3042: Active gate structure 3042A~3042B: Gate section 3044: Active gate structure 3044A~3044B: Gate section 3050: Power Supply Structure 3052: Dielectric Structure 3060: Contact Structure 3070: Contact Structure 4200: Layout 4201: Boundary 4210~4220: Active Zone 4230: Gate structure 4230A~4230B: Gate section 4232: Gate structure 4232A~4232B: Gate section 4234: Gate structure 4234A~4234B: Gate section 4236: Gate structure 4236A~4236B: Gate section 4240~4252:MD (Source / Drain Contact Structure) 4261~4263: Cutting patterns 4280~4282: Power Supply Structure 4300: Layout 4310~4320: Active Zone 4330: Gate structure 4330A~4330B: Gate section 4332: Gate structure 4332A~4332B: Gate section 4334: Gate structure 4334A~4334B: Gate section 4336: Gate structure 4336A~4336B: Gate section 4340~4352:MD (Source / Drain Contact Structure) 4361~4363: Cutting patterns 4400: Layout 4402~4410: M0 orbital 4411~4419:VD 4500: Layout 4502~4514: BM0 orbital 4515:BVD 4517~4523:BVG 4525:BVD 4527:BVG 4529:BVG 4531:BVD 4535:BVD 4537:BVG 4539:BVG 4541:BVD AA: Line BB: Line DMY1: Transistor DMY2: Transistor PU1: Transistor PU2: Transistor

[0197] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a substrate having a first side and a second side opposite to each other; a first transistor and a second transistor having a first conductivity in a first layer on the first side of the substrate; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor having a second conductivity in a second layer on the first side of the substrate and above the first layer; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side of the substrate, wherein the first interconnect structure and the second interconnect structure are configured to carry a supply voltage, and the third interconnect structure and the fourth interconnect structure are configured to carry a ground voltage; and a power supply structure extending vertically through the first layer and the second layer, and used to electrically couple a source / drain terminal of the third transistor and a source / drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively. When viewed from above, the power supply structure is inserted between the fifth and fourth transistors along a first lateral direction, and also between the third and sixth transistors along the first lateral direction.

2. The semiconductor device as claimed in claim 1, further comprising: a first dummy transistor disposed next to the first transistor along a second lateral direction perpendicular to the first lateral direction, and having a source / drain terminal replaced by a first isolation structure; and a second dummy transistor disposed next to the second transistor along the second lateral direction, and having a source / drain terminal replaced by a second isolation structure.

3. The semiconductor device as claimed in claim 2, further comprising: a first contact structure electrically connected to the source / drain terminal of the third transistor; a second contact structure electrically connected to the source / drain terminal of the fourth transistor; a third contact structure vertically disposed below the first isolation structure and electrically connected to the third interconnect structure; and a fourth contact structure vertically disposed below the second isolation structure and electrically connected to the fourth interconnect structure.

4. The semiconductor device as claimed in claim 3, wherein the power supply structure is formed as a monolithic wall structure for connecting the first contact structure and the second contact structure to the third contact structure and the fourth contact structure.

5. The semiconductor device as claimed in claim 3, wherein the power supply structure is formed as a first through-hole structure and a second through-hole structure, the first through-hole structure being used to connect the first contact structure to the third contact structure, and the second through-hole structure being used to connect the second contact structure to the fourth contact structure.

6. A semiconductor device comprising: a first active region formed on a first side of a substrate at a first layer and extending along a first lateral direction; a second active region formed on the first layer and extending along the first lateral direction; a first gate structure formed on the first layer, extending in a second lateral direction and traversing the first active region and the second active region; a second gate structure formed on the first layer, extending in the second lateral direction and traversing the first active region and the second active region; a third active region formed on a second layer above the first layer on the first side, extending in the first lateral direction, and perpendicularly above and aligned with the first active region; a fourth active region formed on the second layer, extending in the first lateral direction, and perpendicularly above and aligned with the second active region; and a third gate structure formed on the second layer, extending in the second lateral direction, and perpendicularly above and aligned with the third active region. A fourth gate structure is formed at the second level, extends in the second lateral direction, and is perpendicular to and aligned with the fourth active region; and a power supply structure extends perpendicularly from the first level to the second level, is inserted between the first active region and the second active region along the second lateral direction, and is inserted between the third active region and the fourth active region along the second lateral direction. The first active region and the second gate structure are operably configured to form a first transistor with a first conductivity of a memory cell; the second active region and the first gate structure are operably configured to form a second transistor with the first conductivity of the memory cell; the third active region and the third gate structure are operably configured to form a third transistor with a second conductivity of the memory cell; the third active region and the fourth gate structure are operably configured to form a fourth transistor with the second conductivity of the memory cell; the fourth active region and the third gate structure are operably configured to form a fifth transistor with the second conductivity of the memory cell; and the fourth active region and the fourth gate structure are operably configured to form a sixth transistor with the second conductivity of the memory cell.

7. The semiconductor device as claimed in claim 6, wherein: the first active region and the first gate structure are operatively configured to form a first dummy first transistor, a source / drain terminal of the first dummy first transistor being replaced by a first isolation structure; and the second active region and the second gate structure are operatively configured to form a second dummy first transistor, a source / drain terminal of the second dummy first transistor being replaced by a second isolation structure.

8. The semiconductor device as claimed in claim 7, further comprising: a first contact structure having at least a portion vertically disposed above and electrically connected to a source / drain terminal of the fourth transistor; a second contact structure having at least a portion vertically disposed above and electrically connected to a source / drain terminal of the fifth transistor; a third contact structure vertically disposed below the first isolation structure; and a fourth contact structure vertically disposed below the second isolation structure.

9. A method of forming a semiconductor device, comprising: forming a first active region extending along a first lateral direction at a first layer on a first side of a substrate; forming a second active region extending along the first lateral direction at the first layer; forming a first gate structure extending along a second lateral direction and traversing the first active region and the second active region at the first layer; forming a second gate structure extending along the second lateral direction and traversing the first active region and the second active region at the first layer; forming a third active region extending in the first lateral direction at a second layer above the first layer on the first side; forming a fourth active region extending along the first lateral direction at the second layer; and forming a third gate structure extending along the second lateral direction at the second layer. A fourth gate structure extending along the second lateral direction is formed at the second level; and a power supply structure extending vertically from the first level to the second level is formed, the power supply structure being inserted between the first active region and the second active region along the second lateral direction, and also being inserted between the third active region and the fourth active region along the second lateral direction. The first active region and the second gate structure are operably configured to form a first transistor with a first conductivity of a memory cell; the second active region and the first gate structure are operably configured to form a second transistor with the first conductivity of the memory cell; the third active region and the third gate structure are operably configured to form a third transistor with a second conductivity of the memory cell; the third active region and the fourth gate structure are operably configured to form a fourth transistor with the second conductivity of the memory cell; the fourth active region and the third gate structure are operably configured to form a fifth transistor with the second conductivity of the memory cell; and the fourth active region and the fourth gate structure are operably configured to form a sixth transistor with the second conductivity of the memory cell.

10. The method of claim 9, further comprising: forming a first interconnect structure on a second side of the substrate for carrying a ground voltage; and forming a second interconnect structure on the second side of the substrate for carrying the ground voltage; wherein the power supply structure is used to electrically couple a plurality of individual source / drain terminals of the fourth transistor and the fifth transistor to the ground voltage.

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