Semiconductor structure and method for forming semiconductor structure

Abstract

The present invention provides a semiconductor structure comprising: a device layer including a device region having a plurality of devices and a precharge circuit; a front-side wiring layer located on the front side of the device layer and including at least signal wiring connected to the device region; a power supply voltage line coupled to the device region; and a back-side wiring layer located on the back side of the device layer. The back-side wiring layer includes: a dummy power rail coupled to the precharge circuit; and a transient line capacitively, non-conductively, coupled to the dummy power rail and to the device region. The precharge circuit is configured such that the dummy power rail responds to a pulse on the transient line and experiences a voltage difference with a power supply voltage applied to the power supply voltage line.

Description

Technical Field

[0001] The present invention relates to electrical, electronic and computer technologies, and more specifically to virtual functionality (e.g., floating nodes) for integrated circuits such as memory circuits and the like. Prior Technology

[0002] Virtual functionality at lower voltages is important for circuits such as memory circuits; the use of virtual nodes is to reduce the required supply voltage of memory. When virtual nodes are formed on the front side of the wafer (i.e., in the back end of the line (BEOL) using continuous stacking of multiple wiring layers such as M1, M2, M3, M4, M5), BEOL congestion increases (due to the presence of too many wires). Furthermore, the voltage boost that can be achieved through virtual nodes is limited by the capacitance between the virtual node and the transient line to which it is capacitively coupled. Summary of the Invention

[0003] The technical principles provide a technique for floating nodes in integrated circuits. In one embodiment, an exemplary semiconductor structure includes: a device layer including a device region having a plurality of devices and a precharge circuit; a front-side wiring layer located on the front side of the device layer and including at least signal wiring connected to the device region; a power supply voltage line coupled to the device region; and a back-side wiring layer located on the back side of the device layer. The back-side wiring layer includes: a dummy power rail coupled to the precharge circuit; and a transient line capacitively, non-conductively, coupled to the dummy power rail and to the device region. The precharge circuit is configured such that the dummy power rail experiences a voltage difference with a power supply voltage applied to the power supply voltage line in response to a pulse on the transient line.

[0004] In another embodiment, another exemplary semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a precharge circuit; a power supply voltage line coupled to the device region; and a wiring layer positioned adjacent to the device layer. The wiring layer includes: a dummy power rail coupled to the precharge circuit; and a transient line capacitively, non-conductively, coupled to both the dummy power rail and the device region. The precharge circuit is configured such that the dummy power rail experiences a voltage difference from a power supply voltage applied to the power supply voltage line in response to a pulse on the transient line. The dummy power rail and the transient line are formed with finger-like conductive teeth separated by a dielectric.

[0005] In another embodiment, an exemplary method of forming a semiconductor structure includes: providing an initial structure comprising a carrier wafer, a plurality of front-side wiring layers extending outward from the carrier wafer, and a device layer extending outward from the plurality of front-side wiring layers, the device layer including a device region and a pre-charge circuit; forming a back-side transient power line on a back side of the device region, the back-side transient power line including wiring in a first metal region, wherein a first via bump extends therefrom; and forming a back-side virtual power rail on the back side of the device region. The back-side virtual power rail includes wiring in a second metal region vertically spaced from the first metal region, and the back-side virtual power rail further includes a second via bump extending therefrom. The first via bump and the second via bump extend toward each other and are finger-shaped and separated from each other by a back-side interlayer dielectric. The back-side virtual power rail is coupled to the pre-charge circuit.

[0006] In another embodiment, another exemplary semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a pre-discharge circuit; a front-side wiring layer located on the front side of the device layer and including at least signal wiring connected to the device region; and a back-side wiring layer located on the back side of the device layer. The back-side wiring layer includes: a dummy power rail coupled to the pre-discharge circuit; and a transient line capacitively, non-conductively, coupled to the dummy power rail and to the device region. The pre-discharge circuit is configured such that the dummy power rail responds to a pulse on the transient line and experiences a voltage difference from an initial ground potential.

[0007] In another example, a typical semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a pre-discharge circuit; and a wiring layer positioned adjacent to the device layer. The wiring layer includes: a dummy power rail coupled to the pre-discharge circuit; and a transient line capacitively, non-conductively, coupled to the dummy power rail and to the device region. The pre-discharge circuit is configured such that the dummy power rail responds to a pulse on the transient line and experiences a voltage difference from an initial ground potential, and the dummy power rail and the transient line form finger-like conductive teeth separated by a dielectric.

[0008] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example rather than limitation, instructions executed on a processor can facilitate actions performed by semiconductor manufacturing equipment by sending appropriate data or commands to cause or assist in the execution of an action. Even when an actor facilitates an action through entities other than those performing the action, the action is still performed by some entities or a combination of entities.

[0009] The techniques disclosed herein can provide significant and advantageous technical effects, as will be further discussed below. Features and advantages will become apparent from the following detailed description of their illustrative embodiments, which will be read in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0010] The following diagrams are presented as examples only and are not restrictive, and throughout several views, the same element symbols (when used) indicate corresponding elements, and in the views:

[0011] Figure 1 depicts an exemplary structure of one aspect of the present invention.

[0012] Figure 2 depicts a first example of a pre-charge circuit (positive boost virtual line) according to one aspect of the present invention.

[0013] Figure 3 depicts a second type of pre-charge circuit (positive boost virtual line) according to one aspect of the present invention.

[0014] Figure 4 depicts a timing diagram of a waveform according to one state of the present invention.

[0015] Figures 5 to 13 depict the steps in a first exemplary manufacturing method according to one aspect of the present invention.

[0016] Figures 14 to 26 depict steps in a second exemplary manufacturing method according to one aspect of the present invention.

[0017] Figure 27 depicts a computing environment according to one embodiment of the present invention.

[0018] Figure 28 is a flowchart of the design process used in semiconductor design and manufacturing.

[0019] Figure 29 depicts a pre-discharge circuit (negative boost virtual line) according to one state of the present invention.

[0020] It should be understood that the elements in the figures are shown for simplicity and clarity. Common and easily understood elements that may be useful or necessary in commercially viable embodiments may not be shown in order to facilitate a less obstructed observation of the illustrated embodiments. Implementation

[0021] The technical principles described herein will be understood within the context of the exemplary embodiments. Furthermore, given the teachings herein, it will be apparent to those skilled in the art that numerous modifications can be made to the embodiments shown within the scope of the claims. That is, no limitation is intended or should be inferred regarding the embodiments shown and described herein.

[0022] Given the discussion herein (referencing the figures discussed below for reference characters), it should be understood that, in one embodiment, the exemplary semiconductor structure includes a device layer 1407, which includes a device region 508Z having a plurality of devices and a pre-charge circuit (e.g., element 301Z). It also includes: a front wiring layer (lower BEOL layer 1408), (further BEOL layers 1411), located on the front side of the device layer and including at least signal wiring connected to the device region; and power supply voltage lines coupled to the device region (represented by any of the metals other than dummy power rails and transient lines). A back wiring layer is located on the back side of the device layer and includes a dummy power rail 1425 coupled to the pre-charge circuit (it should be noted that, as those skilled in the art will understand from the background, coupling generally means conductive coupling, except for capacitive coupling between element 1425 and element 1419A). Transient line 1419A is capacitively, non-conductively, coupled to the dummy power rail and coupled to the device region. The precharge circuit is configured so that the virtual power rail responds to pulses on the transient line and experiences a voltage difference with the supply voltage applied to the supply voltage line. Technical advantages include achieving logic / memory functionality at low voltages by using coupling capacitors to form floating nodes. Forming on the back side provides area savings due to increased density. One or more embodiments overcome the need for separate voltage suppliers / voltage regulators / voltage converters; for example, boosting positive or negative voltages to bit lines in a memory array, where the device region includes the memory array.

[0023] Referring to the vias extending from elements 1419A and 1425 with BILD therebetween, in one or more embodiments, the virtual power rail and transient line are formed with finger-like conductive teeth separated by dielectric. Technical advantages include enhanced coupling capacitance by forming finger-like vias between the virtual power rail and the transient supply line.

[0024] In some cases, the virtual power rails and transient lines are vertically spaced apart, and the finger-shaped conductive teeth are vertical through-holes. Technical advantages include enhanced coupling capacitance by forming finger-shaped through-holes with an easily manufactured structure between the virtual power rails and transient supply lines.

[0025] Referring to Figure 2, in some cases, the precharge circuit includes a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail. Technical advantages include ease of manufacture and suitability for a wide range of operating frequencies.

[0026] At least some of these configurations further include a controller and power supply 303 configured to supply input pulse waveforms to the transient supply line and the gate of the p-type field-effect transistor. Technical advantages include the operation of the control circuitry to achieve the indicated benefits.

[0027] In some situations, the input pulse waveforms are in phase and the voltage difference is positive. The technical advantage includes providing a positive voltage boost to the circuit when helpful.

[0028] On the other hand, in some situations, the input pulse waveform is out of phase and the voltage difference is negative. Technical advantages include providing a negative voltage to the circuit, which can be "tweaked" when necessary.

[0029] Referring to Figure 3, in some cases, the precharge circuit includes: a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail; and an n-type field-effect transistor having a first drain-source terminal coupled to the first drain-source terminal of the p-type field-effect transistor, a gate coupled to the gate of the p-type field-effect transistor, and a second drain-source terminal coupled to the second drain-source terminal of the p-type field-effect transistor. Technical advantages include that the precharge circuit is easy to manufacture and provides a higher boost voltage, but may be more suitable for higher frequency / shorter cycle circuits.

[0030] At least some of these configurations further include controllers and power supplies configured to supply input pulse waveforms to transient supply lines and the gates of p-type and n-type field-effect transistors. Technical advantages include the operation of the control circuitry to achieve the indicated benefits.

[0031] In some situations, the input pulse waveforms are in phase and the voltage difference is positive. The technical advantage includes providing a positive voltage boost to the circuit when helpful.

[0032] On the other hand, in some situations, the input pulse waveform is out of phase and the voltage difference is negative. Technical advantages include providing a negative voltage to the circuit for "fine-tuning" where helpful.

[0033] In another embodiment, another exemplary semiconductor structure includes a device layer having dielectric 509, a device region 508 having a plurality of devices, and a pre-charge circuit (element 301 generally represents the pre-charge circuit and the pre-discharge circuit). A supply voltage line is coupled to the device region (represented by any of the metals other than the virtual power rail and the transient line). A wiring layer is positioned adjacent to the device layer and includes a virtual power rail 585 coupled to the pre-charge circuit and a transient line (e.g., M2 with teeth 589) capacitively and non-conductively coupled to the virtual power rail and coupled to the device region. The pre-charge circuit is configured such that the virtual power rail responds to pulses on the transient line and experiences a voltage difference with the supply voltage applied to the supply voltage line, and the virtual power rail and the transient line are formed with forked conductive teeth separated by the dielectric (teeth 585 and teeth 589 separated by ILD 595B). Technical advantages include achieving logic / memory functionality at low voltages by using coupling capacitors to form floating nodes; overcoming the need for separate voltage suppliers / voltage regulators / voltage converters; providing positive or negative voltage boosts to bit lines in the memory array, where the device area includes the memory array; and enhancing coupling capacitance by forming finger-shaped vias between virtual power rails and transient supply lines.

[0034] In some cases, the virtual power rails and transient lines are vertically spaced apart, and the finger-shaped conductive teeth include vertical through-holes. Technical advantages include enhanced coupling capacitance by forming finger-shaped through-holes with an easily manufactured structure between the virtual power rails and transient supply lines.

[0035] Referring to Figure 2, in some cases, the precharge circuit includes a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail. Technical advantages include ease of manufacture and suitability for a wide range of operating frequencies.

[0036] Some of these configurations further include a controller and power supply 303 configured to supply input pulse waveforms to the transient supply line and the gate of the p-type field-effect transistor. Technical advantages include the operation of the control circuitry to achieve the indicated benefits.

[0037] In some such situations, the input pulse waveforms are in phase and the voltage difference is positive. The technical advantage includes providing a positive voltage boost to the circuit when helpful.

[0038] On the other hand, in other such situations, the input pulse waveforms are out of phase and the voltage difference is negative. Technical advantages include providing a negative voltage "fine-tuning" to the circuit where helpful.

[0039] Referring to Figure 3, in some cases, the precharge circuit includes: a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail; and an n-type field-effect transistor having a first drain-source terminal coupled to the first drain-source terminal of the p-type field-effect transistor, a gate coupled to the gate of the p-type field-effect transistor, and a second drain-source terminal coupled to the second drain-source terminal of the p-type field-effect transistor. Technical advantages include that the precharge circuit is easy to manufacture and provides a higher boost voltage, but may be more suitable for higher frequency / shorter cycle circuits.

[0040] Some of these configurations further include a controller and power supply 303 configured to supply input pulse waveforms to transient supply lines and the gates of p-type and n-type field-effect transistors. Technical advantages include the operation of the control circuitry to achieve the indicated benefits.

[0041] In some such situations, the input pulse waveforms are in phase and the voltage difference is positive, or the input pulse waveforms are out of phase and the voltage difference is negative. Technical advantages include, where helpful, providing a positive voltage boost to the circuit, or, where helpful, providing a negative voltage "fine-tuning" to the circuit, depending on the specific circumstances.

[0042] In another example, referring to Figures 14 through 26, an exemplary method for forming a semiconductor structure is considered. Referring to Figure 18, an initial structure is provided, comprising a carrier wafer, a plurality of front-side wiring layers extending outward from the carrier wafer, and a device layer extending outward from the plurality of front-side wiring layers, the device layer including a device region and pre-charge circuitry. Referring to Figures 19 through 23, another step includes forming back-side transient power lines on the back side of the device region. The back-side transient power lines include wiring in a first metal region, from which a first via bump extends. Referring to Figures 24 through 26, yet another step includes forming a back-side virtual power rail on the back side of the device region. The back-side virtual power rail includes wiring in a second metal region vertically spaced from the first metal region. The back-side virtual power rail further includes a second via bump extending therefrom. The first and second via bumps extend toward each other in a forked manner and are separated from each other by a back-side interlayer dielectric. The rear-side virtual power rail is coupled to the pre-charge circuit. Technical advantages include providing a structure with the advantages discussed above.

[0043] In another embodiment, referring to Figures 5 through 13, another exemplary method for forming a semiconductor structure is considered. Referring to Figure 5, an initial structure including a substrate and a device layer extending outward from the substrate is provided. The device layer includes a device region and a pre-charge circuit. Referring to Figures 6 through 8, another step includes forming a middle-of-line contact and back-end process wiring extending outward from the device layer. The back-end process wiring includes a transient power line connected to the device region via at least one of the middle-of-line contacts. Yet another step includes forming a first via bump extending from the transient power line, as shown in Figure 9. Referring to Figures 10 through 13, yet another step includes forming a virtual power rail vertically spaced from the transient power line. The virtual power rail includes a second via bump extending from it, and the first and second via bumps extend toward each other in a forked manner and are separated from each other by an interlayer dielectric. The virtual power rail is coupled to the pre-charge circuit. Technological advantages include technologies that provide structures with the advantages discussed above.

[0044] In another embodiment, the method of operating the circuitry is generally applicable to the embodiments disclosed herein, including providing a semiconductor structure. The semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a pre-charge circuit; a power supply voltage line coupled to the device region; and a wiring layer positioned adjacent to the device layer. The wiring layer includes a dummy power rail coupled to the pre-charge circuit, and a transient line capacitively and non-conductively coupled to the dummy power rail and coupled to the device region. Further steps include: applying a power supply voltage to the power supply voltage line; applying a pulse to the transient line; and using the pre-charge circuitry to cause the dummy power rail to respond to the pulse on the transient line and experience a voltage difference with the power supply voltage applied to the power supply voltage line. Technical advantages include achieving low-voltage logic / memory functionality by using coupling capacitors to form floating nodes.

[0045] In an additional configuration, referring to Figure 29, another semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a pre-discharge circuit; a front wiring layer located on the front side of the device layer and including at least signal wiring connected to the device region; and a back wiring layer located on the back side of the device layer. The back wiring layer includes a dummy power rail coupled to the pre-discharge circuit and a transient line capacitively and non-conductively coupled to the dummy power rail and coupled to the device region. The pre-discharge circuit is configured such that the dummy power rail responds to pulses on the transient line and experiences a voltage difference from the initial ground potential. For a suitable negative boost dummy line system, the technical benefits are generally similar to those discussed above for positive boost dummy lines.

[0046] In some cases, virtual power rails and transient lines are formed with forked conductive teeth separated by dielectric materials. Technical advantages include enhancing coupling capacitance in a manner largely similar to that described above.

[0047] In another additional configuration, referring to Figure 29, a further semiconductor structure includes: a device layer comprising a device region having a plurality of devices and a pre-discharge circuit; and a wiring layer positioned adjacent to the device layer and including: a dummy power rail coupled to a pre-charge circuit; and a transient line capacitively, non-conductively coupled to the dummy power rail and to the device region. The pre-discharge circuit is configured such that the dummy power rail responds to pulses on the transient line by experiencing a voltage difference from the initial ground potential, and the dummy power rail and transient line are formed with forked conductive teeth separated by a dielectric. For a suitable negative boost dummy line system, the technical benefits are generally similar to those discussed above for positive boost dummy lines.

[0048] The techniques disclosed herein can provide substantial and beneficial technical effects. Some embodiments may not have these potential advantages, and such potential advantages may not be needed in all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of the following:

[0049] The functionality of logic / memory at low voltages is achieved by using coupling capacitors to form floating nodes.

[0050] The coupling capacitance is enhanced by forming finger-shaped vias between the virtual power rail and the transient supply line.

[0051] The functionality of logic / memory at low supply voltages is achieved by using coupling capacitors.

[0052] Using through holes on the back side provides area savings for increased density.

[0053] As mentioned, virtual functionality at lower voltages is important for circuits such as memory circuits; the use of virtual nodes is to reduce the required supply voltage of memory. In one or more embodiments, the concept of a virtual node uses the spacing between two metal structures (e.g., horizontal lines and / or vertical vias) to achieve capacitive coupling.

[0054] Figure 1 depicts an exemplary structure according to one embodiment of the present invention. It should be noted that the pre-charge circuit (represented by element 301) is controlled by a suitable controller (depicted for illustration as part of a combined controller and power supply 303, but a separate controller and power (e.g., voltage) supply circuit may also be used); both elements 301 and 303 are further discussed below. Also note the virtual power rail 309. In the non-limiting example of Figure 1, the virtual power rail 309 is formed in the metal layer M2 (which may be the back side according to Figures 14 to 26, or the front side according to Figures 5 to 13). The transient line 305 can switch from VDD to ground or from ground to VDD. The pre-charge circuit, controller, and power supply 303 are schematically depicted in Figure 1. The pre-charge circuit is coupled to the virtual power rail 309 via via 313, metal lines 307 at layer M1, via 315, and via 319. The virtual power rail 309 and the transient line 305 are capacitively coupled via conductive coupling to vias 317-1 and 317-2 of the transient line 305 and vias 321-1, 321-2, and 321-3 of the virtual power rail 309. The vias 317-1, 317-2 and 321-1, 321-2, and 321-3 are interdigitated. They are capacitively coupled rather than conductively coupled by dielectric materials (such as ILD or BILD discussed and illustrated below). An additional metal layer M3 with lines 323-1, 323-2, and 323-3 extending perpendicularly to the page is also shown. It should be understood that multiple additional layers of wiring and vias may exist, and the virtual power rail 309 and the transient line 305 may be formed at different metal layers than in the example of Figure 1.

[0055] The controller of the controller and power supply 303 performs the functions as defined herein; given the teachings and descriptions of the functions herein, known power / voltage supplies and known control circuitry techniques may be used; for example, multi-cycle or pipelined, wired or microprogrammed, using any suitable family of technologies (e.g., 7 nm CMOS, 5 NM CMOS and the like). For instance, the specified functions may be individualized in the logic circuitry system described below with respect to Figure 28.

[0056] It should be understood that the capacitive coupling of the virtual power rail 309 and the transient line 305 is enhanced by providing finger-shaped vias, for example, in a zigzag manner. In a non-limiting example, vias 321-1, 321-2, and 321-3 are unlanded damascene vias, and vias 317-1 and 317-2 are unlanded subtractive vias.

[0057] Figure 2 depicts a first exemplary precharge circuit according to one embodiment of the present invention. This first exemplary precharge circuit includes a p-type field-effect transistor (PFET) 379 having a first source-drain terminal 383 connected to a fixed voltage power supply rail 395 at Vdd or VCS. The gate 385 of the PFET 379 is provided with an input waveform 397. A second source-drain terminal 381 is connected to a virtual power rail 309 through a resistor Rv 393. The virtual power rail 309 is capacitively coupled to a transient supply line 305 through a capacitor Cc 391, and in the example of Figure 2, is coupled to ground through a capacitor Cv 389. The transient supply line 305 has an applied waveform 399. Using a suitable controller and power supply, the transistor is turned on by a signal on its gate when power needs to be supplied to the line via capacitive coupling.

[0058] In this context, the "coupling" between line 305 and rail 309 means that when the transient supply line voltage rises (the transient supply line 305 has an applied voltage that fluctuates in a low-high-low-high pattern as seen at 399), the virtual power rail 309 will exhibit an upward "short-time pulse waveform interference (glitch)". This means that the virtual power rail 309 will be higher than the initial voltage (e.g., Vdd). This is desirable because a voltage higher than Vdd can be dynamically generated using the coupling between rail 309 and line 305 without applying any voltage higher than Vdd. In other words, the virtual power rail 309 can be "lifted" due to the capacitance between rail 309 and line 305.

[0059] Placing rails 309 and lines 305 on the front side of the wafer requires all signal lines, dummy lines, coupling lines, and the like to be on one side, thus causing congestion and limiting density. Advantageously, one or more embodiments overcome these limitations by using embedded signal lines on the back side; that is, back-side power and signal delivery to the floating lines.

[0060] Referring again to Figure 2, when the input signal (input waveform 397) on the gate 385 of PFET 379 is zero, the PFET is turned on, and it initializes the virtual power rail 309 to high (i.e., Vdd or VCS; Vdd is the digital supply voltage and VCS is the cell supply voltage). Any voltage applied to the first source-drain terminal 383 of PFET 379 will be reflected on the virtual power rail 309. Then, PFET 379 is turned off by applying a high voltage to its gate 385. In the example of Figure 2, the same signal applied to the transient supply line 305 (application waveform 399) is applied to the gate 385 of PFET 379, as seen at 397 (i.e., similar polarity). When the signal on gate 385 goes high, the PFET is turned off. The charge on the virtual power rail 309 remains and "floats" at Vdd or VCS, depending on the specific situation. When the voltage on the transient supply line 305 (applied waveform 399) increases from low to high, due to the capacitance Cc 391, the virtual power rail 309 experiences a "short-time pulse waveform disturbance" upward, as seen in the small plot 387. This "boosts" or "emphasizes" the voltage to the upper line by an amount of δV, reaching a level higher than Vdd or VCS. In one or more embodiments, δV is approximately 0.1 V to 0.2 V.

[0061] It is noteworthy that the polarity of the transient supply line pulse (applied waveform 399) can alternatively be 180 degrees out of phase with the pulse on the gate 385 of the PFET 379 (input waveform 397), such that instead of both waveforms starting low (0 voltage, logic zero) and changing high (Vdd or VCS, logic one), applied waveform 399 starts high and changes low. In this condition, the virtual power rail 309 experiences downward rather than upward short-time pulse waveform interference. That is, when the input waveform 397 to the PFET is in phase with the transient line pulse (applied waveform 399), a positive short-time pulse waveform interference of +δV is obtained, while when they are 180 degrees out of phase, a negative short-time pulse waveform interference of -δV is obtained. In other words, in the example depicted in Figure 2, the two sawtooth waves are in phase and provide positive short-time pulse waveform interference / boost; if they are 180 degrees out of phase, a negative short-time pulse waveform interference / boost is obtained. In other words, when the signal is in phase, the transient supply line 305 pushes the virtual power rail 309 upward through Cc, but when the signal is out of phase, it pulls the virtual power rail 309 downward through Cc.

[0062] Cc 391 is therefore the capacitance between rail 309 and line 305, which have a dielectric material (such as ILD or BILD discussed below). Determining this capacitance is typically complex because the geometry is not simply that of a parallel-plate capacitor comprising both vertical and horizontal elements. However, given the teachings herein, those skilled in the art can determine the capacitance between rail 309 and line 305 (e.g., using finite element analysis). In one or more embodiments, the vias 321-1, 321-2, 321-3 coupled to the virtual power rail 309 are offset from the vias 317-1, 317-2 coupled to the transient line 305 to adjust Cc. Any of the vias can be a conventional via shaped like a coffee cup (truncated cone), or a line or slot (such as a component with a rectangular cross-section extending into the plane of the paper). Therefore, the rails 309 with through holes 321-1, 321-2, and 321-3 and the line 305 with through holes 317-1 and 317-2 form two plates of a capacitor with a capacitance value Cc. The value of Cc will depend on the horizontal gap between the teeth and the vertical gap between the end of the tooth and the opposite line. A number of finger-shaped through holes can be provided. The virtual rails 309 can be further extended to M3, M4, ... as needed, and the transient line 305 extends similarly.

[0063] One or more embodiments advantageously (i) form the structure of the invention from the back side to reduce congestion and increase density and / or (ii) increase capacitance Cc, and thus increase dynamic boost δV by enhancing capacitance with finger-type vias.

[0064] Figure 3 depicts a second exemplary pre-charge circuit according to one aspect of the present invention; components similar to those in Figure 2 have the same numbering and are not described further except to the extent necessary to describe the construction and operation of the example in Figure 3. The short-time voltage pulse waveform interference here is designated as δV' and the small plot is designated as 387A. The fixed voltage power supply rail at Vdd or VCS is designated as 395A here. An n-type FET (NFET) 369 is connected in parallel with the PFET 379 between rail 395 and resistor 393 (resistor 393 is the wire resistance of that virtual power rail (as shown in the figure)). The NFET 369 has a first source-drain terminal 363 coupled to rail 395A, a second source-drain terminal 361 connected to rail 309 through resistor 393, and a gate 365 coupled to the gate 385 of the PFET 379.

[0065] Of course, those familiar with this technique will recall that the NFET turns on when the gate-source voltage Vgs exceeds the threshold voltage, and the PFET turns on when the gate-source voltage Vgs is less than the threshold voltage. When the dummy power rail sawtooth waveform (input waveform 397) applied to the gates of the PFET and NFET is low, the PFET turns on and the NFET turns off. The dummy power rail 309 is charged to Vdd or VCS, depending on the situation. When the dummy power rail sawtooth waveform (input waveform 397) goes high, the PFET turns off, and the gate of the NFET is at Vdd or VCS, depending on the situation. In this condition, the first drain-source terminal 363 of the NFET, which acts as the drain, is also at Vdd, and the second drain-source terminal 361 of the NFET, which acts as the source, is also at Vdd; therefore, the Vgs of the NFET is zero. At this point, NFET 369 acts only as a capacitor and, compared to the first embodiment where it pulls the virtual power rail 309 even higher, it also functions beyond the transient supply line 305 through Cc. Consider operation at a relatively slow speed (e.g., 10 MHz). Compared to a faster circuit (e.g., 50 MHz), the sawtooth period will increase accordingly, and the circuit will begin to leak charge. When PFET 379 is off, NFET 369 will eventually turn on, and the virtual power rail 309 will reach Vdd or VCS minus Vt, meaning the charge will not deplete from that line and will not become zero, but it will not remain at the "boost" value. The embodiment of Figure 3 therefore provides a higher boost than the embodiment of Figure 2, but due to leakage issues, it may be more suitable for higher frequency / shorter cycle circuits than the embodiment of Figure 2.

[0066] Figures 2 and 3 illustrate an illustrative positive dynamic virtual line. Referring to Figure 29, it should be noted that in another configuration, by changing the PFET 379 in Figure 2 to the NFET 2979 in Figure 29 and connecting it to ground (GND) 2995 and virtual line 2909, virtual line 2909 can be initialized to GND and later float by turning off NFET 2979. Changing the voltage of transient line 2905 from high to low, due to capacitive coupling, yields a negative value on the virtual line. In short, according to the configuration of the present invention, both techniques (negative boost and positive boost) can be advantageously achieved through back-side virtual power transfer. In addition to those discussed in this paragraph, components 2905, 2909, 2999, 2997, 2995, 2993, 2991, 2989, 2987, 2985, 2983, 2981, and 2979 are otherwise similar in manner to their respective corresponding components 305, 309, 399, 397, 395, 393, 391, 389, 387, 385, 383, 381, and 379 in Figure 2. Of course, those familiar with this technique will understand that the NFET turns on when the gate-source voltage Vgs exceeds the threshold voltage Vt, and the PFET turns on when the gate-source voltage Vgs is less than the threshold voltage Vt.

[0067] It is worth noting that, generally, embodiments can be used for memory and other very large-scale integrated circuit (VLSI) chip applications (e.g., logic). One non-limiting example is using the form of the invention to provide a positive or negative voltage boost to bit lines in a memory array.

[0068] Figure 4 depicts the transient line voltage waveform (applied waveform 399); the pre-charge waveform (input waveform 397) applied to the gate of the PFET in Figure 2 and the gates of both the PFET and FFET in Figure 3; and the waveforms 387 and 387A of the virtual power rail 309 (floating line). It should be noted that the timing margin TM can be, for example, 100 picoseconds to 200 picoseconds, and will depend on the pulse width. As mentioned above, the boost δV, δV' can be 0.1 V to 0.2 V higher than Vdd. "GND" refers to ground. Figure 4 applies to the embodiments of Figure 2 and Figure 3. It should be noted that for Figures 2 and 3, δV and δV' can be similar, as this (0.1 V to 0.2 V) is a preferred boost that can be achieved through the interconnect capacitor 391. The capacitance of the NFET 369 can be adjusted by reducing its size to obtain a similar preferred boost in both embodiments. Again, it should be noted that the 0.1 V to 0.2 V range is a non-limiting example and different embodiments may have different boosts.

[0069] Figure 5 depicts a precursor structure 500 according to an illustrative embodiment, which has a pre-charge circuit (represented by element 301) (as shown in Figure 2 or Figure 3) and a device region 508 (e.g., a plurality of field-effect transistors) on the front side of a substrate 502 (in the non-limiting example depicted). Note also should be paid to dielectric 509. Those skilled in the art will generally be familiar with integrated circuit fabrication up to the front-end process (FEOL) device fabrication as shown, and, in light of the teachings herein, a precursor structure having a pre-charge circuit in the device layer (including 301 and 308) can be fabricated.

[0070] Figure 6 depicts the precursor structure 500 of Figure 5 following the formation of the mid-cycle (MOL) contact 599 and the back-cycle (BEOL) wiring 597, which includes the power lines VDD and VSS, as shown. Note also the interlayer dielectric (ILD) 595. The pre-charge circuitry and device area 508 are connected to the wiring 597 via the contact 599.

[0071] Figure 7 depicts the structure of Figure 6 after the formation of additional vias and metal wire layers; note that M2 is used for illustration here, but this illustrative structure applies to any metal layer: M1, M3, M4, ..., Mx. The additional ILD here is designated as 595A. Note the cavity 593 used for depositing the additional metal.

[0072] Figure 8 depicts the structure of Figure 7 after the cavity has been filled with metal 591 (Ru in a non-limiting example).

[0073] Figure 9 depicts the structure of Figure 8 after subtractive patterning and etching to form the first through-hole bump (tooth 589) across the metal layer M2. The remaining metal 591 in Figure 8 is designated as 591A in Figure 9.

[0074] Figure 10 depicts the structure of Figure 9 after the deposition of an additional ILD. The ILD after the additional deposition is referred to as 595B.

[0075] Figure 11 depicts the structure of Figure 10 after patterning for the via layer V2 and the metal layer M3. Note that the metal layers are typically labeled M1, M2, M3, ..., while the via layers are typically labeled V1 (between M1 and M2), V2 (between M2 and M3), V3 (between M3 and M4), ... Note the cavity 587 used for depositing additional metal. The cavity 587 should not be etched deep enough to reach the via (tooth 589). As shown in Figure 12, the ILD 595B layer should be maintained to isolate the downward via from the upward via.

[0076] Figure 12 depicts the structure of Figure 11 after the via layer V2 and the metal layer M3 are metallized with additional metal to form the virtual power rail 585.

[0077] Figure 13 depicts the structure of Figure 12 after the formation of the additional BEOL interconnect layer 583. Referring to Figure 13 and also back to Figures 1 through 3, a pre-charge circuit can be implemented, for example, as shown in Figure 2 or Figure 3. The via 313 in Figure 1 is similar to the contact 599 in Figure 13, connecting to element 301 and then to layer M1, reaching the virtual power rail. The portion M2 with the upward-protruding via (tooth 589) represents the transient line 305 connected to device area 508 as shown, while layer M3 with the downward-protruding via represents the virtual power rail 309 (note that the example in Figure 1 is shown formed at M1 and M2, not M2 and M3).

[0078] In light of the foregoing, it should be understood that, in one embodiment, the exemplary method includes: providing / forming a FEOL circuit having a device area and a pre-charge circuit area (FIG. 5); forming MOL contacts and BEOL wires, wherein the power supply wires are connected to the device area (FIG. 6 to 8); forming through-hole bumps throughout the power supply wires (FIG. 9); and forming another metal wire having through holes falling between the through-hole bumps associated with the power supply wires, wherein the other metal wire is connected to the pre-charge circuit area (FIG. 10 to 13).

[0079] Furthermore, in light of the foregoing, it should be understood that in another embodiment, the exemplary semiconductor device includes a virtual power rail 309 and a transient line 305 coupled through separate via structures (e.g., sawtooth via structures 317-1, 317-2, 321-1, 321-2, 321-3 as shown). In the non-limiting example shown in FIG13, the virtual power rail is connected to a front-side precharge circuit. Embodiments can be used, for example, to boost the floating line positively or negatively for the functionality of logic and memory connected to the transient power structure including the precharge circuit.

[0080] In addition to the procedure just described, alternative procedures are also possible, which add the benefit of forming virtual functionality on the back side. Now refer to Figure 14. Note that the starting structure includes a substrate 1401, an etch stop layer 1403, an additional substrate material (e.g., Si) 1405, a device layer 1407 including a pre-charge circuit (or pre-discharge circuit), device areas and dielectric materials (not shown or numbered separately, but generally similar to those dielectric materials discussed above); a lower BEOL layer 1408, which includes metal lines and vias not numbered separately and an ILD 1409; further BEOL layers 1411, and a carrier wafer 1413 formed above 1411.

[0081] Figure 15 shows the structure of Figure 14 after it has been flipped.

[0082] Figure 16 shows the structure of Figure 15 after the substrate 1401 has been removed and the etching has stopped on the etch stop layer 1403.

[0083] Figure 17 shows the structure of Figure 16 after the etch stop layer 1403 has been removed.

[0084] Figure 18 shows the structure of Figure 17 after the remaining Si 1405 is removed down to device layer 1407.

[0085] Figure 19 depicts the structure of Figure 18 after the formation of the back-side contacts 1415 and the back-side wiring layer BM1 1414, as shown, including power lines for VDD and VSS. Note also the back-side interlayer dielectric (BILD) 1412. The pre-charge circuitry and device area in device layer 1407 are connected to the wiring via contacts 1415. In the non-limiting example of Figure 19, the front-side BEOL (lower BEOL layer 1408) carries only signals, and the back-side BEOL formed in BILD 1412 carries only power.

[0086] Figure 20 depicts the structure of Figure 19 after the formation of the back-side via layer BV1 and the patterning of the back-side metal layer BM2 (typically cavity 1417, into which the metals for BV1 and BM2 are deposited). An additional BILD is deposited, and the BILD is now designated as 1412A. It should be noted that the back-side BM2 is used for illustration here, and the illustrative structure applies to any back-side layer: back-side BM1, BM3, BM4, ..., BMx.

[0087] Figure 21 depicts the structure of Figure 20 after the back-side via layer BV1 and the back-side metal layer BM2 are metallized with a metal such as Ru 1419.

[0088] Figure 22 depicts the structure of Figure 21 after subtractive patterning and etching to form the first back-side via bump (tooth 1421) across the back-side metal layer BM2. The remaining metal 1419 of Figure 21 is designated as 1419A in Figure 22.

[0089] Figure 23 depicts the structure of Figure 22 after the deposition of an additional BILD. The BILD after the additional deposition is referred to as 1412B.

[0090] Figure 24 depicts the structure of Figure 23 after patterning of the back-side via layer BV2 and the back-side metal layer BM3. Note that the back-side metal layers are typically labeled BM1, BM2, BM3, ..., while the back-side via layers are typically labeled BV1 (between BM1 and BM2), BV2 (between BM2 and BM3), BV3 (between BM3 and BM4), ... Note the cavity 1423 used for depositing additional metal. The cavity 1423 should not be etched deep enough to reach the via (tooth 1421). As shown in Figure 24, the layer BILD 1412B should be maintained to isolate the downward via from the upward via.

[0091] Figure 25 depicts the structure of Figure 24 after the back-side via layer BV2 and the back-side metal layer BM3 are metallized with additional metal to form the virtual power rail 1425.

[0092] Figure 26 depicts the structure of Figure 25 after the formation of the additional back-side interconnect layer 1427. Referring to Figure 26 and also back to Figures 1 through 3, a pre-charge circuit can be implemented, for example, as shown in Figure 2 or Figure 3. The via 313 in Figure 1 is similar to the contact 1415 in Figure 26, connecting to the pre-charge circuit and then to the BM1 layer, reaching the virtual power rail. The BM2 portion with upward-protruding vias (tooth 1421) represents the transient line 305 connected to the device area, and the BM3 layer with downward-protruding vias represents the virtual power rail 309 (note that the example in Figure 1 is shown formed at M1 and M2, not at BM2 and BM3). Note that element 301Z typically represents both the charging circuit and the pre-discharging circuit.

[0093] Based on the above discussion, it should be understood that, in another embodiment, the exemplary method includes: forming a back-side transient power line in BMx-1 with a first via bump on the upper side (Figure 22); and forming a back-side virtual power rail in BMx with a second via bump on the lower side (Figure 25), wherein the first via bump and the second via bump are offset and separated by BILD. In this embodiment, the back-side virtual power rail is routed to the pre-charge (discharge) circuit in the device layer 1407 on the front side of the wafer.

[0094] Furthermore, given the foregoing discussion, it should be understood that in another embodiment, the exemplary semiconductor device includes a back-side virtual power rail 309 and a back-side transient line 305 coupled through a discrete via structure (e.g., sawtooth via structures 317-1, 317-2, 321-1, 321-2, 321-3). In the non-limiting example shown in FIG26, the back-side virtual power rail is connected to a front-side pre-charge circuit in the device layer. Embodiments can be used, for example, to positively or negatively boost the floating line for the functionality of logic and memory connected to the transient power structure including the pre-charge circuit. That is, typically, the structure connected to the circuit shown in FIG1 can be formed on the front side as in FIG13 or on the back side as in FIG26.

[0095] Although, as illustrated in the accompanying drawings, the virtual power rail 309 and the transient supply line 305 are vertically spaced apart, in other embodiments, the virtual power rail and the transient supply line may be horizontally spaced apart from each other by means of horizontal forked protrusions separated by dielectric material. [ ]

[0096] Furthermore, it is worth noting that the examples in the figures typically depict interdigitation. However, it is also possible, for example, to use interdigitation or, in the absence of interdigitation, to place a long solid line immediately next to the virtual line for coupling.

[0097] Given the teachings herein, for any component for which example materials are not described, those skilled in the art may select appropriate materials, and for any fabrication step for which specific illustrative procedures are not described, those skilled in the art may select appropriate known procedures. Illustrative known procedures generally include, in no particular order, preparation (deposition / patterning) of nanosheet stacks with sacrificial SiGe regions, etch-back of sacrificial SiGe, formation of shallow trench isolation (STI), dummy gates including gate spacers, internal spacers, and BDI, dummy gate disconnection, dummy gate removal, channel release, HKMG stack deposition, self-aligned contact (SAC) cap and trench metal contact formation, and lithography, masking, and patterning. Those skilled in the art will be familiar with the "dummy gate" procedure used to form HKMGs. More generally, those skilled in the art will be familiar with epitaxial growth, self-aligned contact formation, and the formation of high-K metal gates. The term "high-K" has a clear meaning for those familiar with the technology within the context of high-K metal gate (HKMG) stacking and is not simply a relative term. These procedures can be used, for example, to form FETs in pre-charge circuits and / or device regions.

[0098] Bulk silicon is a non-limiting example of a suitable substrate material; other materials are also possible.

[0099] Semiconductor device manufacturing involves various steps in a device patterning process. For example, the fabrication of a semiconductor wafer may begin with, for instance, multiple device patterns generated by computer-aided design (CAD), followed by an effort to replicate these device patterns onto a substrate. The replication process may involve various exposure techniques and the use of various subtractive (etching) and / or additive (deposition) material processing steps. For example, in a photolithography process, a photoresist layer may first be applied to the top of a substrate and then selectively exposed according to one or more predetermined device patterns. The portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may undergo some variation in their solubility in certain solutions. The photoresist may then be developed in a developing solution, thereby removing the unirradiated (in negative resists) or irradiated (in positive resists) portions of the resist layer to create a photoresist pattern or photomask. The photoresist pattern or photomask may then be replicated or transferred to the substrate beneath the photoresist pattern.

[0100] Those skilled in this art use a variety of techniques to remove material at various stages of semiconductor structure formation. As used herein, these procedures are generally referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selected materials during semiconductor structure formation. Standard Clean 1 (SC1) contains a strong base (typically ammonium hydroxide) and hydrogen peroxide. SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. Those skilled in this art have a thorough understanding of etching techniques and applications; therefore, a more detailed description of such procedures is not presented herein.

[0101] Although the overall manufacturing method and the resulting structure are novel, certain individual processing steps required to implement this method can utilize known semiconductor manufacturing techniques and tools. Given the teachings herein, these techniques and tools will be familiar to those generally skilled in the art. For example, those skilled in this art will be familiar with epitaxial growth, self-aligned contact formation, and the formation of high-k metal gates. The term "high-k" has a specific meaning for those skilled in the art within the context of high-k metal gate (HKMG) stacking and is not simply a relative term. Furthermore, one or more of the processing steps and tools used to manufacture semiconductor devices are described in numerous readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001; and PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, all of which are hereby incorporated by reference. It should be emphasized that although some individual processing steps are described in this article, these steps are merely illustrative, and those familiar with this technique will be familiar with several equally suitable alternatives.

[0102] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for ease of interpretation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in the given figures. This does not imply that un-depicted semiconductor layers are omitted in actual integrated circuit devices.

[0103] Those familiar with this technology should understand that the exemplary structures described above can be distributed in their original form (i.e., a single wafer with multiple unpackaged wafers), as bare dies, as packages, or incorporated as part of intermediate or final products.

[0104] Integrated circuits in the manner described in this invention can be employed in virtually any application and / or electronic system. In view of the teachings provided herein, those skilled in the art will be able to anticipate other implementations and applications of the embodiments disclosed herein.

[0105] A computer system that can use circuits and / or control procedures used in semiconductor design, manufacturing, and / or testing according to the present invention.

[0106] Now refer to Figure 27.

[0107] The various forms disclosed herein are described by descriptive text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). Regarding any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, also depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, in parallel, or in a manner that at least partially overlaps in time.

[0108] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe one or more storage media (also referred to as “mediums”) commonly included in a group of one or more storage devices, which collectively include machine-readable program code corresponding to instructions and / or data for performing computer operations specified in a given CPP technical solution. “Storage device” is any tangible means capable of retaining and storing instructions for use by a computer processor. Computer-readable storage media may be, but is not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of the foregoing. Some known types of storage devices that include such media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), CD-ROM, DVD, memory sticks, floppy disks, mechanical encoding devices (such as punch cards or dimples / pads formed in the main surface of the disc), or any suitable combination of the foregoing. As used in this disclosure, computer-readable storage media should not be construed as storing transient signals in themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating via waveguides, light pulses transmitted via fiber optic cables, electrical signals transmitted via wires, and / or other transmission media. As will be understood by those skilled in the art, data typically moves at random points in time during the normal operation of the storage device (e.g., during access, defrauding, or garbage collection), but this does not render the storage device transient, because the data is not transient when it is stored.

[0109] The computing environment 100 includes examples of environments for executing at least some of the computer program code involved in implementing the methods of the present invention, such as the electronic design automation tool 200 discussed below with respect to FIG28. In addition to block 200, the computing environment 100 also includes, for example, a computer 101, a wide area network (WAN) 102, an end-user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor group 110 (including a processing circuit system 120 and cache memory 121), a communication mesh architecture 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 200, as identified above), a peripheral device group 114 (including a user interface (UI) device group 123, storage 124, and an Internet of Things (IoT) sensor group 125), and a network module 115. Remote server 104 includes remote database 130. Public cloud 105 includes gateway 140, cloud provisioning module 141, host physical machine group 142, virtual machine group 143, and container group 144.

[0110] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other portable computer, mainframe computer, quantum computer or any other form of computer or mobile device that is known or to be developed in the future, capable of executing programs, accessing networks or querying databases, such as remote database 130. As is fully understood in the field of computer technology, and depending on the technology, the performance of a computer implementation method may be distributed across multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 100, the detailed discussion focuses on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 may reside in the cloud, even if it is not shown in the cloud in Figure 27. On the other hand, unless it can be definitively indicated to any extent, computer 101 is not required to be in the cloud.

[0111] Processor group 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry system 120 may be distributed across multiple packages, such as across multiple cooperating integrated circuit chips. Processing circuitry system 120 may implement multiple processor threads and / or multiple processor cores. Cache memory 121 is memory located within the processor chip package and is typically used for data or code that should be quickly accessed by the threads or cores executing on processor group 110. Cache memory is typically organized into multiple tiers depending on its relative proximity to the processing circuitry system. Alternatively, some or all of the cache memory used in the processor group may be located "off-chip". In some computing environments, processor group 110 may be designed to work with qubits and perform quantum operations.

[0112] Computer-readable program instructions are typically loaded onto computer 101 to cause the processor assembly 110 of computer 101 to perform a series of operational steps and thereby affect the computer-implemented method, such that the instructions executed thereby will perform the methods specified in the flowcharts and / or descriptions of the computer-implemented method included in this document (collectively, the "method of the invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache memory 121 and another storage medium discussed below. The program instructions and associated data are accessed by processor assembly 110 to control and direct the execution of the method of the invention. In computing environment 100, at least some of the instructions for executing the method of the invention may be stored in block 200 of persistent storage 113.

[0113] The communication mesh architecture 111 is a signal transmission path that allows various components of computer 101 to communicate with each other. Typically, this mesh architecture is constructed from switches and conductive paths, such as those forming buses, bridges, physical input / output ports, and the like. Other types of signal communication paths, such as fiber optic communication paths and / or wireless communication paths, can be used.

[0114] Volatile memory 112 is any type of volatile memory known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, but this is not necessary unless explicitly indicated. In computer 101, volatile memory 112 is located in a single package and inside computer 101, but alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 101.

[0115] Persistent storage 113 is any form of non-volatile storage for a computer, known or to be developed in the future. Non-volatile means that the stored data is maintained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage 113. Persistent storage 113 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, deleted, and rewritten. Some familiar forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known dedicated operating systems or open-source portable operating system interfaces employing a kernel. The code included in block 200 typically includes at least some of the computer code involved in performing the methods of the present invention.

[0116] Peripheral device group 114 includes the peripheral device group of computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, Near Field Communication (NFC) connectivity, cable-based connections (e.g., Universal Serial Bus (USB) cables), plug-in connections (e.g., Secure SD cards), connections via local area networks, and even connections via wide area networks such as the Internet. In various embodiments, UI device group 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 124 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 124 may be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., where computer 101 natively stores and processes large databases), this storage may then be provided by peripheral storage devices designed for storing large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor group 125 consists of sensors that can be used in Internet of Things (IoT) applications. For example, one sensor may be a thermometer, and another sensor may be a motion detector.

[0117] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include: hardware, such as a modem or Wi-Fi transceiver; software for packetizing and / or depacketizing data for transmission over a communication network; and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and forwarding functions of network module 115 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software Defined Networking (SDN)), the control and forwarding functions of network module 115 are executed on physically separate devices, such that the control functions manage several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can generally be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0118] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology known or to be developed in the future for transmitting computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a localized area such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0119] End-user device (EUD) 103 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 101), and may take any of the forms described above in connection with computer 101. EUD 103 typically receives helpful and useful information from the operation of computer 101. For example, under the assumption that computer 101 is designed to provide recommendations to the end-user, these recommendations will typically be transmitted from computer 101's network module 115 to EUD 103 via WAN 102. In this way, EUD 103 may display or otherwise present recommendations to the end-user. In some embodiments, EUD 103 may be a client device, such as a simplified client, a complex client, a mainframe computer, a desktop computer, etc.

[0120] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 can be controlled and used by the same entity operating computer 101. Remote server 104 refers to a machine that collects and stores helpful and useful data for use by other computers such as computer 101. For example, in a hypothetical situation where computer 101 is designed and programmed to provide recommendations based on historical data, this historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0121] The public cloud 105 is any computer system available on demand to multiple entities, particularly data storage (cloud storage) and computing power, without requiring direct active management by the user. Cloud computing typically utilizes resource sharing to achieve harmony and economies of scale. Direct and active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud provisioning module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers constituting the host machine group 142, which is the total range of physical computers in and / or available to the public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine group 143 and / or containers from container group 144. It should be understood that such VCEs can be stored as images and can be transferred as images or between various physical machine hosts after individualization of VCE execution. The cloud orchestration module 141 manages the transmission and storage of images, deploys new execution personalizations of VCE, and manages the activity execution personalizations of VCE deployments. The gateway 140 is a collection of computer software, hardware, and firmware that allows the public cloud 105 to communicate via WAN 102.

[0122] Here is a further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." New active execution instances of a VCE can be individualized from the image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space execution instances, called containers, to exist. From the perspective of the program running within it, these isolated user-space execution instances typically behave like a real computer. A computer program running on a typical operating system can utilize all of the computer's resources, such as connectivity, files and folders, network sharing, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container; this feature is called containerization.

[0123] Private cloud 106 is similar to public cloud 105, except that computing resources are available only to a single enterprise. While private cloud 106 is depicted as communicating with WAN 102, in other embodiments, private cloud may be completely disconnected from the internet and accessed only through a local area network (LAN). A hybrid cloud is a combination of multiple clouds of different types (e.g., private, group, or public cloud types) typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability across the multiple constituent clouds. In this embodiment, both public cloud 105 and private cloud 106 are parts of a larger hybrid cloud.

[0124] Illustrative design programs for semiconductor design, manufacturing, and / or testing

[0125] One or more embodiments utilize computer-aided semiconductor integrated circuit design simulation, testing, placement, and / or fabrication. In this regard, Figure 28 illustrates a block diagram of an exemplary design flow 700 used for, for example, semiconductor IC logic design, simulation, testing, placement, and fabrication. Design flow 700 includes programs, machines, and / or mechanisms for processing design structures or devices to produce logically or otherwise functionally equivalent representations of the design structures and / or devices, such as those analyzable using the techniques disclosed herein or similar methods. Design structures processed and / or produced by design flow 700 may be encoded on a machine-readable storage medium to include data and / or instructions that, when executed or otherwise processed on a data processing system, produce logically, structurally, mechanically, or otherwise functionally equivalent representations of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in IC design programs such as designing, fabricating, or simulating circuits, components, devices, or systems. For example, the machine may include: a lithography machine, a machine and / or equipment for generating a mask (e.g., an e-beam writer), a computer or equipment for simulating a design structure, any device for manufacturing or testing a program, or any machine for programming a functionally equivalent representation of a design structure to any media (e.g., a machine for programming a programmable gate array).

[0126] Design flow 700 can vary depending on the type of representation being designed. For example, design flow 700 for building application-specific integrated circuits (ASICs) may differ from design flow 700 for designing standard components or design flow 700 for individualizing the design execution into a programmable array, such as a programmable gate array (PGA) or field-programmable gate array (FPGA) provided by Altera® or Xilinx®.

[0127] Figure 28 illustrates multiple such design structures including an input design structure 720 preferably processed by design program 710. Design structure 720 may be a logic simulation design structure generated and processed by design program 710 to produce a logically equivalent functional representation of a hardware device. Design structure 720 may also or alternatively include data and / or program instructions that, when processed by design program 710, produce a functional representation of the physical structure of the hardware device. Regardless of representing functional and / or structural design features, design structure 720 may be generated using electronic computer-aided design (ECAD) implemented by a core developer / designer. When coded on a gate array or storage medium or the like, design structure 720 may be accessed and processed by one or more hardware and / or software modules within design program 710 to simulate or otherwise functionally represent electronic components, circuits, electronic or logic modules, devices, apparatuses, or systems. Therefore, design structure 720 may include files or other data structures including human- and / or machine-readable source code, compiled structures, and computer-executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of a hardware logic design. Such data structures may include hardware description language (HDL) design entities or other data structures that conform to or are compatible with lower-level HDL design languages ​​(such as Verilog and VHDL) and / or higher-level design languages ​​(such as C or C++).

[0128] Design program 710 preferably employs and incorporates design / simulation functional equivalents for synthesizing, translating, or otherwise processing components, circuits, devices, or logic structures to produce hardware and / or software modules that may contain a network connection table 780 containing a design structure such as design structure 720. Network connection table 780 may contain a compiled or otherwise processed data structure representing a list of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., describing connections to other components and circuits in the integrated circuit design. Network connection table 780 may be synthesized using an iterative process, wherein network connection table 780 is resynthesized one or more times depending on the design specifications and parameters for the device. As with other design structure types described herein, network connection table 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium, such as a magnetic disk or optical disk drive, a programmable gate array, a CF card, or other flash memory. Alternatively, or in an alternative, the media may be system or cache memory, buffer space, or other suitable memory.

[0129] Design program 710 may include hardware and software modules for processing various input data structure types, including network connection table 780. These data structure types may reside, for example, in library element 730, and include common components, circuits, and device groups for a given manufacturing technology (e.g., different technology nodes: 32 nm, 45 nm, 90 nm, etc.), including models, layouts, and symbol representations. The data structure types may further include design specifications 740, characterization data 750, verification data 760, design rules 770, and test data files 785, which may include input test patterns, output test results, and other test information. Design program 710 may further include, for example, standard mechanical design programs, such as stress analysis, thermal analysis, mechanical event simulation, and program simulations for operations such as casting, molding, and compression molding. Those skilled in the art of mechanical design will understand the scope of possible mechanical design tools and applications used in design program 710 without departing from the scope and spirit of this invention. Design program 710 may also include modules for performing standard circuit design procedures (such as timing analysis, verification, design rule checking, placement and routing operations).

[0130] Design program 710 employs and incorporates logical and physical design tools, such as HDL compilers and simulation model building tools, to process design structure 720 along with some or all of the depicted supporting data structures and any additional mechanical design or data (if applicable), to produce a second design structure 790. Design structure 790 resides on a storage medium or programmable gate array in a data format used for exchanging data about mechanical devices and structures (e.g., stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format to store or present information about such mechanical design structures). Similar to design structure 720, design structure 790 preferably includes one or more files, data structures, or other computer-coded data or instructions that reside on a data storage medium and, when processed by an ECAD system, produce one or more logically or otherwise functionally equivalent forms of IC designs or their likenesses. In one embodiment, design structure 790 may include a compiled executable HDL simulation model that functionally simulates the device to be analyzed.

[0131] Design structure 790 may also employ data formats and / or symbol data formats used for exchanging layout data of integrated circuits (e.g., information stored in GDSII (GDS2), GL1, OASIS, mapping files, or any other suitable format for storing such design data structures). Design structure 790 may contain information such as symbol data, mapping files, test data files, design content files, manufacturing data, layout parameters, wires, metal levels, vias, shapes, data for routing through manufacturing lines, and any other data required by the manufacturer or other designer / developer to produce the device or structure as described herein (e.g., .lib files). Design structure 790 may then proceed to stage 795, where, for example, design structure 790: continues to tape-out, is made public for manufacturing, is made public to a mask house, is sent to another design studio, is sent back to the customer, etc.

[0132] The embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to constitute a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Given the teachings herein, many other embodiments will become apparent to those skilled in the art; other embodiments are utilized and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. It should also be noted that in some alternative implementations, some steps of the illustrative method may not be performed in the order indicated in the figures. For example, depending on the functionality involved, two steps shown in a sequential manner may actually be performed substantially in parallel, or some steps may sometimes be performed in reverse order. The figures are also representative only and not drawn to scale. Therefore, this specification and figures should be viewed in an illustrative rather than restrictive sense.

[0133] The term "embodiment" is used individually and / or collectively herein for convenience only and is not intended to limit the scope of this application to any single embodiment or inventive concept (where more than one embodiment is actually shown). Therefore, although specific embodiments have been illustrated and described herein, it should be understood that configurations achieving the same purpose may replace the specific embodiments shown; that is, this disclosure is intended to cover any and all adaptations or variations of the various embodiments. In view of the teachings herein, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art.

[0134] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms “comprises and / or comprising”, when used in this specification, designate the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as “bottom,” “top,” “above,” “above,” “below,” and “below” are used to indicate the relative positioning of elements or structures relative to each other at a relative height. If a layer of structure is described herein as being “above” another layer, it should be understood that an intermediate element or layer may or may not be present between the two specified layers. If a layer is described as being “directly above” another layer, it indicates that the two layers are in direct contact. When terms are used herein and in the claims of the appended patent applications, “about” means within plus or minus ten percent.

[0135] The corresponding structures, materials, actions, and equivalents of any component or step plus functional element within the following claims are intended to include any structure, material, or action used to perform a function in conjunction with other claimed elements as specifically claimed. Descriptions of various embodiments are presented for illustrative and descriptive purposes but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. These embodiments were chosen and described to best explain the principles and practical applications, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the specific uses covered.

[0136] An abstract is provided to comply with 37 CFR § 1.76(b), requiring that the abstract allow the reader to quickly determine the nature of the technical disclosure. It should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing embodiments, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the invention. This method of disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly stated in each claim. In fact, as reflected in the appended claims, the claimed subject matter may lie in fewer than all the features of a single embodiment. Therefore, the following claims are hereby incorporated into the embodiments, wherein each claim is treated, in itself, as a separately claimed subject matter.

[0137] In view of the teachings provided herein, those skilled in the art will be able to consider other implementations and applications of the art and the disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and various other changes and modifications may be made therein by those skilled in the art without departing from the scope of the appended claims.

[0138] 100: Computing Environment 101: Computer 102: Wide Area Network (WAN) 103: End User Device (EUD) 104: Remote Server 105: Public Cloud 106: Private Cloud 110: Processor Group 111: Communication Mesh Architecture 112: Volatile memory 113: Persistent storage 114: Peripheral Device Group 115: Network Module 120: Processing circuit system 121: Cache memory 122: Operating System 123: User Interface (UI) Device Group 124: Storage 125: Internet of Things (IoT) Sensor Pack 130: Remote Database 140: Gate device 141: Cloud-based orchestration module 142: Mainframe machine group 143: Virtual Machine Group 144: Container Group 200: Block / Electronic Design Automation Tools 301: Components 303: Controllers and power supplies / components 305: Transient Line / Transient Supply Line / Component 307: Metal Wire 309: Virtual Power Rail / Component 313: Through hole 315: Through hole 317-1: Through-hole / Sawtooth Through-hole Structure 317-2: Through-hole / Sawtooth Through-hole Structure 319: Through hole 321-1: Through-hole / Sawtooth Through-hole Structure 321-2: Through-hole / sawtooth through-hole structure 321-3: Through-hole / Sawtooth Through-hole Structure 323-1: Line 323-2: Line 323-3: Line 361: Second source-drain pole quantum 363: First drain-source extreme particle 365: Gate 369:n-type FET (NFET) 379: p-type field-effect transistor (PFET) / device 381: Second source-drain terminal / component 383: First source-drain terminal / component 385: Gate / Component 387: Subheadings / Drawings / Components / Waveforms 387A: Small Label Plotting / Waveform 389: Capacitors / Components 391: Interconnect capacitors / components / capacitors 393: Resistors / Components 395: Fixed Voltage Power Supply Rail / Component / Rail 395A: Fixed voltage power supply rail / rail 397: Input waveform / component 399: Apply waveform / component 500: Front-wheel drive structure 502:Substrate 508: Unit Area 508Z: Device Area [ ] 509: Dielectric 585: Virtual Electric Rail / Gear 587: Cavity 589: Teeth 591: Metal 591A: Residual Metal 593: Cavity 595: Interlayer Dielectric (ILD) 595A:ILD 595B:ILD 597: Back-end Processing (BEOL) Wiring / Wiring 599: Mid-cycle (MOL) contact / contact 700: Design Process 710: Design Program 720: Design Structure 730: Library Components 740: Design Specifications 750: Specific Data 760: Verification Data 770: Design Rules 780: Network Connection Table 785: Test Data Archive 790: Design Structure 795: Stage 1401:Substrate 1403: Etching Stop Layer 1405: Additional substrate material 1407: Device Layer 1408: Lower BEOL layer 1409:ILD 1411: More BEOL layers 1412: Backside interlayer dielectric (BILD) 1412A:BILD 1412B:BILD 1413: Carrier wafer 1414: Backside wiring layer BM1 1415: Contact / Backside Contact 1417: Cavity 1419A: Residual Metal / Component / Transient Line 1421: Teeth 1423: Cavity 1425: Virtual Power Rail / Component 1427: Additional backside interconnect layer 2905: Transient Line / Component 2909: Virtual Line / Component 2979: NFET / Component 2981: Components 2983: Components 2985: Components 2987: Components 2989: Components 2991: Components 2993: Components 2995: Ground (GND) / Component 2997: Components 2999: Components BM2: Backside metal layer BM3: Backside metal layer BILD: Backside interlayer dielectric BV1: Backside through-hole layer BV2: Backside through-hole layer Cc: Capacitor Cv: Capacitor GND: Earth M1: Wiring layer / Metal layer M2: Wiring layer / Metal layer M3: Wiring layer / Metal layer ILD: Interlayer Dielectric Rv: Resistance TM: Timing Margin V1: Through-hole layer V2: Through-hole layer VCS: Unit Power Supply VDD: Digital power supply voltage Vdd: Digital power supply voltage δV: Boost pressure δV': Boost pressure +δV: Positive short-time pulse waveform interference -δV: Negative short-time pulse waveform interference

Claims

1. A semiconductor structure comprising: a device layer including a device region having a plurality of devices and a pre-charge circuit; a front-side wiring layer located on a front side of the device layer and including at least signal wiring connected to the device region; a power supply voltage line coupled to the device region; and a back-side wiring layer located on a back side of the device layer and including: A virtual power rail coupled to the precharge circuit; a transient line capacitively and nonconductively coupled to the virtual power rail and to the device region; wherein the precharge circuit is configured such that the virtual power rail responds to a pulse on the transient line and experiences a voltage difference with a supply voltage applied to the supply voltage line.

2. The semiconductor structure of claim 1, wherein the virtual power rail and the transient line are formed with finger-like conductive teeth separated by a dielectric.

3. The semiconductor structure of claim 2, wherein the virtual power rail and the transient line are vertically spaced apart from each other, and the forked conductive teeth include vertical through holes.

4. The semiconductor structure of claim 3, wherein the precharge circuit includes a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail.

5. The semiconductor structure of claim 4 further includes a controller and a power supply configured to supply an input pulse waveform to a transient supply line and the gate of the p-type field-effect transistor.

6. The semiconductor structure of claim 5, wherein the input pulse waveforms are in phase and the voltage difference is positive.

7. The semiconductor structure of claim 5, wherein the input pulse waveforms are out of phase and the voltage difference is negative.

8. The semiconductor structure of claim 3, wherein the precharge circuit comprises: a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail; and an n-type field-effect transistor having a first drain-source terminal coupled to the first drain-source terminal of the p-type field-effect transistor, a gate coupled to the gate of the p-type field-effect transistor, and a second drain-source terminal coupled to the second drain-source terminal of the p-type field-effect transistor.

9. The semiconductor structure of claim 8 further includes a controller and a power supply configured to supply an input pulse waveform to a transient supply line and the gates of the p-type field-effect transistor and the n-type field-effect transistor.

10. The semiconductor structure of claim 9, wherein the input pulse waveforms are in phase and the voltage difference is positive.

11. The semiconductor structure of claim 9, wherein the input pulse waveforms are out of phase and the voltage difference is negative.

12. A semiconductor structure comprising: a device layer including a device region having a plurality of devices and a pre-charge circuit; a power supply voltage line coupled to the device region; and a wiring layer positioned adjacent to the device layer and comprising: A virtual power rail coupled to the pre-charging circuit; and a transient line, which is capacitively but not conductively coupled to the virtual power rail and to the device region; wherein: the precharge circuit is configured such that the virtual power rail responds to a pulse on the transient line and experiences a voltage difference with a supply voltage applied to the supply voltage line; and the virtual power rail and the transient line are formed with forked conductive teeth separated by a dielectric.

13. The semiconductor structure of claim 12, wherein the virtual power rail and the transient line are vertically spaced apart from each other, and the forked conductive teeth include vertical through holes.

14. The semiconductor structure of claim 13, wherein the precharge circuit includes a p-type field-effect transistor having a first drain-source terminal coupled to one of the supply voltage lines, a gate, and a second drain-source terminal coupled to one of the virtual power rails.

15. The semiconductor structure of claim 14, further comprising a controller and a power supply configured to supply an input pulse waveform to a transient supply line and the gate of the p-type field-effect transistor.

16. The semiconductor structure of claim 15, wherein the input pulse waveforms are in phase and the voltage difference is positive.

17. The semiconductor structure of claim 15, wherein the input pulse waveforms are out of phase and the voltage difference is negative.

18. The semiconductor structure of claim 13, wherein the precharge circuit comprises: a p-type field-effect transistor having a first drain-source terminal coupled to the supply voltage line, a gate, and a second drain-source terminal coupled to the virtual power rail; and an n-type field-effect transistor having a first drain-source terminal coupled to the first drain-source terminal of the p-type field-effect transistor, a gate coupled to the gate of the p-type field-effect transistor, and a second drain-source terminal coupled to the second drain-source terminal of the p-type field-effect transistor.

19. The semiconductor structure of claim 18, further comprising a controller and a power supply configured to supply an input pulse waveform to a transient supply line and the gates of the p-type field-effect transistor and the n-type field-effect transistor.

20. The semiconductor structure of claim 19, wherein the input pulse waveforms are in phase and the voltage difference is positive.

21. The semiconductor structure of claim 19, wherein the input pulse waveforms are out of phase and the voltage difference is negative.

22. A semiconductor structure comprising: a device layer including a device region having a plurality of devices and a pre-discharge circuit; a front-side wiring layer located on a front side of the device layer and including at least signal wiring connected to the device region; and a back-side wiring layer located on a back side of the device layer and including: A virtual power rail coupled to the pre-discharge circuit; and a transient line capacitively, non-conductively coupled to the virtual power rail and to the device region; wherein the pre-discharge circuit is configured such that the virtual power rail responds to a pulse on the transient line and experiences a voltage difference from an initial ground potential.

23. The semiconductor structure of claim 22, wherein the virtual power rail and the transient line are formed with finger-like conductive teeth separated by a dielectric.

24. A semiconductor structure comprising: a device layer including a device region having a plurality of devices and a pre-discharge circuit; and a wiring layer positioned adjacent to the device layer and comprising: A virtual power rail coupled to the pre-discharge circuit; and a transient line, which is capacitively but not conductively coupled to the virtual power rail and to the device area; wherein: the pre-discharge circuit is configured such that the virtual power rail responds to a pulse on the transient line and experiences a voltage difference with an initial ground potential; and the virtual power rail and the transient line are formed with forked conductive teeth separated by a dielectric.

25. A method of forming a semiconductor structure, the method comprising: providing an initial structure including a carrier wafer, a plurality of front-side wiring layers extending outward from the carrier wafer, and a device layer extending outward from the plurality of front-side wiring layers, the device layer including a device region and a pre-charge circuit; forming a back-side transient power line on a back side of the device region, the back-side transient power line including wiring in a first metal region, wherein a first via bump extends therefrom; forming a back-side virtual power rail on the back side of the device region, the back-side virtual power rail including wiring in a second metal region vertically spaced apart from the first metal region, the back-side virtual power rail further including a second via bump extending therefrom, the first via bump and the second via bump extending toward each other and being finger-like and separated from each other by a back-side interlayer dielectric, the back-side virtual power rail being coupled to the pre-charge circuit.

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