Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for fabricating resistive random access memory (RAM). The method mainly involves first providing a substrate including an alignment mark region and a resistive RAM region, then forming an interlayer dielectric layer on the substrate, forming a contact plug within the interlayer dielectric layer, forming a first lower electrode layer on the resistive RAM region and the alignment mark region, removing the first lower electrode layer and the interlayer dielectric layer from the alignment mark region to form a groove, and then planarizing the first lower electrode layer.

Claims

1. A method for fabricating resistive random access memory (RAM), characterized in that it comprises: providing a substrate including an alignment mark region and a resistive RAM region; forming an interlayer dielectric layer on the substrate; forming a contact plug within the interlayer dielectric layer; forming a first lower electrode layer on the resistive RAM region and the alignment mark region; forming a second lower electrode layer on the first lower electrode layer; removing the first lower electrode layer and the interlayer dielectric layer from the alignment mark region to form a groove; and planarizing the first lower electrode layer; wherein, The nitrogen concentration of the first lower electrode layer is greater than that of the second lower electrode layer.

2. The method as described in claim 1 further comprises: removing the first lower electrode layer and the interlayer dielectric layer using a patterned mask to form the groove; removing the patterned mask; and planarizing the first lower electrode layer.

3. The method as described in claim 1, further comprising: forming a second lower electrode layer on the first lower electrode layer; forming a resistive switching layer on the second lower electrode layer; forming an upper electrode on the resistive switching layer; patterning the upper electrode, the resistive switching layer, the second lower electrode layer, and the first lower electrode layer; forming a masking layer on the upper electrode and the interlayer dielectric layer; forming a first intermetallic dielectric layer surrounding the masking layer; forming a second intermetallic dielectric layer on the first intermetallic dielectric layer; and forming a metal interconnect in the second intermetallic dielectric layer and connecting to the upper electrode.

4. The method as described in claim 3, wherein the first lower electrode layer and the second lower electrode layer have different thicknesses.

5. The method as described in claim 3, wherein the upper electrode comprises: a first upper electrode; and a second upper electrode disposed on the first upper electrode.

6. The method as described in claim 5, wherein the first upper electrode comprises tanium nitride (TaN) and the second upper electrode comprises titanium nitride (TiN).

7. A resistive random access memory, characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; and a lower electrode disposed on the contact plug, wherein the lower electrode comprises: a first lower electrode layer, wherein the top surface of the first lower electrode layer comprises a flat surface; and a second lower electrode layer; a resistive switching layer disposed on the lower electrode; and an upper electrode disposed on the resistive switching layer, wherein the upper electrode comprises a first upper electrode, and the first upper electrode comprises a nitrogen concentration gradient; wherein the nitrogen concentration of the first lower electrode layer is greater than the nitrogen concentration of the second lower electrode layer.

8. The resistive random access memory as described in claim 7, further comprising: a cover layer disposed next to the upper electrode; a first intermetallic dielectric layer surrounding the cover layer; a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer; and a metal interconnect disposed in the second intermetallic dielectric layer and connected to the upper electrode.

9. The resistive random access memory as described in claim 7, wherein the first lower electrode layer and the second lower electrode layer have different thicknesses.

10. The resistive random access memory as described in claim 7, wherein the thickness of the first lower electrode layer is greater than the thickness of the second lower electrode layer.

11. The resistive random access memory as described in claim 7, wherein the first lower electrode layer comprises a T-shape.

12. The resistive random access memory as described in claim 7, wherein the sidewall of the first lower electrode layer is flush with the sidewall of the second lower electrode layer.

13. A resistive random access memory, characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; a lower electrode disposed on the contact plug, wherein the lower electrode comprises: a first lower electrode layer, wherein the top surface of the first lower electrode layer comprises a flat surface; and a second lower electrode layer; a resistive switching layer disposed on the lower electrode; and an upper electrode disposed on the resistive switching layer, wherein the upper electrode comprises: a first upper electrode; and a second upper electrode disposed on the first upper electrode; wherein the nitrogen concentration of the first lower electrode layer is greater than the nitrogen concentration of the second lower electrode layer, and the first upper electrode comprises a nitrogen concentration gradient.

14. The resistive random access memory as described in claim 13, wherein the first upper electrode comprises tantan nitride (TaN) and the second upper electrode comprises titanium nitride (TiN).

15. The resistive random access memory as described in claim 13, wherein the second upper electrode comprises a nitrogen concentration gradient.

16. The resistive random access memory as described in claim 13, wherein the first upper electrode and the second upper electrode comprise a nitrogen concentration gradient.

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