Catalyst influenced pattern transfer technology

Abstract

Various embodiments of the present invention generally relate to semiconductor device architectures and manufacturing techniques. More particularly, some embodiments of the present invention relate to the use of catalyst-influenced chemical etching (CICE) techniques applied to the etching of silicon in three-dimensional memory architectures and transistors. CICE is a catalyst-based etching method that can be used on semiconductors and multilayer semiconductors. Various embodiments of the CICE process can use catalysts to etch semiconductor substrates and create high aspect ratio features. Manufacturing tools for achieving this are also disclosed. This should enable the adoption of this technology in the manufacture of semiconductor devices.

Claims

1. A method for manufacturing a high aspect ratio structure, the method comprising the steps of: patterning a catalyst layer on a surface of a semiconductor material, wherein the catalyst layer includes a plurality of features and links between two or more of the plurality of features; exposing the patterned catalyst layer on the surface of the semiconductor material to an etchant, wherein the patterned catalyst layer causes etching of the semiconductor material to form the high aspect ratio structure corresponding to the plurality of features and gaps corresponding to the links; and depositing one or more materials sufficient to fill the gaps.

2. The method as described in claim 1, wherein the gaps are filled by one of the following techniques: atomic layer deposition, chemical vapor deposition, and electroplating.

3. The method as described in claim 1, wherein the one or more materials used to fill the gaps are one of the following: an electrode material and a dielectric.

4. The method as described in claim 1, wherein the high aspect ratio structure serves as a capacitor.

5. The method as described in claim 1, wherein the high aspect ratio structure serves as a MIM capacitor.

6. The method as claimed in claim 1, wherein the semiconductor material is one of the following: a single-crystal bulk silicon wafer, a layer of polycrystalline silicon deposited on a substrate, a layer of amorphous silicon deposited on a substrate, a silicon-on-insulator (SOI) wafer, and a layer of epitaxial silicon grown on a substrate.

7. The method as claimed in claim 1, wherein the catalyst layer comprises one or more of the following: Au, Pt, Pd, Ru, Ag, Cu, Ni, W, TiN, TaN, RuO2, IrO2 and graphene.

8. The method as described in claim 3, wherein the electrode material comprises polycrystalline silicon, W, TiN, Co, or TaN.

9. The method as described in claim 3, wherein the dielectric comprises HfO2, ZrO2 or Al2O3.

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