Electronic memory device, a method for fabricating an electronic memory device, and a method for revising an IC layout design

Abstract

An electronic memory device includes a non-memory cell region and a memory cell region, which contain circuitry formed in a substrate. The memory cell region includes first, second, and third segments. In a top view, the first segment is closest to the non-memory cell region. The second and third segments are both further away from the non-memory cell region than the first segment. In a cross-sectional side view, a first interconnect structure is disposed on a first side of the substrate. The first interconnect structure includes a first interconnect layer and a second interconnect layer. The first and second interconnect layers are configured to route memory signals to the first and second segments, respectively. A second interconnect structure is disposed on a second side of the substrate. The second interconnect structure includes a third interconnect layer configured to route memory signals to the third segment.

Claims

1. An electronic memory device, comprising: A non-memory cell region includes a non-memory cell circuit at least partially formed in a substrate; a memory cell region includes a memory cell circuit at least partially formed in the substrate, wherein the memory cell region includes at least a first segment, a second segment and a third segment, wherein in a top view, the first segment is closest to the non-memory cell region, and wherein in the top view, the second segment and the third segment are both further away from the non-memory cell region than the first segment; A first interconnect structure, in a cross-sectional side view, is disposed on a first side of the substrate, wherein the first interconnect structure includes at least a first interconnect layer and a second interconnect layer, wherein the first interconnect layer is configured to route a specific type of memory signal from the non-memory cell region to a first segment of the memory cell region, wherein the second interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a second segment of the memory cell region; and a second interconnect structure, in the cross-sectional side view, is disposed on a second side of the substrate, wherein the second side is different from the first side, wherein the second interconnect structure includes at least a third interconnect layer, wherein the third interconnect layer is configured to route the specific type of memory signal from the non-memory cell region to a third segment of the memory cell region.

2. The electronic memory device as described in claim 1, wherein: The electronic memory device includes a static random access memory device; and the specific type of memory signal includes a bit line signal of the static random access memory device.

3. The electronic memory device as claimed in claim 1, wherein: in the top view, the third segment is further away from the non-memory cell region than the second segment; the memory cell region further includes a fourth segment; in the top view, the fourth segment is further away from the non-memory cell region than the third segment; the second interconnect structure further includes a fourth interconnect layer; the fourth interconnect layer is configured to route a specific type of memory signal from the non-memory cell region to the fourth segment of the memory cell region; in the cross-sectional side view, the first interconnect structure further includes an additional interconnect layer disposed between the first interconnect layer and the second interconnect layer; the additional interconnect layer does not include a plurality of conductive elements for routing the specific type of memory signal; and the non-memory cell region includes an input / output circuit as the non-memory cell circuit of the electronic memory device.

4. The electronic memory device as described in claim 1, wherein: The first interconnect layer includes a first conductive element configured to route a specific type of memory signal from the non-memory cell region to the first segment of the memory cell region; the second interconnect layer includes a second conductive element configured to route the specific type of memory signal from the non-memory cell region to the second segment of the memory cell region; the third interconnect layer includes a third conductive element configured to route the specific type of memory signal from the non-memory cell region to the third segment of the memory cell region; in the top view, the third conductive element has a larger lateral dimension than the second conductive element; in the top view, the first conductive element, the second conductive element, and the third conductive element all extend along a first direction; in the top view, in the first direction, the second conductive element has a larger dimension than the first conductive element; In the top view, in the first direction, the third conductive element has a larger size than the second conductive element; and in the top view, in a second direction perpendicular to the first direction, both the second conductive element and the third conductive element have a larger size than the first conductive element.

5. The electronic memory device as described in claim 4, wherein: The first interconnect layer further includes a fourth conductive element located in the second segment of the memory cell region and a fifth conductive element located in the third segment of the memory cell region; the memory cell region further includes a first strip region located between the first segment and the second segment of the memory cell region and a second strip region located between the second segment and the third segment of the memory cell region; the first strip region includes one or more first conductive vias facilitating a routing operation that routes a specific type of memory signal from the second conductive element of the second interconnect layer to the fourth conductive element of the first interconnect layer; and the second strip region includes one or more second conductive vias facilitating a routing operation that routes a specific type of memory signal from the third conductive element of the third interconnect layer to the fifth conductive element of the first interconnect layer.

6. A method for manufacturing an electronic memory device, comprising: A non-memory cell circuit is formed in a first region of a substrate, and a memory cell circuit is formed in a second region of the substrate, wherein in a planar top view, the first region and the second region are arranged adjacent to each other in a first horizontal direction; In a cross-sectional side view, a first interconnect structure is formed on a front side of the substrate, wherein the first interconnect structure includes at least a first interconnect layer and a second interconnect layer disposed on the first interconnect layer, wherein the first interconnect layer includes a first conductive element configured to route a predefined memory signal to a memory cell circuit located in a first segment of a second region, wherein the second interconnect layer includes a second conductive element configured to route the predefined memory signal to a memory cell circuit located in a second segment of a second region; and in the cross-sectional side view, a second interconnect structure is formed on a back side of the substrate, wherein the second interconnect structure includes at least a third interconnect layer, wherein the third interconnect layer includes a third conductive element configured to route the predefined memory signal to a memory cell circuit located in a third segment of a second region, wherein the third segment and the second segment are both further away from the first region than the first segment.

7. A method of manufacturing an electronic memory device as claimed in claim 6, wherein: in the plan view, the first interconnect structure and the second interconnect structure are formed such that, in a second horizontal direction perpendicular to the first horizontal direction, the second conductive element and the third conductive element are wider than the first conductive element; the third segment is further away from the first region than the second segment; and the first interconnect structure and the second interconnect structure are formed such that, in the second horizontal direction, the third conductive element is wider than the second conductive element.

8. A method for modifying integrated circuit layout design, comprising: A first integrated circuit layout design for accessing an electronic memory device, wherein the first integrated circuit layout design includes: a non-memory cell region; a memory cell region disposed adjacent to the non-memory cell region in a first horizontal direction; a first signal line extending from the non-memory cell region to the memory cell region in the first horizontal direction, wherein the first signal line extends through a large portion of the memory cell region in the first horizontal direction; and a modification operation performing a modification of the first integrated circuit layout design to a second integrated circuit layout design, wherein the modification operation includes configuring at least a second signal line and a third signal line such that, in the first horizontal direction, the second signal line and the third signal line extend from the non-memory cell region to different portions of the memory cell region, wherein the second signal line and the third signal line are configured to carry a signal of the same type as that of the first signal line, and the second signal line and the third signal line are disposed on a plurality of interconnect layers different from the first signal line.

9. A method for modifying an integrated circuit layout design as described in claim 8, wherein: the modification operation performed on the first integrated circuit layout design is such that, in a second horizontal direction, both the second signal line and the third signal line are configured to have a width greater than that of the first signal line, wherein the second horizontal direction is different from the first horizontal direction; the modification operation performed on the first integrated circuit layout design is such that, in the first horizontal direction, the third signal line has a larger size than that of the second signal line; and the modification operation of the first integrated circuit layout design further includes configuring one or more strip regions in the memory cell region, the one or more strip regions being configured to route multiple electrical signals from the second signal line or the third signal line to the first signal line.

10. A method for modifying the layout design of integrated circuits as described in claim 8, wherein: In the first integrated circuit layout design and the second integrated circuit layout design, the first signal line is disposed in a first interconnect layer of the front interconnect structure of one of the electronic memory devices; and in the second integrated circuit layout design, the second signal line is disposed in a second interconnect layer of the front interconnect structure, which is different from the first interconnect layer, and the third signal line is disposed in a third interconnect layer of the back interconnect structure of one of the electronic memory devices.

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