Electronic device and a method for forming the same

Abstract

This application provides an electronic device comprising: a packaging substrate; two intermediates disposed on the packaging substrate; an electronic component mounted on the two intermediates for electrical coupling to the packaging substrate via the two intermediates; a mold cover formed on the packaging substrate and including two sets of interconnects extending through the mold cover and each set of interconnects being electrically coupled to one of the two intermediates; two semiconductor dies mounted on the mold cover and the electronic component to form a gap between the two semiconductor dies and above the electronic component, wherein each of the two semiconductor dies is electrically coupled to one of the two intermediates via one set of interconnects; and a heat sink attached to and thermally coupled to the two semiconductor dies, wherein a portion of the heat sink extends downward into the gap for thermal coupling to the electronic component.

Description

[Technical Field]

[0001] This application generally relates to semiconductor technology, and more specifically, to an electronic device and a method for forming the electronic device. [Previous Technology]

[0002] The semiconductor industry has always faced complex integrated challenges as consumers demand smaller, faster, and higher-performing electronic devices, and increasingly more functionality packaged into a single device. In recent years, System-on-a-Chip (SOC) modules have been widely used in integrated electronic devices. Typically, in high-performance devices, SOC modules can be packaged with various semiconductor modules, such as memory dies, to provide better performance and more functionality.

[0003] Therefore, there is a need for an electronic device with improved integration level, heat dissipation capability and various electronic modules. [Summary of the Invention]

[0004] The purpose of this application is to provide an electronic device with improved integration level, heat dissipation capability and various electronic modules.

[0005] According to one aspect of this application, an electronic device is provided. The electronic device includes: a packaging substrate; two intermediates disposed on the packaging substrate; an electronic element mounted on the two intermediates for electrical coupling to the packaging substrate via the two intermediates; a mold cover formed on the packaging substrate to enclose the two intermediates and expose the electronic element, wherein the mold cover includes two sets of interconnects extending through the mold cover and each set of interconnects is electrically coupled to one of the two intermediates; two semiconductor dies mounted on the mold cover and the electronic element to form a gap between the two semiconductor dies and above the electronic element, wherein each of the two semiconductor dies is electrically coupled to one of the two intermediates via one set of interconnects; and a heat sink attached to and thermally coupled to the two semiconductor dies, wherein a portion of the heat sink extends downward into the gap for thermal coupling to the electronic element.

[0006] According to another aspect of this application, a method for forming an electronic device is provided. The method includes: providing a packaging substrate; placing two interposers on the packaging substrate; mounting electronic components on the two interposers; forming a mold cover on the packaging substrate to enclose the two interposers and expose the electronic components; forming two sets of interconnects through the mold cover to electrically couple each of the two sets of interconnects to one of the two interposers; mounting two semiconductor dies on the mold cover and the electronic components to form a gap between the two semiconductor dies and above the electronic components, wherein each of the two semiconductor dies is electrically coupled to one of the two interposers via one of the two sets of interconnects; and attaching a heat sink to the two semiconductor dies to thermally couple the heat sink to the two semiconductor dies, wherein a portion of the heat sink extends downward into the gap to thermally couple with the electronic components.

[0007] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the invention. Furthermore, the drawings incorporated in and forming a part of this specification illustrate embodiments of the invention and, together with this specification, serve to explain the principles of the invention.

Implementation Method

[0012] The following detailed description of exemplary embodiments of this application refers to the drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art may further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of this application.

[0013] In this application, unless otherwise expressly stated, the use of the singular includes the plural form. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" is not restrictive. Additionally, unless otherwise expressly stated, terms such as "element" or "assembly" cover both elements and assemblies comprising one unit and elements and assemblies comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0014] As used herein, for ease of description, spatial relative terms such as “below,” “below,” “above,” “upper,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” and “side” may be used to describe the relationship between an element or feature and another element (or feature) or feature (or feature), as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0015] As mentioned above, in some high-performance devices, SOC modules can be packaged in conjunction with various semiconductor modules, such as memory dies, to provide better performance and versatility. Recently, 2.5D electronic packaging has been widely adopted due to its smaller size compared to conventional 2D electronic packaging. Typically, a 2.5D electronic package includes an interposer attached to a package substrate for mounting SOC modules and memory dies side-by-side on it, so as to electrically couple the SOC module to the memory die via the interposer. However, the package size and heat dissipation capabilities of this 2.5D electronic package still need improvement in order to integrate more components in a single semiconductor device.

[0016] To address this problem, in some embodiments, a novel electronic device is provided. The electronic device includes two semiconductor dies mounted on an electronic component, each of the two semiconductor dies overlapping a portion of the electronic component to form a gap between the two semiconductor dies. The electronic device also includes a heat sink thermally coupled to the two semiconductor dies, a portion of which extends downward into the corresponding gap, allowing the heat sink to be thermally coupled to the electronic component. Therefore, the volume level and heat dissipation capability of this electronic package can be improved, thereby achieving better performance.

[0017] Figures 1A to 1E illustrate the various steps of an electronic device according to a first embodiment of this application and a method for forming the electronic device. The electronic device formed using the method is shown in Figure 1E.

[0018] As shown in FIG1A, the package substrate 100 has embedded interconnects (not shown). The package substrate 100 includes a top surface and a bottom surface opposite to each other. The top surface of the package substrate 100 can serve as a platform on which electronic modules can be mounted. In some embodiments, the semiconductor package can be a double-sided molding (DSM) package, and therefore, the bottom surface can also serve as another platform on which other electronic modules can be mounted or attached. Multiple sets of conductive pads (not shown) can be formed on the top surface and / or bottom surface of the package substrate 100 for mounting electronic modules. It is understood that the multiple sets of conductive pads can be exposed portions of interconnects embedded within the package substrate 100. In some embodiments, the package substrate 100 may include a printed circuit board.

[0019] Next, two intermediaries 101 are placed on the top surface of the packaging substrate 100. More specifically, the two intermediaries 101 are placed side by side on the top surface of the packaging substrate 100, and in some embodiments, the top surfaces of the two intermediaries 101 are flush with each other to form a flat plane above the packaging substrate 100. As shown in FIG1A, the two intermediaries 101 may form a gap between them and above the packaging substrate 100. In some embodiments, the two intermediaries 101 may each provide an electrical connection between various electronic modules mounted on the intermediaries 101 in subsequent processes to reduce the distance between the various electronic modules. In some embodiments, each of the two intermediaries 101 may include at least one conductive line (not shown) surrounded by an intermediary substrate. The intermediary substrate may contain a dielectric material such as silicon dioxide or a semiconductor material such as silicon, or may contain other dielectric materials such as epoxy resin or similar polymers or dielectric materials. Each of the conductive lines may have a first conductive pad at one end and a second conductive pad at the other end, both of which are exposed from the top surface of the interposer 101, wherein a main segment connecting the two ends extends and is embedded in the interposer substrate. In some embodiments, each of the two interposers 101 may include two or more conductive lines, depending on the number of pads on the electronic module attached to the interposer 101 and requiring electrical connection to other components. Furthermore, each of the two interposers 101 may include additional connection structures to enable the interposer 101 to be electrically coupled to interconnects within the package substrate 100 via additional electrical connections, such as conductive posts between the interposer 101 and the package substrate 100.

[0020] As shown in FIG. 1B, electronic component 102 is mounted on two interposers 101 via solder bumps and is thus electrically coupled to package substrate 100 via the two interposers 101. More specifically, electronic component 102 is mounted on at least a portion of the front surface of each of the two interposers 101 and is thus positioned across the gap between the two interposers 101. In the embodiment shown in FIG. 1B, electronic component 102 includes a potentially large system-on-a-chip (SOC) device. In some other embodiments, electronic component 102 may include other electronic modules, such as a central processing unit (CPU) module, a graphics processing unit (GPU) module, or other pre-molded electronic packages. As mentioned above, in some embodiments, the two interposers 101 are flush with each other, and therefore electronic component 102 can be supported on the interposers 101 without significant tilting relative to package substrate 100.

[0021] Next, a mold cap 110 is formed on the packaging substrate 100 to encapsulate the two intermediaries 101 and the electronic component 102, but exposing the front surface of the electronic component 102. In some embodiments, the mold cap 110 is formed using a molding technique such as injection molding, which covers the respective top surfaces of the electronic component 102 and the two intermediaries 101 for encapsulation. More specifically, a molding material can be applied to the packaging substrate 100, which fills the gap between the two intermediaries 101 and covers the electronic component 102 and the two intermediaries 101. The molding material can then be heated and cured, thus forming the mold cap 110, which has a protrusion 103a extending downward onto the packaging substrate 100 and between the two intermediaries 101. Thus, the two intermediaries 101 and the electronic component 102 can be encapsulated by the mold cap 110 and secured at specific locations on the packaging substrate 100. In some embodiments, the molding material includes epoxy resin, polyester resin, or any other suitable material. In some other embodiments, the mold cover 110 may be formed using various other molding techniques, including transfer molding, compression molding, or film-assisted molding (FAM). Optionally, the intermediate element 101 and the electronic component 102 may be overmolded, wherein an excess portion of the molding material is formed over the electronic component 102. In this case, the mold cover 110 may be subjected to a grinding process to remove the excess portion of the mold cover 110 over the electronic component 102 until the front surface of the electronic component 102 is exposed.

[0022] Subsequently, as shown in FIG1C, two sets of interconnects 121 are formed through the mold cover 110 and surround the electronic element 102 at two opposite sides of the electronic element 102. The interconnects 121 are electrically coupled to the two intermediaries 101. In this embodiment, each set of the two sets of interconnects 121 may include two or more conductive vias mounted on one of the two intermediaries 101. More specifically, the formation process of the conductive vias may include the following steps. First, two sets of through holes are formed within the mold cover 110. Each set of the two sets of through holes is aligned with one of the two intermediaries 101, and each set of through holes may include two or more through holes, each through hole exposing the top surface of one of the two intermediaries 101. The through holes may be formed using laser ablation or techniques such as etching, milling, drilling, clamping, or combinations thereof. Next, each of the through holes may be filled with a conductive material such as silver or copper to form a corresponding conductive via through the mold cover 110. Through-holes or vias can be aligned with corresponding conductive pads or other similar structures on the intermediaries 101 so that the conductive vias are electrically coupled to the two intermediaries 101. In the embodiment shown in FIG. 1C, each of the two intermediaries 101 is electrically coupled to two conductive vias (i.e., a set of interconnects 121) for further connection of additional electronic modules thereon. In some other embodiments, depending on the actual layout of the electronics, each of the two sets of interconnects 121 may include more than two conductive vias. In some embodiments, planarization processes such as mechanical polishing or chemical mechanical polishing techniques may be implemented to achieve a flat top surface of the conductive vias for uniform mounting of subsequent additional electronic modules thereon.

[0023] Subsequently, as shown in FIG1D, two semiconductor dies 131 are mounted on the mold cover 110 and the electronic component 102. In some embodiments, the two semiconductor dies 131 may have the same height, so their top surfaces may be flush with each other. In some other embodiments, the top surfaces of the semiconductor dies 131 may not be flush with each other. Each of the two semiconductor dies 131 is electrically coupled to one of the two interposers 101 via one of the two sets of interconnects 121. Thus, the two semiconductor dies 131 and the electronic component 102 can be electronically connected via the two sets of interconnects 121 and the two interposers 101. Furthermore, the two semiconductor dies 131 and the electronic component 102 may also be electrically coupled to interconnects within the package substrate 100 to form an integrated circuit device. The design of the two interposers 101 that electrically couple the two semiconductor dies 131 and the electronic component 102 is flexible and can be placed at any location on the package substrate 100 depending on the layout of the electronic device. In some embodiments, each of the two semiconductor dies 131 may include a memory die, such as a high-bandwidth memory die. In some other embodiments, each of the two semiconductor dies 131 may include a logic die. It is understood that additional semiconductor dies 131 may be mounted on the mold cover 110 and the electronic component 102. For example, one or more semiconductor dies 131 may be mounted on the mold cover 110 and optionally on the electronic component 102, and electrically coupled to the package substrate 102 via one of the intermediaries 101.

[0024] In this embodiment, two semiconductor dies 131 are arranged around the electronic component 102, and each of the two semiconductor dies 131 overlaps a portion of the electronic component 102. In this way, a gap is formed between the two semiconductor dies 131 and exposes the front surface of the electronic component 102. The size of the gap can be determined based on the size of the two semiconductor dies 131, the size of the electronic component 102, and the total working area designed for the electronic device. Compared to conventional 2.5D electronic packages where the electronic component and semiconductor dies are mounted side-by-side on an interposer, the overlap area between the two semiconductor dies 131 and the electronic component 102 helps the electronic device achieve a smaller size and a higher level of integration. In other words, a larger overlap area between the two semiconductor dies 131 and the electronic component 102 allows for a smaller package size for the electronic device. In some embodiments, the two semiconductor dies 131 are mounted to the front surface of two sets of interconnects 121 via solder bumps or other conductive structures. Next, an underfill 130 is formed between the bottom surfaces of the two semiconductor dies 131 and the top surfaces of the mold cover 110 and the electronic component 102 to bond the semiconductor dies 131, the mold cover 110 and the electronic component 102 together.

[0025] In some other embodiments, two additional semiconductor dies may be further mounted onto two semiconductor dies 131, each of which may overlap a portion of a corresponding semiconductor die 131 below the additional semiconductor die. Each of the two additional semiconductor dies may also be electrically coupled to one of the two interposers 101 via an additional set of interconnects. In this way, the integration level of the electronic device can be further improved.

[0026] It is also understood that at least one additional interposer may be further placed on the package substrate 100. Furthermore, at least one additional set of interconnects may be mounted on the at least one additional interposer. At least one additional semiconductor die may be attached to the at least one additional set of interconnects for electrical coupling to the at least one interposer, and the at least one additional semiconductor die may be placed at the same level as the two semiconductor dies 131. In other words, more interposers, multiple sets of interconnects, and semiconductor dies may be mounted on the package substrate 100 in a similar manner to the interposer 101, multiple sets of interconnects 121, and semiconductor die 131 shown in FIG. 1D.

[0027] Subsequently, as shown in FIG1E, a thermal interface material 140 is formed on the top surfaces of the two semiconductor dies 131 and a portion of the electronic component 102. The thermal interface material 140 may include thermal paste, thermal adhesive (e.g., metal oxide, carbon black, carbon nanotubes), phase change material, or metallic thermal interface material (e.g., indium alloy and sintered silver). The thermal interface material 140 can improve the heat transfer effect from the electronic component 102 and the two semiconductor dies 131 to the functional module attached thereto.

[0028] Next, the heat sink 160 is attached to the two semiconductor dies 131 and the electronic component 102. More specifically, the heat sink 160 includes a base portion 160b attached to the two semiconductor dies 131 via a thermal interface material 140, and a head portion 160a extending downward from the base portion 160b into a gap (defined by the space between the two semiconductor dies 131) to be attached to the electronic component 102 via the thermal interface material 140. Thus, both the semiconductor dies 131 and the electronic component 102 can be thermally coupled to the heat sink 160. In this way, both the semiconductor dies 131 and the electronic component 102 are in direct contact with the heat sink 160 via the thermal interface material 140 to allow for more efficient heat transfer. In this way, despite the height difference between the electronic component 102 and the semiconductor dies 131, the heat generated from both the semiconductor dies 131 and the electronic component 102 can be dissipated outside the electronic device by the heat sink 160 and the thermal interface material 140. Therefore, it is possible to form an electronic device 170 with a smaller size and improved heat dissipation capabilities.

[0029] In some other embodiments, the electronic component 102 (e.g., a system-on-a-chip (SOC) module, a central processing unit (CPU) module, or a graphics processing unit (GPU) module) may generate more heat than the semiconductor die 131. In the embodiment shown in FIG1E, the heat sink 160 has a uniform structure and the same material in both the base portion 160b and the head portion 160a. The head portion 160a and the base portion 160b may be integrally formed heat sink 160. The integral heat sink 160 may be pre-formed to match the shape of the semiconductor die 131 and the electronic component 102. In some other embodiments, the head portion 160a may have a different structure than the base portion 160b to compensate for the difference in heat generated between the semiconductor die 131 and the electronic component 102. For example, the head portion 160a may be structurally configured to have a higher heat dissipation efficiency than the base portion 160b to dissipate more heat away from the electronic component 102 over a period of time. In some other embodiments, the head portion 160a and the base portion 160b may comprise different materials. For example, the material of the head portion 160a may have a greater thermal conductivity than the material of the base portion 160b. In this case, the head portion 160a may be formed first on the electronic component 102, and then the base portion 160b may be formed on the two semiconductor dies 131 and the head portion 160a.

[0030] Furthermore, as shown in FIG1E, the size of the head portion 160a can be smaller than the gap between the two semiconductor dies 131, thereby leaving two openings or channels 150, each of which is arranged between the lateral surface of the head portion 160a and the lateral surface of one of the two semiconductor dies 131. The openings 150 can provide space for the expansion of the heat sink 160 when heat is generated, thereby preventing damage to the electronic device due to thermal expansion. It is also understood that a flexible film can be formed between each of the two semiconductor dies 131 and the head portion 160a, the flexible film providing a buffer for the expansion of the heat sink 160. In some other embodiments, the size of the head portion 160a can be the same as the size of the gap between the two semiconductor dies 131.

[0031] In some embodiments, the electronic device can be applied in packages that require smaller size and higher heat dissipation capabilities, particularly highly integrated packages with high-performance modules such as system-on-a-chip (SOC) modules, central processing (CPU) modules, graphics processing (GPU) modules, or high bandwidth memory (HBM), which may have high power consumption and generate a large amount of heat during operation.

[0032] Figures 2A to 2E illustrate the various steps of an electronic device according to a second embodiment of this application and a method for forming the electronic device. The electronic device formed using the method is shown in Figure 2E.

[0033] As shown in FIG. 2A, the packaging substrate 200 has embedded interconnects. Next, a portion of the packaging substrate 200 is removed using techniques such as laser ablation or etching, milling, drilling, clamping, or combinations thereof to form two cavities within the packaging substrate 200. Next, two intermediaries 201 are placed in the two cavities respectively, and the two intermediaries are electrically coupled to the packaging substrate 200. The front surfaces of the two intermediaries 201 and the front surface of the packaging substrate 200 are flush with each other to uniformly mount additional modules thereon. The two intermediaries 201 embedded in the cavities of the packaging substrate 200 can utilize the thickness of the packaging substrate 200, thus further contributing to reducing the height of the electronic device and increasing the integration level.

[0034] Subsequently, as shown in FIG2B, the electronic component 202 is mounted on the two intermediate members 201 via solder bumps. More specifically, the electronic component 202 is mounted on at least a portion of the front surface of each of the two intermediate members 201 and spans the gap between the two intermediate members 201. Next, a mold cap 210 is formed on the front surface of the package substrate 200 and the front surfaces of the two intermediate members 201 to enclose the two intermediate members 201 and the electronic component 202, but exposes the front surface of the electronic component 202.

[0035] Subsequently, as shown in FIG2C, two sets of interconnects 221 are formed through the mold cover 210 to electrically couple each of the two sets of interconnects 221 to one of the two intermediaries 201. In this embodiment, each of the two sets of interconnects 221 may include two conductive vias mounted on one of the two intermediaries 201. In some other embodiments, depending on the actual layout of the electronics, each of the two sets of interconnects 221 may include one or more conductive vias.

[0036] Subsequently, as shown in FIG2D, two semiconductor dies 231 are mounted on the mold cover 210 and the electronic component 202 via the underfill 230 to form a gap between the two semiconductor dies 231 and above the electronic component 202, and each of the two semiconductor dies 231 is electrically coupled to one of the two interposers 201 via one of the two sets of interconnects 221. Therefore, the two semiconductor dies 231 and the electronic component 202 can be electronically connected via the two sets of interconnects 221 and the two interposers 201. In addition, the two semiconductor dies 231 and the electronic component 202 can also be electrically coupled to interconnects within the package substrate 200 to form an integrated circuit device.

[0037] Subsequently, as shown in FIG2E, a thermal interface material 240 is formed on the top surfaces of the two semiconductor dies 231 and the top surface of the electronic component 202. Next, a heat sink 260 is attached to the two semiconductor dies 231 and the electronic component 202. More specifically, the heat sink 260 includes a base portion 260b attached to the two semiconductor dies 231 via the thermal interface material 240, and a head portion 260a extending downward from the base portion 260b into a gap for attachment to the electronic component 202 via the thermal interface material 240. Thus, both the semiconductor dies 231 and the electronic component 202 can be thermally coupled to the heat sink 260 to achieve higher heat dissipation efficiency. In this way, an electronic device 270 with a smaller size and higher heat dissipation capacity is formed.

[0038] In some other embodiments, two additional semiconductor dies may be further mounted onto two semiconductor dies 231, each of which may overlap a portion of a corresponding semiconductor die 231 below the additional semiconductor die. Each of the additional semiconductor dies may also be electrically coupled to one of the two interposers 201 via an additional set of interconnects.

[0039] The details of the formation process and structure of the electronic device can be similar to those shown in the formation process and structure of the electronic device illustrated in Figures 1A to 1E, and will not be described in detail here for the sake of simplicity.

[0040] Although an exemplary method for forming an electronic device of this application has been described in conjunction with the corresponding figures, those skilled in the art will understand that the method for forming an electronic device can be modified and adapted without departing from the scope of the invention.

[0041] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented, without departing from the broad scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art from the description and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that this application and the examples herein be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended. [Simplified Explanation of the Diagram]

[0008] The drawings referenced herein form part of this specification. The features shown in the drawings are only illustrative of some embodiments of this application, and not all embodiments of this application, unless the detailed description clearly indicates otherwise, and the reader of this specification should not infer the contrary.

[0009] Figures 1A to 1E illustrate the various steps of an electronic device and a method for forming an electronic device according to a first embodiment of this application.

[0010] Figures 2A to 2E illustrate the various steps of an electronic device and a method for forming an electronic device according to a second embodiment of the present application.

[0011] Use the same diagram number to refer to the same or similar parts throughout the diagram.

Claims

1. An electronic device, the electronic device comprising: One packaging substrate; Two intermediary components are placed on the packaging substrate; An electronic component mounted on the two intermediates for electrical coupling to the package substrate via the two intermediates; a mold cover formed on the package substrate to enclose the two intermediates and expose the electronic component, wherein the mold cover includes two sets of interconnects extending through the mold cover and each set of interconnects is electrically coupled to one of the two intermediates. Two semiconductor dies are mounted on the mold cover and the electronic component to form a gap between the two semiconductor dies and above the electronic component, wherein each of the two semiconductor dies is electrically coupled to one of the two intermediates via one of the two sets of interconnects. And a heat sink attached to and thermally coupled to the two semiconductor dies, wherein a portion of the heat sink extends downward into the gap to thermally couple with the electronic component.

2. The electronic device according to claim 1, wherein, The two intermediate members are placed side by side on the packaging substrate and have a top surface that is flush with each other to support the electronic components thereon.

3. The electronic device according to claim 2, wherein, The packaging substrate includes two cavities, each of which receives one of the two intermediaries.

4. The electronic device according to claim 2, wherein, The mold cover includes a protrusion that extends downward onto the packaging substrate and is located between the two intermediaries.

5. The electronic device according to claim 1, wherein, The electronic components include system-on-a-chip devices.

6. The electronic device according to claim 1, wherein, Each of the two semiconductor dies includes a memory die.

7. The electronic device according to claim 1, wherein, Each of the two sets of interconnects includes at least one conductive via.

8. The electronic device according to claim 1, wherein, Each of the two semiconductor dies overlaps with a portion of the electronic component.

9. A method for forming an electronic device, the method comprising: Provide a packaging substrate; Two intermediate components are placed on the packaging substrate; An electronic component is installed on the two intermediate components; A mold cover is formed on the packaging substrate to encapsulate the two intermediate components and expose the electronic components; two sets of interconnects are formed through the mold cover to electrically couple each of the two sets of interconnects to one of the two intermediate components. Two semiconductor dies are mounted on the mold cover and the electronic component to form a gap between the two semiconductor dies and above the electronic component, wherein each of the two semiconductor dies is electrically coupled to one of the two intermediates via one of the two sets of interconnects. And attaching a heat sink to the two semiconductor dies to thermally couple the heat sink to the two semiconductor dies, wherein a portion of the heat sink extends downward into the gap to thermally couple with the electronic component.

10. The method according to claim 9, wherein, The process of placing two intermediaries on the packaging substrate includes: placing the two intermediaries side by side on the packaging substrate such that the top surfaces of the two intermediaries are flush with each other.

11. The method according to request item 10, wherein, Before placing two intermediaries on the packaging substrate, the method further includes: forming two cavities within the packaging substrate, each of the two cavities being used to receive one of the two intermediaries.

12. The method according to request item 10, wherein, Forming a mold cover on the packaging substrate further includes: forming the mold cover having a protrusion that extends downward onto the packaging substrate and is located between the two intermediaries.

13. The method according to claim 9, wherein, Each of the two sets of interconnects includes at least one conductive via, and the process of forming the two sets of interconnects through the mold cover includes: etching the mold cover to form two sets of through holes within the mold cover, such that each set of through holes includes at least one through hole and exposes the top surface of one of the two intermediates; and filling the two sets of through holes with a conductive material to form a plurality of conductive vias through the mold cover.

14. The method according to claim 9, wherein, The electronic components include system-on-a-chip devices.

15. The method according to claim 9, wherein, Each of the two semiconductor dies includes a memory die.

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