Semiconductor device and methods of forming the same

Abstract

A method includes the following steps: forming a conductive feature adjacent to a source / drain region; exposing a first surface of the conductive feature and the first surface of the source / drain region; forming a metal oxide layer on the conductive feature and a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein removing the silicon oxide layer exposes a second surface of the source / drain region; forming a silicate region on the second surface of the source / drain region; removing the metal oxide layer, wherein removing the metal oxide layer exposes a second surface of the conductive feature; and depositing a first conductive material on the silicate region and the second surface of the conductive feature.

Claims

1. A method of forming a semiconductor device, comprising: forming a source / drain region; forming a contact etch-stop layer over the source / drain region; forming an interlayer dielectric layer over the contact etch-stop layer; forming a first contact plug in the interlayer dielectric layer and the contact etch-stop layer; performing a first etching process to form an opening in the interlayer dielectric layer and the contact etch-stop layer, wherein the opening exposes a plurality of surfaces of the source / drain region and a plurality of surfaces of the first contact plug, wherein the opening exposes a metal oxide layer on the first contact plug; and performing a siliconization process to form a siliconization region on a surface of the source / drain region. A second etching process is performed to remove the metal oxide layer; and a second contact plug is formed in the opening, wherein the second contact plug is electrically connected to the silicate region and the first contact plug, wherein a conductivity of the silicate region is between a conductivity of the source / drain region and a conductivity of the second contact plug.

2. The method as described in claim 1 further includes depositing a self-assembling material over the first contact plug prior to performing the silicate formation process.

3. The method as described in claim 1, wherein the second etching process is performed prior to the silicate formation process.

4. A method of forming a semiconductor device, comprising: forming a conductive feature adjacent to a source / drain region; exposing a first surface of the conductive feature and a first surface of the source / drain region; forming a metal oxide layer on the conductive feature and a silicon oxide layer on the source / drain region; removing the silicon oxide layer, wherein removing the silicon oxide layer exposes a second surface of the source / drain region; forming a silicate region on the second surface of the source / drain region; removing the metal oxide layer, wherein removing the metal oxide layer exposes a second surface of the conductive feature; and depositing a first conductive material on the silicate region and the second surface of the conductive feature.

5. The method as described in claim 4, wherein forming the silicate region also removes the metal oxide layer.

6. The method as described in claim 4, wherein depositing the first conductive material also removes the metal oxide layer.

7. The method as described in claim 4, wherein the formation of the silicate region also forms a residual layer over the metal oxide layer.

8. A semiconductor device comprising: a lower transistor including a lower source / drain region; a higher transistor including an upper source / drain region; a vertical interconnect extending to the lower source / drain region and the upper source / drain region; a silicide region located on the upper source / drain region; a first metal overlay layer located on the silicide region; a second metal overlay layer located on the vertical interconnect; and a metal filler layer covering the first metal overlay layer and the second metal overlay layer.

9. The semiconductor device as claimed in claim 8, wherein an interface between the second metal overlay layer and the vertical interconnect is free of metal oxide.

10. The semiconductor device as claimed in claim 8, wherein the silicon region extends between the second metal overlay material layer and the vertical interconnect.

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