Semiconductor memory device and refresh control method thereof

Abstract

A semiconductor memory device, a column redundancy circuit, and a control method thereof are provided to suppress unnecessary power consumption. The semiconductor memory device includes: an array of memory cells having multiple segments, each segment having multiple ordinary word lines and multiple redundant word lines; and a column redundancy circuit configured to activate non-defective ordinary word lines and non-defective redundant word lines during a refresh operation; wherein activation and replacement of defective ordinary word lines and defective redundant word lines are not performed in each segment.

Description

[Technical Field]

[0001] This invention relates to a semiconductor memory device and a control method thereof, and particularly to a semiconductor memory device and a refresh control method thereof that improves power consumption during refresh operations. [Previous Technology]

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device that stores information by storing charge in capacitors. It is a volatile memory that loses its stored information when power is no longer supplied. Because DRAM memory cells use the amount of charge stored in capacitors to store information, a refresh operation must be performed periodically to prevent information loss due to leakage current. In other words, all memory cells need to be refreshed before information is lost due to leakage current, and the refresh cycle is determined by the specifications.

[0003] In recent years, with the miniaturization of DRAM manufacturing processes, the capacity of memory cells has also decreased, and the retention time in each memory cell has tended to be shortened. Therefore, as disclosed in U.S. Patent Publication No. 9,269,458 (hereinafter referred to as Patent Document 1), in many DRAMs, the number of refresh operations is reduced by activating (enabling) more word lines simultaneously during refresh operations than during normal operations (startup operations).

[0004] Patent Document 1 discloses a semiconductor device having a redundancy determination circuit. In response to at least one ordinary memory cell belonging to the first and second memory blocks being replaced by a redundant memory cell in a refresh mode, the redundancy determination circuit sets the ordinary cell region of the aforementioned ordinary memory cell belonging to the replacement source to be inactive, and sets the redundant memory cell region to which the redundant memory cell to which the replacement target belongs and the ordinary memory cell region to which the unreplaced ordinary memory cell belongs to be active.

[0005] However, during the refresh operation of this semiconductor device, it is prohibited to select ordinary memory cells that belong to the same memory mat as the redundant memory cell to be replaced. However, if the redundant memory cell region containing the redundant memory cell to be replaced and the ordinary memory cell region to which the ordinary memory cell to be replaced is activated at the same time during the refresh operation, it will lead to an unnecessary increase in power consumption. [Summary of the Invention]

[0006] In view of the above problems, the object of the present invention is to provide a semiconductor memory device and a refresh control method thereof that can suppress unnecessary power consumption during refresh operation.

[0007] The semiconductor memory device of the present invention includes: an array of memory cells having multiple segments, each segment having multiple ordinary character lines and multiple redundant character lines; and a column redundancy circuit configured to activate non-defective characters among the ordinary character lines and non-defective characters among the redundant character lines during a refresh operation; wherein activation and replacement of defective characters among the ordinary character lines and defective characters among the redundant character lines are not performed in each segment.

[0008] The column redundancy circuit of the present invention controls the activation and deactivation of ordinary character lines and redundant character lines of a memory cell array, wherein the memory cell array has multiple segments, each segment having multiple ordinary character lines and multiple redundant character lines; wherein the column redundancy circuit is configured to: during a refresh operation, sequentially activate the aforementioned ordinary character lines or the aforementioned redundant character lines in each of the aforementioned segments one by one, so that multiple of the aforementioned ordinary character lines or the aforementioned redundant character lines are activated; and, during the aforementioned refresh operation, if the aforementioned ordinary character line or the aforementioned redundant character line to be activated is defective, the aforementioned ordinary character line or the aforementioned redundant character line is not activated in the aforementioned segment containing the ordinary character line or the aforementioned redundant character line, nor is any other aforementioned ordinary character line or the aforementioned redundant character line replaced.

[0009] The control method of the semiconductor memory device of the present invention includes: configuring a memory cell array to include a plurality of segments, each segment having a plurality of ordinary character lines and a plurality of redundant character lines; during a refresh operation, activating defective ordinary character lines and defective redundant character lines by means of a column redundancy circuit, wherein activation and replacement of defective ordinary character lines and defective redundant character lines are not performed in each segment.

[0010] The semiconductor memory device and refresh control method of the present invention can suppress unnecessary power consumption during refresh operation by not activating or replacing defective word lines during refresh operation.

Implementation Method

[0012] Hereinafter, the control circuit and semiconductor memory device related to embodiments of the present invention will be described with reference to the drawings. However, these embodiments are merely examples and are not intended to limit the scope of the present invention. It should be noted that when the same constituent elements are distinguished by position, etc., "_n" (n is an integer) will be added after the reference symbol for distinction.

[0013] Figure 1 shows a configuration example of a semiconductor memory device according to a first embodiment of the present invention. In this embodiment, the semiconductor memory device 1 (e.g., DRAM) includes row redundancy circuitry 10. Furthermore, in this embodiment, for the sake of simplicity, conventional configurations provided in the semiconductor memory device (e.g., address buffers, command decoders, row decoders, input / output interface units, etc.) are not shown.

[0014] The semiconductor memory device 1 may include a memory cell array 2, a control circuit 3, a column redundancy circuit 10, and a column decoder 4. Furthermore, the structure of the memory cell array 2 will be described later.

[0015] The control circuit 3 synchronizes with the internal clock signal to generate various control signals, performs read / write operations on the memory cell array 2, and uses the column redundancy circuit 10 to control the semiconductor memory device. Furthermore, in this embodiment, the start-up and refresh operations via the column redundancy circuit 10 are primarily described. The control circuit 3 outputs a refresh status signal REF, indicating the refresh operation state, to the column redundancy circuit 10, and activates the refresh status signal REF to a high level during the refresh operation.

[0016] Furthermore, the control circuit 3 internally includes an address circuit (not shown) to generate an address signal RA indicating the column address and a redundancy enable signal RWL_EN. The redundancy enable signal RWL_EN is used to activate the redundant word lines; when the redundancy enable signal RWL_EN is activated (high level), the redundant word lines can be activated. The control circuit 3 outputs the address signal RA and the redundancy enable signal RWL_EN to the column redundancy circuit 10.

[0017] The column redundancy circuit 10 of this embodiment is configured to control the activation / deactivation of the ordinary character lines and redundant character lines of the memory cell array 2. The column redundancy circuit 10 generates a disable signal HIT and a select signal RWLSEL based on the refresh status signal REF, the address signal RA, and the redundancy enable signal RWL_EN. The disable signal HIT is used to deactivate the ordinary character lines. When a high-level disable signal HIT is generated, activation of the ordinary character lines is disabled, thus the ordinary character lines are deactivated (low level). The select signal RWLSEL is used to replace ordinary character lines with redundant character lines. When the select signal RWLSEL is generated at a high level, the redundant character line receiving this high-level select signal RWLSEL is activated (high level).

[0018] The memory cell array 2 is illustrated in Figure 2. Please note that although specific numbers are used in the following description, the invention is not limited thereto. The memory cell array 2 is composed of word lines extending along a first direction and column lines extending along a second direction perpendicular to the first direction, and these lines together constitute memory cells. Each word line and column line may be provided with redundant word lines and redundant column lines for backup, so that repair can be performed on a word line or column line basis in the event of a fault. Furthermore, bit lines are formed along the column lines, and these bit lines connect to multiple memory cells. Please note that detailed drawings of the bit lines and memory cells are omitted in the figure.

[0019] The memory cell array 2 is divided into multiple segments 5. Each segment 5 includes a first predetermined number of ordinary character lines and a second predetermined number of redundant character lines, wherein the first predetermined number is greater than the second predetermined number. In this embodiment, the memory cell array 2 has 32,756 ordinary character lines and 256 redundant character lines, and is composed of four segments 5. Each segment 5 includes ordinary character lines and redundant character lines (collectively referred to as character lines), and is configured such that only one character line is activated during a refresh operation. Furthermore, these segments 5 are configured to have the same number of ordinary character lines and the same number of redundant character lines.

[0020] Each segment 5 may consist of 8 column blocks RBLK. A column block RBLK is a region of bit lines shared by the word lines of the memory cell array 2, sandwiched between the sense amplifiers SA. There are 32 column blocks RBLK00 to RBLK31, each consisting of 1024 ordinary word lines and 8 redundant word lines. The number of redundant word lines in each column block RBLK is not limited, as long as they are evenly distributed in each segment 5. That is, in this embodiment, each segment 5 includes 8244 ordinary word lines and 64 redundant word lines, but they can be evenly distributed to each column block RBLK, or, for example, in segment 5_0, column blocks RBLK00 to RBLK06 do not include redundant word lines, and column block RBLK07 may include 64 redundant word lines.

[0021] The address signal RA allocated to such a memory cell array 2 is, for example, 15 bits, wherein bits <14:13> of the address signal RA can be used to indicate which segment 5, bits <12:10> can be used to indicate which column block RBLK in segment 5, and bits <9:0> can be used to indicate the address of the ordinary character line and the redundant character line in each column block RBLK. In addition, in this embodiment, the bits <14:13> allocated in the address signal RA to indicate the address of segment 5 can be set as the first address, and the bits <12:0> allocated to indicate the address of ordinary character line and redundant character line can be set as the second address.

[0022] Figure 3 is a schematic block diagram showing the relationship between the column redundancy circuit 10 and the segments 5. As described above, the refresh status signal REF, the address signal RA, and the redundancy enable signal RWL_EN are input to the column redundancy circuit 10, and the column redundancy circuit 10 generates a disable signal HIT and a select signal RWLSEL based on these signals. Here, the column redundancy circuit 10 generates a disable signal HIT (HIT_0 to HIT_3) for each segment 5_0 to 5_3. Furthermore, the number of select signals RWLSEL generated by the column redundancy circuit 10 is the same as the number of redundant character lines in the memory cell array 2. The column redundancy circuit 10 inputs the disable signal HIT and the select signal RWLSEL to the multiple segments 5 constituting the memory cell array 2 via the column decoder 4. For example, the column redundancy circuit 10 outputs the generated disable signals HIT_0 to HIT_3 to segments 5_0 to 5_3 respectively.

[0023] The startup and refresh operations of such a column redundancy circuit 10 will be described with reference to FIG4. First, the startup operation (normal read and write operations) will be described. During the startup operation, the refresh status signal REF is input to the column redundancy circuit 10 at a low level, and the redundancy enable signal RWL_EN is input at a low level. In this case, when the column redundancy circuit 10 generates a low-level inhibit signal HIT during the startup operation, the normal character line corresponding to the address signal RA in the memory cell array 2 is activated. Furthermore, when the inhibit signal HIT is generated at a high level, it indicates that the normal character line corresponding to the address signal RA is defective, so the normal character line corresponding to the address signal RA will not be activated, and the corresponding redundant character line will be activated. The redundant character line to be replaced is not limited to the redundant character line in the same segment 5. For example, if the normal character line in segment 5_0 is defective, it can be replaced by the redundant character lines in other segments 5, namely segments 5_1 to 5_3.

[0024] Next, the refresh operation will be explained. During the refresh operation, the refresh status signal REF is input to the column redundancy circuit 10 at a high level, and the ordinary character lines and redundant character lines are activated sequentially. Specifically, when the ordinary character lines are activated sequentially, the redundancy enable signal RWL_EN is input to the column redundancy circuit 10 at a low level, and the column redundancy circuit 10 generates a suppress signal HIT for each segment 5. In each segment 5, when the suppress signal HIT received by the column decoder 4 is at a low level, the ordinary character line corresponding to the address signal RA is activated. When the suppress signal HIT is at a high level, it indicates that the ordinary character line corresponding to the address signal RA is defective, and the column decoder 4 prevents both the ordinary character line and the redundant character line in the corresponding segment 5 from being activated. In this way, the ordinary character line will not be replaced by the redundant character line. Furthermore, when the redundancy enable signal RWL_EN is input to the column redundancy circuit 10 at a high level, the column redundancy circuit 10 generates a disable signal HIT for each segment 5. In each segment 5, when the disable signal HIT received by the column decoder 4 is at a low level, the ordinary character line corresponding to the address signal RA is deactivated, and the redundant character line is activated. When the disable signal HIT becomes a high level, the column decoder 4 deactivates both the ordinary character line and the redundant character line in the corresponding segment 5.

[0025] In the refresh operation illustrated in Figure 5, taking the case where the ordinary character line WL_N_3 and the redundant character line WL_R_1 in segment 5_0 are defective as an example, during the startup operation, the redundant character line WL_R_0 provides relief for the ordinary character line WL_N_3, while all character lines in other segments 5 are without defects. At the start of the refresh operation, the redundancy enable signal RWL_EN is input to the column redundancy circuit 10 at a low level, and the ordinary character lines are activated first. At this time, the address signal RA<12:0> is input to the column redundancy circuit 10, and the character lines with the same address in each segment 5 are activated simultaneously. Then, the address signal RA is added by an address counter (not shown), thereby activating the ordinary character lines WL_N_0 to WL_N_2 in these segments 5 in parallel. Therefore, when there are no defects, four ordinary character lines corresponding to the address signal RA are activated simultaneously in the entire memory cell array 2. This allows this embodiment to reduce the time required for refresh operations.

[0026] In other words, if the ordinary character lines in segment 5 corresponding to the address signal RA are not defective, the column redundancy circuit 10 will continuously output a low-level inhibit signal HIT to the column decoder 4, causing the column decoder 4 to sequentially activate the ordinary character lines starting from ordinary character line WL_N_0. When the incrementing address signal RA indicates ordinary character line WL_N_3, the column redundancy circuit 10 will output a high-level inhibit signal HIT to the column decoder 4, causing all ordinary character lines and redundant character lines in segment 5_0 to be deactivated. Conversely, because the ordinary character lines WL_N_3 in segments 5_1 to 5_3 are not defective, the ordinary character lines WL_N_3 in segments 5_1 to 5_3 are activated simultaneously. In other words, at this time, three ordinary character lines are activated in the entire memory cell array 2. Next, the address signal RA increments according to the address counter, and since there are no defects in the ordinary word lines WL_N_4 of each segment 5_0 to 5_3, the ordinary word lines WL_N_4 of these segments 5_0 to 5_3 can be activated simultaneously. In this way, the remaining ordinary word lines WL_N_5 to WL_N_8243 of each segment can be activated sequentially (when there are no defects).

[0027] Similarly, during the refresh operation, when the redundancy enable signal RWL_EN is input at a high level, the corresponding redundant character line is activated. The address counter causes the redundant character lines WL_R_0 to WL_R_63 in each segment 5 to be activated sequentially, and a total of 4 redundant character lines are activated simultaneously in the entire memory cell array 2. In this case, in segment 5 where the redundant character lines are not defective, the redundancy enable signal RWL_EN continues to be input at a high level, and is activated sequentially starting from the redundant character line WL_R_0. On the other hand, in segment 5_0 where the redundant character line WL_R_1 is defective, when the address signal RA indicates the redundant character line WL_R_1, the column redundancy circuit 10 outputs a high-level inhibit signal HIT, at which time all ordinary character lines and redundant character lines in segment 5_0 are not activated. Therefore, only 3 redundant character lines in the entire memory cell array 2 are activated at this time. Next, the address counter increments the address signal RA, and the redundant character line WL_R_2 of the next address is activated because there are no defects in any segment 5. In this way, the remaining redundant character lines of each segment can be activated sequentially (in the case of no defects).

[0028] In this embodiment, since a dedicated inhibit signal HIT is generated for each segment 5, activation / deactivation control can be performed independently for each segment 5 during the refresh operation. When the inhibit signal HIT is generated at a high level, both the ordinary character line and the redundant character line in the corresponding segment 5 are deactivated. As a result, during the refresh operation, if either the ordinary character line or the redundant character line is defective, both character lines are deactivated, thereby suppressing unnecessary power consumption. Furthermore, in conventional semiconductor devices, there are limitations on the redundant memory cell selected for replacement when the ordinary memory cell is defective, resulting in poor redundancy efficiency and low yield. However, in this embodiment, during the startup operation, there are no limitations on which segment 5 is replaced by a redundant character line when the ordinary character line is defective, thus improving the yield of the semiconductor memory device 1.

[0029] As shown in Figures 6 to 8, the column redundancy circuit 10 of this embodiment includes a normal word line control circuit 11 and a redundancy word line control circuit 12. The normal word line control circuit 11 is configured to control whether to replace normal word lines with redundancy word lines, and operates when the redundancy enable signal RWL_EN is at a low level. The normal word line control circuit 11 generates a normal word line disable signal HIT_N and a select signal RWLSEL based on the address signal RA and the redundancy enable signal RWL_EN, wherein the normal word line disable signal HIT_N indicates that the activation of normal word lines is disabled.

[0030] The redundant character line control circuit 12 is used to deactivate the defective redundant character line when it is defective, and operates when the redundancy enable signal RWL_EN is at a high level. The redundant character line control circuit 12 generates a redundant character line disable signal HIT_R based on the address signal RA and the redundancy enable signal RWL_EN. The redundant character line disable signal HIT_R indicates that activation of the redundant character line is disabled. When the redundant character line corresponding to the address signal RA is defective, the redundant character line disable signal HIT_R stops the activation of the redundant character line.

[0031] As shown in Figure 7, the ordinary character line control circuit 11 includes a character line determination circuit 11A and a segment determination circuit 11B. The character line determination circuit 11A is configured to compare the input address signal RA with fuse information and generate an output signal COMP indicating whether there is a defect in the ordinary character line corresponding to the address signal RA. The segment determination circuit 11B is configured to determine whether there is a defect in the ordinary character line of each segment 5 based on the output signal COMP from the character line determination circuit 11A and generate an ordinary character line inhibit signal HIT_N.

[0032] Specifically, the character line determination circuit 11A may include a comparison unit 111, a fuse information unit 112, and a determination fuse 113. The comparison unit 111 is configured to compare the address signal RA<12:0> input to the ordinary character line control circuit 11 with the address of the ordinary character line to be replaced stored in the fuse information unit 112, and input a signal indicating whether the ordinary character line corresponding to the address signal RA<12:0> is defective to the AND circuit A1. In addition, 13 bits may be extracted from the address signal RA<14:0> (shown in Figure 6) input to the column redundancy circuit 10 as the address signal RA<12:0> input to the ordinary character line control circuit 11, wherein the address signal RA<14:13> used to indicate segment 5 is not input to the comparison unit 111.

[0033] Furthermore, the signal indicating whether the fuse 113 has blown (whether to use redundant character lines to replace ordinary character lines) is input to the AND circuit A1. The AND circuit A1 also receives the inverted redundant enable signal RWL_EN. The AND circuit A1 performs AND operations based on these input signals and outputs the output signal COMP. That is, the output signal COMP is a signal indicating whether there is a defect in the ordinary character lines in segment 5 when the ordinary character lines are activated during the refresh operation. Therefore, when the redundant enable signal RWL_EN is input at a low level, and the address signal RA<12:0> matches the address stored in the fuse information unit 112, and it is further determined that the fuse 113 has been blown, the output signal COMP is output at a high level.

[0034] The output signal COMP is input to AND circuits A2 to A5 respectively. Furthermore, the output signal COMP is input to segment 5 as a selection signal RWLSEL, wherein the output signal COMP is input at a high level to the segment with defective ordinary character lines and at a low level to other segments. The fuse information of address signals RA<14:13> is decoded and input to AND circuits A2 to A5 respectively for segment selection. Specifically, the inverted signal representing the fuse information corresponding to address signal RA<13> and the inverted signal representing the fuse information corresponding to address signal RA<14> are input to AND circuits A2 and A4. The inverted signal representing the fuse information corresponding to address signal RA<13> and the inverted signal representing the fuse information corresponding to address signal RA<14> are input to AND circuits A3 and A5.

[0035] Each of the AND circuits A2 to A5 outputs temporary ordinary character line disable signals HIT_N_0_# to HIT_N_3_# according to the output signal COMP and the address signal RA<14:13>. The column redundancy circuit 10 has ordinary character line control circuits 11 in number corresponding to the number of redundant character lines possessed by the memory cell array 2, and these ordinary character line control circuits 11 all generate and output temporary ordinary character line disable signals HIT_N_0_# to HIT_N_3_# in a similar manner. Therefore, this # corresponds to the number of redundant character lines in the memory cell array 2, and in this embodiment, # is any number between 0 and 255. These temporary ordinary character line inhibit signals HIT_N_0_0 to HIT_N_0_255 are input to OR circuit OR1. Similarly, these temporary ordinary character line inhibit signals HIT_N_1_# to HIT_N_3_# are input to OR circuits OR2 to OR4 respectively, and ordinary character line inhibit signals HIT_N_0 to HIT_N_3 are output from each of OR circuits OR1 to OR4. When the output signal COMP is output at a high level, any one of the ordinary character line inhibit signals HIT_N_0 to HIT_N_3 becomes high.

[0036] As shown in Figure 8, the redundant character line control circuit 12 includes redundant character line control circuits 12_0 to 12_3 corresponding to segment 5. However, since the configuration of the redundant character line control circuits 12 in each segment 5 is the same, only the redundant character line control circuit 12_0 of segment 5_0 is described as an example. The redundant character line control circuit 12 receives the address signal RA<5:0> indicating the redundant character line and the redundancy enable signal RWL_EN in the address signal RA. The redundant character line control circuit 12 has a judgment fuse 121 for setting the redundant character line corresponding to the address signal RA to be inactive, and when the redundant character line is defective, this judgment fuse 121 is cut off. The AND circuit A6 receives and performs calculations on the address signal RA<5:0> and the signal indicating the state of the judgment fuse 121, and outputs the result of the calculation to the OR circuit OR5. The number of fuse 121, AND circuit A6, and OR circuit OR5 can be equal to the number of redundant character lines in segment 5_0, i.e., 64. AND circuit A7 receives and performs an AND operation on the output of each OR circuit OR5 and the redundancy enable signal RWL_EN, and outputs the result as the redundant character line disable signal HIT_R_0. Similarly, corresponding to each segment 5_1 to 5_3, redundant character line control circuits 12_1 to 12_3 generate redundant character line disable signals HIT_R_1 to HIT_R_3, respectively.

[0037] Referring to Figure 6, the redundant circuit 10 further includes OR circuits OR6 to OR9. The ordinary character line inhibit signal HIT_N (HIT_N_0~HIT_N_3) and the redundant character line inhibit signal HIT_R (HIT_R_0~HIT_R_3) corresponding to each segment 5 are input to OR circuits OR6 to OR9 to perform OR operation to generate inhibit signals HIT (HIT_0~HIT_3) for each segment 5 (5_0~5_3). That is, when the ordinary character line inhibit signal HIT_N or the redundant character line inhibit signal HIT_R becomes high, the inhibit signal HIT is output at a high level, and all character lines in segment 5 that receive this high-level inhibit signal HIT become inactive.

[0038] In this way, the inhibit signal HIT for different segments is generated separately and input to the corresponding segment 5. Therefore, during the refresh operation, the word lines corresponding to the address signal RA can be activated simultaneously in multiple segments 5. However, if the word lines in a certain segment 5 are defective, all word lines in that segment will be deactivated, thereby suppressing unnecessary power consumption.

[0039] It should be noted that the ordinary character line control circuit and redundant character line control circuit of the present invention are only required to achieve the above functions, and are not limited to the examples described in the above embodiments. For example, a modified example of the ordinary character line control circuit of the present invention can be configured as shown in Figure 9.

[0040] As shown in Figure 9, the ordinary character line control circuit 21 includes a character line judgment circuit 21A and a segment judgment circuit 21B, which can perform the same functions as the ordinary character line control circuit 11. The character line judgment circuit 21A generates an output signal COMP to indicate whether there is a defect in the ordinary character line corresponding to the address signal RA. The segment judgment circuit 21B determines whether there is a defect in the ordinary character line in each segment 5 by latching the output signal COMP from the character line judgment circuit 21A, and generates an ordinary character line disable signal HIT_N to prevent the ordinary character line from being activated. The character line judgment circuit 21A is the same as the character line judgment circuit 11A, so its description will be omitted.

[0041] In the ordinary character line control circuit 21, the number of output signals COMP generated by the character line judgment circuit 21A is equal to the number of redundant character lines (i.e., 256), and all output signals COMP are input to the OR circuit OR11 for OR operation and output as temporary inhibit signals HIT_N'. The temporary inhibit signals HIT_N are input to multiple latch circuits Latch0 to Latch3 (the number of which is the same as the number of segments), and latched according to latch signals LAT_0 to LAT_3 for each segment 5 (5_0 to 5_3) to generate ordinary character line inhibit signals HIT_N_0 to HIT_N_3.

[0042] Figure 10 shows a latch signal generation circuit 100 according to an embodiment of the present invention. The latch signal generation circuit 100 includes a plurality of inverters INV1, INV2 and a plurality of AND circuits A8 to A11. Address signals RA<14>, RA<13> (or their inverted signals) and latch signals LAT are input to each AND circuit A8 to A11 to generate latch signals LAT_0 to LAT_3 corresponding to each segment 5_0 to 5_3. Latch signals LAT_0 to LAT_3 are input to latch circuits Latch0 to Latch3.

[0043] For example, Figure 11 shows a timing diagram according to the embodiment of Figure 10 when the ordinary character lines of segments 5_1 and 5_3 are defective. In this case, the temporary inhibit signal HIT_N' becomes high in response to the latch signals LAT_1 and LAT_3.

[0044] Relative to the temporary inhibit signal HIT_N', when latch signals LAT_0 to LAT_3 of segments 5_0 to 5_3 based on address signals RA<14:13> are input, among the ordinary character line inhibit signals HIT_N_0 to HIT_N_3, only the ordinary character line inhibit signals HIT_N_1 and HIT_N_3 will output high levels. The ordinary character line control circuit 21 is configured according to this objective. Furthermore, as shown in Figure 11, when the latch signal LAT completes four high-level outputs, the WL activation signal WL_ON output from the control circuit 3 is activated. When this WL activation signal WL_ON is input to the column decoder 4 at a high level, character line activation begins.

[0045] In the above embodiments, DRAM is used as an example of semiconductor memory device, but the present invention is not limited thereto. For example, semiconductor memory device may be SRAM (Static Random Access Memory), flash memory, or other semiconductor memory devices that require refresh operations.

[0046] The embodiments and modifications described above are for the purpose of facilitating understanding of the invention and are not intended to limit the invention. Therefore, each element disclosed in the above embodiments and modifications is intended to encompass all design variations and equivalents within the scope of the invention. [Simplified Explanation of the Diagram]

[0011] Figure 1 is an exemplary block diagram showing a semiconductor memory device according to a first embodiment of the present invention. Figure 2 is a structural diagram showing a memory cell array. Figure 3 is a schematic diagram illustrating the relationship between the column redundancy circuit and the memory cell array. Figure 4 is a diagram illustrating the control of the column redundancy circuit. Figure 5 is a diagram illustrating a specific example of the control of the column redundancy circuit. Figure 6 is a schematic diagram showing the structure of the column redundancy circuit. Figure 7 is a schematic diagram showing the structure of the ordinary word line control circuit of the column redundancy circuit. Figure 8 is a schematic diagram showing the structure of the redundant word line control circuit of the column redundancy circuit. Figure 9 is a diagram showing a modified example of the ordinary WL control circuit of the column redundancy circuit. Figure 10 is a diagram showing details of a modified example of the ordinary WL control circuit of the column redundancy circuit. Figure 11 is an example of a timing diagram in a modified example of the ordinary word line control circuit of the column redundancy circuit.

Claims

1. A semiconductor memory device, comprising: The memory cell array contains multiple segments, each segment having multiple ordinary character lines and multiple redundant character lines; And a column redundancy circuit, configured to activate non-defective ordinary character lines and non-defective redundant character lines during a refresh operation, wherein activation and replacement of defective ordinary character lines and defective redundant character lines are not performed in each segment; wherein the segments include a first segment and a second segment, the first segment having multiple first ordinary character lines and multiple first redundant character lines, and the second segment having multiple second ordinary character lines and multiple second redundant character lines, the column redundancy circuit is further configured to: generate a first inhibit signal and a second inhibit signal for the first segment and the second segment respectively during the refresh operation. Based on the first prohibition signal and the second prohibition signal, one of the first ordinary character lines without defects and one of the second ordinary character lines without defects are activated simultaneously, or one of the first redundant character lines without defects and one of the second redundant character lines without defects are activated simultaneously, while the defective characters in the first ordinary character lines, the defective characters in the second ordinary character lines, the defective characters in the first redundant character lines, and the defective characters in the second redundant character lines are not activated.

2. The semiconductor memory device as described in claim 1, wherein, The number of the first ordinary character lines is greater than the number of the first redundant character lines, and the number of the second ordinary character lines is greater than the number of the second redundant character lines.

3. The semiconductor memory device as described in claim 1, wherein the redundant circuitry is further configured to: receive an address signal, wherein the address signal includes a first address for indicating the first segment or the second segment, and a second address for indicating the first ordinary character lines, the second ordinary character lines, the first redundant character lines, or the second redundant character lines; and during the refresh operation, simultaneously activating, based on the second address, one of the first ordinary character lines without defects and one of the second ordinary character lines without defects, or simultaneously activating one of the first redundant character lines without defects and one of the second redundant character lines without defects.

4. The semiconductor memory device as described in claim 3, wherein the redundant circuitry is further configured to receive a low-level refresh status signal and a low-level redundant enable signal during startup operation, and to generate a first disable signal, a second disable signal, and a select signal based on the address signal, the refresh status signal, and the redundant enable signal, wherein when the first disable signal or the second disable signal corresponding to the address signal is at a high level, the select signal is generated at a high level, thereby activating one of the first redundant character lines that receives the select signal and one of the second redundant character lines that is not defective.

5. The semiconductor memory device as described in claim 3, wherein the redundant circuitry includes: The ordinary character line control circuit is configured to generate a first ordinary character line inhibit signal for inhibiting the activation of a defective one of the first ordinary character lines, and a second ordinary character line inhibit signal for inhibiting the activation of a defective one of the second ordinary character lines. The redundant character line control circuit is configured to generate a first redundant character line disable signal for disabling activation of defective first redundant character lines, and a second redundant character line disable signal for disabling activation of defective second redundant character lines. When the first ordinary character line disable signal or the first redundant character line disable signal is activated, the redundant circuit generates a high-level first disable signal, and when the second ordinary character line disable signal or the second redundant character line disable signal is activated, the redundant circuit generates a high-level second disable signal.

6. The semiconductor memory device as described in claim 5, wherein the general character line control circuitry includes: A character line determination circuit is configured to compare the address signal with fuse information to generate an output signal indicating whether one of the first ordinary character lines and the second ordinary character lines corresponding to the address signal is defective; and a segment determination circuit is configured to determine whether one of the first ordinary character lines and the second ordinary character lines corresponding to the address signal is defective based on the output signal from the character line determination circuit, and when a defect is determined, generate a high-level first ordinary character line inhibit signal or a high-level second ordinary character line inhibit signal.

7. The semiconductor memory device as described in claim 6, wherein the number of segment determination circuits is multiple and the same as the number of redundant character lines of the memory cell array, and the segment determination circuits generate multiple temporary ordinary character line inhibit signals based on the fuse information, the decoded fuse information and the output signal.

8. The semiconductor memory device as described in claim 6, wherein the segment determination circuit latches the output signal based on the address signal to generate the first ordinary character line inhibit signal and the second ordinary character line inhibit signal.

9. The semiconductor memory device as described in claim 7, wherein, These segment determination circuits include multiple AND circuits. Each AND circuit performs AND operations on the output signal, the fuse information, or the decoded fuse information to generate temporary ordinary character line disable signals. The temporary ordinary character line disable signals corresponding to the first segment are input to the first OR circuit to generate the first ordinary character line disable signal, while the temporary ordinary character line disable signals corresponding to the second segment are input to the second OR circuit to generate the second ordinary character line disable signal.

10. The semiconductor memory device as described in claim 8, wherein, The segment determination circuit has a first latch circuit corresponding to the first segment and a second latch circuit corresponding to the second segment. The output signal is input to the first latch circuit and the second latch circuit. The segment determination circuit latches the output signal according to the address signal to generate the first ordinary character line inhibit signal and the second ordinary character line inhibit signal.

11. The semiconductor memory device as described in claim 6, wherein, The redundant character line control circuit compares the address signal with the fuse information to determine whether the first redundant character lines and the second redundant character lines are defective. When one of the first redundant character lines corresponding to the address signal is defective, the first redundant character line is output as a high-level inhibit signal. When one of the second redundant character lines corresponding to the address signal is defective, the second redundant character line is output as a high-level inhibit signal.

12. The semiconductor memory device described in any one of claims 1 to 11, wherein the semiconductor memory device is dynamic random access memory (DRAM).

13. The semiconductor memory device as described in claim 3, wherein the redundant circuitry is further configured to: receive a high-level refresh status signal during the refresh operation; during the period of receiving a low-level redundant enable signal, according to the address signal, the low-level first disable signal, and the low-level second disable signal, sequentially activate non-defective first ordinary character lines in the first segment starting from the address signal, and concurrently activate non-defective second ordinary character lines in the second segment starting from the address signal; during the period of receiving the high-level redundant enable signal, according to the address signal, the low-level first disable signal, and the low-level second disable signal, sequentially activate non-defective first redundant character lines in the first segment starting from the address signal, and concurrently activate non-defective second redundant character lines in the second segment starting from the address signal; During the period of receiving the low-level redundancy enable signal, when the high-level first disable signal is received, the defective ones among the first ordinary character lines are prohibited from activation; when the high-level second disable signal is received, the defective ones among the second ordinary character lines are prohibited from activation. During the period of receiving the high-level redundancy enable signal, when the high-level first disable signal is received, the defective ones among the first redundant character lines are prohibited from activation; and when the high-level second disable signal is received, the defective ones among the second redundant character lines are prohibited from activation.

14. A refresh control method for a semiconductor memory device, comprising: The memory cell array is configured to contain multiple segments, each segment having multiple ordinary character lines and multiple redundant character lines; During the refresh operation, non-defective ordinary character lines and non-defective redundant character lines are activated by a column redundancy circuit, wherein the activation and replacement of defective ordinary character lines and defective redundant character lines are not performed in each segment; wherein the segments include a first segment and a second segment, the first segment having multiple first ordinary character lines and multiple first redundant character lines, and the second segment having multiple second ordinary character lines and multiple second redundant character lines, and the method further includes: generating a first inhibit signal and a second inhibit signal for the first segment and the second segment respectively during the refresh operation. Specifically, based on the first prohibition signal and the second prohibition signal, one of the first ordinary character lines without defects and one of the second ordinary character lines without defects are activated simultaneously, or one of the first redundant character lines without defects and one of the second redundant character lines without defects are activated simultaneously, while the defective characters in the first ordinary character lines, the defective characters in the second ordinary character lines, the defective characters in the first redundant character lines, and the defective characters in the second redundant character lines are not activated.

15. The refresh control method as described in request item 14 further includes: Receive an address signal, wherein the address signal includes a first address for indicating the first segment or the second segment, and a second address for indicating the first ordinary character lines, the second ordinary character lines, the first redundant character lines, or the second redundant character lines, wherein during the refresh operation, one of the first ordinary character lines without defects and one of the second ordinary character lines without defects are simultaneously activated according to the second address, or one of the first redundant character lines without defects and one of the second redundant character lines without defects are simultaneously activated.

16. The refresh control method as described in claim 15, wherein generating the first prohibition signal and the second prohibition signal for the first segment and the second segment respectively includes: A first ordinary character line prohibition signal is generated to prohibit activation of defective individuals among the first ordinary character lines, and a second ordinary character line prohibition signal is generated to prohibit activation of defective individuals among the second ordinary character lines; a first redundant character line prohibition signal is generated to prohibit activation of defective individuals among the first redundant character lines, and a second redundant character line prohibition signal is generated to prohibit activation of defective individuals among the second redundant character lines, wherein when the first ordinary character line prohibition signal or the first redundant character line prohibition signal is activated, a high-level first prohibition signal is generated, and when the second ordinary character line prohibition signal or the second redundant character line prohibition signal is activated, a high-level second prohibition signal is generated.

17. The refresh control method as described in claim 16, wherein the step of generating the first ordinary character line disable signal and the second ordinary character line disable signal includes: The address signal is compared with fuse information to generate an output signal indicating whether one of the first ordinary character lines and the second ordinary character lines corresponding to the address signal is defective; and based on the output signal, it is determined whether one of the first ordinary character lines and the second ordinary character lines corresponding to the address signal is defective, and when a defect is determined, a high-level first ordinary character line inhibit signal or a high-level second ordinary character line inhibit signal is generated.

18. The refresh control method as described in request item 15, further comprising during the refresh operation: Receive high-level refresh status signals; During the reception of a low-level redundant enable signal, based on the address signal, the low-level first disable signal, and the low-level second disable signal, in the first segment, the non-defective first ordinary character lines are sequentially activated starting from the address signal, and in parallel in the second segment, the non-defective second ordinary character lines are sequentially activated starting from the address signal; During the reception of a high-level redundant enable signal, based on the address signal, the low-level first disable signal, and the low-level second disable signal, in the first segment, the non-defective first redundant character lines are sequentially activated starting from the address signal, and in parallel in the second segment, the non-defective second redundant character lines are sequentially activated starting from the address signal. During the period of receiving the low-level redundancy enable signal, when the high-level first disable signal is received, the defective ones among the first ordinary character lines are prohibited from activation; when the high-level second disable signal is received, the defective ones among the second ordinary character lines are prohibited from activation. During the period of receiving the high-level redundancy enable signal, when the high-level first disable signal is received, the defective ones among the first redundant character lines are prohibited from activation; and when the high-level second disable signal is received, the defective ones among the second redundant character lines are prohibited from activation.

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