Gaa fet structure and processing methods

Abstract

This disclosure describes a method for reducing the width of an isolation structure between adjacent source / drain contact structures of a field-effect transistor (FET). The method includes patterning an isolation layer stack using a patterned mask structure. The width of the patterned mask structure is reduced by an ion implantation and wet etching process. The isolation layer stack is etched through the reduced patterned mask structure to form an isolation structure with a smaller width.

Claims

1. A processing method comprising: providing a substrate including source / drain (S / D) regions formed on adjacent fin structures, wherein the S / D regions are surrounded by a first dielectric layer; depositing an etch stop layer on the first dielectric layer; depositing a second dielectric layer on the etch stop layer; depositing a metal-based layer on the second dielectric layer; depositing a capping layer on the metal-based layer; depositing a silicon layer on the capping layer; etching the capping layer and the metal-based layer to form a first opening; performing ion implantation on the sidewalls of the capping layer and the metal-based layer to form an implantation portion on the sidewalls of the capping layer and the metal-based layer; etching the implantation portion through the first opening to form a second opening; etching the second dielectric layer, the etch stop layer, and the first dielectric layer through the second opening to form an S / D contact opening; and filling the S / D contact opening with a metal layer.

2. The method of claim 1, wherein performing the ion implantation comprises: directing ions at an angle between about 2° and about 88° onto the sidewalls of the capping layer and the metal-based layer.

3. The method of claim 1, further comprising: etching the implanted portion with diluted hydrogen fluoride and diluted ammonium hydroxide.

4. The method of claim 1, further comprising: ion implanting the capping layer and the sidewalls of the metal-based layer with at least one of argon ions, xenon ions or oxygen ions.

5. A processing method comprising: providing a GAA FET having a first dielectric layer; forming an etch stop layer and a second dielectric layer on the first dielectric layer; depositing a metal-based layer on the second dielectric layer; depositing an oxide layer on the metal-based layer; etching the metal-based layer and the oxide layer to form a first opening; ion implanting the sidewalls of the metal-based layer and the oxide layer with inert ions to form an implantation region; etching the implantation region to form a second opening larger than the first opening; etching the second dielectric layer, the etch stop layer, the first dielectric layer, and a portion of a source / drain (S / D) region of the GAA FET to form a trench; and filling the trench with a contact layer.

6. The method of claim 5, further comprising: forming a patterned layer stack on the oxide layer, wherein forming the patterned layer stack comprises: depositing a silicon layer on the oxide layer; forming a first patterned layer on the silicon layer; forming a second patterned layer on the first patterned layer; and patterning and etching the first patterned layer, the second patterned layer and the silicon layer to form a first patterned mask structure.

7. The method of claim 5, wherein ion implantation of the sidewalls of the metal-based layer comprises: implanting the sidewalls of the metal-based layer and the oxide layer with xenon ions.

8. The method of claim 5, further comprising: increasing the thickness of the implantation area by increasing the concentration of xenon ions.

9. A gate all-around field-effect transistor (GAA FET) structure comprising: a first GAA FET including a first channel region and a first source / drain (S / D) region; a second GAA FET including a second channel region and a second source / drain region; and an isolation structure disposed between a first contact structure of the first S / D region and a second contact structure of the second S / D region, wherein a vertical sidewall of the isolation structure forms an angle equal to or greater than about 84° with respect to a horizontal direction.

10. The structure of claim 9, wherein the isolation structure comprises: a first dielectric layer; an etch stop layer disposed on the first dielectric layer; and a second dielectric layer disposed on the etch stop layer.

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