Non-volatile memory device and method for manufacturing the same

Abstract

A method for manufacturing a non-volatile memory element includes forming a two-layer structure on a substrate and forming a gap between the two-layer structures; forming a floating gate layer covering the two-layer structure and filling the gap, the floating gate layer including a recessed region; filling the recessed region with a first masking layer; removing a portion of the first masking layer to form a first mask in the recessed region; removing a portion of the floating gate layer to retain the floating gate layer located within the gap, the top surface of the floating gate layer being laterally separated from the first mask; converting the top surface of the floating gate layer into a second mask under the cover of the first mask; removing the first mask within the recessed region; and etching the floating gate layer using the second mask as an etching mask.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device, and more particularly to a non-volatile memory device and a method for manufacturing the same. [Previous Technology]

[0002] Non-volatile memory can repeatedly perform operations such as storing, reading and erasing data, and the data stored in it will not disappear after the non-volatile memory is turned off. Therefore, non-volatile memory has been widely used in personal computers and electronic devices.

[0003] Traditional non-volatile memory structures have a stacked gate structure, including a tunneling oxide layer, a floating gate, a coupling dielectric layer, and a control gate sequentially disposed on a substrate. When a program write or erase operation is performed on such a flash memory element, appropriate voltages are applied to the source region, drain region, and control gate, respectively, so that electrons are injected into the floating gate or pulled out from the floating gate.

[0004] In the write and erase operations of non-volatile memory, a higher gate coupling ratio (GCR) between the floating gate and the control gate usually represents a lower operating voltage, thus significantly improving the operating speed and efficiency of flash memory. However, during the write or erase operation, electrons must be injected into or pulled out of the floating gate through a tunneling oxide layer located below it, which often leads to damage to the tunneling oxide layer structure, thereby reducing the reliability of the memory element.

[0005] To improve the reliability of memory devices, an erase gate is adopted and incorporated into the memory device. By applying a positive voltage to the erase gate, electrons are pulled out from the floating gate. In this way, since the electrons are pulled out through the tunneling oxide layer disposed on the floating gate, rather than through the tunneling oxide layer below the floating gate, the reliability of the memory device is further improved.

[0006] U.S. Patent Application US 20240162315 A1 discloses a non-volatile memory device. This application is related to this application but is not considered prior art. Referring to Figures 1 and 2 of US 20240162315 A1, Figure 1 is a planar schematic diagram of the non-volatile memory device, and Figure 2 is a cross-sectional schematic diagram corresponding to lines A-A', B-B', and C-C' in Figure 1. Common methods for defining the floating gate in US 20240162315 A1 include first planarizing a floating gate layer made of polysilicon to expose two adjacent select gate stacks, and then using photolithography and etching processes to pattern the planarized floating gate layer located between the select gate stacks.

[0007] However, the patterning of photolithography inevitably causes changes in the size (e.g., width) of the floating gate, which often leads to significant changes in the erase voltage applied to the erase gate during the erase operation, resulting in poorer consistency of electrical characteristics among multiple memory elements.

[0008] Therefore, there is still a need to improve the manufacturing method of memory components in order to minimize the aforementioned floating gate width variation. [Summary of the Invention]

[0009] This invention provides a non-volatile memory element and a method for manufacturing the same. The non-volatile memory element can erase stored data more efficiently and / or exhibits improved uniformity of electrical characteristics between memory elements.

[0010] According to certain embodiments of the present disclosure, a method for manufacturing a non-volatile memory element is disclosed, comprising the following steps: providing a substrate; forming two stacked structures on the substrate, each stacked structure including a select gate layer and a select gate dielectric layer, and forming a gap between the two stacked structures; forming a floating gate layer on the substrate, the floating gate layer covering the two stacked structures and the substrate, and filling the gap, wherein the floating gate layer includes a recessed region; filling a first masking layer into the recessed region; removing an upper portion of the first masking layer to form a first mask located in the recessed region; removing an upper portion of the floating gate layer to retain the floating gate layer in the gap, wherein the two top surfaces of the floating gate layer located in the gap are laterally separated from the first masking layer; under the cover of the first masking layer, converting the two top surfaces of the floating gate layer into a second masking layer; removing the first masking layer located in the recessed region; and using the second masking layer as an etching mask to etch the floating gate layer.

[0011] According to certain embodiments of this disclosure, a non-volatile memory element is disclosed, comprising at least one memory cell. The memory cell includes a substrate, a select gate, and a floating gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally separated from the select gate. The floating gate includes two first top edges, two first sidewalls, and two second sidewalls. The first top edges are disposed opposite each other along a first direction, each first top edge being higher than the top surface of the select gate, wherein one of the two first top edges is adjacent to the select gate and laterally separated from the bottom surface of the floating gate. The first sidewalls are disposed opposite each other along the first direction and respectively connect to the two first top edges. The second sidewalls are disposed opposite each other along a second direction different from the first direction.

[0012] The above and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiments shown in conjunction with the figures.

Implementation Method

[0014] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature is formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," so that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate the relationship between different embodiments and / or configurations.

[0015] Furthermore, regarding the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the package structure during use and operation. As the orientation of the package structure changes (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0016] Although the invention disclosed herein is described below by way of specific embodiments, the inventive principles of this invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0017] Figure 1 is a top view schematic diagram of a non-volatile memory element shown in certain embodiments of the present disclosure. Referring to Figure 1, the non-volatile memory element 100 may be a NOR flash memory element containing at least one memory cell, such as four memory cells respectively housed in the first to fourth memory cell regions 110, 112, 114, and 116. The structures in the first memory cell region 110 and the second memory cell region 112 are mirror-symmetric to each other, and the structures in the third memory cell region 114 and the fourth memory cell region 116 are also mirror-symmetric to each other. According to one embodiment of the present disclosure, the non-volatile memory element 100 contains more than four memory cells, and these memory cells may be arranged in a multi-row, multi-column array.

[0018] Referring to FIG1, the non-volatile memory element includes a substrate 200 and an isolation structure 102. The substrate 200 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The isolation structure 102 may be made of an insulating material and is used to define the active region 103 of the memory cell.

[0019] Each memory cell includes a source region 222 and a drain region 244, which are disposed within the active region 103 defined by the isolation structure 102. Both the source region 222 and the drain region 244 can be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 244 may differ from the conductivity type of the substrate 200, or from the conductivity type of the doped well (not shown) used to house the source region 222 and the drain region 244. The source region 222 may be disposed at one end of the active region 103, and the drain regions 244 may be arranged at the other end of the active region 103. According to certain embodiments of this disclosure, the source region 222 is a continuous region extending along the Y direction and is shared by memory cells in the same column.

[0020] Each memory cell may also include a select gate 204 disposed on the substrate 200 and adjacent to the drain region 244. The select gate 204 may extend along the Y direction and be shared by memory cells located in the same row. The select gate 204 may be made of a conductive material, such as polysilicon or metal, and may serve as a word line to control the switching of the channel regions of memory cells located below the word line, so that the channel regions of memory cells in the same row may be turned on or off simultaneously.

[0021] The dielectric spacer 212 may be disposed on the side wall of the selector gate 204 to insulate the selector gate 204 from other conductive components. The dielectric spacer 212 may be a single-layer, double-layer, or multi-layer structure and may be disposed on each side wall of the selector gate 204, but is not limited thereto.

[0022] Each memory cell also includes a floating gate 224a disposed on the substrate 200 and adjacent to the source region 222. The floating gate 224a is located on one side of the select gate 204, and the drain region 244 is disposed on the other side of the select gate 204. The floating gate 224a is made of a conductive material, such as polysilicon or other semiconductor materials. The floating gates 224a are spaced apart from each other to avoid direct current conduction between multiple floating gates. Since the floating gates 224a are separated from each other, each floating gate 224a can be independently programmed or erased, thereby determining the state of each memory cell, such as a "1" or "0" state.

[0023] Each memory cell also includes an upper gate structure 236 disposed above the select gate 204. The upper gate structure 236 may extend along the Y direction and be shared by memory cells located in the same row. Depending on different needs, the upper gate structure 236 may serve as an erase gate structure, pulling out electrons by the apex corner and / or apex edge of the floating gate 224a; or it may serve not only as an erase gate structure but also as a control gate structure, allowing hot carriers to be injected into the floating gate 224a from the carrier channel.

[0024] An intermediate structure 240 is disposed within the gap between adjacent floating gates 224a, surrounding the periphery of the floating gates 224a. Depending on the requirements, the intermediate structure 240 may include an insulating structure to prevent leakage current between adjacent floating gates 224a, or the intermediate structure 240 may serve as a control gate structure to allow hot carriers (e.g., electrons) to be injected into the floating gates 224a from the channel.

[0025] Figure 2 is a schematic cross-sectional view of a non-volatile memory element corresponding to lines A-A', B-B', and C-C' in Figure 1 in certain embodiments of this disclosure, wherein the upper gate structure covers the floating gate and the intermediate structure. Referring to the cross-sectional view AA' in Figure 2, the drain region 242 is respectively disposed in the first memory cell region 110 and the second memory cell region 112. The source region 222 is disposed at the boundary between the first memory cell region 110 and the second memory cell region 112.

[0026] For the memory cells in the first memory cell region 110, a select gate dielectric layer 202 is disposed between the substrate 200 and the select gate 204. By applying a predetermined bias voltage to the select gate 204, the carrier channel located below the select gate dielectric layer 202 can be turned on or off. An insulating layer 206 can be selectively disposed between the select gate 204 and the upper gate structure 236 to prevent leakage current between the two.

[0027] The upper gate structure 236 includes an upper gate dielectric layer 234 and an upper gate 235 stacked sequentially. The upper gate dielectric layer 234 may be made of a dielectric material that allows electrons to pass through via the Fowler-Nordheim (FN) tunneling mechanism. The upper gate 235 may be made of a conductive material, such as polysilicon or metal. The top surface of the upper gate structure 236 is higher than the top surface of the floating gate 224a. Furthermore, the upper gate structure 236 may extend further toward the selector gate 204 such that a portion of the upper gate structure 236 may extend beyond the sidewall of the selector gate 204 and cover the top surface 224a_0 of the floating gate 224a.

[0028] The floating gate 224a includes two first sidewalls 224a_1 disposed opposite each other along the X direction. The first sidewalls 224a_1 may be vertical or inclined sidewalls, rather than curved surfaces. The top surface 224a_0 of the floating gate 224a is a flat or slightly inclined surface, rather than a curved surface. It should be noted that the floating gate 224a shown in FIG2 can be regarded as a rectangular floating gate, because the outline of the floating gate is approximately rectangular in the cross-sectional view AA'.

[0029] A floating gate dielectric layer 218 is disposed on the substrate 200 and is located at least between the substrate 200 and the floating gate 224a. The material of the floating gate dielectric layer 218 is, for example, silicon oxide or other materials. During a write operation, hot electrons can pass through the floating gate dielectric layer 218 and accumulate in the floating gate 224a.

[0030] As described above, the intermediate structure 240 may include an insulating structure, or the intermediate structure 240 may also include a control gate structure (the control gate structure may cover the sidewalls 224a_1, 224a_2 of the floating gate 224a to provide additional coupling). The intermediate structure 240 includes a thin dielectric layer 238 and an intermediate layer 239. The thin dielectric layer 238 is disposed on the first sidewall 224a_1 of the floating gate 224a, and the intermediate layer 239 is disposed between adjacent floating gates 224a. According to certain embodiments of this disclosure, the top surface 239_0 of the intermediate structures 240a, 240b is lower than the top surface 224a_0 of the floating gate 224a.

[0031] In some embodiments, when the intermediate structure 240 includes a control gate structure, the thin dielectric layer 238 may be a stacked coupling dielectric layer 248 consisting of silicon oxide / silicon nitride / silicon oxide, but is not limited thereto; the intermediate layer 239 may be made of a conductive material, such as polysilicon or metal, but is not limited thereto.

[0032] Depending on different requirements, the upper gate structure 236 can serve as an erase gate structure, pulling out electrons via the apex and / or top edge of the floating gate 224a; or it can serve not only as an erase gate structure but also as a control gate structure, attracting hot carriers to be injected into the floating gate 224a through the carrier channel. On one hand, when the intermediate structure 240b is configured as a control gate structure, the upper gate structure 236 serves only as an erase gate structure and not as a control gate structure; on the other hand, when the intermediate structure 240a is configured as an insulating structure, the upper gate structure 236 can serve as both an erase gate and a control gate structure.

[0033] According to the above embodiment, the non-volatile memory element 100 includes an upper gate structure 236 disposed above the select gate 204 and the floating gate 224a. However, in other embodiments, the upper gate structure 236 may be replaced by an embedded erase gate structure (not shown) disposed below the floating gate 224a and formed in a trench (not shown) of the substrate 200. In this configuration, the lower tip (not shown) of the floating gate 224a may be partially covered by the embedded erase gate structure. During the erase operation of the non-volatile memory element 100, electrons originally stored in the floating gate 224a can be more effectively pulled out from the lower tip of the floating gate 224a by applying a bias voltage to the embedded erase gate structure.

[0034] Referring to the cross-sectional view BB' in FIG2, the selective gate 204, the upper gate structure 236, and the intermediate structures 240a and 240b (e.g., intermediate substrate structures or control gate structures) are further disposed on the isolation structure 102. A portion of the intermediate structures 240a and 240b may be disposed between the upper gate structure 236 and the isolation structure 102, which extends beyond the sidewall of the selective gate 204, or a portion of the intermediate structures 240a and 240b may be disposed between the upper gate structure 236 and the substrate 200.

[0035] Referring to the cross-sectional view CC' in FIG2, each floating gate 224a includes two second sidewalls 224a_2 disposed opposite to each other along the Y direction. The second sidewalls 224a_2 can be vertical or inclined sidewalls. The upper part of the second sidewalls 224a_2 of the floating gate 224a can be covered by the upper gate structure 236, and the lower part is covered by the intermediate structures 240a, 240b (e.g., intermediate substrate structure or control gate structure). According to some embodiments of the present disclosure, 60% to 95% of the surface area of ​​each second sidewall 224a_2 is covered by the intermediate layer 239, so the contact area between the upper gate structure 236 and the second sidewalls 224a_2 is small. In addition, due to the presence of the intermediate structures 240a, 240b, the bottom surface of the upper gate structure 236 extending beyond the second sidewalls 224a_2 of the floating gate 224a can be separated from the isolation structure 102, the floating gate dielectric layer 218 and the substrate 200.

[0036] According to certain embodiments of this disclosure, non-volatile memory elements may also include other components, such as vias, bit lines, interlayer dielectric layers, etc., and the structure shown in FIG2 can be modified based on actual needs.

[0037] Figure 3 is an enlarged cross-sectional view of the non-volatile memory element region R1 shown in Figure 2 in certain embodiments of this disclosure. Referring to Figure 3, the floating gate 224a includes two first top edges 226a_1 disposed opposite each other along a first direction (e.g., the X direction). One of the first top edges 226a_1 is adjacent to the select gate 204, and the other of the first top edges 226a_1 is away from the select gate 204. The floating gate 224a further includes a top tip 228 extending toward the upper gate structure 236, and thus laterally separated from the bottom surface of the floating gate 224a. Since the top tip 228 extends toward the upper gate structure 236, the top tip 228 can be partially embedded in the upper gate structure 236. The top edge of the top tip 228 is the first top edge 226a_1 adjacent to the select gate 204.

[0038] By applying a bias voltage to the upper gate structure 236, most of the electrons stored in the floating gate 224a can be pulled out via the top tip 228 embedded in the upper gate structure 236. The first sidewalls 224a_1 of the floating gate 224a, arranged along a first direction (such as the X direction), are respectively connected to the first top edge 226a_1. The second sidewalls (not shown) of the floating gate 224a are arranged along a second direction (such as the Y direction) and are covered by an intermediate dielectric layer 239 made of dielectric material, or by a conductive intermediate layer 239 serving as a control gate (i.e., a coupling gate). Since 65% to 95% of the second sidewall (i.e., the sidewall perpendicular to the Y direction) is covered by the intermediate layer 239, and both first top edges 226a_1 are higher than the lowest bottom surface of the upper gate 235, even if there is a misalignment between the upper gate 235 and the floating gate 224a, the coupling ratio between the upper gate structure 236 and the lower floating gate 224a will not change significantly, thereby improving the electrical characteristic consistency among multiple non-volatile memory elements.

[0039] Figures 4 to 13 are cross-sectional views of various stages in the manufacturing process of non-volatile memory elements (as shown in Figures 1 to 3) in certain embodiments of this disclosure, wherein the cross-sectional view AA' in Figures 4 to 13 corresponds to line A-A' in Figure 1, the cross-sectional view BB' corresponds to line B-B' in Figure 1, and the cross-sectional view CC' corresponds to line C-C' in Figure 1.

[0040] Referring to cross-sectional views AA' and CC' in Figure 4, the structure formed in this manufacturing stage includes at least a substrate 200, a dual stacked structure 310, a dielectric spacer 212, a floating gate dielectric layer 314, and a floating gate layer 316.

[0041] According to certain embodiments of this disclosure, the substrate 200 may be a semiconductor substrate having a suitable conductivity type, such as p-type or n-type. The material of the substrate 200 may include, but is not limited to, silicon, germanium, gallium nitride or other suitable semiconductor materials.

[0042] Stacked structures 310 are disposed on substrate 200 and are laterally separated from each other. Each stacked structure 310 sequentially includes a select gate dielectric layer 302, a select gate layer 304, and an insulating layer 306. The select gate layer 304 is made of a conductive material. In subsequent processes, the select gate layer 304 can be patterned to form a select gate (not shown) to control the switching of carrier channels disposed in the substrate 200 below the select gate layer 304. The insulating layer 306 is made of an insulating material, such as silicon oxide or silicon oxynitride, but not limited to these, and the insulating layer 306 is used to electrically isolate the select gate layer 304 from the layer above it.

[0043] Dielectric spacer 212 is formed on the sidewalls 211 and 213 of the stacked structure 310. The material of the dielectric spacer 212 may be a silicon oxide / silicon nitride / silicon oxide stacked structure or a silicon nitride / silicon oxide stacked structure.

[0044] A floating gate dielectric layer 314 is formed on the stacked structure 310 and within the gap 312 between the stacked structures 310. The material of the floating gate dielectric layer 314 is, for example, silicon oxide, or other materials that allow hot electrons to tunnel through.

[0045] A floating gate layer 316 is disposed on top of a floating gate dielectric layer 314. The thickness of the floating gate layer 316 can be appropriately controlled so that it conforms to the shape of the underlying structure. The floating gate layer 316 can be made of a conductive material, such as polycrystalline silicon or metal, but is not limited thereto.

[0046] The floating gate layer 316 includes a recessed region 318 located directly above the gap 312. The bottom surface 318_1 of the recessed region 318 may be higher than the top surface 310_0 of the stacked structure 310. In section AA', the thickness T11 of the floating gate layer 316 located below the recessed region 318 is less than the thickness T12 of the floating gate layer 316 in section CC'.

[0047] Figure 5 is a cross-sectional view after the manufacturing stage as shown in Figure 4. In Figure 5, the thickness of the floating gate layer 316 is reduced to the required value through an etch-back process. This process continues to etch the floating gate layer 316 until the bottom surface 318_1 of the recessed region 318 is lower than the top surface 310_0 of the stacked structure 310. When the etch-back process is completed, the thickness T21 of the floating gate layer 316 located below the recessed region 318 in cross-section AA' is still less than the thickness T22 of the floating gate layer 316 in cross-section CC'.

[0048] In some embodiments, if the thickness of the floating gate layer 316 can be properly controlled to the required value in the deposition process shown in FIG4, the back etching process shown in FIG5 can be omitted.

[0049] Figure 6 is a cross-sectional view after the manufacturing stage as shown in Figure 5. In Figure 6, a first masking layer 330 is formed on the floating gate layer 316 and fills the recessed region 318. The first masking layer 330 is formed by, for example, chemical vapor deposition (CVD), but is not limited to this. The material of the first masking layer 330 is different from the material of the floating gate layer 316. For example, the first masking layer 330 may be an insulating material or a semiconductor material. In some embodiments, the first masking layer 330 is an insulating material, such as silicon oxide, silicon nitride, or silicon nitride. After the first masking layer 330 is formed, a planarization process is performed on the first masking layer 300 until a flat top surface 330_0 is obtained.

[0050] Figure 7 is a cross-sectional view after the manufacturing stage as shown in Figure 6. Referring to Figures 7 and 6, a single etch-back process or a series of etch-back processes can be performed on the first masking layer 330 and the floating gate layer 316 to remove the upper part of the first masking layer 330 and the floating gate layer 316. During the etch-back process, the top surface 316_0 of the floating gate layer 316 will be exposed from the first masking layer 330.

[0051] In some embodiments, when the etch selectivity ratio between the first masking layer 330 and the floating gate layer 316 is 0.7 to 1.3, it can be considered that the upper part of the first masking layer 330 and the upper part of the floating gate layer 316 will be removed simultaneously. In some embodiments, if the etch selectivity is not in the range of 0.7 to 1.3, the upper parts of the first masking layer 330 and the floating gate layer 316 can be removed separately by a series of etch-back processes.

[0052] After the etch-back process is completed, as shown in FIG7, a first mask 336 is formed in the recessed area 318, and the upper part of the floating gate layer 316 is removed to leave the lower part of the floating gate layer 316 in the gap 312. The floating gate layer 316 in the gap 312 includes a top surface 316_0 that is laterally separated from each other and exposed from the first mask 336.

[0053] Figure 8 is a cross-sectional view of Figure 7 after the manufacturing stage. Referring to Figure 8, under the cover of the first mask 336, the top surface 316_0 of the floating gate layer 316 exposed from the first mask 336 is transformed into the second mask 340.

[0054] The conversion process may include a heat treatment process, an ion implantation process, and / or an amorphization process. In some embodiments, if the conversion process includes a heat treatment process, the exposed top surface of the floating gate layer 316 may be oxidized and / or nitrided (in this case, the first masking layer 330 in FIG. 6 will be a non-nitride material, and its top surface will be nitrided resistant), forming a second masking layer 340 composed of oxides and / or nitrides, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, if the conversion process includes an ion implantation process, the exposed top surface of the floating gate layer 316 will be modified to contain a second masking layer 340 containing dopants, which may contain carbon, oxygen, nitrogen, or combinations thereof, but are not limited thereto. In some embodiments, if the conversion process includes an amorphization process, the exposed top surface of the floating gate layer 316 may be modified to contain a second masking layer 340 with an amorphous structure.

[0055] In some embodiments, the maximum thickness of the first mask 336 is greater than the maximum thickness of each of the second masks 340, and the bottom surface 336_1 of the first mask 336 is lower than the bottom surface 340_1 of the second mask 340. Since the material and / or structure of the first mask 336 is different from that of the second mask 340, in the subsequent process of removing the first mask 336, the etch selectivity ratio between the first mask 336 and the second mask 340 is greater than 3.

[0056] Figure 9 is a cross-sectional view after the manufacturing stage as shown in Figure 8. Referring to Figure 9, the first mask 336 in the recessed area 318 is removed, exposing the bottom surface 318_1 of the recessed area 318. Since the etch selectivity ratio of the first mask 336 to the second mask 340 is greater than 3 (e.g., 5, 10, 20, 100 or any value between them) when the first mask 336 is removed, the second mask 340 can still be retained on the floating gate layer 316 when the first mask 336 is completely removed. In some embodiments, when the first mask 336 in the recessed area 318 is removed, the bottom surface 318_1 of the recessed area 318 is lower than the bottom surface 340_1 of each of the second masks 340.

[0057] Figure 10 is a cross-sectional view after the manufacturing stage as shown in Figure 9. Referring to Figure 10, an anisotropic etching process is performed on the floating gate layer 316 using the second mask 340 as an etching mask. In this way, the floating gate layer 316 in the gap 312 can be divided into two separate parts, namely two floating gate layers 350. The floating gate layers 350 in the first memory cell region 110 and the second memory cell region 112 can be laterally separated from each other along the X direction, and each floating gate layer 350 can extend along the Y direction. Since each floating gate layer 350 is a self-aligned structure and has vertical or inclined sidewalls, it is not necessary to use photolithography to form the floating gate layer 350.

[0058] Figure 11 is a cross-sectional view after the manufacturing stage as shown in Figure 10. Referring to the cross-sectional view AA' of Figure 10, the source region 222 is formed in the substrate 200. In some embodiments, the method for forming the source region 222 may include, for example, an ion implantation process. The implanted dopant may be determined as an n-type dopant or a p-type dopant depending on the design of the memory element.

[0059] After the source region 222 is formed, a photolithography process is performed to form a stacked layer on the stacked structure 310 and the floating gate layer 350. Referring to cross-sections AA' and CC' of FIG11, the stacked layer includes at least a bottom layer 360 and a patterned photoresist layer 362 stacked from bottom to top. The bottom layer 360 may be a single layer or a multi-layer stack, which may include an organic dielectric layer (ODL), a spin-on carbon layer (SOC), a bottom anti-reflective coating (BARC), etc. The bottom layer 360 can fill the gaps 312 and form a flat top surface. In some embodiments, in order to form a bottom layer 360 with a flat top surface, at least one sublayer of the bottom layer may be formed using a spin coating process.

[0060] Referring to cross-sections AA' and CC' of FIG11, the patterned photoresist layer 362 includes at least two strip structures. Each strip structure extends along the X direction (as shown in cross-section AA'), and the strip structures are separated from each other along the Y direction (as shown in cross-section CC').

[0061] Referring to the cross-sectional view BB' of FIG11, the bottom layer 360 is not covered by the patterned photoresist layer 362. Therefore, in the subsequent etching process, the exposed bottom layer 360 will be removed.

[0062] Figure 12 is a cross-sectional view after the manufacturing stage as shown in Figure 11. Referring to Figures 11 and 12, an etching process or a series of etching processes are performed to transfer the pattern of the patterned photoresist layer 362 to the floating gate layer 350 below.

[0063] Referring to the cross-sectional view AA' of FIG12, during the etching process, the bottom layer 360 covered by the patterned photoresist layer 362 may be slightly etched, so the thickness of the bottom layer 360 will be reduced.

[0064] Referring to the cross-sectional view BB' of FIG12, compared to the portion of the bottom layer 360 covered by the patterned photoresist layer 362 in cross-sectional view AA', the bottom layer 360 that was not originally covered by the patterned photoresist layer 362 is etched to a greater extent. In addition, portions of the second mask 340 and the floating gate layer 350 that were not originally covered by the patterned photoresist layer 362 are also etched simultaneously during this etching process.

[0065] Referring to the cross-sectional view CC' of FIG12, the portion of the floating gate layer 350 that was not originally covered by the patterned photoresist layer 362 will be etched. As a result, at least one recessed region 366 can be formed in the floating gate layer 350 during the etching process.

[0066] Figure 13 is a cross-sectional view after the manufacturing stage as shown in Figure 12. The etching process shown in Figure 12 can continue until several floating gates 224a as shown in Figure 13 are formed.

[0067] Referring to the cross-sectional view AA' of FIG12, after the manufacturing stage of FIG12, the bottom layer 360 originally covered by the patterned photoresist layer 362 can be further etched, so that the thickness of the bottom layer 360 is further reduced.

[0068] Referring to the cross-sectional view BB' of FIG12, when the etching process is completed, the bottom layer 360 that was not originally covered by the patterned photoresist layer 362 can be completely removed. In addition, when the etching process is completed, the second mask 340 and the floating gate layer 350 that were not originally covered by the patterned photoresist layer 362 will also be completely removed.

[0069] Referring to the cross-sectional view CC' of FIG12, the portion of the floating gate layer 350 that was not originally covered by the patterned photoresist layer 362 will be completely removed, resulting in the formation of floating gates 224a that are separated from each other.

[0070] After the manufacturing stage of FIG13, the remaining bottom layer 360 can be peeled off, and the second cover 340 covering the floating gate 224a can also be removed. After the second cover 340 is removed, the floating gate 224a may include a top tip 228, which is laterally separated from the bottom surface of the floating gate 224a.

[0071] Next, the select gate layer 304 can be patterned to form a select gate 204 as shown in Figures 1 to 3. At least one drain region 244, for example two drain regions 244, can be formed on both sides of the select gate 204. In subsequent processes, the drain regions 224 can be electrically coupled to each other via vias or contacts.

[0072] Subsequently, other electronic components can be manufactured through a suitable manufacturing process to obtain non-volatile memory elements with structures similar to those shown in Figures 1 to 3.

[0073] Figures 14 and 15 are schematic cross-sectional views of the various stages of manufacturing the non-volatile memory element shown in Figures 1 to 3, according to the alternative embodiments disclosed herein. Some processes in Figures 4 to 13 may be replaced or modified by the processes shown in Figures 14 and 15. For the sake of brevity, only the main differences between the two embodiments are described. In Figures 14 and 15, cross-section AA' corresponds to line A-A' in Figure 1, cross-section BB' corresponds to line B-B', and cross-section CC' corresponds to line C-C'.

[0074] Referring to Figures 8 and 14, the process stage in Figure 14 follows the process stage in Figure 8. In the cross-sectional view CC' of Figure 8, the second mask 340 is continuously distributed along the Y direction. Next, the second mask 340 is patterned using photolithography and etching processes to obtain the second mask 340 discontinuously distributed along the Y direction as shown in the cross-sectional view CC' of Figure 14.

[0075] Next, referring to Figures 14 and 15, using the second mask 340 as an etching mask, a single etching process or a series of etching processes are performed on the underlying floating gate layer 350 to transfer the pattern of the second mask 340 to the floating gate layer 350. As shown in Figure 15, several floating gates 224a are formed. During this pattern transfer process, there is no organic dielectric layer (ODL), spin-coated carbon layer (SOC), or bottom anti-reflective coating (BARC) on the floating gate layer 350. Therefore, no organic matter or conductive residue remains on the substrate 200 when the floating gates 224a are formed.

[0076] Other processes similar to those shown in Figures 4 to 13 can be performed to obtain non-volatile memory elements with structures similar to those shown in Figures 1 to 3.

[0077] According to the above embodiments, the process stages illustrated in Figures 4 to 15 can be used to manufacture non-volatile memory elements with structures similar to those in Figures 1 to 3. In alternative embodiments, the process shown in Figures 4 to 15 can also be modified to manufacture non-volatile memory elements in which an embedded erase gate structure (not shown) is formed in a trench (not shown) of the substrate 200. In this configuration, the lower tip (not shown) of the floating gate 224a can be partially covered in the embedded erase gate structure. During the erase operation of the non-volatile memory element 100, by applying a bias voltage to the embedded erase gate structure, the previously stored electrons can be extracted more effectively from the lower tip of the floating gate 224a. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0013] The drawings disclosed herein are used to further illustrate the present invention and are incorporated into and constitute a part of this specification. These drawings illustrate embodiments of the present invention and are accompanied by detailed textual descriptions to explain the principles of the invention. Figure 1 is a top view of a non-volatile memory element shown in some embodiments of the present disclosure. Figure 2 is a cross-sectional view of a non-volatile memory element corresponding to lines A-A', B-B', and C-C' in some embodiments of the present disclosure. Figure 3 is an enlarged cross-sectional view of the region of the non-volatile memory element shown in Figure 2 in some embodiments of the present disclosure. Figures 4 to 13 are cross-sectional views of various stages in the manufacturing process of the non-volatile memory element in some embodiments of the present disclosure. Figures 14 to 15 are cross-sectional views of various stages in the manufacturing process of the non-volatile memory element in alternative embodiments of the present disclosure.

Claims

1. A method for manufacturing a non-volatile memory element, comprising: Provide a substrate; A dual stacked structure is formed on the substrate, each stacked structure including a selectable gate layer and a selectable gate dielectric layer, and a gap is formed between the dual stacked structures; a floating gate layer is formed on the substrate, the floating gate layer covering the dual stacked structures and the substrate, and filling the gap, wherein the floating gate layer includes a recessed region; a first masking layer is filled into the recessed region; an upper portion of the first masking layer is removed to form a first mask in the recessed region; an upper portion of the floating gate layer is removed to retain the floating gate layer in the gap, wherein the two top surfaces of the floating gate layer located in the gap are laterally separated from the first mask; under the coverage of the first mask, the two top surfaces of the floating gate layer are converted into a plurality of second masks; the first masks located in the recessed region are removed; and the second masks are used as an etching mask to etch the floating gate layer.

2. The method for manufacturing a non-volatile memory element as described in claim 1, wherein, When the first masking layer is filled into the recessed area, a bottom surface of the first masking layer is lower than a top surface of each of the stacked structures.

3. The method for manufacturing a non-volatile memory element as described in claim 1, wherein, When the upper part of the floating gate layer is removed, the floating gate layer includes a top surface exposed to the first shield.

4. The method of manufacturing a non-volatile memory element as claimed in claim 1, wherein the removal of the upper portion of the first masking layer and the removal of the upper portion of the floating gate layer are performed simultaneously.

5. The method for manufacturing a non-volatile memory element as described in claim 1, wherein, When the two top surfaces of the floating gate layer are converted into the second shields, each of the top surfaces of the floating gate layer located in the gap will be oxidized to form the second shields.

6. The method of manufacturing a non-volatile memory element as claimed in claim 1, wherein the material of the first mask is different from the material of the second masks.

7. The method of manufacturing a non-volatile memory element as claimed in claim 6, wherein the material of the first mask comprises a nitride or a nitrogen oxide, and the material of the second masks comprises an oxide or a nitrogen oxide.

8. The method of manufacturing a non-volatile memory element as claimed in claim 6, wherein when removing the first mask located in the recessed region, the etch selectivity ratio between the first mask and the second masks is greater than 3.

9. The method of manufacturing a non-volatile memory element as claimed in claim 1, wherein the maximum thickness of the first mask is greater than the maximum thickness of each of the second masks.

10. The method of manufacturing a non-volatile memory element as claimed in claim 1, wherein after removing the first mask located in the recessed region, a bottom surface of the recessed region is lower than a bottom surface of each of the second masks.

11. The method of manufacturing a non-volatile memory element as described in claim 1, wherein, After etching the floating gate layer, the method further includes patterning the floating gate layer to form a plurality of floating gates that are separated from each other.

12. The method of manufacturing a non-volatile memory element as described in claim 1, wherein, Before etching the floating gate layer, in a top view, the second masks are continuously distributed along a direction, and the method further includes: before etching the floating gate layer, patterning the second masks such that the second masks are discontinuously distributed along the direction.

13. The method of manufacturing a non-volatile memory element as claimed in claim 1, wherein at least one floating gate is formed by etching the floating gate layer, and the at least one floating gate includes a top tip extending toward one of the stacked structures.

14. The method of manufacturing a non-volatile memory element as claimed in claim 13, wherein a portion of the top tip is laterally separated from a bottom surface of the at least one floating gate.

15. A non-volatile memory element comprising at least one memory cell, the at least one memory cell comprising: One substrate; A selector gate is disposed on the substrate; The system includes: a floating gate disposed on the substrate and laterally separated from the selection gate; two first top edges disposed opposite each other along a first direction, each first top edge being higher than a top surface of the selection gate, wherein one of the two first top edges is adjacent to the selection gate, and the first top edge adjacent to the selection gate is laterally separated from a bottom surface of the floating gate; two first sidewalls disposed opposite each other along the first direction and respectively connecting the two first top edges; and two second sidewalls disposed opposite each other along a second direction, the second direction being different from the first direction.

16. The non-volatile memory element as claimed in claim 15, wherein one of the two first sidewalls is opposite to the select gate and is a vertical sidewall or an inclined sidewall.

17. The non-volatile memory element as claimed in claim 15, wherein the two second sidewalls are vertical or inclined sidewalls, respectively.

18. The non-volatile memory element as claimed in claim 15, further comprising: An intermediate structure covers one of the two first sidewalls of the floating gate and is disposed opposite to the selection gate along the first direction; wherein the floating gate is located between the intermediate structure and the selection gate, a top surface of the intermediate structure is at the same height as or lower than one of the two first top edges of the floating gate, and the intermediate structure includes an insulating structure or a control gate.

19. The non-volatile memory element as claimed in claim 15, wherein the floating gate further includes a top tip, and a top edge of the top tip is adjacent to the first top edge of the selected gate.

20. The non-volatile memory element as claimed in claim 15, further comprising an upper gate structure covering the select gate and the floating gate, wherein the first top edge adjacent to the select gate is embedded in the upper gate structure.

Images