A receiver employing reference-free clock clock data recovery technology

Abstract

A receiver is configured to apply channel compensation to an input data signal to generate a data input to be decoded, generate a clock output, decode the data input to be decoded into a decoded output based on the clock output, and convert the decoded output into a converted output. The receiver determines whether a condition is met, including: the digital value of the data portion representing a sample of the converted output is equal to an upper limit value; and the voltage level of a first sample in the data input to be decoded is greater than the voltage level of a second sample generated before the first sample. When the condition is met, the receiver determines whether the frequency of the clock output is slow or fast based on a portion of the samples in the decoded output. The receiver adjusts the frequency of the clock output based on the determination of the clock output frequency.

Claims

1. A receiver comprising: a channel compensator for receiving an input data signal in Pulse Amplitude Modulation (PAM)-2M format and applying channel compensation to the input data signal to generate a data input to be decoded in PAM-R format due to pulse shaping and including a plurality of samples, the input data signal including a plurality of samples arranged in a time sequence, the samples of the data input to be decoded respectively corresponding to the samples of the input data signal, wherein M≥1; an oscillator for generating a frequency-adjustable clock output; and a decoder electrically connected to the channel compensator and the oscillator to receive the data input to be decoded and the clock output, and decoding the data input to be decoded according to the clock output into a decoded output including a plurality of samples, the samples of the decoded output respectively corresponding to the samples of the input data signal, and the samples of the decoded output being a digital representation of the samples of the data input to be decoded; A processor, electrically connected to the decoder to receive the decoded output, and also electrically connected to the oscillator, is used to convert the decoded output into a converted output comprising multiple samples, each sample of the converted output corresponding to a sample of the input data signal, and each of the samples of the converted output having a data portion, the data portion being a digital representation of a corresponding sample of the input data signal; wherein, The processor determines whether a first condition is met based on the decoded output and the converted output. The first condition includes: a bit value of the data portion of a first sample of the converted output corresponding to a first sample of the input data signal is equal to an upper limit value representing a plurality of bit values ​​of the data portions of the converted output samples; a voltage level of a first sample of the data input to be decoded corresponding to the first sample of the input data signal is greater than a voltage level of a second sample of the data input to be decoded corresponding to a second sample of the input data signal; and the second sample of the input data signal is in temporal order preceding the first sample of the input data signal. When the first condition is met, the processor refers to a first sample of the decoded output corresponding to the first sample of the input data signal, and refers to other samples of the decoded output, to determine whether the frequency of the clock output is slow or fast; and the other samples of the decoded output correspond to other samples in the input data signal that are in temporal order following the first sample. Specifically, when the processor determines that the frequency of the clock output is slow, it controls the oscillator to increase the frequency of the clock output; when the processor determines that the frequency of the clock output is fast, it controls the oscillator to decrease the frequency of the clock output.

2. The receiver as described in claim 1, wherein, When the first condition is satisfied, the first sample of the decoded output and the other samples indicate a voltage level of the input data to be decoded. If the voltage level gradually increases from below a first reference level to between a second reference level and a third reference level, then the frequency of the clock output is determined to be slow, and the second reference level is greater than the first reference level and less than the third reference level.

3. The receiver as described in claim 2, wherein, When the first condition is satisfied, the voltage level of the data to be decoded is indicated by the first sample and the other samples of the decoded output. If the voltage level gradually decreases from between the second reference level and the third reference level to below the first reference level, the frequency of the clock output is determined to be fast.

4. The receiver as described in claim 2, wherein: M≥2; The pulse shaping is 1+0.5D pulse shaping; The decoder decodes the input data to be decoded into the decoded output according to a number of () clipping levels; The first condition also includes that the voltage level of the first sample of the input data to be decoded is substantially equal to the third largest clipping level among the clipping levels; The first reference level is equal to the third largest clipping level among the clipping levels; The second reference level is equal to the second largest clipping level among the clipping levels; The third reference level is equal to the largest clipping level among the clipping levels.

5. The receiver as described in claim 4, wherein, The first condition also includes that the voltage level of the second sample of the data to be decoded is substantially no greater than the fifth largest cut level among the cut levels in order of size.

6. The receiver as described in claim 1, wherein, When the bit value of the data portion representing the first sample of the conversion output is greater than the bit value of the data portion representing the second sample of the conversion output, it is determined that the voltage level of the first sample in the data input to be decoded is greater than the voltage level of the second sample, and the second sample of the data input to be decoded corresponds to the second sample of the input data signal.

7. The receiver as described in claim 1, wherein: M≥2; The pulse shaping is 1+0.5D pulse shaping; The decoder decodes the input data to be decoded into the decoded output according to a number of () clipping levels; The first condition also includes that the voltage level of the first sample of the input data to be decoded is substantially equal to one of the clipping levels that is the third largest clipping level in order of size.

8. The receiver as described in claim 1, wherein, The processor also determines whether a second condition is met, the second condition including: the bit value of the data portion of the first sample of the converted output is equal to a lower limit value of the bit values ​​of the data portions of the samples of the converted output; the voltage level of the first sample of the data input to be decoded is less than the voltage level of the second sample of the data input to be decoded; when the second condition is met, the processor refers to the first sample of the decoded output and the other samples to determine whether the frequency of the clock output is slow or fast.

9. The receiver as described in claim 8, wherein, When the second condition is satisfied, the voltage level of the data to be decoded is indicated by the first sample and the other samples of the decoded output. If the voltage level gradually decreases from above a fourth reference level to between a fifth reference level and a sixth reference level, then the frequency of the clock output is determined to be slow, and the fifth reference level is greater than the sixth reference level and less than the fourth reference level.

10. The receiver as described in claim 9, wherein, When the second condition is satisfied, the voltage level of the input data to be decoded is indicated by the first sample and the other samples of the decoded output. If the voltage level gradually rises from between the fifth reference level and the sixth reference level to above the fourth reference level, the frequency of the clock output is determined to be fast.

11. The receiver as described in claim 9, wherein: M≥2; The input data to be decoded is in PAM-M format due to pulse shaping of 1+0.5D; The decoder decodes the input data to be decoded into the decoded output according to a number of () clipping levels; The second condition also includes that the voltage level of the first sample of the input data to be decoded is substantially equal to the third smallest clipping level among the clipping levels; The fourth reference level is equal to the third smallest clipping level among the clipping levels; The fifth reference level is equal to the second smallest clipping level among the clipping levels; The sixth reference level is equal to the smallest clipping level among the clipping levels.

12. The receiver as described in claim 11, wherein, The second condition also includes that the voltage level of the second sample of the data to be decoded is substantially not less than the fifth smallest clipping level among the clipping levels in order of size.

13. The receiver as described in claim 8, wherein, When the bit value of the data portion representing the first sample of the conversion output is less than the bit value of the data portion representing the second sample of the conversion output, it is determined that the voltage level of the first sample in the data input to be decoded is less than the voltage level of the second sample, and the second sample of the data input to be decoded corresponds to the second sample of the input data signal.

14. The receiver as described in claim 8, wherein: M≥2; The input data to be decoded is in PAM-M format due to pulse shaping of 1+0.5D; The decoder decodes the input data to be decoded into the decoded output according to a number of () clipping levels; The second condition also includes that the voltage level of the first sample of the input data to be decoded is substantially equal to the third smallest clipping level among the clipping levels in order of size.

15. A receiver comprising: a channel compensator for receiving an input data signal in Pulse Amplitude Modulation (PAM)-2M format and applying channel compensation to the input data signal to generate a data input to be decoded in PAM-R format due to pulse shaping and including a plurality of samples, the input data signal including a plurality of samples arranged in a time sequence, the samples of the data input to be decoded respectively corresponding to the samples of the input data signal, wherein M≥1; an oscillator for generating a frequency-adjustable clock output; and a decoder electrically connected to the channel compensator and the oscillator to receive the data input to be decoded and the clock output, and decoding the data input to be decoded according to the clock output into a decoded output including a plurality of samples, the samples of the decoded output respectively corresponding to the samples of the input data signal, and the samples of the decoded output being digital representations of the samples of the data input to be decoded. A processor, electrically connected to the decoder to receive the decoded output, and also electrically connected to the oscillator, is used to convert the decoded output into a converted output comprising multiple samples, each sample of the converted output corresponding to a sample of the input data signal, and each of the samples of the converted output having a data portion, the data portion being a digital representation of one of the corresponding samples of the input data signal; wherein, The processor determines whether a condition is met based on the decoded output and the converted output. The condition includes: a bit value of the data portion of the first sample of the converted output corresponding to a first sample of the input data signal is equal to a lower limit value; a voltage level of a first sample of the data input to be decoded corresponding to the first sample of the input data signal is greater than a voltage level of a second sample of the data input to be decoded corresponding to a second sample of the input data signal; and the second sample of the input data signal is arranged in time before the first sample of the input data signal.

16. The receiver as described in claim 15, wherein, When the condition is satisfied, the first sample and some other samples of the decoded output indicate a voltage level of the input data to be decoded. If the voltage level gradually decreases from above a first reference level to between a second reference level and a third reference level, then the frequency of the clock output is determined to be slow, and the second reference level is less than the first reference level and greater than the third reference level.

17. The receiver as described in claim 16, wherein, When the condition is met, the voltage level of the input data to be decoded is indicated by the first sample and the other samples of the decoded output. If the voltage level gradually increases from between the second reference level and the third reference level to above the first reference level, then the frequency of the clock output is determined to be fast.

18. The receiver as described in claim 16, wherein, M≥2; The input data to be decoded is in PAM-M format due to pulse shaping of 1+0.5D; The decoder decodes the input data to be decoded into the decoded output according to a number of () clipping levels; The condition also includes that the voltage level of the first sample of the input data to be decoded is substantially equal to the third smallest clipping level among the clipping levels; The first reference level is equal to the third smallest clipping level among the clipping levels; The second reference level is equal to the second smallest clipping level among the clipping levels; The third reference level is equal to the smallest clipping level among the clipping levels.

19. The receiver as described in claim 18, wherein, The condition also includes that the voltage level of the second sample of the data to be decoded is not substantially greater than the fifth smallest cut level among the cut levels in order of size.

20. The receiver as described in claim 15, wherein, When the bit value of the data portion representing the first sample of the conversion output is less than the bit value of the data portion representing the second sample of the conversion output, it is determined that the voltage level of the first sample in the data input to be decoded is less than the voltage level of the second sample, and the second sample of the data input to be decoded corresponds to the second sample of the input data signal.

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