Manufacturing methods of electronic components

Abstract

This invention provides a method for manufacturing an electronic component, which sequentially includes the following steps: providing a wafer body, applying a silver paste composition, forming a semi-sintered layer, providing a wafer and lead frame with the semi-sintered layer, applying the semi-sintered layer, and sintering. This method reduces misalignment, streamlines processes, simplifies manufacturing, and lowers cost risks. The resulting electronic component exhibits high thrust strength, low porosity, and minimal thickness variation.

Claims

1. A method for manufacturing an electronic component, comprising first fabricating a wafer (10) having a semi-sintered layer and then subsequently fabricating an electronic component (100), wherein the wafer (10) having the semi-sintered layer comprises a wafer body (11) and a semi-sintered layer (12) covering the wafer body (11), the wafer body (11) comprising a crystal material layer (110) and a back metal layer (BM), the crystal material layer (110) comprising a crystal material upper surface (F) and a crystal material lower surface (B) corresponding to the crystal material upper surface (F), the back metal layer (BM) covering the crystal material lower surface (B), and the semi-sintered layer (12) comprising a crystal material upper surface (F) and a back metal layer (BM) covering the crystal material lower surface (B), the semi-sintered layer (10) comprising a crystal material lower ... The back metal layer (BM) is a back metal lower surface (BMS) covered by the back metal layer (BM); the back metal layer (BM) forms a wafer circuit pattern (P1) on the lower surface (B) of the crystal material, and the area on the lower surface (B) of the crystal material without the wafer circuit pattern (P1) is a non-wafer circuit pattern area (NP1); the semi-sintered layer (12) includes a half-sintered pattern (P0) and a non-sintered pattern area (NP0), the half-sintered pattern (P0) is covered on the lower surface of the wafer circuit pattern (P1), the non-sintered pattern area (NP0) is correspondingly disposed on the non-wafer circuit pattern area (NP1), and the semi-sintered layer (12) does not cover the non-wafer circuit pattern area (NP1); wherein, The manufacturing method of the electronic component includes the following steps in sequence: a chip body provision step (S1), which provides the chip body (11); a silver paste coating step (S2), in which a silver paste is coated onto the upper surface of the chip circuit pattern (P1) in a silver paste coating manner, and the silver paste is not coated onto a non-chip circuit pattern area (NP1) to form a half-sintered semi-finished product; a half-sintered layer formation step (S3): the half-sintered semi-finished product is half-sintered under half-sintering protective atmosphere and half-sintering conditions, so that the silver paste is transformed into the half-sintered layer (12) to form the chip (10) with the half-sintered layer; A step (S4) of providing a wafer (10) with a semi-sintered layer and a lead frame (20) involves providing the wafer (10) with the semi-sintered layer and a lead frame (20), with the semi-sintered layer (12) facing the upper surface of the lead frame (20). A lead frame circuit pattern (P2) is provided on the upper surface of the lead frame (20), and the area on the upper surface of the lead frame (20) without the lead frame circuit pattern (P2) is a non-lead frame circuit pattern area (NP2). A step (S5) of coating the semi-sintered layer involves aligning the semi-sintered pattern (P0) and coating it onto the upper surface of the lead frame circuit pattern (P2), and aligning and correspondingly placing the non-sintered pattern area (NP0) on the non-lead frame circuit pattern area (NP2) to form a sintered semi-finished product. A sintering step (S6) involves sintering the sintered semi-finished product under a sintering protective atmosphere and sintering conditions, so that the semi-sintered layer (12) and the semi-sintered pattern (P0) become a bonding layer (12') and a sintered pattern (P0') respectively, to form the electronic component (100).

2. The method for manufacturing the electronic component as described in claim 1, wherein, The thickness of the semi-sintered layer (12) is 90% to 98% of the thickness of the silver paste composition, and / or the thickness of the bonding layer (12') is 79.33% to 96.4% of the thickness of the silver paste composition.

3. A method for manufacturing an electronic component as described in claim 1, wherein, The semi-sintering conditions are 70℃~120℃ for 3~10 minutes without pressure, and the sintering conditions are 250℃ with a pressure of 10MPa applied to the sintered semi-finished product for 5 minutes.

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