Integrated circuit device, and manufacturing method of memory macro

Abstract

A memory macro includes input / output (I / O) circuitry located in a semiconductor wafer; a row of memory cells including a first and a second subset of consecutive memory cells extending away from the I / O circuitry in the semiconductor wafer, wherein the first subset is located between the I / O circuitry and the second subset; a first bit line coupled to the I / O circuitry and extending along the first subset on either the front or back side of the semiconductor wafer and terminating in the second subset; and a second bit line coupled to the I / O circuitry and extending along the first and second subsets on either the front or back side. Each memory cell in the first subset is electrically connected to the first bit line, and each memory cell in the second subset is electrically connected to the second bit line.

Description

[Technical Field]

[0001] This disclosure relates to an integrated circuit device and a method for manufacturing a memory macro. [Previous Technology]

[0002] An integrated circuit (IC) typically comprises numerous IC devices fabricated according to one or more IC layouts. IC devices sometimes include memory circuitry, where information is stored as bits in individual memory cells. The type of memory cell may include static random-access memory (SRAM) cells, in which multiple transistors are programmed for write operations and accessed for read operations. In some cases, the transistors are implemented as complementary field-effect transistor (CFET) devices, where the upper FET is stacked over the lower FET. [Summary of the Invention]

[0003] Some embodiments of this disclosure include integrated circuit devices. The integrated circuit device includes a first bit line extending along the front side of a semiconductor wafer in a first direction, a second bit line extending along the back side of the semiconductor wafer in the first direction, and a first CFET SRAM cell and a second CFET SRAM cell positioned between the first bit line and the second bit line. The first CFET SRAM cell includes a first front via structure for electrically connecting a first channel of the first CFET SRAM cell to the first bit line, and the second CFET SRAM cell includes a first back via structure for electrically connecting a second channel of the second CFET SRAM cell to the second bit line. The front and back via structures are aligned in a direction perpendicular to the first direction, and the front and back via structures are disposed at relative positions to the first and second CFET SRAM cells.

[0004] Some embodiments of this disclosure include a method of manufacturing a memory macro. The method of manufacturing a memory macro includes constructing a row of memory cells in a semiconductor wafer, wherein constructing the row of memory cells includes constructing a first subset and a second subset of consecutive memory cells, and the first subset includes constructing a first subset and a second subset of consecutive memory cells, and the first subset is positioned between the second subset of the memory macro and I / O circuitry; forming a first front metal segment from the I / O circuitry to the second subset and above the first subset, wherein the first front metal segment is electrically connected to each memory cell of one of the first subset or the second subset; and forming a first back metal segment from the I / O circuitry to the second subset and above the first subset, wherein the first back metal segment is electrically connected to each memory cell of the other of the first subset or the second subset. The first front metal segment and the first back metal segment are disposed at relative positions within the row of memory cells.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, values, operations, materials, configurations, or the like are described below to simplify some embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of some embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0008] In various embodiments, the memory macro row includes first and second subsets of consecutive memory cells extending away from the input / output (I / O) circuitry, one of the front or back bit lines electrically connected to the I / O circuitry and the first subset and terminating in the second subset, and another of the front or back bit lines extending beyond the first subset and electrically connected to the I / O circuitry and the second subset. By separating the bit lines into separate front and back paths through electrical connections, parasitic resistance and capacitance bit line loads are reduced compared to other methods, thereby improving speed and power performance during read and write operations.

[0009] In some embodiments, the memory cell includes a static random-access memory (SRAM) cell that includes a complementary field-effect transistor (CFET) device, wherein stacked channel gates are used to separately connect adjacent cells to either a front-side or back-side bit line, thereby enabling support for a continuous boundary between a first subset and a second subset. The memory cell density is thus maintained compared to a method where the boundary between the first subset and the second subset does not include cells capable of separating front-side and back-side bit line connections.

[0010] Figure 1 is a schematic diagram of memory macro 100; Figures 2A and 2B are schematic diagrams and plan views of SRAM memory cells 200 and corresponding integrated circuit (IC) layout diagrams 200 and devices 200; Figures 3A to 4C depict IC layout diagrams according to various embodiments and embodiments of corresponding IC devices in which the boundary between the first and second subsets of memory cells includes instances of memory cells 200. According to various embodiments, Figure 5 depicts a method of operating memory macro 100; Figure 6 depicts a method of generating IC layout diagrams; Figure 7 depicts a method of manufacturing IC devices; Figure 8 is a block diagram of an IC layout diagram generation system; and Figure 9 is a block diagram of an IC manufacturing system and associated IC manufacturing processes.

[0011] The figures in this document, such as Figures 1 through 4C, are simplified for illustrative purposes. These figures depict IC structures, devices, and layouts that include and exclude various features to facilitate the discussion below. In various embodiments, in addition to the features depicted in Figures 1 through 4C, the IC structures, devices, and / or layouts also include one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, body connections, or other transistor elements, dielectric layers, isolation structures, or the like.

[0012] In IC layout diagrams / devices 200-400, reference indicators represent both IC device features and IC layout features used to at least partially define the corresponding IC device features in a manufacturing process (e.g., the method 700 described below with respect to Figure 7 and / or the IC manufacturing process associated with the IC manufacturing system 900 described below with respect to Figure 9). Therefore, IC layout diagram / device 200 represents a plan view of both IC layout diagram 200 and the corresponding IC device 200, and IC layout diagrams / devices 300 and 400 represent views of both IC layout diagrams 300 and 400 and the corresponding IC devices 300 and 400.

[0013] Figure 1 depicts a memory macro 100 oriented in a semiconductor wafer 100B with respect to the X and Y directions in a non-limiting example. In some embodiments, the semiconductor wafer 100B is referred to as substrate 100B or wafer 100B.

[0014] Memory macro 100, also referred to in some embodiments as memory circuit 100, IC 100, or circuit 100, includes at least one array 100A of memory cells 110 for storing data, and memory circuitry for controlling one or more circuits for controlling the data input, output, and storage operations described below. In some embodiments, memory cells 110 include static random-access memory (SRAM) cells. In various embodiments, SRAM cells include 5T transistor SRAM cells, 6T transistor SRAM cells (e.g., memory cell 200 below), 8T transistor SRAM cells, 9T transistor SRAM cells, or SRAM cells having other numbers of transistors. In various embodiments, memory cell 110 includes a dynamic random-access memory (DRAM) cell, a read-only memory (ROM) cell, a non-volatile memory (NVM) cell, or other memory cell types capable of storing data. The representation of memory cell 110 depicted in Figure 1 is a non-limiting example provided for illustrative purposes.

[0015] The memory macro 100 includes two instances of a region control circuit (CNT), an I / O circuit (MIO), a word line driver (WLD), and a memory array 100A. In some embodiments, the memory macro 100 includes fewer or more instances of the memory array 100A and correspondingly includes more or fewer numbers of region control circuits (CNT), region I / O circuits (MIO), and / or word line drivers (WLD). In some embodiments, in addition to the circuitry depicted in Figure 1, the memory macro 100 also includes one or more circuits.

[0016] The area control circuit CNT is located between and electrically coupled to the two instances of the I / O circuit MIO, and is located adjacent to the word line driver WLD, which is located between and electrically connected to the two instances of the memory array 100A. In various embodiments, the memory macro 100 includes one or more of addresses, data, and / or signal lines (not shown), complementary bit line pairs BLL / BLBL and BLU / BLBU, and word lines WL, thereby electrically coupling the global control circuit (not shown), the area control circuit CNT, the I / O circuit MIO, the word line driver WLD, and the memory array 100A to each other.

[0017] Each of the global control circuit, the regional control circuit CNT, the I / O circuit MIO, and the character line driver WLD is used to perform operations in operation, thereby responding to a combination of address, clock, control, and / or data signals (not shown) to input data into or output from the corresponding instance of memory cell 110 of each instance in the memory array 100A.

[0018] In the embodiment depicted in Figure 1, a representative example of the memory array 100A includes rows 100C of memory cells 110 (two examples depicted for illustrative purposes), each row including a subset 100AU of consecutive memory cells 110 and a subset 100AL of consecutive memory cells 110 located between 100AU and I / O circuit MIO. In some embodiments, subsets 100AU and 100AL are collectively referred to as individual upper library 100AU and lower library 100AL. Subsets 100AU and 100AL are adjacent to each other at boundary 100AB.

[0019] Each of bit lines BLL and BLBL is electrically connected to the I / O circuit MIO and to each instance of memory cell 110 included in subset 100AL, and extends in the X direction along subset 100AL to include instances of memory cell 110 included in subset 100AL and adjacent to boundary 100AB. Thus, each of bit lines BLL and BLBL is considered to extend to boundary 100AB and / or subset 100AU, and / or terminate at boundary 100AB and / or subset 100AU.

[0020] Each of the bit lines BLU and BLBU is electrically connected to the I / O circuit MIO and to each instance of the memory cell 110 included in the subset 100AU, and extends in the X direction along each of the subsets 100AL and 100AU to include the instance of the memory cell 110 included in the subset 100AU and furthest from the I / O circuit MIO.

[0021] One of the bit line pairs BLL / BLBL or BLU / BLBU is located on the front side of the semiconductor wafer 100B, and the other of the bit line pairs BLL / BLBL or BLU / BLBU is located on the back side of the semiconductor wafer 100B.

[0022] In some embodiments, bit lines BLL and BLBL include metal segments located in the lowest front metal layer or the lowest back metal layer, each of which extends from the I / O circuit MIO along subset 100AL to boundary 100AB. In some embodiments, the lowest front metal layer is referred to as the front metal zero layer, and the lowest back metal layer is referred to as the back metal zero layer.

[0023] In some embodiments, bit lines BLU and BLBU include metal segments located in the lowest front metal layer or the lowest back metal layer, wherein each metal segment extends from the I / O circuit MIO along each of the subsets 100AL and 100AU.

[0024] In some embodiments, each of the bit lines BLU and BLBU includes a first metal segment located in a front or back metal layer (e.g., a third metal layer, also referred to as a metal layer 2 in some embodiments) above the lowest front or back metal layer, extending from the I / O circuit MIO along subset 100AL to boundary 100AB; a second metal segment located in the corresponding lowest front or back metal layer, extending from boundary 100AB along each memory cell 110 in subset 100AU; and a via structure electrically connecting the first and second metal segments to each other.

[0025] In some embodiments, memory cell 110 includes CFET-based memory cell 200, and the metal segments of bit line pairs BLL / BLBL and BLU / BLBU are configured according to the embodiments described below with respect to Figures 2B to 4C. In some embodiments, memory cell 110 includes memory cell features other than the CFET-based features of memory cell 200, and the metal segments of bit line pairs BLL / BLBL and BLU / BLBU are configured according to the corresponding bit line features of the embodiments described below with respect to Figures 2B to 4C.

[0026] The total two bit line pairs BLL / BLBL and BLU / BLBU included in each row 100C depicted in Figure 1 are non-limiting examples provided for illustrative purposes. In some embodiments, each row 100C includes bit line configurations other than the total two bit line pairs, for example, a single bit line BLL is located on one of the front or back sides of the semiconductor wafer 100B, and a single bit line BLU is located on the other of the back or front side of the semiconductor wafer 100B.

[0027] Thus, the memory circuit 100 includes an example of a memory macro row 100C, which includes subsets 100AL and 100AU of consecutive memory cells 110 extending away from the I / O circuit MIO, one of the front or back directional bit lines BLL and / or BLBL electrically connected to the I / O circuit MIO and subset 100AL and terminating at subset 100AU, and the other of the front or back directional bit lines BLU and / or BLBU extending beyond subset 100AL and electrically connected to the I / O circuit MIO and subset 100AU. Compared to other methods, by including bit line electrical connections that separate the front and back paths, the parasitic resistive and capacitive bit line loads in the circuit 100 are reduced, thereby improving speed and power performance during read and write operations.

[0028] Figure 2A is a schematic diagram of the 6T SRAM memory cell 200, and Figure 2B is a plan view of the corresponding IC layout / device 200. An example of the memory cell 200 can be used as the memory cell 110 described above with respect to Figure 1.

[0029] As depicted in Figure 2B, the transistors of memory cell 200 are configured as stacked CFET devices, wherein an n-type FET is overlaid with a p-type FET. Other transistor configurations (e.g., stacked CFET devices in which a p-type FET is overlaid with an n-type FET) are also within the scope of some embodiments of this disclosure.

[0030] The memory cell 200 includes n-type transistors N1 to N6 and p-type transistors P1 to P4, and in some embodiments includes P5 and P6, complementary bit lines BL and BLB, a power supply voltage node VDD for allocating power supply voltage VDD, and a reference voltage node VSS for allocating reference voltage VSS.

[0031] Each of transistors N1 and N4 includes a gate electrically connected to the word line WL for receiving the word line signal WL, and in some embodiments, each of transistors P1 and P4 includes a gate electrically connected to the word line WLB for receiving a word line signal WLB that is complementary to the word line signal WL.

[0032] In some embodiments, transistors N1 and N4, and P1 and P4 (if applicable), are referred to as channel gates N1, N4, P1, and P4. In some embodiments, transistor pairs N1 / P1 and N4 / P4 are configured as transmission gates.

[0033] Transistors P2 and N2 are connected in series between the power supply voltage node VDD and the reference voltage node VSS, and include drain terminals coupled to each other at node D1 and gate terminals coupled to each other at node D2. Transistors P3 and N3 are connected in series between the power supply voltage node VDD and the reference voltage node VSS, and include drain terminals coupled to each other at node D2 and gate terminals coupled to each other at node D1. Transistor pairs P2 / N2 and P3 / N3 are thus configured as cross-coupled inverters, which are capable of storing data as complementary bits on nodes D1 and D2 during operation.

[0034] Transistors N1 and N4 are respectively coupled between bit lines BL and BLB and nodes D1 and D2, thereby selectively coupling node D1 to bit line BL and node D2 to bit line BLB in response to signal WL during operation. In some embodiments, transistors P1 and P4 are respectively coupled between bit lines BL and BLB and nodes D1 and D2, thereby selectively coupling node D1 to bit line BL and node D2 to bit line BLB in response to signal WLB during operation.

[0035] As depicted in Figure 2B, memory cell 200 (corresponding to the dashed boundary) includes transistors N1, N2, P1, and P2 located in CFET active region / region A1 and transistors N3, N4, P3, and P4 located in CFET active region / region A2. In various embodiments, CFET active regions / regions A1 and A2 correspond to transistors N1-N4 overlying individual transistors P1-P4 or transistors P1-P4 overlying individual transistors N1-N4.

[0036] The orientation of memory cell 200 relative to the X and Y directions is a non-limiting example provided for illustrative purposes. In some embodiments, instances of memory cell 200 have an orientation different from that depicted in Figure 2B, for example, opposite to the X direction. In some embodiments, a plurality of memory cells (e.g., the subset 100AL or 100AU described above) include instances of memory cell 200 having alternating orientations relative to the X direction, whereby adjacent instances of memory cell 200 share a boundary portion (and corresponding features) extending along the Y direction, as further described below.

[0037] In some embodiments, for example, in the IC layout diagrams / devices 300 and 400 described below, adjacent instances of memory cells 200 share a boundary corresponding to the boundary 100AB described above.

[0038] Transistor pairs N1 / P1, N2 / P2, N3 / P3, and N4 / P4 include individual gate regions / structures G1 to G4, and shared source / drain (S / D) regions / structures (not shown for clarity) in the corresponding portions of active regions / regions A1 and A2 adjacent to the gate regions / structures G1 to G4. Each gate structure G1 to G4 surrounds one or more channel portions (not shown for clarity) extending in the X direction between the corresponding S / D regions / structures of the corresponding active region / region A1 or A2.

[0039] The shared S / D area / structure is electrically connected to each other via metal-like defined (MD) areas / segments MD1~MD6, and / or via via-hole areas / structures V1, V3, V4, and V6 to metal areas / segments S1, S3, S4, and S6, as described below. Gate areas / structures G1 and G4 are electrically connected to metal areas / segments S2 and S5 via via-hole areas / structures V2 and V5, as described below. Gate areas / structures G2 and G3 are electrically connected to individual MD areas / segments MD5 and MD2 via instances of the contact point area / structure BCT.

[0040] An active region / area, such as active region / area A1 or A2, is a region included in the IC layout diagram during the manufacturing process as part of an active region (also referred to as oxide diffusion or definition (OD)) defined directly in the semiconductor substrate or in an n-type or p-type well region / area (not shown for clarity), wherein one or more IC device features, such as channel portions and / or S / D structures, are formed. In some embodiments, the active region is an n-type or p-type active region of a corresponding n-type or p-type FET of a CFET device. In various embodiments, the active region (structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or the like), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga)), or another suitable material.

[0041] In some embodiments, the active region is included in the IC layout diagram during the manufacturing process as a portion defining the nanosheet structure (e.g., a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping). In some embodiments, the channel portion corresponds to the nanosheet structure. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0042] The S / D region / structure is a region included in the IC layout diagram during the manufacturing process as a portion defining the S / D structure (also referred to as a semiconductor structure in some embodiments, having a doping type opposite to that of the corresponding active region / area). In some embodiments, the S / D region / structure is configured to have a lower resistivity than adjacent channel portions. In some embodiments, the S / D region / structure includes one or more portions having a doping concentration greater than one or more doping concentrations present in the corresponding channel portions. In some embodiments, the S / D region / structure includes an epitaxial region of a semiconductor material (e.g., Si, SiGe, and / or silicon carbide SiC). In some embodiments, the S / D region / structure includes one or more MD regions / segments.

[0043] The MD region / segment is a conductive region in the IC layout during the manufacturing process, defined in and / or on a semiconductor substrate and capable of electrically connecting to the underlying S / D structure and / or the underlying and / or overlying via structure. In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) overlying and contacting the substrate and having a sufficiently small thickness to enable the formation of an insulating layer between the MD segment and the overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing low-resistance (i.e., resistance levels below predetermined thresholds corresponding to one or more permissible levels based on the effect of resistance on circuit performance) electrical connections between IC structural elements.

[0044] In various embodiments, the MD segment includes a segment of the semiconductor substrate and / or epitaxial layer with a doping level, for example, based on the implantation process, sufficient to enable the segment to have a low resistance level. In various embodiments, the doped MD segment includes one or more doped materials having a doping concentration of about 1*10¹⁶ per cubic centimeter (cm⁻³) or higher.

[0045] In some embodiments, the manufacturing process includes two MD layers, and the MD section / segment refers to one or both of the two MDs in the manufacturing process. In some embodiments, the MD segment is used to electrically connect to the S / D structure of a single p-type or n-type FET of the CFET device and to electrically isolate it from the S / D structure of the other p-type or n-type FET of the CFET device. In some embodiments, the MD segment (also referred to in some embodiments as MD local interconnect (MDLI)) is used to electrically connect to the S / D structures of both the p-type FET and the n-type FET of the CFET device.

[0046] Gate region / structure, for example, gate region / structure G1~G4, is a region included in the IC layout diagram during the manufacturing process as part of defining the gate structure. The gate structure includes a volume of one or more conductive segments, such as a gate electrode, comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials, thereby using one or more conductive segments to control the voltage supplied to the adjacent gate dielectric layer.

[0047] The dielectric layer, for example, the gate dielectric layer, comprises a volume of one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials having a k value of less than 3.8 or high-k materials having a k value of greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable for providing high resistance, i.e., a resistance level above a predetermined threshold value, which corresponds to one or more permissible levels based on the effect of resistance on circuit performance.

[0048] The metal region / segment, for example, metal regions / segments S1~S6 or contact point regions / structures BCT, are areas included in the IC layout diagram during the manufacturing process as part of defining the metal line structure. The metal line structure includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials from a given metal layer of the manufacturing process. In various embodiments, the metal region / segment corresponds to a first metal layer (also referred to as metal zero layer in some embodiments) or a second or higher level metal layer of the manufacturing process.

[0049] Via regions / structures, such as via regions / structures V1 to V6, are areas included in the IC layout diagram during the manufacturing process as part of defining the via structure. The via structure includes one or more conductive materials to provide electrical connection between the overlying conductive structure (e.g., metal regions / segments S1 to S6) and the underlying conductive structure (e.g., gate electrodes of gate regions / structures G1 to G4 or MD regions / segments MD1 to MD6).

[0050] The via area / structure and metal area / segment correspond to the manufacturing process for forming features on the front or back side of a semiconductor wafer (e.g., semiconductor wafer 100B). As depicted in Figure 2B, the memory cell 200 includes electrical connections to each of the front side FS and the back side BS.

[0051] The front FS includes examples of metal regions / segments S1, S2, S5, and S6 configured as reference nodes / voltages VSS and word lines / signals WL, and via regions / structures V1, V2, V5, and V6; examples of metal regions / segments S3 and via regions / structures V3 configured as front bit lines BLFS corresponding to one of the aforementioned bit lines BLL or BLU; and examples of metal regions / segments S4 and via regions / structures V4 configured as front bit lines BLBFS corresponding to one of the aforementioned bit lines BLBL or BLBU.

[0052] The backside BS includes metal sections S1, S2, S5, and S6 configured as power supply nodes / voltages VDD and word lines / signals WLB, and via sections / structures V1, V2, V5, and V6; an example of a metal section S3 and via section V3 configured as a backside bit line BLBS corresponding to one of the aforementioned bit lines BLL or BLU; and an example of a metal section S4 and via section V4 configured as a backside bit line BLBBS corresponding to one of the aforementioned bit lines BLBL or BLBU.

[0053] Each instance of the metal region / segment S1 to S6 is located in the lowest metal layer at the corresponding front or back position, and each instance of the via region / structure V1 to V6 is used to electrically connect the corresponding instance of the metal region / segment S1 to S6 to the corresponding one in the MD region / segment MD1, MD3, MD4, or MD6 or the gate region / structure G1 or G4.

[0054] Examples of metal regions / segments S1, S3, S4, and S6 corresponding to the power supply voltage node VDD, the reference voltage node VSS, and the bit lines BLFS, BLBS, BLBFS, and BLBBS extend in the X direction over multiple instances of the memory cell 200. Examples of metal regions / segments S2 and S5 corresponding to the word lines WL and WLB partially extend in the X direction over a given instance of the memory cell 200 and are electrically connected, for example, to overlying features (not shown for clarity), such as via regions / structures and metal regions / segments extending in the Y direction.

[0055] MD region / segment MD1 corresponds to an MD instance used to electrically connect the S / D region / structure of transistor N2 to the reference voltage node VSS via the corresponding front instance of via region / structure V1 and metal region / segment S1, and an MD instance used to electrically connect the S / D region / structure of transistor P2 to the power supply voltage node VDD via the corresponding back instance of via region / structure V1 and metal region / segment S1. The instance of MD region / segment MD1, via region / structure V1, and metal region / segment S1 are thus used to electrically connect each of the reference voltage node VSS and the power supply voltage node VDD to each of the instances of memory cell 200 depicted in Figure 2B and to the adjacent reverse instance of memory cell 200 (if present).

[0056] MD region / segment MD6 corresponds to an MD instance used to electrically connect the S / D region / structure of transistor N3 to the reference voltage node VSS via the corresponding front instance of via region / structure V6 and metal region / segment S6, and an MD instance used to electrically connect the S / D region / structure of transistor P3 to the power supply voltage node VDD via the corresponding back instance of via region / structure V6 and metal region / segment S6. The instance of MD region / segment MD6, via region / structure V6, and metal region / segment S6 are thus used to electrically connect each of the reference voltage node VSS and the power supply voltage node VDD to each of the instances of memory cell 200 depicted in Figure 2B and to the adjacent reverse instance of memory cell 200 (if present).

[0057] MD section / segment MD2 is MDLI, which is used to electrically connect the S / D region / structure shared by transistor pairs N1 / N2 and P1 / P2 to the gate region / structure G3 included in each of transistors N3 and P3 via instances of contact point BCT. The combination of MD section / segment MD2, gate region / structure G3, and instances of contact point BCT thus corresponds to node D1.

[0058] MD section / segment MD5 is MDLI, which is used to electrically connect the S / D region / structure shared by transistor pairs N3 / N4 and P3 / P4 to the gate region / structure G2 included in each of transistors N2 and P2 via an instance of the contact point BCT. The combination of MD section / segment MD5, gate region / structure G2, and an instance of the contact point BCT thus corresponds to node D2.

[0059] In some embodiments, the gate region / structure G1 is included in each of the transistors N1 and P1, and the MD region / segment MD3 is MDLI, which is used to electrically connect the S / D region / structure of transistors N1 and P1 to one of the bit lines BLFS or BLBS via corresponding front or back instances of the via region / structure V3 and the metal region / segment S3. The gate region / structure G1 is electrically connected to a corresponding one of the word lines WL via a front instance of the via region / structure V2 and the metal region / segment S2, or electrically connected to the word line WLB via a back instance of the via region / structure V2 and the metal region / segment S2. The gate region / structure G1 and transistors N1 and P1 are thus configured as a single-channel gate for transistors N1 and P1 that can electrically connect one of the bit lines BLFS or BLBS to the instance of memory cell 200 depicted in Figure 2B and the adjacent reverse instance of memory cell 200 (if present) in response to the corresponding instance of the word line signal WL or WLB.

[0060] Similarly, in some embodiments, the gate region / structure G4 is included in each of the transistors N4 and P4, and the MD region / segment MD4 is MDLI, which is used to electrically connect the S / D region / structure of transistors N4 and P4 to one of the bit lines BLBFS or BLBBS via corresponding front or back instances of the via region / structure V4 and the metal region / segment S4. The gate region / structure G4 is electrically connected to one of the corresponding word lines WL or WLB via either the front instance of the via region / structure V5 and the metal region / segment S5 or via the back instance of the via region / structure V5 and the metal region / segment S5. The gate region / structure G4 and transistors N4 and P4 are thus configured to be able to electrically connect one of the bit lines BLBFS or BLBBS to the transistors N4 and P4 of the memory cell 200 instance depicted in Figure 2B and the adjacent reverse instance of the memory cell 200 (if present) in response to the corresponding instance of the word line signal WL or WLB.

[0061] In some embodiments, an example of a memory cell 200 including the single-channel gates N1 / P1 and N4 / P4 configured as described above is called a single-sided CFET SRAM cell.

[0062] In some embodiments, the gate region / structure G1 includes an electrically isolated portion included in transistors N1 and P1, and the MD region / segment MD3 includes an MD instance for electrically connecting the S / D region / structure of transistor N1 to bit line BLFS via a front instance of via region / structure V3 and metal region / segment S3, and an MD instance for electrically connecting the S / D region / structure of transistor P1 to bit line BLBS via a back instance of via region / structure V3 and metal region / segment S3. A portion of the gate region / structure G1 is electrically connected to word line WL via a front instance of via region / structure V2 and metal region / segment S2, and a portion of the gate region / structure G1 is electrically connected to word line WLB via a back instance of via region / structure V2 and metal region / segment S2. The gate region / structure G1 and transistors N1 and P1 are thus configured as channel gate pairs capable of electrically connecting bit line BLFS to each of the instances of memory cell 200 depicted in Figure 2B and adjacent reverse instances of memory cell 200 (if present) in response to the corresponding instance of word line signal WL, and electrically connecting bit line BLBS to each of the instances of memory cell 200 depicted in Figure 2B and adjacent reverse instances of memory cell 200 (if present) in response to the corresponding instance of word line signal WLB.

[0063] Similarly, in some embodiments, the gate region / structure G4 includes an electrically isolated portion included in transistors N4 and P4, and the MD region / segment MD4 includes an MD instance for electrically connecting the S / D region / structure of transistor N4 to bit line BLBFS via a front instance of via region / structure V4 and metal region / segment S4, and an MD instance for electrically connecting the S / D region / structure of transistor P4 to bit line BLBBS via a back instance of via region / structure V4 and metal region / segment S4. A portion of the gate region / structure G4 is electrically connected to word line WL via a front instance of via region / structure V5 and metal region / segment S5, and a portion of the gate region / structure G4 is electrically connected to word line WLB via a back instance of via region / structure V5 and metal region / segment S5. The gate region / structure G4 and transistors N4 and P4 are thus configured as channel gate pairs capable of electrically connecting bit line BLBFS to each of the memory cell 200 instance and adjacent reverse instance (if present) depicted in Figure 2B in response to the corresponding instance of word line signal WL, and electrically connecting bit line BLBBS to each of the memory cell 200 instance and adjacent reverse instance (if present) depicted in Figure 2B in response to the corresponding instance of word line signal WLB.

[0064] In some embodiments, an example of a memory cell 200 including the channel gate pairs N1 / P1 and N4 / P4 configured as described above is called a dual-sided CFET SRAM cell, for example, an IC layout / device 300 or 400 including adjacent reverse examples of the memory cell 200 described below with respect to Figures 3A to 4C.

[0065] By means of the configuration described above, instances of memory cell 200 enable the bit line electrical connections that are separated into front and back paths, so that memory circuits, such as memory macro 100 described above with respect to Figure 1, can realize the benefits discussed above with respect to memory macro 100.

[0066] Figures 3A to 3E depict an IC layout / device 300 comprising adjacent reverse examples of IC layout / device 200 according to some embodiments. Figure 3A depicts a plan view along the X and Y directions; Figure 3B depicts a cross-sectional view along the X and Z directions according to line A-A' of Figure 3A; Figure 3C depicts a cross-sectional view along the X and Z directions according to line B-B' of Figure 3A; Figure 3D depicts a cross-sectional view along the Y and Z directions according to line C-C' of Figure 3A; and Figure 3E depicts a cross-sectional view along the Y and Z directions according to line D-D' of Figure 3A. The following discussion of the IC layout / device 300 relates to the features described above with respect to Figures 1 to 2B.

[0067] As depicted in Figures 3A to 3E, the IC layout / device 300 includes each of adjacent reverse instances of the memory cell 200, including the features described above, wherein instances of MD regions / segments MD1 and MD4, via regions / structures V1 and V4, and metal regions / segments S1 and S4 are shared at boundary 100AB, thereby being included in each instance of the memory cell 200.

[0068] Instances of memory cells 200 adjacent to boundary 100AB along the negative X direction are included in subset 100AU, and instances of memory cells 200 adjacent to boundary 100AB along the positive X direction are included in subset 100AL.

[0069] In the embodiments depicted in Figures 3B to 3E, bit lines BLFS and BLBS correspond to individual bit lines BLU and BLL, while bit lines BLBFS and BLBBS correspond to individual bit lines BLBU and BLBL. Each of the back-side bit lines BLBS and BLBBS extends along subset 100AL and terminates at boundary 100AB, and each of the front-side bit lines BLFS and BLBFS extends along subsets 100AL and 100AU.

[0070] In subset 100AU, the MD region / segment MD3 of the MDLI configured as a common S / D region / structure of transistor pair N1 / P1 is electrically connected to bit line BLFS via a front instance of via region / structure V3 and metal region / segment S3. In subset 100AL, the MD region / segment MD3 of the MDLI configured as a common S / D region / structure of transistor pair N1 / P1 is electrically connected to bit line BLBS via a back instance of via region / structure V3 and metal region / segment S3. Each instance of transistor pair N1 / P1 is thus electrically coupled to a corresponding bit line BLFS or BLBS.

[0071] At boundary 100AB, an instance of the MD region / segment MD4 of a single transistor N4 is electrically connected to the bit line BLBFS via a front instance of the via region / structure V4 and the metal region / segment S4, and an instance of the MD region / segment MD4 of a single transistor P4 is electrically connected to the bit line BLBBS via a back instance of the via region / structure V4 and the metal region / segment S4. Each instance of the stacked transistors N4 and P4 is thus coupled to each of the bit lines BLBFS and BLBBS respectively.

[0072] As depicted in Figures 3A to 3E, the IC layout / device 300 is thus configured to include stacked transistors N4 and P4, which are configured as channel gates that can be separately controlled via instances of gate regions / structures G4 to selectively couple front-side and back-side bit lines to nodes D2 of adjacent reverse instances of memory cells 200.

[0073] In some embodiments, the IC layout / device 300 is otherwise used to include stacked transistors, such as transistors N1 and P1, configured as separately controllable channel gates to selectively couple front-side and back-side bit lines to nodes of adjacent reverse instances of memory cell 200, such as node D1.

[0074] By including a stacked channel gate for separating adjacent cells to front or back bit lines, IC layout / device 300 enables support for a continuous boundary between a first subset and a second subset, thereby maintaining memory cell density compared to a method where the boundary between the first subset and the second subset does not include cells that can separate front and back bit line connections.

[0075] Figures 4A to 4C depict an IC layout / device 400, which is an adjacent reverse example of IC layout / device 200 according to some embodiments. IC layout / device 400 corresponds to IC layout / device 300 as described above, except for the reconfiguration of bit lines BLFS and BLBFS, including the addition of via regions / structures V7 and V8 and metal regions / segments S7 and S8, as described below.

[0076] Figure 4A depicts a plan view along the X and Y directions, Figure 4B depicts a cross-sectional view along the X and Z directions according to line E-E' of Figure 4A, and Figure 4C depicts a cross-sectional view along the X and Z directions according to line F-F' of Figure 4A. The following discussion of the IC layout / device 400 relates to the features described above with respect to Figures 1 to 2B.

[0077] As depicted in Figures 4A to 4C, the IC layout / device 400 includes via regions / structures V7 and V8 at or near boundary 100AB, which are used to electrically connect corresponding front instances of metal regions / segments S3 and S4 to the overlying metal regions / segments S7 and S8.

[0078] Each of the metal regions / segments S7 and S8 corresponds to the third metal layer of the IC layout / device 400 in the manufacturing process, and the via regions / structures V7 and V8 correspond to the stack of vias and metal features used to electrically connect instances of the metal regions / segments S3 and S4 to the corresponding overlying metal regions / segments S7 and S8.

[0079] As depicted in Figures 4B and 4C, instances of metal sections / segments S3 and S4 terminate at boundary 100AB, and metal sections / segments S7 and S8 extend along subset 100AL in the positive X direction.

[0080] Examples of metal regions / segments S3 and S7 and via regions / structures V7 are thus configured together as front bit lines BLFS, and examples of metal regions / segments S4 and S8 and via regions / structures V8 are thus configured together as front bit lines BLBFS.

[0081] Compared to the IC layout / device 300 which includes front-side bit lines BLFS and BLBFS configured as described above, the IC layout / device 400 thus includes front-side bit lines BLFS and BLBFS, which are used to reduce parasitic resistance and capacitive bit line loads, thereby further improving speed and power performance during read and write operations, while compromising reduced routing flexibility.

[0082] Figure 5 is a flowchart of a method 500 for operating a memory macro according to some embodiments. The method 500 can be performed on a memory macro, such as the memory macro 100 described above with respect to Figures 1 to 4C.

[0083] The order of operations of method 500 depicted in Figure 5 is for illustrative purposes only; the operations of method 500 can be performed simultaneously or in a different order than that depicted in Figure 5. In some embodiments, operations other than those depicted in Figure 5 are performed before, between, during, and / or after the operations depicted in Figure 5.

[0084] At operation 510, one of the front or back bit lines is used to perform a first read or write operation on the memory cells of a first subset of the rows of memory cells.

[0085] In some embodiments, performing a first read or write operation on memory cells of a first subset of a row of memory cells using front or back bit lines includes performing a first read or write operation on memory cells 110 of a subset 100AL or 100AU of row 100C using one or more bit lines BLU, BLBU, BLL, or BLBL, as described above with respect to Figure 1.

[0086] In some embodiments, performing a first read or write operation on a memory cell using a front-side or back-side bit line includes performing a first read or write operation on memory cell 200 using one or more of bit lines BLFS, BLBFS, BLBS, or BLBBS, as described above with respect to Figures 2A to 4C.

[0087] At operation 520, a second read or write operation is performed on the memory cells of a second subset of the row of memory cells using the other of the front or back bit lines.

[0088] In some embodiments, performing a second read or write operation on memory cells of a second subset of a row of memory cells using front-side or back-side bit lines includes performing a read or write operation on memory cells 110 of another subset 100AL or 100AU of row 100C using one or more of bit lines BLU, BLBU, BLL, or BLBL, as described above with respect to Figure 1.

[0089] In some embodiments, performing a second read or write operation on a memory cell using a front-side or back-side bit line includes performing a second read or write operation on memory cell 200 using one or more of bit lines BLFS, BLBFS, BLBS, or BLBBS, as described above with respect to Figures 2A to 4C.

[0090] By performing some or all of the operations of the execution method 500, read and write operations are performed using bit lines located on both sides of the semiconductor wafer, thereby enabling the benefits discussed above regarding the memory macro 100, memory cell 200, and IC layout / device 300 and 400.

[0091] Figure 6 is a flowchart of a method 600 for generating an IC layout diagram according to some embodiments. In some embodiments, generating an IC layout diagram includes generating one or more of the IC layout diagrams 200, 300, or 400 described above with respect to Figures 2A to 4C.

[0092] In some embodiments, some or all of method 600 is executed by a computer processor. In some embodiments, some or all of method 600 is executed by a processor 802 of the IC layout generation system 800 described below with respect to Figure 8.

[0093] In some embodiments, one or more operations of method 600 are a subset of the operations of a method for forming an IC device. In some embodiments, one or more operations of method 600 are a subset of the operations of an IC manufacturing process, for example, the IC manufacturing process described below with respect to manufacturing system 900 and Figure 9.

[0094] In some embodiments, the operation of method 600 is performed in the order depicted in Figure 6. In some embodiments, the operation of method 600 is performed simultaneously and / or in a different order than that depicted in Figure 6. In some embodiments, one or more operations are performed before, between, during, and / or after the execution of one or more operations of method 600.

[0095] At operation 610, a row of memory cells is configured to be located between a second subset of the memory macro and the I / O circuit. Configuring the row of memory cells includes configuring row 100C of memory cells 110 to be located between a subset 100AU of the memory macro 100 described above with respect to Figure 1 and the I / O circuit MIO, which is a subset 100AL.

[0096] In some embodiments, configuring the memory cell includes configuring the memory cell 200 according to one or more of the IC layout diagrams 200-400 described above with respect to Figures 2A to 4C.

[0097] At operation 620, the front metal region is configured to extend from the I / O circuit to the second subset and include electrical connections to one of the first or second subset. Configuring the front metal region from the I / O circuit to the second subset includes overlapping the front metal region with the first subset.

[0098] In some embodiments, configuring the front metal area includes configuring one or both of the bit line BLU or BLBU (including electrical connections to subset 100AU) or the bit line BL or BLBL (including electrical connections to subset 100AL), as described above with respect to Figure 1.

[0099] In some embodiments, the first front metal region is configured from the I / O circuit to the second subset and overlaps with the first subset, including one of a pair of front metal regions configured from the I / O circuit to the second subset and overlapping with the first subset, wherein each of the pair of front metal regions includes an electrical connection to each memory cell in one of the first subset or the second subset.

[0100] In some embodiments, configuring the first front metal region includes configuring the first front metal region in the lowest front metal layer of a manufacturing process for constructing a memory macro in a semiconductor wafer.

[0101] In some embodiments, configuring the first front metal area includes configuring one or both of the bit lines BLFS or BLBFS described above with respect to IC layout diagram / device 300 and Figures 3A to 3E.

[0102] In some embodiments, the first front metal region includes an electrical connection to each memory cell in the second subset, and configuring the first front metal region includes configuring a first front metal segment in a third front metal layer of the manufacturing process, configuring a third metal region in a lowest front metal layer that overlaps with the second subset, and configuring a via region that overlaps with the first front metal region and the third front metal region.

[0103] In some embodiments, configuring the first front metal area includes configuring one or both of the bit lines BLFS or BLBFS described above with respect to IC layout diagram / device 400 and figures 4A to 4C.

[0104] At operation 630, the back-side metal region is used to extend from the I / O circuit to the second subset and includes an electrical connection to the other of the first or second subset. Configuring the back-side metal region from the I / O circuit to the second subset includes overlapping the back-side metal region with the first subset.

[0105] In some embodiments, configuring the back metal area includes configuring one or both of the bit line BLU or BLBU (including electrical connections to subset 100AU), or one or both of the bit line BL or BLBL (including electrical connections to subset 100AL), as described above with respect to Figure 1.

[0106] In some embodiments, configuring a first back-side metal region from the I / O circuit to the second subset and overlapping the first subset includes configuring one of a pair of back-side metal regions from the I / O circuit to the second subset and overlapping the first subset, wherein each of the pair of back-side metal regions includes an electrical connection to each memory cell in one of the first subset or the second subset.

[0107] In some embodiments, configuring the first backside metal region includes configuring the first backside metal region in the lowest backside metal layer of the manufacturing process.

[0108] In some embodiments, configuring the first back-side metal region includes configuring one or both of the bit lines BLBS or BLBBS described above with respect to IC layout diagrams / devices 300 and 400 and figures 3A to 4C.

[0109] At operation 640, in some embodiments, the IC layout diagram is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in an IC layout library as described below with respect to Figure 8, for example, the IC layout library 807 of the IC layout diagram generation system 800.

[0110] In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in non-volatile computer-readable memory or a cell library (e.g., a database), and / or includes storing the IC layout diagram via a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram via a network 814 of the EDA system 800 described below with respect to Figure 8.

[0111] At operation 650, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithography exposures based on an IC layout diagram as described below with respect to Figure 9. For example, one or more lithography exposures may be performed based on an IC layout diagram as described below with respect to Figure 9.

[0112] By performing some or all of the operations of method 600, at least partially defining the memory macro, wherein the bit line connections have separate front and back paths, the benefits discussed above with respect to memory macro 100 and IC layout / device 200-400 can be achieved.

[0113] Figure 7 is a flowchart of a method 700 for manufacturing an IC device according to some embodiments. Method 700 is operable to form one or more of the memory macro 100 or IC devices 200-400 described above with respect to Figures 1 to 4C.

[0114] In some embodiments, the operation of method 700 is performed in the order depicted in Figure 7. In some embodiments, the operation of method 700 is performed in a different order than that depicted in Figure 7. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 700. In some embodiments, performing some or all of the operations of method 700 includes performing one or more operations as described below with respect to IC manufacturing system 900 and Figure 9.

[0115] At operation 710, in some embodiments, a row of memory cells comprising a first subset located between the second subset and the I / O circuitry is constructed in the semiconductor wafer. Constructing the row includes constructing each of the first subset and the second subset as a contiguous set of memory cells in a memory macro.

[0116] In some embodiments, constructing memory cells includes constructing subsets 100AL and 100AU, wherein subset 100AL is between subset 100AU of memory macro 100 described above with respect to Figure 1 and I / O circuit MIO.

[0117] In some embodiments, constructing the first subset and the second subset includes constructing the first subset and the second subset of CFET SRAM cells, including forming a front via structure on each corresponding CFET SRAM cell of one of the first or second subset of CFET SRAM cells, and forming a back via structure on each corresponding CFET SRAM cell of the other of the first or second subset of CFET SRAM cells.

[0118] In some embodiments, constructing a memory cell includes constructing the memory cell 200 according to one or more of the IC layout diagrams / devices 200-400 described above with respect to Figures 2A to 4C.

[0119] In various embodiments, the process of constructing a memory cell includes performing a plurality of manufacturing operations, such as lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for depositing and forming one or more active regions, gates, S / D, and via structures, as described above with respect to Figures 1 through 4C.

[0120] At operation 720, a front metal segment is formed from the I / O circuit to the second subset and electrically connected to one of the first or second subset. The formation of the front metal segment from the I / O circuit to the second subset includes forming a front metal segment above the first subset.

[0121] In some embodiments, forming the front metal segment includes forming one or both of the bit lines BLU or BLBU electrically connected to the subset 100AU, or one or both of the bit lines BL or BLBL electrically connected to the subset 100AL, as described above with respect to Figure 1.

[0122] In some embodiments, forming a first front metal segment from the I / O circuit to the second subset and over the first subset includes one of a pair of front metal segments from the I / O circuit to the second subset and over the first subset, wherein each of the pair of front metal segments is electrically connected to each memory cell of one of the first subset or the second subset.

[0123] In some embodiments, forming the first front metal segment includes forming a first back metal segment in the lowest front metal layer of a manufacturing process for constructing a memory macro in a semiconductor wafer.

[0124] In some embodiments, forming the first front metal segment includes forming one or both of the bit lines BLFS or BLBFS described above with respect to IC layout diagram / device 300 and Figures 3A to 3E.

[0125] In some embodiments, the first front metal segment is electrically connected to each memory cell in the second subset, and forming the first front metal segment includes forming the first front metal segment in a third front metal layer of the manufacturing process, forming the third metal segment in the lowest front metal layer of the semiconductor wafer above the second subset, and forming a via structure between the first front metal segment and the third front metal segment.

[0126] In some embodiments, forming the first front metal segment includes forming one or both of the bit lines BLFS or BLBFS described above with respect to IC layout diagram / device 400 and Figures 4A to 4C.

[0127] In various embodiments, forming the front metal segment includes performing a plurality of manufacturing operations, such as lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing the isolation structure according to the configuration described above with respect to Figures 2A through 4C.

[0128] At operation 730, a back-side metal segment is formed from the I / O circuit to the second subset and electrically connected to the other of the first or second subset. The formation of the back-side metal segment from the I / O circuit to the second subset includes forming a back-side metal segment above the first subset.

[0129] In some embodiments, forming a back-side metal segment includes forming one or both of a bit line BLU or BLBU electrically connected to the subset 100AU, or one or both of a bit line BL or BLBL electrically connected to the subset 100AL, as described above with respect to Figure 1.

[0130] In some embodiments, forming a first back-side metal segment from the I / O circuit to the second subset and over the first subset includes one of a pair of back-side metal segments from the I / O circuit to the second subset and over the first subset, wherein each of the pair of back-side metal segments is electrically connected to each memory cell of the other of the first subset or the second subset.

[0131] In some embodiments, forming the first backside metal segment includes forming the first backside metal segment in the lowest backside metal layer of the manufacturing process for constructing a memory macro in a semiconductor wafer.

[0132] In some embodiments, forming the first back-side metal segment includes forming one or both of the bit lines BLBS or BLBBS described above with respect to IC devices 300 and 400 and Figures 3A to 4C.

[0133] In various embodiments, forming the first back-side metal segment includes performing a plurality of manufacturing operations, such as lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing metal lines according to the configuration described above with respect to Figures 2A through 5.

[0134] At operation 740, in some embodiments, additional electrical connections are constructed to include memory cells in the memory macro.

[0135] In some embodiments, constructing additional electrical connections includes constructing additional electrical connections to include memory cells 110 in the memory macro 100 described above with respect to Figure 1.

[0136] In various embodiments, forming additional electrical connections includes performing a plurality of manufacturing operations, such as lithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing vias and metal segments.

[0137] By performing some or all of the operations of method 700, a memory macro is formed, wherein the bit line connections have separate front and back paths, thereby enabling the benefits discussed above regarding memory macro 100 and IC layout diagrams / devices 200-400.

[0138] Figure 8 is a block diagram of an IC layout generation system 800 according to some embodiments. The method for designing IC layouts according to one or more embodiments described herein is implementable; for example, according to some embodiments, an IC layout generation system 800 is used.

[0139] In some embodiments, the IC layout generation system 800 is a general-purpose computing device, including a hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the storage medium 804 is encoded with, i.e., stored computer program code 806 (i.e., a set of executable instructions). The instructions of the computer program code 806 executed by the hardware processor 802 represent (at least part) an EDA tool, an EDA tool implementing a method, such as a part or all of the method 600 for generating an IC layout described above with respect to Figures 1 to 5 (hereinafter referred to as the mentioned process and / or method).

[0140] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is used to execute computer program code 806 encoded in computer-readable storage medium 804 so that IC layout generation system 800 can be used to perform part or all of the mentioned processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0141] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 804 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0142] In one or more embodiments, computer-readable storage medium 804 stores computer program code 806 that enables an IC layout generation system 800 (wherein this execution representation (at least partially) EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 804 also stores information that facilitates the performance of part or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 804 stores an IC layout library 807 of IC layouts, including such IC layouts as disclosed herein, for example, IC layouts 200-400 described above with respect to Figures 1 to 4C.

[0143] The IC layout generation system 800 includes an I / O interface 810. The I / O interface 810 is coupled to an external circuit system. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 802.

[0144] The IC layout generation system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more IC layout generation systems 800.

[0145] The IC layout generation system 800 receives information via the I / O interface 810. The information received via the I / O interface 810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 802. This information is transferred to the processor 802 via the bus 808. The IC layout generation system 800 also receives UI-related information via the I / O interface 810. This information is stored as a user interface (UI) 842 in a computer-readable storage medium 804.

[0146] In some embodiments, part or all of the mentioned processes and / or methods are implemented as standalone software applications for processor execution. In some embodiments, part or all of the mentioned processes and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, part or all of the mentioned processes and / or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as software applications used by the IC layout generation system 800. In some embodiments, the layout including standard cells is generated using tools such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0147] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards, and the like.

[0148] Figure 9 is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on an IC layout diagram, the manufacturing system 900 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of semiconductor integrated circuits.

[0149] In Figure 9, the IC manufacturing system 900 includes entities such as a design room 920, a mask room 930, and an IC manufacturer / wafer fab (“fab”) 950, which interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 920, mask room 930, and IC fab 950 are owned by a single larger company. In some embodiments, two or more of the design room 920, the mask room 930, and the IC wafer fab 950 coexist in a common facility and use common resources.

[0150] The design studio (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns, such as IC layouts 200-400 described above with respect to Figures 1 to 4C. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers constituting various components of the IC device 960 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed in and on various material layers of a semiconductor substrate (such as a silicon wafer). The design studio 920 implements appropriate design procedures to form the IC design layout 922. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 922 is presented in one or more data files containing information on the geometric patterns. For example, an IC design layout diagram 922 can be expressed in GDSII file format or DFII file format.

[0151] Masking chamber 930 includes data preparation 932 and mask manufacturing 944. Masking chamber 930 uses IC design layout 922 to manufacture one or more masks 945 for manufacturing various layers of IC device 960 according to IC design layout 922. Masking chamber 930 performs mask data preparation 932, in which IC design layout 922 is translated into a representative data file (RDF). Mask data preparation 932 provides the RDF to mask manufacturing 944. Mask manufacturing 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 945 or a semiconductor wafer 953. Design layout 922 is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC wafer fab 950. In Figure 9, mask data preparation 932 and mask manufacturing 944 are illustrated as separate components. In some embodiments, mask data preparation 932 and mask manufacturing 944 can be collectively referred to as mask data preparation.

[0152] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can produce self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masking, other fitting techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0153] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that examines the IC design layout 922, which has undergone processing in an OPC using a set of mask generation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margin, take into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask manufacturing 944, which may undo modifications performed by the OPC to satisfy the mask generation rules.

[0154] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), which simulates the process implemented by IC wafer fab 950 to manufacture IC device 960. LPC simulates this process based on IC design layout 922 to produce a simulated manufactured device, such as IC device 960. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitability factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0155] It should be understood that the above description of mask data preparation 932 has been simplified for clarity. In some embodiments, data preparation 932 includes additional features, such as logic operations (LOPs), to modify the IC design layout 922 according to manufacturing rules. Additionally, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0156] After mask data preparation 932 and during mask manufacturing 944, mask 945 or a group of masks 945 is manufactured based on a modified IC design layout 922. In some embodiments, mask manufacturing 944 includes performing one or more lithography exposures based on IC design layout 922. In some embodiments, an electron beam (e-beam) or multiple e-beams are used to form a pattern on the mask (photomask or master photomask) 945 based on the modified IC design layout 922. Mask 945 can be formed using various techniques. In some embodiments, mask 945 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams such as ultraviolet (UV) or EUV beams used to expose image-sensitive material layers (e.g., photoresist layers) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in an opaque area. In another example, mask 945 is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 945, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and image quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 944 is used in a variety of processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0157] IC wafer fab 950 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 950 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of a plurality of IC products, a second manufacturing facility that can provide back-end-of-line (BEOL) manufacturing for interconnection and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry business.

[0158] IC wafer fab 950 includes wafer fabrication tools 952 for performing various manufacturing operations on semiconductor wafers 953, such that IC device 960 is manufactured according to a mask (e.g., mask 945). In various embodiments, fabrication tools 952 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0159] IC wafer fab 950 uses a mask 945 manufactured by mask chamber 930 to manufacture IC device 960. Therefore, IC wafer fab 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC wafer fab 950 using mask 945 to form IC device 960. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate, or other suitable substrate on which a material layer is formed. Semiconductor wafer 953 further includes one or more of various doped regions, dielectric features, multi-quasi-interconnects, and the like (formed in subsequent manufacturing steps).

[0160] In some embodiments, the memory macro includes I / O circuitry located in a semiconductor wafer; a row of memory cells including a first subset and a second subset of consecutive memory cells extending away from the I / O circuitry in the semiconductor wafer, wherein the first subset is located between the I / O circuitry and the second subset; a first bit line coupled to the I / O circuitry and extending along the first subset on one of the front or back sides of the semiconductor wafer and terminating in the second subset; and a second bit line coupled to the I / O circuitry and extending along the first subset and the second subset on the other of the front or back sides, wherein each memory cell in the first subset is electrically connected to the first bit line and each memory cell in the second subset is electrically connected to the second bit line. In some embodiments, a first bit line is coupled to the I / O circuit and extends along a first subset on either the front or back side, terminating in one of the first bit line pairs in a second subset. A second bit line is coupled to the I / O circuit and extends along both the first and second subsets on either the front or back side. Each memory cell in the first subset is electrically connected to each bit line in the first bit line pair, and each memory cell in the second subset is electrically connected to each bit line in the second bit line pair. In some embodiments, the first bit line includes a metal segment extending from the I / O circuit in the lowest back side metal layer. In some embodiments, the second bit line includes a first metal segment extending from the I / O circuit along the first and second subsets in the lowest front side metal layer. In some embodiments, the second bit line includes a first metal segment extending from the I / O circuit along a first subset to a second subset in a first front metal layer, a second metal segment extending along the second subset away from the first subset in a lowest front metal layer, and a via structure for electrically connecting the first metal segment and the second metal segment at the boundary between the first subset and the second subset. In some embodiments, each memory cell in a row of memory cells includes a CFET SRAM cell, each CFET SRAM cell in the first subset includes one of a corresponding front via or a back via for electrically connecting the CFET SRAM cell to the first bit line, and each CFET SRAM cell in the second subset includes the other of a corresponding front via or a back via for electrically connecting the CFET SRAM cell to the second bit line. In some embodiments, the I / O circuit is used to perform read and write operations on the memory cells of the first subset using the first bit line, and to perform read or write operations on the memory cells of the second subset using the second bit line.

[0161] In some embodiments, an integrated circuit device includes a first bit line extending along the front side of a semiconductor wafer in a first direction, a second bit line extending along the back side of the semiconductor wafer in the first direction, and a first CFET SRAM cell and a second CFET SRAM cell positioned between the first bit line and the second bit line. The first CFET SRAM cell includes a first front-side via structure for electrically connecting a first channel gate of the first CFET SRAM cell to the first bit line, and the second CFET SRAM cell includes a first back-side via structure for electrically connecting a second channel gate of the second CFET SRAM cell to the second bit line. The front and back-side via structures are aligned in a direction perpendicular to the first direction. In some embodiments, the first channel gate includes an n-type FET, and the second channel gate includes a p-type FET. In some embodiments, the first channel gate includes a first gate structure electrically connected to the front-side word line, and the second channel gate includes a second gate structure electrically disconnected from the first gate structure and electrically connected to the back-side word line. In some embodiments, the IC device includes a third bit line extending along the front side of a semiconductor wafer in a first direction and a fourth bit line extending along the back side of the semiconductor wafer in the same first direction. A first CFET SRAM cell includes a second front via structure for connecting a third channel gate of the first CFET SRAM cell to the third bit line, and a second CFET SRAM cell includes a second back via structure for connecting a fourth channel gate of the second CFET SRAM cell to the fourth bit line. In some embodiments, the IC device includes a plurality of first CFET SRAM cells including the first CFET SRAM cells and a plurality of sub-second CFET SRAM cells including the second CFET SRAM cells. Each of the plurality of first CFET SRAM cells includes a corresponding first front via structure for connecting a corresponding first channel gate of the first CFET SRAM cell to the first bit line, and each of the plurality of second CFET SRAM cells includes a corresponding first back via structure for connecting a corresponding second channel gate of the second CFET SRAM cell to the second bit line. In some embodiments, the first bit line includes a first metal segment extending in a first direction in the lowest front metal layer, and the second bit line includes a second metal segment extending in the first direction in the lowest back metal layer. In some embodiments, the first bit line includes a third metal segment extending in the first direction and covering the first metal segment, and a through-hole structure for electrically connecting the first metal segment and the third metal segment to each other.

[0162] In some embodiments, a method of forming a memory macro includes constructing a row of memory cells in a semiconductor wafer, wherein constructing the row of memory cells includes constructing a first subset and a second subset of consecutive memory cells, and the first subset is positioned between the second subset of the memory macro and I / O circuitry; forming a first front metal segment from the I / O circuitry to the second subset and over the first subset, wherein the first front metal segment is electrically connected to each memory cell of one of the first subset or the second subset; and forming a first back metal segment from the I / O circuitry to the second subset and over the first subset, wherein the first back metal segment is electrically connected to each memory cell of the other of the first subset or the second subset. In some embodiments, forming the first front metal segment includes forming the first front metal segment in the lowest front metal layer of the semiconductor wafer. In some embodiments, a first front-side metal segment is electrically connected to each memory cell in a second subset. Forming the first front-side metal segment includes forming the first front-side metal segment in a third front-side metal layer of a semiconductor wafer, and the method includes forming a third metal segment above the second subset in a lowest front-side metal layer of the semiconductor wafer, and forming a via structure between the first metal segment and the third front-side metal segment. In some embodiments, forming a first back-side metal segment includes forming the first back-side metal segment in a lowest back-side metal layer of the semiconductor wafer. In some embodiments, forming a first front-side metal segment from the I / O circuit to the second subset and over the first subset includes forming one of a pair of front-side metal segments from the I / O circuit to the second subset and over the first subset, wherein each of the pair of front-side metal segments is electrically connected to each memory cell of one of the first subset or the second subset. Forming a first back-side metal segment from the I / O circuit to the second subset and over the first subset includes forming one of a pair of back-side metal segments from the I / O circuit to the second subset and over the first subset, wherein each of the pair of back-side metal segments is electrically connected to each memory cell of the other of the first subset or the second subset. In some embodiments, constructing a first subset and a second subset of memory cells includes constructing a first subset and a second subset of CFET SRAM cells. One of the first subset or the second subset of constructing CFET SRAM cells includes forming a front via structure on each corresponding CFET SRAM cell, and the other of the first subset or the second subset of constructing CFET SRAM cells includes forming a back via structure on each corresponding CFET SRAM cell.

[0163] The foregoing summarizes the features of several embodiments, enabling those skilled in the art to better understand the nature of some embodiments of this disclosure. Those skilled in the art should understand that some embodiments of this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of some embodiments of this disclosure. [Simplified Explanation of the Diagram]

[0005] Some embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standards, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of description. Figure 1 is a schematic diagram of a memory macro according to some embodiments. Figures 2A and 2B are schematic diagrams of an IC layout and apparatus according to some embodiments. Figures 3A to 3E are schematic diagrams of an IC layout and apparatus according to some embodiments. Figures 4A to 4C are schematic diagrams of an IC layout and apparatus according to some embodiments. Figure 5 is a flowchart of a method for operating a memory macro according to some embodiments. Figure 6 is a flowchart of a method for generating an IC layout according to some embodiments. Figure 7 is a flowchart of a method for manufacturing an IC apparatus according to some embodiments. Figure 8 is a block diagram of an IC layout generation system according to some embodiments. Figure 9 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. [Biomaterial Storage]

[0165] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An integrated circuit device, comprising: a first bit line extending along a front side of a semiconductor wafer in a first direction; a second bit line extending along a back side of the semiconductor wafer in the first direction; and a first complementary field-effect transistor (FPGA) static random access memory (SRAM) cell and a second complementary field-effect transistor (FPGA) static random access memory (SRAM) cell positioned between the first bit line and the second bit line, wherein the first FPGA static random access memory cell includes a first front-side via structure for gate-connecting a first channel of the first FPGA static random access memory cell to the first bit line, and the second FPGA static random access memory cell includes a first back-side via structure for gate-connecting a second channel of the second FPGA static random access memory cell to the second bit line. The front through-hole structure and the back through-hole structure are aligned in a direction perpendicular to the first direction, and the front through-hole structure and the back through-hole structure are disposed at the relative positions of the first complementary field-effect transistor static random access memory unit and the second complementary field-effect transistor static random access memory unit.

2. The integrated circuit device as claimed in claim 1, wherein the first channel gate includes a first gate structure electrically connected to a front-side character line, and the second channel gate includes a second gate structure electrically disconnected from the first gate structure and electrically connected to a rear-side character line.

3. The integrated circuit device as claimed in claim 1, further comprising: a third bit line extending along the front side of the semiconductor wafer in the first direction; and a fourth bit line extending along the back side of the semiconductor wafer in the first direction, wherein the first complementary field-effect transistor static random access memory cell further comprises a second front-side via structure for gate-connecting a third channel of one of the first complementary field-effect transistor static random access memory cells to the third bit line, and the second complementary field-effect transistor static random access memory cell further comprises a second back-side via structure for gate-connecting a fourth channel of one of the second complementary field-effect transistor static random access memory cells to the fourth bit line.

4. The integrated circuit device as claimed in claim 1, wherein the first bit line comprises a first metal segment extending in a first direction in a lowest front metal layer, and the second bit line comprises a second metal segment extending in the first direction in a lowest back metal layer, wherein the first bit line further comprises: a third metal segment extending in the first direction and covering the first metal segment; and a via structure for electrically connecting the first metal segment and the third metal segment to each other.

5. The integrated circuit device as claimed in claim 1, wherein the first element line includes a metal segment extending from an input / output circuit in a lowest back metal layer.

6. The integrated circuit arrangement as claimed in claim 1, wherein the second bit line includes a first metal segment extending from an input / output circuit in a lowest front metal layer.

7. The integrated circuit device as claimed in claim 6, wherein the material of the first metal segment includes copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), or aluminum (Al).

8. The integrated circuit arrangement as claimed in claim 1, wherein the first complementary field-effect transistor static random access memory cell and the second complementary field-effect transistor static random access memory cell comprise a plurality of n-type transistors and a plurality of p-type transistors coupled to each other.

9. A method of manufacturing a memory macro, the method comprising: constructing a row of memory cells in a semiconductor wafer, wherein constructing the row of memory cells includes constructing a first subset and a second subset of consecutive memory cells, and the first subset being positioned between the second subset of the memory macro and an input / output circuit; forming a first front metal segment from the input / output circuit to the second subset and above the first subset, wherein the first front metal segment is electrically connected to each memory cell in either the first subset or the second subset; and forming a first back metal segment from the input / output circuit to the second subset and above the first subset, wherein the first back metal segment is electrically connected to each memory cell in the other of the first subset or the second subset; wherein the first front metal segment and the first back metal segment are disposed at opposite positions of the row of memory cells.

10. The method of claim 9, wherein the first front metal segment is electrically connected to each memory cell in the second subset, the formation of the first front metal segment includes forming the first front metal segment in a third front metal layer of the semiconductor wafer, and the method further includes: forming a third metal segment in a lowest front metal layer of the semiconductor wafer above the second subset; and forming a via structure between the first front metal segment and the third metal segment.

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