Vertical power semiconductor device

Abstract

A vertical power semiconductor device comprises a semiconductor substrate, a semiconductor layer, gate components, a Schottky metal and a source contact layer, sequentially stacked, a first well disposed within the semiconductor layer, and a source electrode disposed within the first well. The semiconductor layer has a top surface, and the gate components and Schottky metal are disposed on the top surface. Each first well has a doped region and a heavily doped region located within the doped region. The source electrode is disposed within the doped region and surrounds the heavily doped region. Each gate component has a dielectric layer, a gate layer, and an insulating layer. The source contact layer covers the top surface, the insulating layer, and the Schottky metal. The gate layer is annular. Partial contact is formed between two adjacent gate layers, and four adjacent gate layers define a via filled with the Schottky metal. The gate layer covers the source electrode and the doped region and surrounds the heavily doped region.

Claims

1. A vertical power semiconductor device, comprising: a semiconductor substrate containing first conductivity type carriers; a semiconductor layer formed on the semiconductor substrate and containing the first conductivity type carriers, the semiconductor layer having a top surface remote from the semiconductor substrate; a plurality of first wells disposed at intervals within the semiconductor layer and containing second conductivity type carriers opposite to the first conductivity type carriers, each first well including a doped region extending from an interior of the semiconductor layer to the top surface and a heavily doped region extending from an interior of the doped region to the top surface with a doping concentration higher than that of the doped region; a plurality of sources disposed in their respective corresponding doped regions and containing the first conductivity type carriers, each source extending from the interior of its respective corresponding doped region to the top surface and surrounding its respective heavily doped region; and a plurality of gate components disposed at intervals on the top surface of the semiconductor layer, each gate component including a dielectric layer disposed on the top surface, a gate layer disposed on the dielectric layer, and an insulating layer covering the dielectric layer and the gate layer; Multiple Schottky metals are disposed at intervals on the top surface of the semiconductor layer; a source contact layer covers and contacts the sources, the heavily doped regions, the insulating layer, and the Schottky metals; and multiple second wells are disposed at intervals within the semiconductor layer and contain second conductivity type carriers, and are spaced apart from the first wells, each second well extending from the interior of the semiconductor layer to the top surface; wherein... Each gate layer, obtained by projecting an orthographic projection downwards from above the source contact layer, is in the form of a first ring. The gate layers of two adjacent gate components are partially in contact, and the gate layers of every four adjacent gate components define a through-hole for filling their respective Schottky metals. Each gate layer covers its corresponding source and doped region and surrounds its corresponding heavily doped region. The second wells, obtained by projecting an orthographic projection downwards from above the source contact layer, are in the form of a second ring. Each second well surrounds its corresponding Schottky metal below, and each gate layer partially covers its corresponding second well.

2. The vertical power semiconductor device as claimed in claim 1, wherein, The first ring shape is selected from either a ring-shaped regular hexagon or a ring-shaped parallelogram.

3. The vertical power semiconductor device as claimed in claim 2, wherein, The first ring is a ring-shaped regular hexagon, and each gate layer in the ring-shaped regular hexagon has a pair of first parallel sides, a pair of second parallel sides, and a pair of third parallel sides. The first parallel sides of each pair of adjacent gate layers are in complete contact, the second parallel sides of each pair of adjacent gate layers are in partial contact, and the third parallel sides of each pair of adjacent gate layers are not in contact. The second parallel sides and third parallel sides of each pair of adjacent gate layers together define their respective through holes for filling their respective Schottky metal.

4. The vertical power semiconductor device as claimed in claim 2, wherein, The first ring is a parallelogram, and each gate layer in the parallelogram has a pair of first parallel sides and a pair of second parallel sides. The first parallel sides of each pair of adjacent gate layers are in partial contact, and the second parallel sides of each pair of adjacent gate layers are not in contact. The first parallel sides and second parallel sides of each pair of four adjacent gate layers together define their respective through holes for filling their respective Schottky metals.

5. The vertical power semiconductor device as described in claim 3 or claim 4, wherein, Each of the through holes obtained by projecting the orthographic projection downward from above the source contact layer is a parallelogram with a predetermined area, and the second ring is an annular parallelogram, such that each of the second wells in the annular parallelogram surrounds the underside of its corresponding Schottky metal.

6. The vertical power semiconductor device as claimed in claim 5, wherein, The predetermined area is between 0.04 μm² and 32 μm².

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